ANALOG DEVICES AD5245 Service Manual

256-Position I2C®-Compatible

V

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FEATURES

256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pin AD0
Computer software replaces µC in factory programming

applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power: I
Wide operating temperature: –40°C
Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs
LCD panel V
LCD panel brightness and contrast control
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

COM

= 5 µs typ on power-up

S

= 8 µA

DD

adjustment

to +125°C

Digital Potentiometer

AD5245

FUNCTIONAL BLOCK DIAGRAM

DD

SCL

SDA

AD0

I2C

INTERFACE

WIPER

REGIS TER

POR

GND

Figure 1.

PIN CONFIGURATION

1

W

2

AD5245

V

DD

TOP VIEW

3

GND

(Not to Scale)

4

SCL

Figure 2.

A

8

7

B

6

AD0

5

SDA

A

W

B

03436-001

03436-002

GENERAL DESCRIPTION

The AD5245 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.

The wiper settings are controllable through an I
digital interface, which can also be used to read back the wiper
register content. AD0 can be used to place up to two devices on
the same bus. Command bits are available to reset the wiper
position to midscale or to shut down the device into a state of
zero power consumption.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

C-compatible

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 8 µA allows usage in portable battery-operated
applications.

Note that the terms digital potentiometer, VR, and RDAC are
used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD5245

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TABLE OF CONTENTS

Features .............................................................................................. 1

Test Cir c ui t s ..................................................................................... 12

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Electrical Characteristics................................................................. 3

5 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4

Timing Characteristics..................................................................... 5

5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

1/06—Rev. A to Rev. B

Changes to Table 3........................................................................... 5

Changes to Ordering Guide......................................................... 19

3/04—Rev. 0 to Rev. A

pdated Format................................................................ Universal

U

Changes to Features.........................................................................1

Changes to Applications ................................................................. 1

Changes to Figure 1......................................................................... 1

Changes to Electrical Characteristics—5 kΩ Version ................3

Changes to Electrical Characteristics—10 kΩ, 50 kΩ,

and 100 kΩ Versions ....................................................................... 4

Changes to Timing Characteristics............................................... 5

Changes to Absolute Maximum Ratings...................................... 6

Moved ESD Caution to Page.......................................................... 6

Changes to Pin Configuration and Function Descriptions ....... 7

Changes to Figures 22 and 23 ...................................................... 11

Moved Figure 25 to Figure 26 ...................................................... 11

Moved Figure 26 to Figure 27 ...................................................... 11

Moved Figure 27 to Figure 25 ...................................................... 11

Deleted Figures 31 and 32 ............................................................12

Changes to Figure 32, Figure 33 and Figure 34 ......................... 12

Changes to Rheostat Operation Section..................................... 13

Added Figure 35.............................................................................13

Changes to Equation 1 and Equation 2 ......................................13

Changes to Table 6 and Table 7.................................................... 13

Theory of Operation ...................................................................... 13

Programming the Variable Resistor......................................... 13

Programming the Potentiometer Divider............................... 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 14

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board ........................................................................ 15

2

I C Interface

2

I C-Compatible 2-Wire Serial Bus

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Added Figure 37 ............................................................................14

Changes to Equation 4.................................................................. 14

Deleted Readback RDAC Value Section .................................... 14

Deleted Level Shifting for Bidirectional Interface Section ...... 14

Moved ESD Protection Section to Page .....................................14

Changes to Figure 38 and Figure 39............................................ 14

Moved Terminal Voltage Operating Range Section to Page.... 14

Changes to Figure 40.....................................................................14

Moved Power-Up Sequence Section to Page .............................14

Moved Layout and Power Supply Bypassing Section to Page . 15

Added Constant Bias to Retain Resistance Setting Section ..... 15

Added Figure 42 ............................................................................15

Added Evaluation Board Section ................................................15

Added Figure 43 ............................................................................15

Moved I

Changes to I2C Compatible 2-Wire Serial Bus Section ........... 16

Moved Table 5 and Table 6 to Page ............................................. 17

(Renumbered as Table 8 and Table 9)

Moved Figure 36, Figure 37, and Figure 38 to Page.................. 17

(Renumbered as Figure 44, Figure 45, and Figure 46)

Moved Multiply Devices on One Bus Section to Page .............18

Updated Ordering Guide .............................................................19

Updated Outline Dimensions...................................................... 19

Moved I

5/03—Revision 0: Initial Version

.................................................................................... 16

........................................... 16

2

C Interface Section to Page...........................................16

2

C Disclaimer to Page..................................................... 20

Rev. B | Page 2 of 20

AD5245

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ELECTRICAL CHARACTERISTICS

5 kΩ VERSION

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106VAB = VDD, wiper = no connect 45 ppm/°C
Wiper Resistance R

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

Capacitance A, B

Capacitance W

5

6

6

Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

8

Power Supply Sensitivity PSS VDD = +5 V ± 10%, code = midscale ±0.02 ±0.05 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x80 1.2 MHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

2

2

3

R-DNL RWB, VA = no connect –1.5 ±0.1 +1.5 LSB
R-INL RWB, VA = no connect –4 ±0.75 +4 LSB
∆R

AB

W

TA = 25°C –30 +30 %

50 120 Ω

DNL –1.5 ±0.1 +1.5 LSB
INL –1.5 ±0.6 +1.5 LSB

WFSE

WZSE

VA, VB, V

W

Code = 0xFF –6 –2.5 0 LSB
Code = 0x00 0 2 6 LSB

GND V

V

DD

f = 1 MHz, measured to GND,

CA, C

B

code = 0x80

90 pF

f = 1 MHz, measured to GND,

C

7

6, 9

W

I

A_SD

CM

IH

IL

IH

IL

IL

C

IL

DD RANGE

DD

P

DISS

S

N_WB

W

code = 0x80 95 pF
VDD = 5.5 V 0.01 1 µA
VA = VB = VDD/2 1 nA

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 µA
5 pF

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3 8 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 44 µW

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
RWB = 2.5 kΩ, RS = 0 6 nV/√Hz

Rev. B | Page 3 of 20

AD5245

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10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity

Resistor Integral Nonlinearity

Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect –1 ±0.1 +1 LSB
R-INL RWB, VA = no connect –2 ±0.25 +2 LSB
∆R

AB

TA = 25°C –30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106VAB = VDD, wiper = no connect 45 ppm/°C
Wiper Resistance R

W

VDD = 5 V 50 120 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

DNL –1 ±0.1 +1 LSB

INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = 0xFF –3 –1 0 LSB
Code = 0x00 0 1 3 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

5

6

VA, VB, V

CA, C

B

W

GND V
f = 1 MHz, measured to GND,

90 pF

code = 0x80

Capacitance W

6

C

W

f = 1 MHz, measured to GND,

95 pF

code = 0x80
Shutdown Supply Current I
Common-Mode Leakage I

A_SD

CM

VDD = 5.5 V 0.01 1 µA

VA = VB = VDD/2 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

IH

IL

IH

IL

IL

C

IL

VDD = 5 V 2.4 V

VDD = 5 V 0.8 V

VDD = 3 V 2.1 V

VDD = 3 V 0.6 V

VIN = 0 V or 5 V ±1 µA

5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

7

DD RANGE

DD

P

DISS

Power Supply Sensitivity PSS

2.7 5.5 V

VIH = 5 V or VIL = 0 V 3 8 µA

VIH = 5 V or VIL = 0 V, VDD = 5 V 44 µW

= 5 V ± 10%,

V

DD

±0.02 ±0.05 %/%

code = midscale

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW

6, 8

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

code = 0x80
Total Harmonic Distortion THD

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t

S

W

VA = 1 V rms, VB = 0 V, f = 1 kHz,

= 10 kΩ

R

AB

VA = 5 V, VB = 0 V,

0.1 %

2 µs

±1 LSB error band
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

All dynamic characteristics use VDD = 5 V.

N_WB

RWB = 5 kΩ, RS = 0 9 nV/√Hz

1

Max Unit

V

DD

Rev. B | Page 4 of 20

AD5245

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TIMING CHARACTERISTICS

5 KΩ, 10 KΩ, 50 KΩ, 100 KΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ1Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time Between STOP and START t

BUF

t

Hold Time (Repeated START) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Repeated START Condition t

SU;STA

t

Data Hold Time t

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

Setup Time for STOP Condition t

SU;STO

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagram ( ) for locations of measured values. Figure 44

4

Standard I2C mode operation guaranteed by design.

2, , 3 4

(Specifications Apply to All Parts)

SCL

1

2

400 kHz

1.3 µs
After this period, the first clock

0.6 µs

pulse is generated.

3

4

5

6

7

8

9

10

1.3 µs

0.6 µs

0.6 µs

0.9 µs
100 ns
300 ns
300 ns

0.6 µs

Rev. B | Page 5 of 20

AD5245

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND V
Terminal Current, A to B, A to W, B to W

Pulsed ±20 mA
Continuous ±5 mA

Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature Range –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 245°C
Thermal Resistance2 θJA: SOT-23-8 230°C/W

1

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

JMAX

– TA)/θJA.

1

) 150°C

JMAX

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 20