ANALOG DEVICES AD5245 Service Manual

256-Position I2C®-Compatible

V

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FEATURES

256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
Fast settling time: t
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pin AD0
Computer software replaces µC in factory programming

applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power: I
Wide operating temperature: –40°C
Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs
LCD panel V
LCD panel brightness and contrast control
Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment

COM

= 5 µs typ on power-up

S

= 8 µA

DD

adjustment

to +125°C

Digital Potentiometer

AD5245

FUNCTIONAL BLOCK DIAGRAM

DD

SCL

SDA

AD0

I2C

INTERFACE

WIPER

REGIS TER

POR

GND

Figure 1.

PIN CONFIGURATION

1

W

2

AD5245

V

DD

TOP VIEW

3

GND

(Not to Scale)

4

SCL

Figure 2.

A

8

7

B

6

AD0

5

SDA

A

W

B

03436-001

03436-002

GENERAL DESCRIPTION

The AD5245 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.

The wiper settings are controllable through an I
digital interface, which can also be used to read back the wiper
register content. AD0 can be used to place up to two devices on
the same bus. Command bits are available to reset the wiper
position to midscale or to shut down the device into a state of
zero power consumption.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

C-compatible

Operating from a 2.7 V to 5.5 V power supply and consuming
less than 8 µA allows usage in portable battery-operated
applications.

Note that the terms digital potentiometer, VR, and RDAC are
used interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD5245

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TABLE OF CONTENTS

Features .............................................................................................. 1

Test Cir c ui t s ..................................................................................... 12

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Electrical Characteristics................................................................. 3

5 kΩ Version.................................................................................. 3

10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 4

Timing Characteristics..................................................................... 5

5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

1/06—Rev. A to Rev. B

Changes to Table 3........................................................................... 5

Changes to Ordering Guide......................................................... 19

3/04—Rev. 0 to Rev. A

pdated Format................................................................ Universal

U

Changes to Features.........................................................................1

Changes to Applications ................................................................. 1

Changes to Figure 1......................................................................... 1

Changes to Electrical Characteristics—5 kΩ Version ................3

Changes to Electrical Characteristics—10 kΩ, 50 kΩ,

and 100 kΩ Versions ....................................................................... 4

Changes to Timing Characteristics............................................... 5

Changes to Absolute Maximum Ratings...................................... 6

Moved ESD Caution to Page.......................................................... 6

Changes to Pin Configuration and Function Descriptions ....... 7

Changes to Figures 22 and 23 ...................................................... 11

Moved Figure 25 to Figure 26 ...................................................... 11

Moved Figure 26 to Figure 27 ...................................................... 11

Moved Figure 27 to Figure 25 ...................................................... 11

Deleted Figures 31 and 32 ............................................................12

Changes to Figure 32, Figure 33 and Figure 34 ......................... 12

Changes to Rheostat Operation Section..................................... 13

Added Figure 35.............................................................................13

Changes to Equation 1 and Equation 2 ......................................13

Changes to Table 6 and Table 7.................................................... 13

Theory of Operation ...................................................................... 13

Programming the Variable Resistor......................................... 13

Programming the Potentiometer Divider............................... 14

ESD Protection ........................................................................... 14

Terminal Voltage Operating Range ......................................... 14

Power-Up Sequence ................................................................... 14

Layout and Power Supply Bypassing ....................................... 14

Constant Bias to Retain Resistance Setting............................. 15

Evaluation Board ........................................................................ 15

2

I C Interface

2

I C-Compatible 2-Wire Serial Bus

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Added Figure 37 ............................................................................14

Changes to Equation 4.................................................................. 14

Deleted Readback RDAC Value Section .................................... 14

Deleted Level Shifting for Bidirectional Interface Section ...... 14

Moved ESD Protection Section to Page .....................................14

Changes to Figure 38 and Figure 39............................................ 14

Moved Terminal Voltage Operating Range Section to Page.... 14

Changes to Figure 40.....................................................................14

Moved Power-Up Sequence Section to Page .............................14

Moved Layout and Power Supply Bypassing Section to Page . 15

Added Constant Bias to Retain Resistance Setting Section ..... 15

Added Figure 42 ............................................................................15

Added Evaluation Board Section ................................................15

Added Figure 43 ............................................................................15

Moved I

Changes to I2C Compatible 2-Wire Serial Bus Section ........... 16

Moved Table 5 and Table 6 to Page ............................................. 17

(Renumbered as Table 8 and Table 9)

Moved Figure 36, Figure 37, and Figure 38 to Page.................. 17

(Renumbered as Figure 44, Figure 45, and Figure 46)

Moved Multiply Devices on One Bus Section to Page .............18

Updated Ordering Guide .............................................................19

Updated Outline Dimensions...................................................... 19

Moved I

5/03—Revision 0: Initial Version

.................................................................................... 16

........................................... 16

2

C Interface Section to Page...........................................16

2

C Disclaimer to Page..................................................... 20

Rev. B | Page 2 of 20

AD5245

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ELECTRICAL CHARACTERISTICS

5 kΩ VERSION

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity
Resistor Integral Nonlinearity
Nominal Resistor Tolerance
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106VAB = VDD, wiper = no connect 45 ppm/°C
Wiper Resistance R

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range

Capacitance A, B

Capacitance W

5

6

6

Shutdown Supply Current
Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

8

Power Supply Sensitivity PSS VDD = +5 V ± 10%, code = midscale ±0.02 ±0.05 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_5K RAB = 5 kΩ, code = 0x80 1.2 MHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the A terminal. The A terminal is open circuited in shutdown mode.

8

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

9

All dynamic characteristics use VDD = 5 V.

2

2

3

R-DNL RWB, VA = no connect –1.5 ±0.1 +1.5 LSB
R-INL RWB, VA = no connect –4 ±0.75 +4 LSB
∆R

AB

W

TA = 25°C –30 +30 %

50 120 Ω

DNL –1.5 ±0.1 +1.5 LSB
INL –1.5 ±0.6 +1.5 LSB

WFSE

WZSE

VA, VB, V

W

Code = 0xFF –6 –2.5 0 LSB
Code = 0x00 0 2 6 LSB

GND V

V

DD

f = 1 MHz, measured to GND,

CA, C

B

code = 0x80

90 pF

f = 1 MHz, measured to GND,

C

7

6, 9

W

I

A_SD

CM

IH

IL

IH

IL

IL

C

IL

DD RANGE

DD

P

DISS

S

N_WB

W

code = 0x80 95 pF
VDD = 5.5 V 0.01 1 µA
VA = VB = VDD/2 1 nA

VDD = 5 V 2.4 V
VDD = 5 V 0.8 V
VDD = 3 V 2.1 V
VDD = 3 V 0.6 V
VIN = 0 V or 5 V ±1 µA
5 pF

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3 8 µA
VIH = 5 V or VIL = 0 V, VDD = 5 V 44 µW

VA = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VA = 5 V, VB = 0 V, ±1 LSB error band 1 µs
RWB = 2.5 kΩ, RS = 0 6 nV/√Hz

Rev. B | Page 3 of 20

AD5245

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10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity

Resistor Integral Nonlinearity

Nominal Resistor Tolerance

2

2

3

R-DNL RWB, VA = no connect –1 ±0.1 +1 LSB
R-INL RWB, VA = no connect –2 ±0.25 +2 LSB
∆R

AB

TA = 25°C –30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106VAB = VDD, wiper = no connect 45 ppm/°C
Wiper Resistance R

W

VDD = 5 V 50 120 Ω

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Differential Nonlinearity
Integral Nonlinearity

4

4

DNL –1 ±0.1 +1 LSB

INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106Code = 0x80 15 ppm/°C
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = 0xFF –3 –1 0 LSB
Code = 0x00 0 1 3 LSB

RESISTOR TERMINALS

Voltage Range
Capacitance A, B

5

6

VA, VB, V

CA, C

B

W

GND V
f = 1 MHz, measured to GND,

90 pF

code = 0x80

Capacitance W

6

C

W

f = 1 MHz, measured to GND,

95 pF

code = 0x80
Shutdown Supply Current I
Common-Mode Leakage I

A_SD

CM

VDD = 5.5 V 0.01 1 µA

VA = VB = VDD/2 1 nA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance

6

IH

IL

IH

IL

IL

C

IL

VDD = 5 V 2.4 V

VDD = 5 V 0.8 V

VDD = 3 V 2.1 V

VDD = 3 V 0.6 V

VIN = 0 V or 5 V ±1 µA

5 pF

POWER SUPPLIES

Power Supply Range V
Supply Current I
Power Dissipation

7

DD RANGE

DD

P

DISS

Power Supply Sensitivity PSS

2.7 5.5 V

VIH = 5 V or VIL = 0 V 3 8 µA

VIH = 5 V or VIL = 0 V, VDD = 5 V 44 µW

= 5 V ± 10%,

V

DD

±0.02 ±0.05 %/%

code = midscale

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW

6, 8

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

600/100/40 kHz

code = 0x80
Total Harmonic Distortion THD

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) t

S

W

VA = 1 V rms, VB = 0 V, f = 1 kHz,

= 10 kΩ

R

AB

VA = 5 V, VB = 0 V,

0.1 %

2 µs

±1 LSB error band
Resistor Noise Voltage Density e

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

VAB = VDD, wiper (VW) = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

All dynamic characteristics use VDD = 5 V.

N_WB

RWB = 5 kΩ, RS = 0 9 nV/√Hz

1

Max Unit

V

DD

Rev. B | Page 4 of 20

AD5245

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TIMING CHARACTERISTICS

5 KΩ, 10 KΩ, 50 KΩ, 100 KΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter Symbol Conditions Min Typ1Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

Bus Free Time Between STOP and START t

BUF

t

Hold Time (Repeated START) t

HD;STA

t

Low Period of SCL Clock t

LOW

t

High Period of SCL Clock t

HIGH

t

Setup Time for Repeated START Condition t

SU;STA

t

Data Hold Time t

HD;DAT

t

Data Setup Time t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

Setup Time for STOP Condition t

SU;STO

1

Typical specifications represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagram ( ) for locations of measured values. Figure 44

4

Standard I2C mode operation guaranteed by design.

2, , 3 4

(Specifications Apply to All Parts)

SCL

1

2

400 kHz

1.3 µs
After this period, the first clock

0.6 µs

pulse is generated.

3

4

5

6

7

8

9

10

1.3 µs

0.6 µs

0.6 µs

0.9 µs
100 ns
300 ns
300 ns

0.6 µs

Rev. B | Page 5 of 20

AD5245

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Value

VDD to GND –0.3 V to +7 V
VA, VB, VW to GND V
Terminal Current, A to B, A to W, B to W

Pulsed ±20 mA
Continuous ±5 mA

Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature Range –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 245°C
Thermal Resistance2 θJA: SOT-23-8 230°C/W

1

Maximum terminal current is bound by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

JMAX

– TA)/θJA.

1

) 150°C

JMAX

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 20

AD5245

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

W

2

AD5245

V

DD

TOP VIEW

3

GND

(Not to Scale)

4

SCL

Figure 3. Pin Configuration

A

8

7

B

6

AD0

5

SDA

03436-002

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 W W Terminal. GND ≤ VW ≤ VDD.
2 V

DD

Positive Power Supply.
3 GND Digital Ground.
4 SCL Serial Clock Input. Positive edge triggered. Pull-up resistor required.
5 SDA Serial Data Input/Output. Pull-up resistor required.
6 AD0 Programmable Address Bit 0 for Two-Device Decoding.
7 B B Terminal. GND ≤ VB ≤ VDD.
8 A A Terminal. GND ≤ VA ≤ VDD.

Rev. B | Page 7 of 20

AD5245

A

A

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

= 5 V

5V

3V

5V
3V

–40°C
+25°C
+85°C

+125°C

03436-003

0.8

0.6

0.4

0.2

0

T MODE INL (LSB)

–0.2

–0.4

RHEOST

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

Figure 4. R-INL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

T MODE DNL (LSB)

–0.2

–0.4

RHEOST

–0.6

–0.8

–1.0

64

32096

128 160 192 224 256

CODE (Decimal)

Figure 5. R-DNL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE INL (LSB)

–0.8

–1.0

Figure 6. INL vs. Code vs. Temperature, V

64

32096

128 160 192 224 256

CODE (Decimal )

DD

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE DNL (LSB)

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal)

Figure 7. DNL vs. Code vs. Temperature, V

DD

= 5 V

–40°C
+25°C
+85°C

+125°C

03436-006

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE INL (LSB)

–0.8

–1.0

03436-004

64

32096

128 160 192 224 256

CODE (Decimal)

5V
3V

03436-007

Figure 8. INL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENTI OMETER MO DE DNL (LSB)

–0.8

–1.0

03436-005

3209664 128 160 192 224 256

CODE (Decimal)

5V

3V

03436-008

Figure 9. DNL vs. Code vs. Supply Voltages

Rev. B | Page 8 of 20

AD5245

A

A

(

www.BDTIC.com/ADI

1.0

0.8

0.6

0.4

0.2

0

T MODE INL (LSB)

–0.2

–0.4

RHEOST

–0.6

–0.8

–1.0

64

32096

128 160 192 224 256

CODE (Decimal)

Figure 10. R-INL vs. Code vs. Temperature, V

1.0

0.8

0.6

0.4

0.2

0

T MODE DNL (LSB)

–0.2

–0.4

RHEOST

–0.6

–0.8

–1.0

3209664 128 160 192 224 256

CODE (Decimal )

Figure 11. R-DNL vs. Code vs. Temperature, V

2.5

DD

DD

= 5 V

= 5 V

–40
+25°C
+85°C

+125°C

–40°C
+25°C
+85°C

+125°C

°C

03436-009

03436-010

2.5

2.0

1.5

1.0

V

= 2.7V

DD

ZSE, ZERO -SCALE ERRO R (µA)

0.5

0

0 40 80 120–40

0 40 80 120–40

TEMPERATURE (°C)

V

DD

= 5.5V

03436-012

Figure 13. Zero-Scale Error vs. Temperature

10

µA)

VDD = 5.5V

1

SUPPLY CURRENT

DD

I

0.1

V

= 2.7V

DD

0 40 80 120–40

TEMPERATURE (°C)

03436-013

Figure 14. Supply Current vs. Temperature

70

2.0

= 2.7V

V

V

DD

DD

= 5.5V

03436-011

1.5

1.0

0.5

FSE, FULL-SCALE ERRO R (LSB)

0

04080120–40

04080120–40

TEMPERATURE (°C)

Figure 12. Full-Scale Error vs. Temperature

Rev. B | Page 9 of 20

60

50

40

30

20

SHUTDOWN CURRENT (nA)

A

I

10

0

Figure 15. Shutdown Current vs. Temperature

0

TEMPERATURE (°C)

40 80 120–40

VDD = 5V

03436-014

AD5245

A

/DIV

/DIV

/DIV

/DIV

www.BDTIC.com/ADI

200

150

100

50

T MODE TEMPCO (ppm/°C)

0

RHEOST

–50

3209664 128 160 192 224 256

Figure 16. Rheostat Mode Tempco ∆R

CODE (Decimal)

/∆T vs. Code

WB

160

140

120

100

80

60

40

20

0

POTENTI OMETER MO DE TEMPCO (ppm/°C)

–20

3209664 128 160 192 224 256

Figure 17. Potentiometer Mode Tempco ∆V

CODE (Decimal )

WB

/∆T vs. Code

REF LE VEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

START 1 000.000 Hz ST OP 1 000 000.000Hz

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02
0x01

10k 100k 1M

Figure 18. Gain vs. Frequency vs. Code, R

MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB

= 5 kΩ

AB

REF LE VEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

3436-015

1k

START 1 000.000 Hz ST OP 1 000 000.000Hz

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

Figure 19. Gain vs. Frequency vs. Code, R

REF LE VEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

03436-016

1k 10k 100k 1M

START 1 000.000 Hz ST OP 1 000 000.000Hz

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

Figure 20. Gain vs. Frequency vs. Code, R

REF LE VEL

0.000dB
0

–6

–12

–18

–24

–30

–36

–42

–48

–54

–60

1k

03436-017

START 1 000.000 Hz ST OP 1 000 000.000Hz

6.000dB

0x80

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k 100k 1M

Figure 21. Gain vs. Frequency vs. Code, R

MARKER 510 634.725Hz
MAG (A/R) –9.049dB

= 10 kΩ

AB

MARKER 100 885.289Hz
MAG (A/R) –9.014dB

= 50 kΩ

AB

MARKER 54 089.173Hz
MAG (A/R) –9.052dB

= 100 kΩ

AB

03436-018

03436-019

03436-020

Rev. B | Page 10 of 20

AD5245

/DIV

www.BDTIC.com/ADI

REF LEVEL
–5.000dB

–5.5

–6.0

–6.5

–7.0

–7.5

–8.0

–8.5

–9.0

R = 100kΩ

–9.5

–10.0

–10.5

10k 100k 1M 10M

START 1 000.000Hz ST OP 1 000 000.000Hz

60

40

0.500dB

5kΩ – 1.026MHz
10kΩ – 511kHz
50kΩ – 101kHz
100kΩ – 54kHz

R = 50kΩ

R = 10kΩ

R = 5kΩ

Figure 22. –3 dB Bandwidth @ Code = 0x80

CODE = 0x80, VA= VDD, VB = 0V

1

2

Ch 1 200mV

03436-021

B

W

Ch 2 5.00 V

B

M 100ns A CH2 3.00 V

W

VW

Figure 25. Large Signal Settling Time, Code 0xFF ≥ 0x00

VA = 5V

= 0V

V

B

SCL

03436-024

PSRR (–dB)

20

PSRR @ VDD = 5V DC ±10% p-p AC

0

Figure 23. PSRR v s. Frequency

900

800

700

600

500

(µA)

400

DD

I

300

200

100

0
10k

Figure 24. I

PSRR @ VDD = 3V DC ±10% p-p AC

10k100 100k 1M1k

FREQUENCY (Hz)

VDD= 5V

CODE = 0x55

CODE = 0xFF

100k 1M 10M

FREQUENCY (Hz)

vs. Frequency

DD

1

2

Ch 1 100mV

03436-022

B

Ch 2 5.00 V

W

B

M 200ns A CH1 152mV

W

Figure 26. Digital Feedthrough

VW

SCL

03436-025

VA = 5V
V

= 0V

B

1

2

Ch 1 5.00V

03436-023

B

W

Ch 2 5.00 V

B

M 200ns A CH1 3.00 V

W

Figure 27. Midscale Glitch, Code 0x80 ≥ 0x7F

VW

SCL

03436-026

Rev. B | Page 11 of 20

AD5245

www.BDTIC.com/ADI

TEST CIRCUITS

Figure 28 to Figure 34 illustrate the test circuits that define the test conditions used in the product specification tables (Table 1 through Table 3).

V+ = V

DUT

A

V+

W

B

DD

1LSB = V+/2

V

MS

N

03436-027

Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error

(INL, DNL)

NO CONNECT

DUT

A

W

B

I

W

V

MS

03436-028

Figure 29. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

A

V

MS2

W

B

V

W

IW = VDD/R

V

MS1

RW = [V

NOMINAL

MS1

– V

MS2

]/I

W

03436-029

Figure 30. Test Circuit for Wiper Resistance

V

A

V

DD

A

V+

W

B

V+ = V

±10%

DD

PSRR (dB) = 20 lo g

PSS (%/ %) =

V

MS

∆V

∆V

MS

DD

∆V

( )

∆V

%

%

MS

DD

Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

OFFSET

GND

DUT

A

V

IN

2.5V

W

B

+15V

–15V

AD8610

V

OUT

03436-031

Figure 32. Test Circuit for Gain vs. Frequency

0.1V

RSW=

I

DUT

W

B

I

SW

GND TO V

SW

CODE = 0x00

DD

0.1V

03436-032

Figure 33. Test Circuit for Incremental On Resistance

NC

DUT

GND

NC

A

W

B

V

DD

I

CM

NC = NO CONNECT

V

CM

03436-033

Figure 34. Test Circuit for Common-Mode Leakage Current

03436-030

Rev. B | Page 12 of 20

AD5245

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD5245 is a 256-position digitally controlled variable
resistor (VR) device.

An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (R
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.

Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (R
The third connection is the next tap point, representing 178 Ω
(2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at 10,100 Ω (R

) of the VR has 256 contact points accessed by

AB

A

B

+ 2 × RW).

AB

A

W

B

W

03436-034

03436-035

RDAC

AND

A

W

B

R

S

R

S

R

S

R

S

A

W

B

Figure 35. Rheostat Mode Configuration

= RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for Data 0x01.

WB

D7
D6
D5
D4
D3
D2
D1
D0

LATCH

DECODER

Figure 36. AD5245 Equivalent RDAC Circuit

The general equation determining the digitally programmed
output resistance between W and B is

WB

256

D

DR ×+×= 2

)( (1)

RR

AB

W

where:

D is the decimal equivalent of the binary code loaded in the

8-bit RDAC register.

R

is the end-to-end resistance.

AB

R

is the wiper resistance contributed by the on resistance of

W

the internal switch.

In summary, if R
circuited, then the following output resistance R

= 10 kΩ and the A terminal is open

AB

WB

is set for the

indicated RDAC latch codes.

Table 6. Codes and Corresponding R

Resistance

WB

D (Dec.) RWB (Ω) Output State

255 9,961 Full Scale (RAB – 1 LSB + RW)
128 5,060 Midscale
1 139 1 LSB
0 100 Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, R

. When these

WA

terminals are used, the B terminal can be opened. Setting the
resistance value for R

starts at a maximum value of resistance

WA

and decreases as the data loaded in the latch increases in value.
The general equation for this operation is

D

−

256

DR ×+×

= 2

)( (2)

256

= 10 kΩ and the B terminal open circuited, the

For R

AB

following output resistance R

RR

ABWA

W

is set for the indicated RDAC

WA

latch codes.

Table 7. Codes and Corresponding RWA Resistance

D (Dec.) RWA (Ω) Output State

255 139 Full Scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero Scale

Typical device-to-device matching is process lot dependent and
can vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in R

AB

with

temperature has a very low 45 ppm/°C temperature coefficient.

Rev. B | Page 13 of 20

AD5245

V

www.BDTIC.com/ADI

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.

to GND, which must be

DD

TERMINAL VOLTAGE OPERATING RANGE

The AD5245 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on Terminals A, B, and W that
exceed V
diodes (see Figure 40).

or GND are clamped by the internal forward-biased

DD

DD

V

I

A

W

V

O

B

03436-036

Figure 37. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,
then connecting the A terminal to 5 V and the B terminal to
ground produces an output voltage at the wiper-to-B starting at
0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V

with respect to ground for any

W

valid input voltage applied to Terminals A and B is

D

DV

W

V

)(

256

A

D

256

−

(3)

256

V

B

+=

A more accurate calculation, which includes the effect of wiper
resistance, V

, is

W

DR

DR

)(

WB

DV

)( +=

W

V

R

A

AB

WA

R

)(

V

(4)

B

AB

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R

and RWB, not the absolute

WA

values. Therefore, the temperature drift reduces to 15 ppm/°C.

ESD PROTECTION

All digital inputs are protected with a series of input resistors and
parallel Zener ESD structures, shown in Figure 38 and Figure 39.
This applies to the digital input pins SDA, SCL, and AD0.

340Ω

LOGIC

GND

Figure 38. ESD Protection of Digital Pins

A, B, W

3436-037

A

W

B

GND

03436-039

Figure 40. Maximum Terminal Voltages Set by V

and GND

DD

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 40), it is important to
power V

and GND before applying any voltage to Terminals

DD

A, B, and W; otherwise, the diode is forward biased such that

is powered unintentionally and can affect the rest of the

V

DD

user’s circuit. The ideal power-up sequence is in the following
order: GND, V
relative order of powering V
not important as long as they are powered after V

, digital inputs, and then VA, VB, and VW. The

DD

, VB, VW, and the digital inputs is

A

and GND.

DD

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disk or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 41). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.

V

DD

+

C3

10µFC10.1µF

V

DD

AD5245

GND

GND

Figure 39. ESD Protection of Resistor Terminals

03436-038

Rev. B | Page 14 of 20

Figure 41. Power Supply Bypassing

03436-040

AD5245

A

R

www.BDTIC.com/ADI

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the
additional cost for the EEMEM, the AD5245 can be considered
a low cost alternative by maintaining a constant bias to retain
the wiper setting. The AD5245 is designed specifically with low
power in mind, which allows low power consumption even in
battery-operated systems. Figure 42 demonstrates the power
consumption from a 3.4 V, 450 mA-hr Li-Ion cell phone battery
that is connected to the AD5245. The measurement over time
shows that the device draws approximately 1.3 µA and
consumes negligible power. Over a course of 30 days, the
battery is depleted by less than 2%, the majority of which is due
to the intrinsic leakage current of the battery itself.

110%

108%

106%

104%

102%

100%

98%

Y LIFE DEPLETED

96%

TTE
B

94%

92%

90%

0

51015

DAYS

Figure 42. Battery Operating Life Depletion

20 25 30

This demonstrates that constantly biasing the potentiometer
can be a practical approach. Most portable devices do not
require the removal of batteries for charging.

TA= 25°C

03436-041

Although the resistance setting of the AD5245 is lost when the
battery needs replacement, such events occur rather infrequently
so that this inconvenience is justified by the lower cost and
smaller size offered by the AD5245. If total power is lost, then
the user should be provided with a means to adjust the setting
accordingly.

EVALUATION BOARD

An evaluation board, along with all necessary software, is
available to program the AD5245 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 43, is straightforward and easy to use. More detailed
information is available in the user manual, which is provided
with the board.

03436-042

Figure 43. AD5245 Evaluation Board Software

The AD5245 starts at midscale upon power-up. To increment or
decrement the resistance, the user can simply move the scroll­bars on the left. To write a specific value, the user should use the
bit pattern in the upper screen and click the
format of writing data to the device is shown in Table 8. To read
the data from the device, the user can simply click the
button. The format of the read bits is shown in Table 9.

Run button. The

Read

Rev. B | Page 15 of 20

AD5245

www.BDTIC.com/ADI

I2C INTERFACE

I2C-COMPATIBLE 2-WIRE SERIAL BUS

The 2-wire I2C serial bus protocol operates as follows:

1.

The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 45). The next byte
is the slave address byte, which consists of the 7-bit slave

W

address followed by an R/
data is read from or written to the slave device). The AD5245
has one configurable address bit, AD0 (see Table 8).

The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/

from the slave device. On the other hand, if the R/
low, the master writes to the slave device.

In write mode, the second byte is the instruction byte.

2.
The first bit (MSB) of the instruction byte is a don’t care.

The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap, where R
This feature effectively overwrites the contents of the
register; therefore, when taken out of reset mode, the RDAC
remains at midscale.

The third MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 Ω in rheostat mode
or 0 V in potentiometer mode. It is important to note that
the shutdown operation does not disturb the contents of the
register. When brought out of shutdown, the previous setting is
applied to the RDAC. Also during shutdown, new settings can
be programmed. When the part is returned from shutdown,
the corresponding VR setting is applied to the RDAC.

The remainder of the bits in the instruction byte are don’t
cares (see Table 8).

bit (this bit determines whether

bit is high, the master reads

W

bit is

W

= RWB.

WA

3.

After acknowledging the instruction byte, the last byte in

write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 45).

In read mode, the data byte follows immediately after the

4.
acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with write mode, in which eight
data bits are followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).

5.

After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10
condition (see Figure 45). In read mode, the master issues a
no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line low
before the 10
STOP condition (see Figure 46).

A repeated write function gives the user flexibility to update
the RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC
has acknowledged its slave address and instruction bytes in
the write mode, the RDAC output updates on each successive
byte. If different instructions are needed, then the write/read
mode has to start again with a new slave address, instruction,
and data byte. Similarly, a repeated read function of the
RDAC is also allowed.

th

clock pulse to establish a STOP

th

clock pulse, which goes high to establish a

Rev. B | Page 16 of 20

AD5245

www.BDTIC.com/ADI

Table 8. Write Mode

S 0 1 0 1 1 0 AD0

Slave Address Byte Instruction Byte Data Byte

Table 9. Read Mode

S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P

Slave Address Byte Data Byte

S = START condition
P = STOP condition
A = Acknowledge
X = Don’t care
W

= Write

A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

W

R = Read
RS = Reset wiper to midscale 0x80
SD = Shutdown connects wiper to B terminal and open circuits

A terminal, but does not change contents of wiper register
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits

t

t

8

t

9

2

SCL

SDA

t

1

PS

t

2

t

3

t

8

t

9

Figure 44. I

t

6

t

4

2

C Interface Detailed Timing Diagram

t

7

t

5

t

10

PS

3436-043

START BY

MASTER

SCL

SDA

1

0

0

FRAME 1 FRAME 2

SLAVE ADDRESS BYTE

1

1 0 AD0 R/W

1 919

XRS X X X X X

SD

ACK BY
AD5245

INSTRUCTION BYTE

Figure 45. Writing to the RDAC Register

19

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY
AD5245

FRAME 3

DATA BYTE

ACK BY
AD5245

STOP BY

MASTER

3436-044

1 919

SCL

D7

D6 D5 D4 D3 D2 D1 D0

FRAME 2

RDAC REGISTER

NO ACK
BY MASTER

STOP BY
MASTER

03436-045

START BY

MASTER

01 0 11 0AD0R/W

SDA

FRAME 1

SLAVE ADDRESS BYTE

Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode

ACK BY
AD5245

Rev. B | Page 17 of 20

AD5245

V

www.BDTIC.com/ADI

Multiple Devices on One Bus

Figure 47 shows two AD5245 devices on the same serial bus.
Each has a different slave address because the states of their
AD0 pins are different. This allows the RDAC within each
device to be written to or read from independently. The master
device’s output bus line drivers are open-drain pull-downs in a

2

C-compatible interface.

fully I

MASTER

+5

R

Figure 47. Multiple AD5245 Devices on One I

R

P

P

+5V

SDA SCL

AD0 AD0

AD5245

SDA SCL

AD5245

2

C Bus

SDA

SCL

03436-046

Rev. B | Page 18 of 20

AD5245

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

2.90 BSC

847

1.60 BSC

13

PIN 1

INDICATOR

1.30

1.15

0.90

0.15 MAX

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 48. 8-Lead Small Outline Transistor Package [SOT-23]

56

2.80 BSC

2

1.95
BSC

0.65 BSC

(RJ-8)

0.22

0.08

1.45 MAX

SEATING
PLANE

Dimensions shown in millimeters

8°
4°
0°

0.60

0.45

0.30

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding RAB (Ω) Ordering Quantity

AD5245BRJ5-R2 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0G 5 k 250
AD5245BRJ5-RL7 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0G 5 k 3,000
AD5245BRJZ5-R2
AD5245BRJZ5-RL7
AD5245BRJ10-R2 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0H 10 k 250
AD5245BRJ10-RL7 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0H 10 k 3,000
AD5245BRJZ10-R2
AD5245BRJZ10-RL7
AD5245BRJ50-R2 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0J 50 k 250
AD5245BRJ50-RL7 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0J 50 k 3,000
AD5245BRJZ50-R2
AD5245BRJZ50-RL7
AD5245BRJ100-R2 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0K 100 k 250
AD5245BRJ100-RL7 –40°C to +125°C 8-Lead SOT-23 RJ-8 D0K 100 k 3,000
AD5245BRJZ100-R2
AD5245BRJZ100-RL71–40°C to +125°C 8-Lead SOT-23 RJ-8 D0K 100 k 3,000
AD5245EVAL

1

Z = Pb-free part.

2

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

1

2

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0G 5 k 250

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0G 5 k 3,000

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0H 10 k 250

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0H 10 k 3,000

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0J 50 k 250

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0J 50 k 3,000

1

–40°C to +125°C 8-Lead SOT-23 RJ-8 D0K 100 k 250

Evaluation Board

Rev. B | Page 19 of 20

AD5245

www.BDTIC.com/ADI

NOTES

Purchase of licensed I
purchaser under the Philips I
Standard Specification as defined by Philips.

2

C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the

2

C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03436-0-1/06(B)

Rev. B | Page 20 of 20