Analog Devices AD5233 a Datasheet

Nonvolatile Memory, Quad

FEATURES

Nonvolatile memory stores wiper setting
4-channel independent programmable
64-position resolution
Power-on refreshed with EEMEM settings
EEMEM restore time: 140 µs typ
Full monotonic operation
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions
SPI®-compatible serial interface with readback function
3 V to 5 V single supply or ±2.5 V dual supply
11 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, T

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

GENERAL DESCRIPTION

The AD5233 is a quad-channel nonvolatile memory,1 digitally
controlled potentiometer
performs the same electronic adjustment function as a
mechanical potentiometer with enhanced resolution, solid state
reliability, and remote controllability. The AD5233 has versatile
programming using an SPI-compatible serial interface for
16 modes of operation and adjustment including scratchpad
programming, memory storing and restoring, increment/
decrement, ±6 dB/step log taper adjustment, wiper setting
readback, and extra EEMEM for user-defined information such
as memory data for other components, look-up tables, or system
identification information.

2

with 64-step resolution. The device

= 55°C

A

64-Position Digital Potentiometer

AD5233

FUNCTIONAL BLOCK DIAGRAM

AD5233

RDAC1

RDAC2

RDAC3

RDAC4

CLK

SDI

SDO

WP

RDY

GND

CS

O1
O2

PR

DECODE

SDI SERIAL
INTERFACE

SDO

EEMEM

CONTROL

11 BYTES

USER EEMEM

DIGITAL
OUTPUT
BUFFER

2

DIGITAL 5

REGISTER

EEMEM5

ADDR

RDAC1

REGISTER

EEMEM1

RDAC2

REGISTER

EEMEM2

RDAC3

REGISTER

EEMEM3

RDAC4

REGISTER

EEMEM4

Figure 1.

In the scratchpad programming mode, a specific setting can be
programmed directly to the RDAC

2

register, which sets the
resistance between Terminals W–A and W–B. This setting can
be stored into the EEMEM and is transferred automatically to
the RDAC register during system power-on.

The EEMEM content can be restored dynamically or through
external

PR

strobing, and a WP function protects EEMEM
contents. To simplif y the programming, independent or
simultaneous increment or decrement commands can be used
to move the RDAC wiper up or down, one step at a time. For
logarithmic ±6 dB step changes in wiper settings, the left or
right bit shift command can be used to double or halve the
RDAC wiper setting.

The AD5233 is available in a thin TSSOP-24 package. The part
is guaranteed to operate over the extended industrial tempera­ture range of −40°C to +85°C.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

V

A1
W1

B1

A2
W2

B2

A3
W3

B3

A4
W4

B4

V

DD

SS

02794-A-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5233

TABLE OF CONTENTS

Specifications..................................................................................... 3

Programming the Potentiometer Divider............................... 20

Electrical Characteristics—10 kΩ, 50 kΩ, and 100 kΩ
Ve rs i on s

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics............................................. 9

Tes t Ci rc u it s ................................................................................. 12

Theory of Operation ...................................................................... 14

Scratchpad and EEMEM Programming.................................. 14

Basic Operation ..........................................................................14

EEMEM Protection.................................................................... 15

Digital Input/Output Configuration........................................ 15

Serial Data Interface................................................................... 15

Daisy-Chain Operation ............................................................. 16

Terminal Voltage Operation Range.......................................... 16

Power-Up Sequence ................................................................... 16

Latched Digital Outputs............................................................ 16

.......................................................................................... 3

Programming Examples............................................................ 20

Flash/EEMEM Reliability.......................................................... 21

Applications..................................................................................... 22

Bipolar Operation from Dual Supplies.................................... 22

Gain Control Compensation.................................................... 22

High Voltage Operation............................................................. 22

DAC.............................................................................................. 22

Bipolar Programmable Gain Amplifier................................... 23

Programmable Low-Pass Filter ................................................ 23

Programmable State-Variable Filter......................................... 23

Programmable Oscillator .......................................................... 24

Programmable Voltage Source with Boosted Output............ 25

Programmable Current Source ................................................ 25

Programmable Bidirectional Current Source......................... 26

Resistance Scaling ...................................................................... 26

Doubling the Resolution........................................................... 27

Re s is t an c e To l er anc e, Dr if t, an d Te m pe ra t ur e Mi s ma t ch
Considerations

............................................................................ 27

Advanced Control Modes ......................................................... 18

RDAC Structure.......................................................................... 19

Programming the Variable Resistor ......................................... 19

REVISION HISTORY

7/04—Data Sheet changed from Rev. 0 to Rev. A

Format updated...................................................................Universal

Changes to Features, General Description, and Block Diagram .1

Changes to Specifications.................................................................3

Replaced Timing Diagrams..............................................................6

Changes to Absolute Maximum Ratings ........................................7

Changes to Pin Function Descriptions...........................................8

Replaced Figure 11 ...........................................................................9

Added Test Circuit (Figure 36) ......................................................13

Rev. A | Page 2 of 28

RDAC Circuit Simulation Model............................................. 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

Changes to Theory of Operation ..................................................14

Changes to Applications .................................................................22

Updated Outline Dimensions........................................................28

Changes to Ordering Guide...........................................................28

3/02—Revision 0: Initial Version

AD5233

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, AND 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS,
RHEOSTAT MODE

Resistor Differential Nonlinearity

2

R-DNL RWB, VA = NC, monotonic −0.5 ±0.1 +0.5 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = NC −0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance ∆RAB/R

AB

D = 0x3F −40 +20 %
Resistance Temperature Coefficient (∆RWB/RWB)/∆T × 106 600 ppm/°C
Wiper Resistance R

W

IW = 100 µA, code = half scale 15 100 Ω

DC CHARACTERISTICS,
POTENTIOMETER DIVIDER MODE

Resolution N 6 Bits
Differential Nonlinearity

3

DNL Monotonic −0.5 +0.1 +0.5 LSB
Integral Nonlinearity3 INL −0.5 +0.1 +0.5 LSB
Voltage Divider Temperature

(∆V

W/VW

)/∆T × 10

6

Code = half scale 15 ppm/°C

Coefficient
Full-Scale Error V
Zero-Scale Error V

WFSE

WZSE

Code = full scale −1.5 0 % FS
Code = zero scale 0 1.5 % FS

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance5 A, B C

4

V

A, B, W

A, B

V
f = 1 MHz, measured to GND,

SS

35 pF

Code = half scale

Capacitance5 W C

W

f = 1 MHz, measured to GND,

35 pF

code = half scale

Common-Mode Leakage Current

5, 6

I

CM

VW = VDD/2 0.015 1 µA

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Input Logic High V
Input Logic Low V
Input Logic High V

Input Logic Low V

Output Logic High (SDO, RDY) V

IH

IL

IH

IL

IH

IL

OH

With respect to GND, VDD = 5 V 2.4 V
With respect to GND, VDD = 5 V 0.8 V
With respect to GND, VDD = 3 V 2.1 V
With respect to GND, VDD = 3 V 0.6 V
With respect to GND,

= +2.5 V, VSS = −2.5 V

V

DD

With respect to GND,
V

= +2.5 V, VSS = −2.5 V

DD

R

= 2.2 kΩ to 5 V

PULL-UP

2.0 V

0.5 V

4.9 V

(see Figure 25)

Output Logic Low V

OL

IOL = 1.6 mA, V

LOGIC

= 5 V

0.4 V

(see Figure 25)

Input Current I

IL

VIN = 0 V or V

DD

±2.5 µA
Input Capacitance5 CIL 4 pF
Output Current5 I

, I

O1

O2

VDD = 5 V, VSS = 0 V, TA = 25°C,

50 mA

sourcing only

= 2.5 V, VSS = 0 V, TA = 25°C,

V

DD

7 mA

sourcing only

POWER SUPPLIES

Single-Supply Power Range V

DD

Dual-Supply Power Range VDD/V
Positive Supply Current I
Negative Supply Current I

DD

SS

SS

VSS = 0 V 2.7 5.5 V
±2.25 ±2.75 V
VIH = VDD or VIL = GND 3.5 10 µA
VIH = VDD or VIL = GND,

= +2.5 V, VSS = −2.5 V

V

DD

0.55 10 µA

1

V

Max Unit

V

DD

Rev. A | Page 3 of 28

AD5233

Parameter Symbol Conditions Min Typ

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current

7

I
Power Dissipation

8

Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −40 mA

SS

IDD (restore)

(restore) VDD = +2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

P

DISS

SS

Bandwidth BW

= VDD or VIL = GND,

V

IH

V

= 0, ISS ≈ 0

SS

= VDD or VIL = GND,

V

IH

= GND, ISS ≈ 0

V

SS

VIH = VDD or VIL = GND 0.018 0.05 mW
∆VDD = 5 V ± 10% 0.002 0.01 %/%

−3 dB, R

AB

= 10 kΩ/50 kΩ/

40 mA

0.3 3 9 mA

630/135/66 kHz

1

Max Unit

100 kΩ

Total Harmonic Distortion THD

W

VW Settling Time t

S

VA = 1 V rms, VB = 0 V, f = 1 kHz,

= 10 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

R

= 50 kΩ, 100 kΩ

AB

VA = VDD, VB = 0 V,

= 0.50% error band,

V

W

0.04 %

0.015 %

0.6/2.2/3.8 µs

code 0x000 to 0x200
for R

= 10 kΩ/50 kΩ/100 kΩ

AB

Resistor Noise Voltage e
Crosstalk (CW1/CW2) C

N_WB

T

RWB = 5 kΩ, f = 1 kHz 9
VA = VDD, VB = 0 V, measure VW

−1

nV/√

nV-s
with adjacent RDAC making
full-scale code change

Analog Crosstalk (CW1/CW2) C

TA

VDD = VA1 = +2.5 V,
V

= VB1 = −2.5 V,

SS

measure V

with VW2 = 5 V p-p

W1

−86/−73/

−68

dB

@ f = 10 kHz,
Code 1 = 0x20, Code 2 = 0x3F,
R

= 10 kΩ/50 kΩ/100 kΩ

AB

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. I
50 kΩ and I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output ADC. VA = VDD and VB = VSS. DNL specification limits of

−1 LSB minimum are guaranteed monotonic operating conditions (see F ).

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from Terminals B and W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see ). To minimize

power dissipation, a NOP instruction should be issued immediately after instruction 1 (0x1).

8

P

DISS

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

> 25 µA for the RAB = 100 kΩ version (see ). Figure 25

W

is calculated from (IDD × VDD) + (ISS × VSS).

igure 26

> 50 µA @ VDD = 2.7 V for the RAB = 10 kΩ version, IW > 50 µA for the RAB =

W

Figure 22

Hz

Rev. A | Page 4 of 28

AD5233

TIMING CHARACTERISTICS

VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Cycle Time (t

) t

CYC

CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width t4, t
Data Setup Time t
Data Hold Time t
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay
CLK to SDO Data Hold Time t
CS High Pulse Width

5

CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Read/Store to Nonvolatile EEMEM
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t

Preset Response Time to Wiper Setting t
Power-On EEMEM Restore Time t

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

7

8

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See the timing diagrams ( and ) for the location of the measured values. All input control voltages are specified with tFigure 2 Figure 3

and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

RDY pin low only for Commands 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_8 > 1 ms; CMD_9, 10 > 0.12 ms; CMD_2, 3 > 20 ms. Device operation at TA = −40°C and

< 3 V extends the save time to 35 ms.

V

DD

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at 25°C is 700,000 cycles.

8

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV

derates with junction temperature, as shown in in the section. Figure 45 Flash/EEMEM Reliability

2, 3

1

t

2

t

3

5

6

7

t

8

t

4

6

9

t

10

11

t

12

t

13

t

14

t

15

t

16

t

17

PRW

PRESP

EEMEM1

20 ns
10 ns
1 t

CYC

Clock level high or low 10 ns
From positive CLK transition 5 ns
From positive CLK transition 5 ns
40 ns

50 ns
RP = 2.2 kΩ, CL < 20 pF 50 ns
RP = 2.2 kΩ, CL < 20 pF 0 ns

4 t

10 ns

CYC

0 ns

0.1 0.15 ms
Applies to Instructions 0x2, 0x3, and 0x9 25 ms

10 ns
Not shown in timing diagram 50 ns
PR pulsed low to refresh wiper positions

70 µs

RAB = 10 kΩ 140 µs

100 kCycles
100 Years

= tF = 2.5 ns (10% to 90% of 3 V)

R

PULL-UP

, and CL.

= 3 V and VDD = 5 V.

DD

Rev. A | Page 5 of 28

AD5233

CS

CPHA = 1

t

12

t

t

CLK

CPOL = 1

HIGH OR

LOW

SDI

t

SDO

t

14

RDY

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICRO CONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

2

8

B16*

1

t

5

B15–MSB

B15–MSB

B15

t

4

t

7

t

6

B0–LSB

t

10

t

11

t

B0

B0–LSB

3

t

t

t

13

t

17

HIGH OR LOW

9

15

t

16

02794-A-002

Figure 2. CPHA = 1 Timing Diagram

CPHA = 1

CS

t

12

t

t

CLK

CPOL = 1

HIGH OR

LOW

SDI

t

SDO

t

14

RDY

*NOTE: EXTRA BIT THAT IS NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICRO CONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

2

8

B16*

1

t

5

B15–MSB

B15–MSB

B15

t

4

t

7

t

6

B0–LSB

t

10

t

11

Figure 3. CPHA = 0 Timing Diagram

t

B0

B0–LSB

t

t

17

13

HIGH OR LOW

t

16

02794-A-003

3

t

9

t

15

Rev. A | Page 6 of 28

AD5233

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameters Ratings

VDD to GND –0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to V

SS

7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
IA, IW, I

Pulsed

B

1

±20 mA

Continuous ±2 mA
Digital Inputs and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range

2

−40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C
Thermal Resistance Junction-to-Ambient θJA128°C/W
Thermal Resistance Junction-to-Case θ

JC

Package Power Dissipation (TJ max − TA)/θ

28°C/W

JA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 7 of 28

AD5233

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24

O2

23

RDY

22

CS

21

PR

20

WP

19

V

DD

18

A4

17

W4

16

B4

15

A3

14

W3

13

B3

02794-A-005

CLK

SDI
SDO
GND

V

W1

W2

O1

SS

A1

B1
A2

B2

1

2
3
4

AD5233

5

TOP VIEW

6

(Not to Scale)

7
8

9
10
11
12

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 O1 Nonvolatile Digital Output 1. Address O1 = 0x4, data bit position D0; defaults to Logic 1 initially.
2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions.

Commands 9 and 10 activate the SDO output for the readback function, delayed by 16 or 17 clock pulses,
depending on the clock polarity before and after the data-word (see Figure 2, Figure 3, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 16 or 17 clock pulses,
depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted-out SDI can be used for daisy­chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5 GND Ground Pin, Logic Ground Reference.
6 V

SS

Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink

40 mA for 25 ms when storing data to EEMEM.
7 A1 Terminal A of RDAC1.
8 W1 Wiper terminal of RDAC1, Address (RDAC1) = 0x0.
9 B1 Terminal B of RDAC1.
10 A2 Terminal A of RDAC2.
11 W2 Wiper terminal of RDAC2, Address (RDAC2) = 0x1.
12 B2 Terminal B of RDAC2.
13 B3 Terminal B of RDAC3.
14 W3 Wiper terminal of RDAC3, Address (RDAC3) = 0x2.
15 A3 Terminal A of RDAC3.
16 B4 Terminal B of RDAC4.
17 W4 Wiper terminal of RDAC4, Address (RDAC4) = 0x3.
18 A4 Terminal A of RDAC4.
19 V
20

DD

WP Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR strobe

Positive Power Supply Pin.

and Instructions 1 and 8, and refreshes the RDAC register from EEMEM. Execute a NOP instruction before

21

22

PR Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM

CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

23 RDY

returning to

register. Factory default loads midscale 32

the logic high transition. Tie

Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and

WP high. Tie WP to VDD, if not used.

until EEMEM is loaded with a new value by the user. PR is activated at

10

PR to VDD, if not used.

PR.

24 O2 Nonvolatile Digital Output 2. Address (O2) = 0x4, data bit position D1; defaults to Logic 1 initially.

Rev. A | Page 8 of 28

AD5233

TYPICAL PERFORMANCE CHARACTERISTICS

–0.05

INL ERROR (LSB)

–0.10

0.20

0.15

0.10

0.05

TA =+25°C
T

= –40°C

A

T

=+85°C

A

0

R-DNL (LSB)

0.20

0.15

0.10

0.05

–0.05

–0.10

TA =+25°C

=–40°C

T

A

=+85°C

T

A

VDD = 5V, VSS = 0V

0

–0.15

–0.20

01632 64

CODE (Decimal)

Figure 5. INL vs. Code, T

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

48

0.20

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0

16 32 64

Figure 6. DNL vs. Code, T

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA =+25°C
T
T

48

=–40°C

A

=+85°C

A

0.20

0.15

0.10

0.05

TA =+25°C
T

=–40°C

A

T

=+85°C

A

VDD = 5V, VSS = 0V

–0.15

–0.20

01632 64

02794-A-006

Figure 8. R-DNL vs. Code, T

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

48

02794-A-009

3000

2500

2000

1500

1000

500

RHEOSTAT MODE TEMPCO (ppm/°C)

0

0

02794-A-007

16 32 64

CODE (Decimal)

Figure 9. (∆R

WB/RWB

VDD = 5V, VSS = 0V

= –40°C TO +85°C

T

A

48

6

)/∆T × 10

02794-A-010

300

200

VDD = 5.5V, VSS = 0V
T

= –40°C TO +85°C

A

V

= 2V

A

V

= 0V

B

0

–0.05

R-INL (LSB)

–0.10

–0.15

–0.20

01632 64

CODE (Decimal)

Figure 7. R-INL vs. Code, T

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

48

02794-A-008

Rev. A | Page 9 of 28

100

POTENTIOMETER MODE TEMPCO (ppm/°C)

0

01632 64

CODE (Decimal)

Figure 10. (∆V

)/∆T × 106 vs. Code, R

W/VW

48

= 10 kΩ

AB

02794-A-011