Alliance Semiconductor Corporation AS7C33256PFS16A-133TQC, AS7C33256PFS16A-100TQI, AS7C33256PFS16A, AS7C33256PFS18A-150TQC, AS7C33256PFS18A-150TQI Datasheet

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Alliance Semiconductor Corporation AS7C33256PFS16A-133TQC, AS7C33256PFS16A-100TQI, AS7C33256PFS16A, AS7C33256PFS18A-150TQC, AS7C33256PFS18A-150TQI Datasheet

March 2001	AS7C33256PFS16A
	AS7C33256PFS18A

3.3V 256K × 16/18 pipeline burst synchronous SRAM

Features

• Organization: 262,144 words × 16 or 18 bits

• Pentium®* compatible architecture and timing

• Fast clock speeds to 166 MHz in LVTTL/LVCMOS

• Asynchronous output enable control

• Fast clock to data access: 3.5/3.8/4.0/5.0 ns

• Economical 100-pin TQFP package

• Fast OE access time: 3.5/3.8/4.0/5.0 ns

• Byte write enables

• Fully synchronous register-to-register operation

• Multiple chip enables for easy expansion

• “Flow-through” mode

• 3.3V core power supply

• Single-cycle deselect

• 2.5V or 3.3V I/O operation with separate VDDQ

• 30 mW typical standby power in power down mode - Dual-cycle deselect also available (AS7C33256PFD16A/ • NTD™* pipeline architecture available

AS7C33256PFD18A)

(AS7C33256NTD16A/AS7C33256NTD18A)

Logic block diagram

LBO

CLK

ADV

Burst logic

256K × 16/18

ADSC

ADSP

CLR

Memory

A[17:0]

array

Address

CLK

16/18

GWE	D	DQb	Q
BWb	Byte Write
	registers

BWE

CLK

DQa

Byte Write

registers

CLK

CE0

Enable

Input

CE1

Output

CE2

registers

CLK

Power

D EnableQ

delay

down

CLK

DATA [17:0]

DATA [15:0]

Pin arrangement

A6	A7	CE0	CE1	NC	NC	BWb	BWa	CE2	V		V CLK			GWE	BWE	OE	ADSC	ADSP	ADV	A8	A9
										DD		SS



100	99	98	97	96	95	94	93	92	91		90		89	88	87	86	85	84	83	82	81

NC	1		80	A17
NC	2		79	NC
NC	3		78	NC
VDDQ	4		77	VDDQ
VSSQ	5		76	VSSQ
NC	6		75	NC
NC	7		74	DQpa/NC
DQb	8		73	DQa
DQb	9		72	DQa
VSSQ	10		71	VSSQ
VDDQ	11		70	VDDQ
DQb	12		69	DQa
DQb	13		68	DQa
FT	14	TQFP 14 × 20mm	67	VSS
VDD	15		66	NC
NC	16		65	VDD
VSS	17		64	ZZ
DQb	18		63	DQa
DQb	19		62	DQa
VDDQ	20		61	VDDQ
VSSQ	21		60	VSSQ
DQb	22		59	DQa
DQb	23		58	DQa
DQpb/NC	24		57	NC
NC	25		56	NC
VSSQ	26		55	VSSQ
VDDQ	27		54	VDDQ
NC	28		53	NC
NC	29		52	NC
NC	30		51	NC

LBO

A10

A11

A12

A13

A14

A15

A16

Note: pins 24, 74 are NC for ×16.

Selection guide

	AS7C33256PFS16A	AS7C33256PFS16A	AS7C33256PFS16A	AS7C33256PFS16A
	–166	–150	–133	–100	Units

Minimum cycle time	6	6.7	7.5	10	ns

Maximum pipelined clock frequency	166	150	133	100	MHz

Maximum pipelined clock access time	3.5	3.8	4	5	ns

Maximum operating current	475	450	425	325	mA

Maximum standby current	130	110	100	90	mA

Maximum CMOS standby current (DC)	30	30	30	30	mA

*Pentium® is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.

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AS7C33256PFS16A

AS7C33256PFS18A

Functional description

The AS7C33256PFS16A and AS7C33256PFS18A are high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) devices organized as 262,144 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.

Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPC™*-based systems in computing, datacomm, instrumentation, and telecommunications systems.

Fast cycle times of 6/6.7/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.

Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes

are HIGH. Burst operation is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium® count

sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/ 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).

BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

•ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.

•WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).

•Master chip select CE0 blocks ADSP, but not ADSC.

The AS7C33256PFS16A and AS7C33256PFS18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging.

*PowerPC™ is a tradenark International Business Machines Corporation.

Capacitance

Parameter	Symbol	Signals	Test conditions	Max	Unit

Input capacitance	CIN	Address and control pins	VIN = 0V	5	pF
I/O capacitance	CI/O	I/O pins	VIN = VOUT = 0V	7	pF

Write enable truth table (per byte)


GWE	BWE	BWn	WEn
L	X	X	T

H	L	L	T

H	H	X	F*

H	L	H	F*

Key:

X = Don’t Care, L = Low, H = High, T=True, F=False * valid read

n = a,b

WE, WEn = internal write signal

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AS7C33256PFS16A

AS7C33256PFS18A

Signal descriptions

Signal

I/O

Properties

Description

CLK

CLOCK

Clock. All inputs except

ZZ,

are synchronous to this clock.

FT,

LBO

A0–A17

SYNC

Address. Sampled when all chip enables are active and

are asserted.

ADSC

ADSP

DQ[a,b]

I/O

SYNC

Data. Driven as output when the chip is enabled and

is active.

Master chip enable. Sampled on clock edges when

is active. When

ADSP

ADSC

CE0

SYNC

CE0

is inactive,

ADSP

is blocked. Refer to the Synchronous Truth Table for more

information.

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

CE1, CE2

SYNC

clock edges when ADSC is active or when CE0 and ADSP are active.

Address strobe (processor). Asserted LOW to load a new address or to enter

ADSP

SYNC

standby mode.

Address strobe (controller). Asserted LOW to load a new address or to enter

ADSC

SYNC

standby mode.

SYNC

Burst advance. Asserted LOW to continue burst read/write.

ADV

Global write enable. Asserted LOW to write all 16/18 bits. When HIGH,

and

BWE

GWE

SYNC

BW[a,b] control write enable.

Byte write enable. Asserted LOW with

= HIGH to enable effect of

GWE

BW[a,b]

BWE

SYNC

inputs.

Write enables. Used to control write of individual bytes when GWE = HIGH and

SYNC

= LOW. If any of

is active with

= HIGH and

= LOW the

BW[a,b]

BWE

BW[a,b]

GWE

BWE

cycle is a write cycle. If all

are inactive, the cycle is a read cycle.

BW[a,b]

Asynchronous output enable. I/O pins are driven when

is active and the chip is

ASYNC

in read mode.

STATIC default =

Count mode. When driven HIGH, count sequence follows Intel XOR convention.

LBO

When driven LOW, count sequence follows linear convention. This signal is

HIGH

internally pulled HIGH.

Flow-through mode.When LOW, enables single register flow-through mode.

STATIC

Connect to VDD if unused or for pipelined operation.

ASYNC

Sleep. Places device in low power mode; data is retained. Connect to GND if

unused.

Absolute maximum ratings

Parameter	Symbol	Min	Max	Unit

Power supply voltage relative to GND	VDD, VDDQ	–0.5	+4.6	V
Input voltage relative to GND (input pins)	VIN	–0.5	VDD + 0.5	V
Input voltage relative to GND (I/O pins)	VIN	–0.5	VDDQ + 0.5	V
Power dissipation	PD	–	1.8	W
DC output current	IOUT	–	50	mA
Storage temperature (plastic)	Tstg	–65	+150	° C
Temperature under bias	Tbias	–65	+135	° C

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.

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AS7C33256PFS16A

AS7C33256PFS18A

Synchronous truth table

CE0

CE1

CE2

ADSP

ADSC

ADV

WEn1

Address accessed

CLK

Operation

L to H

Deselect

Hi−

L to H

Deselect

Hi−

L to H

Deselect

Hi−

L to H

Deselect

Hi−

L to H

Deselect

Hi−

External

L to H

Begin read

Hi− Z2

External

L to H

Begin read

Hi−

External

L to H

Begin read

Hi− Z2

External

L to H

Begin read

Hi−

L to H

Cont. read

L to H

Cont. read

Hi−

Current

L to H

Suspend read

Current

L to H

Suspend read

Hi−

L to H

Cont. read

L to H

Cont. read

Hi−

Current

L to H

Suspend read

Current

L to H

Suspend read

Hi−

External

L to H

Begin write

L to H

Cont. write

L to H

Cont. write

Current

L to H

Suspend write

Current

L to H

Suspend write

Key: X = Don’t Care, L = Low, H = High.

1See “Write enable truth table” on page 2 for more information. 2Q in flow through mode

3For write operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold

time.

Recommended operating conditions

Parameter		Symbol	Min	Nominal	Max	Unit

Supply voltage		VDD	3.135	3.3	3.6	V
		VSS	0.0	0.0	0.0

3.3V I/O supply		VDDQ	3.135	3.3	3.6	V
voltage		VSSQ	0.0	0.0	0.0

2.5V I/O supply		VDDQ	2.35	2.5	2.9	V
voltage
		VSSQ	0.0	0.0	0.0

	Address and	VIH	2.0	–	VDD + 0.3	V
Input voltages†	control pins	VIL	–0.5*	–	0.8

	I/O pins	VIH	2.0	–	VDDQ + 0.3	V

		VIL	–0.5*	–	0.8

Ambient operating temperature		TA	0	–	70	° C

* VIL min = –2.0V for pulse width less than 0.2 × tRC.

† Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.

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