Alliance Semiconductor Corporation AS7C3256-20TI, AS7C3256-20TC, AS7C3256-20PC, AS7C3256-20JI, AS7C3256-20JC Datasheet
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January 2001 |
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AS7C256 |
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Advance Information |
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AS7C3256 |
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® |
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5V/3.3V 32K X 8 CMOS SRAM (Common I/O) |
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Features |
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• AS7C256 (5V version) |
- 7.2 mW (AS7C3256) / max CMOS I/O |
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• AS7C3256 (3.3V version) |
• 2.0V data retention |
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• Industrial and commercial temperature |
• Easy memory expansion with |
CE |
and |
OE |
inputs |
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• Organization: 262,144 words × 16 bits |
• TTL-compatible, three-state I/O |
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• High speed |
• 28-pin JEDEC standard packages |
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- 12/15/20 ns address access time |
- 300 mil PDIP |
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- 5/6/7/9 ns output enable access time |
- 300 mil SOJ |
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• Very low power consumption: ACTIVE |
- 8 × 13.4 TSOP |
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- 660mW (AS7C256) / max @ 12 ns |
• ESD protection ≥ 2000 volts |
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- 216mW (AS7C3256) / max @ 12 ns |
• Latch-up current ≥ 200 mA |
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•Very low power consumption: STANDBY
- 22 mW (AS7C256) / max CMOS I/O
Logic block diagram |
Pin arrangement |
VCC
GND 
A0
A1
A2
A3
A4
A5
A6
A14
Row decoder
Input buffer |
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I/O7 |
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256 X 128 X 8 |
amp |
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Array |
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Sense |
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(262,144) |
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I/O0 |
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Column decoder |
WE |
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Control |
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OE |
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circuit |
CE
A A A A A A A 7 8 9 10 11 12 13
28-pin TSOP I (8×13.4) |
28-pin DIP, SOJ (300 mil) |
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OE |
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1 |
(22) |
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(21) |
28 |
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A10 |
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A11 |
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2 |
(23) |
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(20) |
27 |
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CE |
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A9 |
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3 |
(24) |
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(19) |
26 |
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I/O7 |
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A8 |
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4 |
(25) |
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(18) |
25 |
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I/O6 |
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A13 |
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5 |
(26) |
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(17) |
24 |
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I/O5 |
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WE |
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6 |
(27) |
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(16) |
23 |
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I/O4 |
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VCC |
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7 |
(28) |
AS7C256 |
(15) |
22 |
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I/O3 |
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A14 |
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8 |
(1) |
AS7C3256 |
(14) |
21 |
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GND |
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A12 |
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9 |
(2) |
(13) |
20 |
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I/O2 |
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A7 |
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10 |
(3) |
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(12) |
19 |
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I/O1 |
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A6 |
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11 |
(4) |
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(11) |
18 |
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I/O0 |
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A5 |
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12 |
(5) |
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(10) |
17 |
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A0 |
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A4 |
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13 |
(6) |
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(9) |
16 |
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A1 |
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A3 |
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14 |
(7) |
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(8) |
15 |
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A2 |
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Note: This part is compatible with both pin numbering conventions used by various manufacturers.
A14 |
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1 |
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A12 |
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2 |
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A7 |
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3 |
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A6 |
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4 |
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A5 |
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5 |
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A4 |
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6 |
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A3 |
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7 |
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A2 |
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8 |
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A1 |
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9 |
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A0 |
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10 |
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I/O0 |
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11 |
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I/O1 |
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12 |
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I/O2 |
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13 |
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GND |
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14 |
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AS7C256 |
AS7C3256 |
28 
VCC
27 
WE
26 
A13
25 
A8
24 
A9
23 
A11
22 
OE
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A10
20 
CE
19 
I/O7
18 
I/O6
17 
I/O5
16 
I/O4
15 
I/O3
Selection guide
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AS7C256-10 |
AS7C256-12 |
AS7C256-15 |
AS7C256-20 |
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AS7C3256-10 |
AS7C3256-12 |
AS7C3256-15 |
AS7C3256-20 |
Unit |
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Maximum address access time |
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10 |
12 |
15 |
20 |
ns |
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Maximum output enable access time |
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5 |
6 |
7 |
ns |
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Maximum operating current |
AS7C256 |
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120 |
115 |
110 |
mA |
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AS7C3256 |
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60 |
55 |
50 |
mA |
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Maximum CMOS standby |
AS7C256 |
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4 |
4 |
4 |
mA |
current |
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AS7C3256 |
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2 |
2 |
2 |
mA |
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1/10/2001 |
Alliance Semiconductor |
P. 1 of 9 |
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Copyright © Alliance Semiconductor. All rights reserved.
AS7C256
AS7C3256
®
Functional description
The AS7C(3)256 is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes ≤ 3.6 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C256 offer 2.0V data retention.
Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 5/6/7/9 ns are
ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C(3)256A is packaged in high volume industry standard packages.
Absolute maximum ratings
Parameter |
Device |
Symbol |
Min |
Max |
Unit |
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Voltage on VCC relative to GND |
AS7C256 |
Vt1 |
–0.5 |
+7.0 |
V |
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AS7C3256 |
Vt1 |
–0.5 |
+5.0 |
V |
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Voltage on any pin relative to GND |
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Vt2 |
–0.5 |
VCC + 0.5 |
V |
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Power dissipation |
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PD |
– |
1.0 |
W |
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Storage temperature (plastic) |
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Tstg |
–65 |
+150 |
oC |
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Ambient temperature with VCC applied |
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Tbias |
–55 |
+125 |
oC |
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DC current into outputs (low) |
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IOUT |
– |
20 |
mA |
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
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CE |
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WE |
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OE |
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Data |
Mode |
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H |
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X |
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X |
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High Z |
Standby (ISB, ISB1) |
L |
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H |
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H |
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High Z |
Output disable (ICC) |
L |
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H |
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L |
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DOUT |
Read (ICC) |
L |
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L |
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X |
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DIN |
Write (ICC) |
Key: X = Don’t care, L = Low, H = High
1/10/2001 |
Alliance Semiconductor |
P. 2 of 9 |
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AS7C256
AS7C3256
®
Recommended operating conditions
Parameter |
Device |
Symbol |
Min |
Typical |
Max |
Unit |
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Supply voltage |
AS7C256 |
VCC |
4.5 |
5.0 |
5.5 |
V |
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AS7C3256 |
VCC |
3.0 |
3.3 |
3.6 |
V |
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AS7C256 |
VIH |
2.2 |
– |
VCC+0.5 |
V |
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Input voltage |
AS7C3256 |
VIH |
2.0 |
– |
VCC+0.5 |
V |
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— |
VIL* |
-0.5* |
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0.8 |
V |
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commercial |
T |
0 |
– |
70 |
oC |
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Ambient operating temperature |
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A |
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industrial |
T |
–40 |
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85 |
oC |
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A |
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* VIL min = –2.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
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-10 |
-12 |
-15 |
-20 |
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Parameter |
Sym |
Test conditions |
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Device |
Min |
Max |
Min |
Max |
Min |
Max |
Min |
Max |
Unit |
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Input leakage |
|ILI| |
VCC = Max, |
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1 |
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1 |
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1 |
µA |
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current |
Vin = GND to VCC |
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Output leakage |
|ILO| |
VCC = Max, |
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1 |
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1 |
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1 |
µA |
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current |
VOUT = GND to VCC |
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Operating |
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AS7C256 |
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– |
120 |
– |
115 |
– |
110 |
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VCC = Max, CE ≤ |
VIL |
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power supply |
ICC |
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mA |
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f = fMax, IOUT = 0mA |
AS7C3256 |
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– |
60 |
– |
55 |
– |
50 |
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current |
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VCC = Max, |
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VIL |
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AS7C256 |
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– |
40 |
– |
35 |
– |
30 |
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ISB |
CE |
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mA |
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Standby power |
f = fMax, IOUT = 0mA |
AS7C3256 |
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– |
20 |
– |
20 |
– |
20 |
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V = Max, |
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V |
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–0.2V |
AS7C256 |
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– |
4.0 |
– |
4.0 |
– |
4.0 |
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supply current |
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CE |
CC |
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ISB1 |
CC |
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mA |
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VIN < GND + 0.2V or |
AS7C3256 |
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– |
2.0 |
– |
2.0 |
– |
2.0 |
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VIN > VCC–0.2V, f = 0 |
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Output voltage |
VOL |
IOL = 8 mA, VCC = Min |
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0.4 |
– |
0.4 |
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0.4 |
V |
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VOH |
IOH = –4 mA, VCC = Min |
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2.4 |
– |
2.4 |
– |
2.4 |
– |
V |
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Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
Parameter |
Symbol |
Signals |
Test conditions |
Max |
Unit |
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Input capacitance |
CIN |
A, |
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Vin = 0V |
5 |
pF |
CE, |
WE, |
OE |
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I/O capacitance |
CI/O |
I/O |
Vin = Vout = 0V |
7 |
pF |
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1/10/2001 |
Alliance Semiconductor |
P. 3 of 9 |
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