Alliance Semiconductor Corporation AS4LC4M4E1-60TI, AS4LC4M4E1-60TC, AS4LC4M4E1-60JI, AS4LC4M4E1-60JC, AS4LC4M4E1-50TI Datasheet

March 2001	AS4LC4M4E0
	AS4LC4M4E1

®

4Mx4 CMOS DRAM (EDO) Family

Features

•Organization: 4,194,304 words × 4 bits

•High speed

-50/60 ns RAS access time

-25/30 ns column address access time

-12/15 ns CAS access time

•Low power consumption

-Active: 500 mW max

-Standby: 3.6 mW max, CMOS I/O

•Extended data out

•Refresh

-4096 refresh cycles, 64 ms refresh interval for AS4LC4M4E0

-2048 refresh cycles, 32 ms refresh interval for AS4LC4M4E1

-RAS-only or CAS-before-RAS refresh or self-refresh

•TTL-compatible, three-state I/O

•JEDEC standard package

-300 mil, 24/26-pin SOJ

•3V power supply

•Industrial and commercial temperature available

																											Pin designation
Pin arrangement
						SOJ													TSOP												Pin(s)	Description
	VCC								GND					VCC										GND					A0 to A11			Address inputs
					1		24											1		24
	I/O0				2		23		I/O3					I/O0				2		23				I/O3
																													RAS			Row address strobe
	I/O1				3		22		I/O2					I/O1				3		22				I/O2
	WE				4	AS4LC4M4E0	21			CAS				WE				4	AS4LC4M4E0	21				CAS
																													CAS			Column address strobe
	RAS				5		20		OE				RAS					5		20				OE
*NC/A11					6		19			A9			*NC/A11					6		19				A9								Write enable
																													WE
	A10				7		18			A8				A10				7		18				A8					I/O0 to I/O3			Input/output
	A0				8		17			A7				A0				8		17				A7
																													OE			Output enable
	A1				9		16			A6				A1				9		16				A6
	A2				10		15			A5				A2				10		15				A5					VCC			Power
	A3				11		14			A4				A3				11		14				A4
	VCC				12		13			GND				VCC				12		13				GND					GND			Ground

* NC on 2K refresh version; A11 on 4K refresh version

Selection guide

Symbol

AS4LC4M4E0/E1-50

AS4LC4M4E0/E1-60

Unit

Maximum

access time

tRAC

50

60

ns

RAS

Maximum column address access time

tCAA

25

30

ns

Maximum

access time

tCAC

12

15

ns

CAS

Maximum output enable

access time

tOEA

13

15

ns

(OE)

Minimum read or write cycle time

tRC

80

100

ns

Minimum fast page mode cycle time

tPC

25

30

ns

Maximum operating current

ICC1

120

110

mA

Maximum CMOS standby current

ICC5

1.0

1.0

mA

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AS4LC4M4E0

AS4LC4M4E1

®

Functional description

The AS4LC4M4E0 and AS4LC4M4E1 are high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in PC, workstation, router and switch applications.

These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion.

Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS going high.

Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:

•RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.

•Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data.

•CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care).

•Normal read or write cycles refresh the row being accessed.

•Self-refresh cycles

Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:

•RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.

•Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data.

•CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care).

•Normal read or write cycles refresh the row being accessed.

•Self-refresh cycles

The AS4LC4M4E0 and AS4LC4M4E1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The AS4LC4M4E0 and AS4LC4M4E1 operate with a single power supply of 3V ± 0.3V. All provide TTL compatible inputs and outputs.

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®

Logic block diagram for 4K refresh

VCC			Refresh controller
GND

RAS	RAS clock	A0
	generator
		A1
		A2	Addressbuffers	decoderRow
		A8
		A3
	CAS clock	A4
CAS	generator	A6
		A7

									A9
						WE	clock		A10
						generator			A11
WE

AS4LC4M4E0

AS4LC4M4E1

Column decoder

Data

I/O

Sense amp

buffers

I/O0 to I/O3

4096 × 1024 × 4

OE

Array

(16,777,216)

Logic block diagram for 2K refresh

VCC			Refresh controller
GND

RAS	RAS clock	A0
	generator
		A1
		A2	Addressbuffers	decoderRow
		A8
		A3
	CAS clock	A4
CAS	generator	A6
		A7
		A9
	WE clock	A10
WE	generator

Column decoder

Data

I/O

Sense amp

buffers

I/O0 to I/O3

2048 × 2048 × 4

OE

Array

(16,777,216)

Substrate bias

generator

Recommended operating conditions

Parameter			Symbol	Min	Nominal	Max	Unit
Supply voltage			VCC	3.0	3.3	3.6	V
			GND	0.0	0.0	0.0	V
Input voltage			VIH	2.0	–	VCC+0.5V	V
			VIL	–0.5†	–	0.8	V
Ambient operating temperature		Commercial	TA	0	–	70	°C
		Industrial		-40	–	85

†VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.

Absolute maximum ratings

Parameter	Symbol	Min	Max	Unit
Input voltage	Vin	-1.0	4.6	V
Input voltage (DQs)	VDQ	-1.0	4.6	V
Power supply voltage	VCC	-1.0	4.6	V
Storage temperature (plastic)	TSTG	-55	+150	°C
Soldering temperature × time	TSOLDER	–	260 × 10	oC × sec

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AS4LC4M4E0

AS4LC4M4E1

®

Parameter	Symbol	Min	Max	Unit
Power dissipation	PD	–	0.5	W
Short circuit output current	Iout	–	50	mA

DC electrical characteristics

-50

-60

Parameter

Symbol

Test conditions

Min

Max

Min

Max

Unit

Notes

Input leakage current

IIL

0V ≤ Vin ≤ +VCC (max)

-5

+5

-5

+5

µA

Pins not under test = 0V

Output leakage current

IOL

DOUT disabled, 0V ≤ Vout ≤ +VCC (max)

-5

+5

-5

+5

µA

Operating power

ICC1

CAS, Address cycling; tRC = min

–

120

–

110

mA

1,2

supply current

TTL standby power

ICC2

RAS = CAS ≥

VIH

–

2.0

–

2.0

mA

supply current

Average power supply

RAS cycling, CAS ≥ VIH,

current, RAS refresh

ICC3

–

120

–

110

mA

1

tRC = min of RAS low after CAS low.

mode or CBR

EDO page mode average

= VIL,

ICC4

RAS

CAS,

–

90

–

80

mA

1, 2

power supply current

address cycling: tHPC = min

CMOS standby power

ICC5

RAS = CAS = VCC - 0.2V

–

1.0

–

1.0

mA

supply current

Output voltage

VOH

IOUT = -2.0 mA

2.4

–

2.4

–

V

VOL

IOUT = 2.0 mA

–

0.4

–

0.4

V

before

refresh

CAS

RAS

ICC6

RAS, CAS cycling, tRC = min

–

120

–

110

mA

current

=

≤

0.2V,

RAS

CAS

=

≥

VCC - 0.2V,

Self refresh current

ICC7

WE

OE

–

0.6

–

0.6

mA

all other inputs at 0.2V or

VCC - 0.2V

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AS4LC4M4E0

AS4LC4M4E1

®

AC parameters common to all waveforms

-50

-60

Symbol

Parameter

Min

Max

Min

Max

Unit

Notes

tRC

Random read or write cycle time

80

–

100

–

ns

tRP

precharge time

30

–

40

–

ns

RAS

tRAS

pulse width

50

10K

60

10K

ns

RAS

tCAS

pulse width

8

10K

10

10K

ns

CAS

tRCD

to

delay time

15

35

15

43

ns

6

RAS

CAS

tRAD

to column address delay time

12

25

12

30

ns

7

RAS

tRSH

to

hold time

10

–

10

–

ns

CAS

RAS

tCSH

to

hold time

40

–

50

–

ns

RAS

CAS

tCRP

to

precharge time

5

–

5

–

ns

CAS

RAS

tASR

Row address setup time

0

–

0

–

ns

tRAH

Row address hold time

8

–

10

–

ns

tT

Transition time (rise and fall)

1

50

1

50

ns

4,5

tREF

Refresh period

–

64

–

64

ms

3

tCP

precharge time

8

–

10

–

ns

CAS

tRAL

Column address to

lead time

25

–

30

–

ns

RAS

tASC

Column address setup time

0

–

0

–

ns

tCAH

Column address hold time

8

10

–

ns

Read cycle

-50

-60

Symbol

Parameter

Min

Max

Min

Max

Unit

Notes

tRAC

Access time from

–

50

–

60

ns

6

RAS

tCAC

Access time from

–

12

–

15

ns

6,13

CAS

tAA

Access time from address

–

25

–

30

ns

7,13

tRCS

Read command setup time

0

–

0

–

ns

tRCH

Read command hold time to

0

–

0

–

ns

9

CAS

tRRH

Read command hold time to

0

–

0

–

ns

9

RAS

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