Alliance Semiconductor Corporation AS7C31026-20TI, AS7C31026-20TC, AS7C31026-20JC, AS7C31026-20BC, AS7C31026-15TI Datasheet

March 2001	AS7C1026
	AS7C31026

®

5V/3.3V 64K×16 CMOS SRAM

Features

•AS7C1026 (5V version)

•AS7C31026 (3.3V version)

•Industrial and commercial versions

•Organization: 65,536 words x 16 bits

•Center power and ground pins for low noise

•High speed

-12/15/20 ns address access time

-6,7,8 ns output enable access time

•Low power consumption: ACTIVE

-880 mW (AS7C1026) / max @ 12 ns

-396 mW (AS7C31026) / max @ 12 ns

•Low power consumption: STANDBY

-28 mW (AS7C1026) / max CMOS I/O

-18 mW (AS7C31026) / max CMOS I/O

•2.0V data retention

•Easy memory expansion with CE, OE inputs

•TTL-compatible, three-state I/O

•JEDEC standard packaging

-44-pin 400 mil SOJ

-44-pin 400 mil TSOP II

-48-ball 6 mm × 8 mm CSP mBGA

•ESD protection ≥ 2000 volts

•Latch-up current ≥ 200 mA

Logic block diagram

A0

VCC

A1

decoder

A2

Array

64K × 16

GND

A3

A4

Row

A5

A6

A7

I/O0–I/O7

I/O

Control circuit

I/O8–I/O15

buffer

WE	Column decoder
A8	A9	A10	A11	A12	A13	A14	A15
UB
OE
LB
CE

Pin arrangement

44-Pin SOJ, TSOP II (400 mil)

A4

1

44

A5

A3

2

43

A6

A2

3

42

A7

48-CSP mini Ball-Grid-Array Package

A1

4

41

OE

1

2

3

4

5

6

A0

5

40

UB

CE

6

39

LB

I/O0

7

38

I/O15

A

LB

OE

A0

A1

A2

NC

I/O1

8

37

I/O14

B

I/O8

UB

A3

A4

CE

I/O0

I/O2

9

36

I/O13

I/O3

10

AS7C1026

AS7C31026

35

I/O12

C

I/O9

I/O10

A5

A6

I/O1

I/O2

VCC

11

34

GND

GND

12

33

VCC

D

VSS

I/O11

NC

A7

I/O3

VDD

I/O4

13

32

I/O11

I/O5

14

31

I/O10

E

VDD

I/O12

NC

NC

I/O4

VSS

I/O6

15

30

I/O9

I/O7

16

29

I/O8

F

I/O14

I/O13

A14

A15

I/O5

I/O6

WE

17

28

NC

A15

18

27

A8

G

I/O15

NC

A12

A13

I/O7

WE

A14

19

26

A9

A13

20

25

A10

H

NC

A8

A9

A10

A11

NC

A12

21

24

A11

NC

22

23

NC

Selection guide

			AS7C1026-12	AS7C1026-15	AS7C1026-20
			AS7C31026-12	AS7C31026-15	AS7C31026-20	Unit
	Maximum address access time		12	15	20	ns
	Maximum output enable access time		6	8	10	ns
	Maximum operating current	AS7C1026	160	150	140	mA
		AS7C31026	110	100	90	mA
	Maximum CMOS standby current	AS7C1026	10	10	15	mA
		AS7C31026	10	10	15	mA

Shaded areas indicate preliminary information.

3/23/01; v.1.0 Alliance Semiconductor P. 1 of 10

Copyright © Alliance Semiconductor. All rights reserved.

AS7C1026

AS7C31026

®

Functional description

The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired.

Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high-performance applications.

When CE is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in CMOS standby mode. The devices also offer 2.0V data retention.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply (AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm × 6 mm.

Absolute maximum ratings

	Parameter		Symbol	Min	Max	Unit
	Voltage on VCC relative to GND	AS7C1026	Vt1	–0.50	+7.0	V
		AS7C31026	Vt1	–0.50	+5.0	V
	Voltage on any pin relative to GND		Vt2	–0.50	VCC +0.50	V
	Power dissipation		PD	–	1.0	W
	Storage temperature (plastic)		Tstg	–65	+150	° C
	Ambient temperature with VCC applied		Tbias	–55	+125	° C
	DC current into outputs (low)		IOUT	–	20	mA

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Truth table

CE

WE

OE

LB

UB

I/O0–I/O7

I/O8–I/O15

Mode

H

X

X

X

X

High Z

High Z

Standby (ISB), ISBI)

L

H

L

L

H

DOUT

High Z

Read I/O0–I/O7 (ICC)

L

H

L

H

L

High Z

DOUT

Read I/O8–I/O15 (ICC)

L

H

L

L

L

DOUT

DOUT

Read I/O0–I/O15 (ICC)

L

L

X

L

L

DIN

DIN

Write I/O0–I/O15 (ICC)

L

L

X

L

H

DIN

High Z

Write I/O0–I/O7 (ICC)

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AS7C1026

AS7C31026

®

CE

WE

OE

LB

UB

I/O0–I/O7

I/O8–I/O15

Mode

L

L

X

H

L

High Z

DIN

Write I/O8–I/O15 (ICC)

L

H

H

X

X

High Z

High Z

Output disable (ICC)

L

X

X

H

H

Key: H = High, L = Low, X = don’t care.

Recommended operating conditions

Parameter		Device	Symbol	Min	Typ	Max	Unit
		AS7C1026	VCC	4.5	5.0	5.5	V
Supply voltage		AS7C31026 (–10)	VCC	3.15	3.3	3.6	V
		AS7C31026 (12/15/20)	VCC	3.0	3.3	3.6	V
		AS7C1026	VIH	2.2	–	VCC + 0.5	V
Input voltage		AS7C31026	VIH	2.0	–	VCC + 0.5	V
			VIL	–0.5†	–	0.8	V
Ambient operating temperature	commercial		TA	0	–	70	°C
	industrial		TA	–40	–	85	°C

† VIL min = –3.0V for pulse width less than tRC/2.

DC operating characteristics (over the operating range)1

-12

-15

-20

Parameter

Sym

Test conditions

Device

Min

Max

Min

Max

Min

Max

Unit

Input leakage

| ILI |

VCC = Max

–

1

–

1

–

1

µA

current

VIN = GND to VCC

Output leakage

| ILO |

VCC

= Max

CE = VIH,

–

1

–

1

–

1

µA

current

VOUT = GND to VCC

VCC = Max,

≤ VIL

AS7C1026

–

160

–

150

–

140

mA

Operating power

ICC

CE

supply current

outputs open,

AS7C31026

–

110

–

100

–

90

mA

f = fMax = 1/tRC

VCC = Max,

≤ VIL,

AS7C1026

–

50

–

50

–

50

CE

Standby

ISB

outputs open,

mA

AS7C31026

–

35

–

35

–

35

f = fMax = 1/tRC

power supply

VCC = Max,

≥ VCC–0.2V,

AS7C1026

–

10

–

10

–

15

current

CE

ISB1

VIN ≤

GND + 0.2V or

mA

AS7C31026

–

10

–

10

–

15

VIN ≥

VCC–0.2V, f = 0

Output

VOL

IOL = 8 mA, VCC = Min

–

0.4

–

0.4

–

0.4

V

voltage

VOH

IOH = –4 mA, VCC = Min

2.4

–

2.4

–

2.4

–

V

Shaded areas indicate preliminary information.

Capacitance (f = 1MHz, T

= 25 ° C, V = NOMINAL)2

a

CC

Parameter

Symbol

Signals

Test conditions

Max

Unit

Input capacitance

CIN

A,

VIN = 0V

5

pF

CE,

WE,

OE,

LB,

UB

I/O capacitance

CI/O

I/O

VIN = VOUT = 0V

7

pF

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