Loading...Alliance Semiconductor Corporation AS7C3256A-20TC, AS7C3256A-20JC, AS7C3256A-15TI, AS7C3256A-15TC, AS7C3256A-15JI Datasheet
...
March 2001 |
|
|
AS7C256A |
|
||
Advance Information |
|
|
AS7C3256A |
|
||
|
® |
|
|
|
|
|
5V/3.3V 32K X 8 CMOS SRAM (Common I/O) |
|
|||||
|
|
|
|
|
|
|
Features |
• Very low power consumption: STANDBY |
|
||||
• AS7C256A (5V version) |
- 11 mW (AS7C256A) / max CMOS I/O |
|
||||
• AS7C3256A (3.3V version) |
- 3.6 mW (AS7C3256A) / max CMOS I/O |
|
||||
• Industrial and commercial temperature |
• Latest 6T 0.25u CMOS technology |
|
||||
• 2.0V data retention |
|
|||||
• Organization: 32,768 words × 8 bits |
|
|||||
• Easy memory expansion with |
|
and |
|
inputs |
|
|
• High speed |
CE |
OE |
|
|||
• TTL-compatible, three-state I/O |
|
|||||
- 10/12/15/20 ns address access time |
|
|||||
- 3/3/4/5 ns output enable access time |
• 28-pin JEDEC standard packages |
|
||||
• Very low power consumption: ACTIVE |
- 300 mil SOJ |
|
||||
- 495mW (AS7C256A) / max @ 10 ns |
- 8 × 13.4 TSOP |
|
||||
- 216mW (AS7C3256A) / max @ 10 ns |
• ESD protection ≥ 2000 volts |
|
||||
• Latch-up current ≥ 200 mA
Logic block diagram |
|
|
|
|
|||
VCC |
|
|
|
|
|
|
|
GND |
|
|
|
|
|
|
|
|
|
|
Input buffer |
|
|
||
A0 |
|
|
|
|
|
|
|
A1 |
decoderRow |
|
(262,144) |
|
Senseamp |
||
A5 |
|
|
|||||
A2 |
|
|
256 X 128 X 8 |
|
|||
A3 |
|
|
|
Array |
|
|
|
A4 |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
A6 |
|
|
|
|
|
|
|
A14 |
|
|
|
|
|
|
|
|
|
Column decoder |
Control |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
circuit |
|
A |
A |
A |
A |
A |
A |
A |
|
7 |
8 |
9 |
10 |
11 |
12 |
13 |
Pin arrangement
28-pin TSOP I (8×13.4) |
28-pin SOJ (300 mil) |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OE |
|
1 |
(22) |
|
(21) |
28 |
|
A10 |
|
|
A11 |
|
2 |
(23) |
|
(20) |
27 |
|
CE |
||
|
|
A9 |
|
3 |
(24) |
|
(19) |
26 |
|
I/O7 |
|
|
|
A8 |
|
4 |
(25) |
|
(18) |
25 |
|
I/O6 |
|
|
A13 |
|
5 |
(26) |
|
(17) |
24 |
|
I/O5 |
||
I/O7 |
WE |
|
6 |
(27) |
|
(16) |
23 |
|
I/O4 |
||
VCC |
|
7 |
(28) |
AS7C256A |
(15) |
22 |
|
I/O3 |
|||
|
|
|
|||||||||
|
A14 |
|
8 |
(1) |
AS7C3256A |
(14) |
21 |
|
GND |
||
|
A12 |
|
9 |
(2) |
(13) |
20 |
|
I/O2 |
|||
|
|
A7 |
|
10 |
(3) |
|
(12) |
19 |
|
I/O1 |
|
|
|
A6 |
|
11 |
(4) |
|
(11) |
18 |
|
I/O0 |
|
|
|
A5 |
|
12 |
(5) |
|
(10) |
17 |
|
A0 |
|
|
|
A4 |
|
13 |
(6) |
|
(9) |
16 |
|
A1 |
|
|
|
A3 |
|
14 |
(7) |
|
(8) |
15 |
|
A2 |
|
|
|
|
|
||||||||
I/O0 Note: This part is compatible with both pin numbering conventions used by various manufacturers.
WE
OE
CE
A14 |
|
1 |
|
||
A12 |
|
2 |
|
||
A7 |
|
3 |
|
||
A6 |
|
4 |
|
||
A5 |
|
5 |
|
||
A4 |
|
6 |
|
||
A3 |
|
7 |
|
||
A2 |
|
8 |
|
||
A1 |
|
9 |
|
||
A0 |
|
10 |
|
||
I/O0 |
|
11 |
|
||
I/O1 |
|
12 |
|
||
I/O2 |
|
13 |
|
||
GND |
|
14 |
|
||
|
|
|
AS7C256A |
AS7C3256A |
28 
VCC
27 
WE
26 
A13
25 
A8
24 
A9
23 
A11
22 
OE
21 
A10
20 
CE
19 
I/O7
18 
I/O6
17 
I/O5
16 
I/O4
15 
I/O3
Selection guide
|
|
AS7C256A-10 |
AS7C256A-12 |
AS7C256A-15 |
AS7C256A-20 |
|
|
|
|
AS7C3256A-10 |
AS7C3256A-12 |
AS7C3256A-15 |
AS7C3256A-20 |
Unit |
|
|
|
|
|
|
|
|
|
Maximum address access time |
|
10 |
12 |
15 |
20 |
ns |
|
|
|
|
|
|
|
||
Maximum output enable access time |
3 |
3 |
4 |
5 |
ns |
||
|
|
|
|
|
|
|
|
Maximum operating current |
AS7C256A |
90 |
80 |
70 |
70 |
mA |
|
|
|
|
|
|
|
||
AS7C3256A |
60 |
50 |
45 |
45 |
mA |
||
|
|||||||
|
|
|
|
|
|
|
|
Maximum CMOS standby |
AS7C256A |
2 |
2 |
2 |
5 |
mA |
|
current |
|
|
|
|
|
|
|
AS7C3256A |
1 |
1 |
1 |
2 |
mA |
||
|
|
|
|
|
|
|
|
3/7/01; V.0.9.2 |
Alliance Semiconductor |
P. 1 of 8 |
|
|
|
Copyright © Alliance Semiconductor. All rights reserved.
AS7C256A
AS7C3256A
®
Functional description
The AS7C(3)256A is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes ≤ 3.6 mW. Normal operation offers 75% power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of the AS7C256A offer 2.0V data retention.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 3/3/4/5 ns are
ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C(3)256A is packaged in high volume industry standard packages.
Absolute maximum ratings
Parameter |
Device |
Symbol |
Min |
Max |
Unit |
|
|
|
|
|
|
|
|
Voltage on VCC relative to GND |
AS7C256A |
Vt1 |
–0.5 |
+7.0 |
V |
|
AS7C3256A |
Vt1 |
–0.5 |
+5.0 |
V |
||
|
||||||
Voltage on any pin relative to GND |
|
Vt2 |
–0.5 |
VCC + 0.5 |
V |
|
Power dissipation |
|
PD |
– |
1.0 |
W |
|
Storage temperature (plastic) |
|
Tstg |
–65 |
+150 |
oC |
|
Ambient temperature with VCC applied |
|
Tbias |
–55 |
+125 |
oC |
|
DC current into outputs (low) |
|
IOUT |
– |
20 |
mA |
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
|
|
|
|
|
|
|
|
CE |
|
WE |
|
OE |
|
Data |
Mode |
|
|
|
|
|
|
|
|
H |
|
X |
|
X |
|
High Z |
Standby (ISB, ISB1) |
L |
|
H |
|
H |
|
High Z |
Output disable (ICC) |
L |
|
H |
|
L |
|
DOUT |
Read (ICC) |
L |
|
L |
|
X |
|
DIN |
Write (ICC) |
Key: X = Don’t care, L = Low, H = High
3/7/01; V.0.9.2 |
Alliance Semiconductor |
P. 2 of 8 |
|
|
|
AS7C256A
AS7C3256A
®
Recommended operating conditions
Parameter |
Device |
Symbol |
Min |
Typical |
Max |
Unit |
|
|
|
|
|
|
|
|
|
Supply voltage |
AS7C256A |
VCC |
4.5 |
5.0 |
5.5 |
V |
|
AS7C3256A |
VCC |
3.0 |
3.3 |
3.6 |
V |
||
|
|||||||
|
AS7C256A |
VIH |
2.2 |
– |
VCC+0.5 |
V |
|
Input voltage |
AS7C3256A |
VIH |
2.0 |
– |
VCC+0.5 |
V |
|
|
— |
VIL* |
-0.5* |
– |
0.8 |
V |
|
|
commercial |
T |
0 |
– |
70 |
oC |
|
Ambient operating temperature |
|
A |
|
|
|
|
|
industrial |
T |
–40 |
– |
85 |
oC |
||
|
|||||||
|
|
A |
|
|
|
|
* VIL min = –2.0V for pulse width less than tRC/2.
DC operating characteristics (over the operating range)1
|
|
|
|
|
|
|
|
|
|
|
-10 |
-12 |
-15 |
-20 |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
Parameter |
Sym |
Test conditions |
|
Device |
Min |
Max |
Min |
Max |
Min |
Max |
Min |
Max |
Unit |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
Input leakage |
|ILI| |
|
VCC = Max, |
|
Both |
|
|
– |
1 |
– |
1 |
– |
1 |
µA |
|||||
current |
|
Vin = GND to VCC |
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
Output leakage |
|ILO| |
|
VCC = Max, |
|
Both |
|
|
– |
1 |
– |
1 |
– |
1 |
µA |
|||||
current |
|
VOUT = GND to VCC |
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
Operating |
|
|
|
|
|
|
|
|
|
AS7C256A |
|
90 |
– |
80 |
– |
70 |
– |
70 |
|
|
|
VCC = Max, CE ≤ |
VIL |
|
|||||||||||||||
power supply |
ICC |
|
|
|
|
|
|
|
|
|
|
mA |
|||||||
|
|
|
|
|
|
|
|
|
|
||||||||||
|
f = fMax, IOUT = 0mA |
AS7C3256A |
|
60 |
– |
50 |
– |
45 |
– |
45 |
|||||||||
current |
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
VCC = Max, |
|
≤ |
VIL |
AS7C256A |
|
30 |
– |
25 |
– |
20 |
– |
20 |
|
|||
|
ISB |
CE |
mA |
||||||||||||||||
Standby power |
|
f = fMax, IOUT = 0mA |
AS7C3256A |
|
30 |
– |
25 |
– |
20 |
– |
20 |
||||||||
|
|
|
|
||||||||||||||||
|
|
|
V |
|
|
= Max, |
|
> |
V –0.2V |
AS7C256A |
|
2 |
– |
2 |
– |
2 |
– |
5.0 |
|
supply current |
|
CC |
CE |
|
|||||||||||||||
ISB1 |
|
|
|
|
|
CC |
|
|
|
|
|
|
|
|
|
mA |
|||
|
|
VIN < GND + 0.2V or |
|
|
|
|
|
|
|
|
|
||||||||
|
|
AS7C3256A |
|
1 |
– |
1 |
– |
1 |
– |
2.0 |
|||||||||
|
|
|
VIN > VCC–0.2V, f = 0 |
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
Output voltage |
VOL |
|
IOL = 8 mA, VCC = Min |
Both |
|
|
– |
0.4 |
– |
0.4 |
– |
0.4 |
V |
||||||
VOH |
|
IOH = –4 mA, VCC = Min |
Both |
|
|
2.4 |
– |
2.4 |
– |
2.4 |
– |
V |
|||||||
|
|
|
|
||||||||||||||||
|
|
|
VCC = 2.0V |
|
|
|
|
|
|
|
|
|
|
|
|||||
Data retention |
|
|
|
> VCC -0.2V |
|
|
|
|
|
|
|
|
|
|
|
||||
ICCDR |
|
CE |
|
Both |
|
.5 |
|
.5 |
|
.5 |
|
1 |
mA |
||||||
current |
|
VIN > VCC -0.2V or VIN < |
|
|
|
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
0.2V |
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Capacitance (f = 1MHz, Ta = room temperature, VCC = NOMINAL)2
Parameter |
Symbol |
Signals |
Test conditions |
Max |
Unit |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
Input capacitance |
CIN |
A, |
|
|
|
|
|
|
Vin = 0V |
5 |
pF |
CE, |
WE, |
OE |
|||||||||
I/O capacitance |
CI/O |
I/O |
Vin = Vout = 0V |
7 |
pF |
||||||
3/7/01; V.0.9.2 |
Alliance Semiconductor |
P. 3 of 8 |
|
|
|
Loading...