This chapter will help you begin troubleshooting your signal generator. The procedures in
this chapter primarily check your instrument for failures that affect the power supplies or
CPU function. An RF block diagram of your signal generator is at the end of this chapter.
Service Guide1-1
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Before You Begin Troubleshooting
Before You Begin Troubleshooting
Be sure to review the warning and caution statements described in Chapter 7 prior to
troubleshooting your signal generator.
Using this Service Guide to Troubleshoot
Several chapters in this service guide work together to help you troubleshoot and repair
your signal generator.
• Chapter 1, “Initial Troubleshooting and RF Block Diagrams,” helps you get
started with some basic checks and instructions.
• Chapter 2, “Assembly-Level Troubleshooting with Block Diagrams,” helps you
identify and verify the failed assembly.
• Chapter 3, “Replaceable Parts (ESG-A & ESG-D),” helps you locate the failed
assembly or cable in the signal generator and also provides you with part numbers and
ordering information.
• Chapter 4, “Replaceable Parts (ESG-AP & ESG-DP),” helps you locate the failed
assembly or cable in the signal generator and also provides you with part numbers and
ordering information.
• Chapter 5, “Assembly Replacement,” gives you step-by-step instructions on how to
remove and replace an assembly.
• Chapter 6, “Post-Repair Procedures,” lists the performance tests and adjustments
that must be performed after an assembly has been repaired or replaced.
1-2Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Signal Generator Options
Signal Generator Options
This section lists the hardware, software, and documentation options you can order with a
new signal generator. Some of the options can be retrofitted into your existing signal
generator. Order a retrofit by requesting either the post-sales option number or the part
number.
Hardware and Software Options Available for New Instruments
Desired
Option
100XXUND
101XXUND
1CMXXXX
1CNXXXX
1CPXXXX
1EMXXXX
1E5XX
1E6XX
200
201
300XXUN7, UN8UND
UN5XXUND
UN7XXUN3,UN4,or
UN8XX
UN9XXUN8
UNAXXUN8UNB
UNBXXUNA
UNDXX
ESG-AESG-DESG-APESG-DP
StandardStandard
XXUN8
XXUN8
Required
Options
UN8
Incompatible
Options
Service Guide1-3
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Signal Generator Options
Adding Hardware and Software Options to Existing Instruments
Desired
Option
100UND150
101UND151
200UN8250
201UN8
300UN7, UN8
UN5UND005
UN7UN3, UN4, or UN8007E4400-60143
UN8008E4400-60170
UN8UN3 or UN4E4400-60160
UN8 and UN9009E4400-60185
UN8 andUN9UN3 or UN4E4400-60184
UND004E4400-60166
UNDUN3 or UN4E4400-60181
Existing
Option
Required Options
Post-Sales
Option
251
Part Number
1-4Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Signal Generator Options
OptionDescription
100Option 100 has two implementations:
Multichannel W-CDMA (Revision 1.0-1.2) Personality - This first
implementation of Option 100 simulates multichannel forward and
reverse link signals according to the developing W-CDMA international
standards. Spreading and frame structure of these signals are
implemented according to March 1999 ARIB 1.0 - 1.2 specification.
Multichannel W-CDMA (3GPP 3.1 12-99) Personality - This second
implementation of Option 100 simulates multichannel downlink and
uplink signals according to the developing W-CDMA international
standards. This option implements a chip rate of 3.84 Mcps, and is based
on the December 1999 3GPP 3.1 specification.
101Multichannel CDMA2000 Personality - This option simulates
multichannel forward and reverse link signals according to the developing
CDMA2000 standard revision 8.
1CMRack Mount Flanges without Handles - This option adds two flanges and
the necessary hardware to rack mount the signal generator in a System II
or System II Plus cabinet.
1CNFront Handles - This option adds two front handles with the necessary
hardware to attach the handles to the front of the signal generator.
1CPRack Mount Flanges with Handles - This option adds two front handles,
two flanges, and the necessary hardware to rack mount the signal
generator in an System II or System II Plus cabinet.
1E5High Stability Timebase - This option replaces the standard timebase
reference assembly with a high-stability timebase reference assembly that
has improved specifications over the standard assembly, including
warranted specifications for aging rate. This feature is standard on
ESG-AP and ESG-DP Series Signal Generators.
1E6High Performance Pulse Input - This option provides high performance
pulse capabilities with rise and fall times < 10 ns and on/off ratios > 70 dB.
1EMMove All Front Panel Connectors to Rear Panel - This option moves all of
the front panel connectors to the rear panel. If you order Option 1EM in
combination with any option that adds front panel connectors,
Option 1EM will cause all of the front panel connectors to be moved to the
rear panel and, in addition, some of the connectors will be changed from
BNC to SMB connectors.
Service Guide1-5
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Signal Generator Options
200Fully Coded 3GPP W-CDMA Personality - This option can be used to
provide fully-coded, multichannel downlink and uplink signals in
compliance with 3GPP specifications. Support for this 3GPP W-CDMA
solution may require the use of two ESG signal generators.
201Multichannel Real-Time cdma2000 Personality - This option can be used
to provide fully-coded, multichannel forward and reverse link signals
supporting both the IS-95 and IS-2000 CDMA standards.
Support for IS-2000 may require the use of two ESG signal generators.
Because IS-2000 provides backward compatibility with IS-95 in RC1 and
RC2 configurations, the Option 201 personality also supports the IS-95
standard.
300Base Station BERT Extension for Option UN7 - This option adds bit error
rate testing for GSM base stations to the ESG/VSA combination.
ES1This option indicates that a more recent version of firmware is resident in
the signal generator than was originally shipped. The operating features
in the new firmware may be different than those documented in your
original manual set.
UN3I/Q Baseband Generator with 1 Mbit Pattern RAM (Obsolete) - This option
is no longer available. Option UN3 provided an I/Q baseband generator
with DECT, GSM, NADC, PDC, PHS, and TETRA digital modulation
formats. Option UN3 is replaced by Option UN8.
UN4I/Q Baseband Generator with 8 Mbit Pattern RAM (Obsolete) - This option
is no longer available. Option UN4 provided an I/Q baseband generator
with DECT, GSM, NADC, PDC, PHS, and TETRA digital modulation
formats. Pre-modulation filtering selections and PRBS capability were
provided. Option UN4 is replaced by Option UN8 with Option UN9.
UN5Multi-Channel CDMA - This option provides multi-channel IS-95 CDMA
capability, which provides flexible, coded-channel setups for CDMA base
stations or mobiles, components, or sub-system test.
UN7Bit Error Rate Test - This option adds a bit error rate test function that
evaluates PN9 or PN15 bit streams for errors. Configuration of data, clock,
and clock gate inputs allow testing of demodulated TDMA or CDMA
formats. A baseband generator must be part of the instrument
configuration.
UN8Real-time I/Q Baseband Generator - This option provides a custom
modulation generator with 1 Mbit of pattern RAM. The custom
modulation generator provides generic symbol building, variable symbol
rates, and variable filter capabilities in addition to TDMA protocols.
UN9+7 MBits RAM - This option adds an additional 7 Mbits of pattern RAM to
Option UN8 for very long data pattern generation. You must purchase
Option UN8 in conjunction with Option UN9.
UNAAlternate Timeslot Power Level Control - This option provides alternate
timeslot power level control for adjacent timeslots in TDMA applications.
1-6Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Signal Generator Options
UNBHigh Power with Mechanical Attenuator - This option provides a
mechanical attenuator that provides 4 to 6 dB more output power than the
standard electronic attenuator.
UNDInternal Dual Arbitrary Waveform Generator - This option provides an
internal dual arbitrary waveform generator that contains an on-board
digital signal processor capable of playing back downloaded waveforms to
generate complex, digitally modulated signals. A 1 Megasample per
channel memory accepts I/Q files from different waveform generation
programs, such as Omnisys and Matlab. 14 bit DACs optimize dynamic
range and reduce noise.
Service Guide1-7
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Contacting Agilent Technologies
Contacting Agilent Technologies
This section prepares you for contacting Agilent Technologies should you have a problem
with your signal generator.
Check the Basics before Contacting Agilent Technologies
Often problems may be solved by repeating what was being done when the problem
occurred. A few minutes spent in performing these simple checks may eliminate time
spent waiting for instrument repair.
• Check that the signal generator is plugged into the proper ac power source.
• Check that the line socket has power.
• Check that the signal generator is turned on.
• Check that the other equipment, cables, and connectors are connected properly and
operating correctly.
• Check the equipment settings in the procedure that was being used when the problem
occurred.
• Check that the test being performed and the expected results are within the
specifications and capabilities of the signal generator. (Refer to the calibration guide.)
• Check the signal generator display for error messages. (Refer to the Error Messages
guide.)
• Check operation by performing the verification procedures in the calibration guide.
Record all results in the performance test record.
Review the Warranty
If there is still a problem, read the warranty printed in Chapter 7, “Safety and Regulatory.”
If your signal generator is covered by a separate maintenance agreement, be familiar with
its terms.
Agilent Technologies offers several maintenance plans to service your signal generator
after warranty expiration. Call your Agilent Technologies sales and service office for full
details.
Calling Agilent Technologies Sales and Service Offices
Sales and service offices are located around the world to provide complete support for your
signal generator. To obtain servicing information, contact the nearest Agilent Technologies
Sales and Service office listed in Table 1-1. For information on ordering parts refer to
Chapter 3 or Chapter 4.
In any correspondence or telephone conversation, refer to the signal generator by its model
number and full serial number. With this information, the Agilent Technologies
representative can quickly determine whether your unit is still within its warranty period.
1-8Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Contacting Agilent Technologies
Table 1-1 Agilent Technologies Sales and Service Offices
China
China Agilent Technologies
38 Bei San Huan X1 Road
Shuang Yu Shu
Hai Dian District
Beijing, China
(86 1) 256-6888
Service Guide1-9
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Contacting Agilent Technologies
Returning Your Signal Generator for Service
Use the information in this section if you need to return the signal generator to
Agilent Technologies.
Packaging the Signal Generator
Use the following steps to package the signal generator for shipment to Agilent
Technologies for service:
1. Fill out a blue repair tag (available at the end of this chapter) and attach it to the
instrument. Be as specific as possible about the nature of the problem. Send a copy of
any or all of the following information:
• Any error messages that appeared on the signal generator display.
• A completed performance test record from the calibration guide for your instrument.
• Any other specific data on the performance of the signal generator.
2. Use the original packaging materials or a strong shipping container that is made of
double-walled, corrugated cardboard with 159 kg (350 lb) bursting strength. The carton
must be both large enough and strong enough to accommodate the signal generator and
allow at least 3 to 4 inches on all sides of the signal generator for packing material.
CAUTIONSignal generator damage can result from using packaging materials other
than those specified. Never use styrene pellets, in any shape, as packaging
materials. They do not adequately cushion the instrument or prevent it from
shifting in the carton. Styrene pellets cause equipment damage by generating
static electricity and by lodging in the signal generator fan.
3. Surround the instrument with at least 3 to 4 inches of packing material, or enough to
prevent the instrument from moving in the carton. If packing foam is not available, the
best alternative is SD-240 Air Cap™ from Sealed Air Corporation (Hayward, CA
94545). Air Cap looks like a plastic sheet covered with 1-1/4 inch air-filled bubbles. Use
the pink Air Cap to reduce static electricity. Wrap the instrument several times in the
material to both protect the instrument and prevent it from moving in the carton.
4. Seal the shipping container securely with strong, nylon adhesive tape.
5. Mark the shipping container “FRAGILE, HANDLE WITH CARE” to ensure careful
handling.
6. Retain copies of all shipping papers.
1-10Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Equipment Required for Troubleshooting
Equipment Required for Troubleshooting
Table 1-2 lists the equipment required to troubleshoot your signal generator. You may use
the recommended model or an equivalent that meets the critical specifications.
Table 1-2 Recommended Test Equipment
Equipment
Digital
Multimeter
Critical Specifications for
Equipment Substitution
Input Resistance: ≤10MΩ Accuracy:
10 mV on 100 V range
Recommended
Model Number
Agilent 3458A
Service Guide1-11
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
Initial Troubleshooting
Perform the following troubleshooting steps in the order they are presented. If you are
unable to identify the failed assembly, go to Chapter 2, “Assembly-Level Troubleshooting
with Block Diagrams,” for further instruction.
NOTEDo not attempt to replace any fuses within the power supply to correct a
problem with your signal generator. If you determine that the power supply is
the failed assembly, replace the power supply.
Step 1: Observe the Front and Rear Panel LEDs
Observing the LEDs on the front and rear panel of the signal generator will determine if
there is a catastrophic failure in the power supply assembly.
1. Ensure the signal generator is plugged in (do not switch the power on) and verify that
the yellow LED on both the front and rear panels is lit. Refer to Figure 1-1 for LED
locations. A lit yellow LED (+15 V_STBY) indicates that line voltage is present.
2. Power on the signal generator and verify that the green LED on both the front and rear
panels is lit. A lit green LED indicates the power supply has received an “ON”
command. The ON/OFF switch toggles a flip-flop latch which biases the proper
transistors in the LED control circuit. This circuit is powered by VBAT, the
battery-backed SRAM supply, so that the on-off state is “remembered” even when the
instrument is unplugged.
Figure 1-1 LED Locations on the Front and Rear Panels
1-12Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Initial Troubleshooting
Step 2: Power On the Signal Generator and Check for Error
Messages
This procedure verifies that the signal generator powers up and that the internal
instrument check identifies no errors. The internal check evaluates the correctness of
operation and returns an error message if a problem is detected.
1. Switch on the signal generator. Let the signal generator warm up for at least five
minutes.
NOTEFor ESG-AP, ESG-DP, and Option 1E5 signal generators, ERROR 514,
Reference Oven Cold will occur whenever the signal generator is powered
up within five minutes of being connected to AC line power. The
annunciator and the ERR annunciator will both turn on. The OVEN COLD
annunciator will automatically clear after approximately five minutes. The
error queue cannot be cleared, however, until the
OVEN COLD annunciator has
turned off.
2. Cycle the power to the signal generator and verify that the green LED on both the front
and rear panels is lit. Refer to Figure 1-1.
OVEN COLD
3. When the display is lit, check to see if the
4. If the
ERR annunciator is turned on, review the error messages in the queue by pressing
Utility > Error Info > View Next Error Message. The first error message in the queue will be
ERR annunciator is turned on.
shown in the text area of the display. Refer to the Error Messages guide for descriptions
of error messages.
If there is more than one error message (each message will be designated as 1 of n),
continue pressing the
View Next Error Message softkey until you have seen and recorded all
of the messages.
5. If you were able to resolve all of the error messages, press Utility > Error Info >
Clear Error Queue(s) to delete the list of error messages.
Service Guide1-13
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
Step 3: Functional Check the Front Panel Keys and Display
1. Press various front panel hardkeys and softkeys to verify they function as expected.
2. Use the contrast keys to verify that the display can be lightened and darkened. Refer to
Figure 1-2.
Figure 1-2 Contrast Keys
1-14Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Initial Troubleshooting
Step 4: Visually Check the Individual Voltage Supplies
1. Unplug the signal generator and remove the instrument cover. Refer to Chapter 5,
“Assembly Replacement,” for removal instructions.
2. Expose the motherboard by removing the top cover. It is secured by 11 screws.
3. Plug in the signal generator and allow it to warm up for at least five minutes.
4. If possible, clear the error queue(s) of messages. Press
Queue(s)
.
Utility > Error Info > Clear Error
5. On the motherboard, locate the 10 LEDs that correspond to the individual voltage
supplies (see Figure 1-3). Verify that all the LEDs are lit. If one or more LEDs are off,
proceed to “Step 6: Isolate the Failed Assembly”.
Figure 1-3 LED Locations on the Motherboard
Service Guide1-15
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
Step 5: Measure the Individual Voltage Supplies
The voltages supplied as inputs from the power supply via J6 to the motherboard are
+15 V (TP502), +15 V standby (+15 V_STBY), −15 V (TP503), +12 V (TP505), and
+5.2 V (TP302). DGND (TP301) is associated with these supplies.
The −6 V (TP508) and −5.2 V (TP509) supplies receive their input from the +5.2 V digital
supply (5.2 VD at TP506). The +5.2 V digital line is filtered to prevent the switching power
supply noise from being induced onto the +5.2 VD supply lines. The −6 V is a bias voltage
for circuits on the output board and other RF circuitry. The −5.2 V is used by the emitter
coupled logic (ECL) digital ICs. The LCD display driver voltage (VLCD), a −14 V to −24 V
source, also receives input from the +5.2 VD supply.
The input to the +32 V supply (TP504) is the +12 V supply.The +32 V supply is used by the
synthesizer/doubler assembly. This supply also includes an LC noise filter.
The +12.5 V regulated supply (TP510) originates from the +15 V input. The −12.5 V
regulated supply (TP511) originates from the −15 V input. These two supplies are used by
the solid-state attenuator and the reverse power protection (RPP). The +10 V reference
(TP501) originates from the +15 V input. The +9 V supply (TP507) originates from the
+10 V reference and the +12 V supply.
1. Unplug the signal generator and turn it upside-down.
2. Expose the motherboard by removing the bottom cover. It is secured by 15 screws.
3. Plug in the signal generator.
4. Measure the voltage of each supply to verify they are within the tolerances listed in
Table 1-3. The voltage supply test point locations are shown in Figure 1-4. If all the
voltages are within tolerance, proceed to “Step 7: Check for Basic CPU Functionality”.
1-16Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
Figure 1-4 Motherboard Test Point Locations
1-18Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Initial Troubleshooting
Step 6: Isolate the Failed Assembly
1. Switch off the signal generator.
2. Remove or disconnect an assembly. Below is a suggested order of removal/disconnection
based upon ease.
For the ESG-A and ESG-D Series:
a. A5 Dual Arbitrary Waveform Generator Board (Option UND)
b. A6 Bit Error Rate Test Board (Option UN7)
c. A7 Baseband Generator Board (Options UN3, UN4, UN8, UN9)
d. A8 Data Generator Board (Options UN3, UN4, UN8, UN9)
e. A21 Demodulator Board (Option 300)
f. Front Panel - disconnect A1W1 ribbon cable
g. A3 Inverter - disconnect A3W1
h. A2 Display - disconnect W10
i. AT1 Electronic Attenuator/RPP - disconnect W13
AT1 Mechanical Attenuator and A19 RPP (Option UNB) - disconnect W13 and
A19W1
j. A25 Pulse Modulator (Option 1E6) - disconnect A25W1
k. B1 Fan - disconnect B1W1 (disconnect only temporarily)
l. B2 Fan - disconnect B2W1 (disconnect only temporarily)
m.A9 Output Board
n. A11 Reference Board
o. A12 Synthesizer/Doubler Board
p. A20 YIG Down Convertor Assembly (Option 300) - disconnect W31
NOTERefer to Chapter 3, “Replaceable Parts (ESG-A and ESG-D Series),” for
information on locating assemblies. Refer to Chapter 5, “Assembly
Replacement,” for information on removing or disconnecting assemblies.
For the ESG-AP and ESG-DP Series:
a. A5 Dual Arbitrary Waveform Generator Board (Option UND)
b. A6 Bit Error Rate Test Board (Option UN7)
c. A7 Baseband Generator Board (Options UN3, UN4, UN8, UN9)
d. A8 Data Generator Board (Options UN3, UN4, UN8, UN9)
e. Front Panel - disconnect A1W1 ribbon cable
f. A3 Inverter - disconnect A3W1
Service Guide1-19
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
g. A2 Display - disconnect W10
h. AT1 Electronic Attenuator/RPP - disconnect W13
AT1 Mechanical Attenuator and A19 RPP (Option UNB) - disconnect W13 and
A19W1
i. A25 Pulse Modulator (Option 1E6) - disconnect A25W1
j. B1 Fan - disconnect B1W1 (disconnect only temporarily)
k. B2 Fan - disconnect B2W1 (disconnect only temporarily)
l. A9 Output Board
m.A11 Reference Board
n. A23 Sampler Board
o. A24 Frac-N/Divider Board
p. A22 YIG Driver Assembly - disconnect W35
NOTERefer to Chapter 4, “Replaceable Parts (ESG-AP and ESG-DP Series),” for
information on locating assemblies. Refer to Chapter 5, “Assembly
Replacement,” for information on removing or disconnecting assemblies.
3. Switch on the signal generator and check the voltage supply LEDs (see Figure 1-3). If
the LEDs are lit, you have likely identified the failed assembly. If one or more LEDs are
still off, switch off the signal generator and replace/reconnect the assembly and repeat
this procedure.
1-20Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Initial Troubleshooting
Step 7: Check for Basic CPU Functionality
The Digital Signal Processor (DSP) performs a self-diagnostic test at power up. If the DSP
is not working, the CPU reports an error.
If the DSP does not seem to be working and the CPU did not report the error, then check
the CLK_OUT signal at TP701. It should be a 16 MHz signal. (Refer to Figure 1-5.)
The eight LEDs of DS201 (see Figure 1-5) indicate the status of the boot and flash ROM for
the CPU. The LEDs form a binary code that can be described as a two digit hexadecimal
code. Table1-4 shows the test sequence and the LED pattern (binary representation) of the
test that is running. If an error occurs and the test is halted, the LED pattern will indicate
which self test halted the process. The LED closest to R201 is the place holder for the Least
Significant Bit (LSB) in the pattern.
Table 1-4 Sequence for DSP Self-Diagnostic Tests
Test Description
LEDs at start of testFF1111 1111
Checksum testFE1111 1110
Bootrom RAM testFD1111 1101
RAM testFC1111 1100
I/O bus testFB1111 1011
Main firmware checksum testFA1111 1010
CPU testAA1010 1010
Test done and OK000000 0000
Hexadecimal
Code
Binary
Equivalent
MSB LSB
Service Guide1-21
Initial Troubleshooting and RF Block DiagramsESG Family Signal Generators
Initial Troubleshooting
Figure 1-5 Location of TP701 and DS201-208 on CPU/Motherboard
1-22Service Guide
ESG Family Signal GeneratorsInitial Troubleshooting and RF Block Diagrams
Additional Information for Troubleshooting the ESG-AP and ESG-DP Series
Additional Information for Troubleshooting the
ESG-AP and ESG-DP Series
Table 1-5 provides frequency-dependent settings for selected points in the RF signal flow of
the ESG-AP and ESG-DP Series Signal Generators.Notice that the settings are relative to
the RF output frequency. This information can improve your understanding of the signal
generator circuitry, especially when used with the RF block diagram.
NOTEThe values for Table 1-5 assume FM modulation is turned off.
Table 1-5 Frac-N, YO, and Other Selected Frequency-Dependent Settings for Several
ESG-A SERIES RF BLOCK DIAGRAM
(STANDARD & OPTION 1E6)
1 GHz REF
LF OUT
A SYNTHESIZER BOARD
.5-1 GHz
F
f
2
Om
/
FM
d/dt
D REFERENCE BOARD
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
5 MHz
X2
X2
B OUTPUT BOARD
.75-1 GHz
.0-.25 GHz
OPTION 1E6
E PULSE MOD
ALC
.25-4 GHz
MODULATOR
2
ALC
MODULATOR
DRIVER
BURST
MODULATOR
.25-4 GHz
ALC
HOLD
ALC
DETECTOR
50
PULSE
INPUT
C ATTENUATOR
/RPP
DETECTOR
FEED FORWARD AM
SHAPING
ALC REF
5dB STEP
ATTENUATOR
DAC
BURST
MODULATOR
DRIVER
HOLD ALC
ALC_REF
IN_BAND_AM
RPP
RF Out
EXT REF
sk766b
EXT 1
INPUT
EXT 2
INPUT
PLL
10 MHz PLL
10 MHz BW
1 GHz PLL
PLL
NC
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
LIN_AM_MOD
PULSE MOD
ESG-A SERIES RF BLOCK DIAGRAM
(STANDARD & OPTION 1E6)
ESG-D SERIES RF BLOCK DIAGRAM
A SYNTHESIZER BOARD
.5-1 GHz
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
F
f
5 MHz
2
Om
/
FM
D REFERENCE BOARD
LF OUT
d/dt
10 MHz SYNTH
X2
X2
1 GHz REF
B OUTPUT BOARD
.25-4 GHz
ALC
HOLD
.0-.25 GHz.0-.25 GHz
ALC
DETECTOR
DETECTOR
SHAPING
DAC
C ATTENUATOR
/RPP
5dB STEP
50
ALC REF
ATTENUATOR
RPP
.75-1 GHz.75-1 GHz
AUX
OUT
(COHERENT
CARRIER)
2
.25-4 GHz
VBLO
DAC
QUAD
IQ MODULATOR
90
ALC
MODULATOR
0
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
CAL
VOLTAGE
Q OFFSET
DAC
DAC
Q GAIN
BURST
MODULATOR
DRIVER
FEED FORWARD AM
HOLD ALC
EXT
I INPUT
EXT
Q INPUT
I OFFSET
DAC
DAC
I GAIN
CAL
VOLTAGE
EXT 1
INPUT
EXT 2
INPUT
EXT REF
PLL
10 MHz PLL
10 MHz BW
PLL
1 GHz PLL
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
ALC_REF
IN_BAND_AM
LIN_AM_MOD
PULSE MOD
sk773b
ESG-D SERIES RF BLOCK DIAGRAM
ESG-D SERIES RF BLOCK DIAGRAM
(OPTIONS UN3 & UN4)
1 GHz REF
B OUTPUT BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
A SYNTHESIZER BOARD
.5-1 GHz
Om
/
FM
d/dt
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
F
f
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
5 MHz
2
10 MHz SYNTH
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
X2
X2
2
10 MHz DIG
EXT 13 MHz
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIG
EVENT 1
EVENT 2
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
EXT
I INPUT
EXT
Q INPUT
I GAIN
E BASEBAND GENERATOR BOARD
PLL_LCK_SIG
MASTER_CLK
BUF_DATA_IN
SYMBOL_SYNC
L DATA_CLK
BBG_BIT_CLK
SUB_I_COUNT
L_BURST
SCRAMBLE_RUN
SYMBOL_SYNC
BURST_GATE
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN3=1M
UN4=8M
DATA
GENERATION
CONTROL
USER_DATA
PLL_CLOCK
SWITCH
MASTER
CLOCK-PLL
DATA
F DATA GENERATOR BOARD
90
DAC
DAC
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
CAL
VOLTAGE
SWITCH & FILTERS
BURST_PULSE
0
CAL
VOLTAGE
BURST MOD
Q OFFSET
DAC
DAC
Q GAIN
BURST_ENVELOPE
INT_ Q_MOD
INT_ I_MOD
ALC
MODULATOR
ALC
MODULATOR
DRIVER
FEED FORWARD AM
LIN_BURST
MODULATOR
BURST
MODULATOR
DRIVER
LOG_BURST
BURST
HOLD ALC
BURST
ALC_REF
IN_BAND_AM
.75-1 GHz.75-1 GHz
.25-4 GHz
ALC
HOLD
.0-.25 GHz.0-.25 GHz
ALC
DETECTOR
DETECTOR
SHAPING
DAC
C ATTENUATOR
/RPP
5dB STEP
50
ALC REF
ATTENUATOR
RPP
sk774b
LIN_AM_MOD
PULSE MOD
ESG-D SERIES RF BLOCK DIAGRAM (OPTIONS UN3 & UN4)
ESG-D SERIES RF BLOCK DIAGRAM
(OPTION UN8 or UN9) Rev C or D
1 GHz REF
B OUTPUT BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
A SYNTHESIZER BOARD
.5-1 GHz
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
F
f
Om
/
d/dt
FM
10 MHz SYNTH
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
5 MHz
2
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
X2
X2
2
10 MHz DIG
EXT 13 MHz
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIGGER
EVENT 1
EVENT 2
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
VBLO
DAC
IQ MODULATOR
90
QUAD
DAC
I OFFSET
DAC
DAC
EXT
I INPUT
EXT
Q INPUT
I GAIN
CAL
VOLTAGE
E BASEBAND GENERATOR BOARD
MASTER
CLOCK-PLL
MPU
GLOBAL CLOCK INPUTS
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN8=1M
UN8&UN9=8M
EVENT1_OUT
USER_DATA_EN
PLL_LCK_SIG
MASTER_CLK
BBG_BIT_CCK
SUB_I_CLK
MPU BUS
DATA
GENERATION
CONTROL
BASEBAND
GEN. I/O
FPGA
FPGA
FPGA
FPGA BUS
DAC
DAC
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
F DATA GENERATOR BOARD
0
CAL
VOLTAGE
BURST MOD
SWITCH &
FILTERS
BURST_PULSE
Q OFFSET
DAC
DAC
Q GAIN
BURST_ENVELOPE
INT_ Q_MOD
INT_ I_MOD
LIN_AM_MOD
ALC
MODULATOR
ALC
MODULATOR
DRIVER
FEED FORWARD AM
LIN_BURST
PULSE_MOD
BURST
MODULATOR
BURST
MODULATOR
DRIVER
LOG_BURST
.75-1 GHz
HOLD ALC
BURST
ALC_REF
IN_BAND_AM
.25-4 GHz
ALC
HOLD
.0-.25 GHz
DETECTOR
SHAPING
ALC
DETECTOR
DAC
50
ALC REF
C ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
sk77c
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UN8 or UN9 ) Rev C or D
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UN7 with UN8)
1 GHz REF
B OUTPUT BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
A SYNTHESIZER BOARD
.5-1 GHz
Om
/
FM
d/dt
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
F
f
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
5 MHz
2
10 MHz SYNTH
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
X2
X2
2
10 MHz DIG
EXT 13 MHz
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIG
EVENT 1
EVENT 2
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
VBLO
DAC
IQ MODULATOR
90
QUAD
DAC
I OFFSET
DAC
DAC
EXT
I INPUT
EXT
Q INPUT
I GAIN
E BASEBAND GENERATOR BOARD (UN8)
PLL_LCK_SIG
MASTER_CLK
BUF_DATA_IN
SYMBOL_SYNC
L DATA_CLK
BBG_BIT_CLK
SUB_I_COUNT
L_BURST
SCRAMBLE_RUN
SYMBOL_SYNC
BURST_GATE
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN3=1M
UN4=8M
DATA
GENERATION
CONTROL
DAC
DAC
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
USER_DATA
PLL_CLOCK
SWITCH
MASTER
CLOCK-PLL
DATA
F DATA GENERATOR BOARD
CAL
VOLTAGE
SWITCH & FILTERS
BURST_PULSE
0
CAL
VOLTAGE
BURST MOD
Q OFFSET
DAC
DAC
Q GAIN
BURST_ENVELOPE
INT_ Q_MOD
INT_ I_MOD
ALC
MODULATOR
ALC
MODULATOR
DRIVER
FEED FORWARD AM
LIN_BURST
MODULATOR
BURST
MODULATOR
DRIVER
LOG_BURST
BURST
.25-4 GHz
ALC
HOLD
.0-.25 GHz.0-.25 GHz
ALC
DETECTOR
DETECTOR
SHAPING
.75-1 GHz.75-1 GHz
HOLD ALC
BURST
ALC_REF
IN_BAND_AM
G BERT MEASURMENT BOARD (UN7)
BERT
DATA IN
BERT
CLK IN
BERT
GATE IN
INPUT
BERT ASIC
DSP
BER
Calculation
DAC
50
ALC REF
BER
SYNC LOSS
BER
NO DATA
BER
ERR OUT
BER
TEST OUT
BER
MEAS END
C ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
sk775b
LIN_AM_MOD
PULSE MOD
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UN7 with UN8)
ESG-D SERIES RF BLOCK DIAGRAM
(OPTIONS UN8 or UN9) Rev B
1 GHz REF
B OUTPUT BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
A SYNTHESIZER BOARD
.5-1 GHz
Om
/
FM
d/dt
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
F
f
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
5 MHz
2
10 MHz SYNTH
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
X2
X2
2
10 MHz DIG
EXT 13 MHz
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIG
EVENT 1
EVENT 2
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
EXT
I INPUT
EXT
Q INPUT
I GAIN
E BASEBAND GENERATOR BOARD
PLL_LCK_SIG
MASTER
CLOCK-PLL
DBMIC
DATA
GENERATION
UN8=1M
UN9=8M
CONTROL
BURST & DELAY
USER_DATA
PLL_CLOCK
SWITCH
DATA
MASTER_CLK
BUF_DATA_IN
SYMBOL_SYNC
L DATA_CLK
BBG_BIT_CLK
SUB_I_COUNT
L_BURST
SCRAMBLE_RUN
SYMBOL_SYNC
BURST_GATE
INTERNAL DATA
GENERATOR
(PATTERN RAM)
90
Q
DAC
Q-ADJ
DAC
I-ADJ
I
DAC
CONTROL
CAL
VOLTAGE
BURST_PLS
-1V_REF
0
Q OFFSET
DAC
DAC
Q GAIN
CAL
VOLTAGE
RECONSTRUCTION
FILTER
RECONSTRUCTION
FILTER
BURST MOD
SWITCH & FILTERS
Q-OFFSET
I-OFFSET
BURST_ENVELOPE
.75-1 GHz.75-1 GHz
.0-.25 GHz.0-.25 GHz
C ATTENUATOR
/RPP
ALC
MODULATOR
ALC
MODULATOR
DRIVER
BURST
MODULATOR
.25-4 GHz
ALC
HOLD
ALC
DETECTOR
DETECTOR
SHAPING
5dB STEP
50
ALC REF
ATTENUATOR
DAC
BURST
MODULATOR
DRIVER
FEED FORWARD AM
INT_ Q_MOD
AUD 2
INT_ I_MOD
AUD 1
LIN_BURST
LOG_BURST
HOLD ALC
BURST
ALC_REF
IN_BAND_AM
RPP
sk776b
F DATA GENERATOR BOARD
BURST_PULSE
LIN_AM_MOD
PULSE MOD
ESG-D SERIES RF BLOCK DIAGRAM
(OPTIONS UN8 or UN9) Rev B
ESG-D SERIES RF BLOCK DIAGRAM
(OPTION UND)
1 GHz REF
B OUTPUT BOARD
A SYNTHESIZER BOARD
.5-1 GHz
F
Om
/
FM
d/dt
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
f
10 MHz SYNTH
5 MHz
2
X2
X2
.75-1 GHz.75-1 GHz
.0-.25 GHz.0-.25 GHz
C ATTENUATOR
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
2
VBLO
DAC
QUAD
IQ MODULATOR
90
ALC
MODULATOR
0
ALC
MODULATOR
DRIVER
BURST
MODULATOR
.25-4 GHz
ALC
DETECTOR
50
DAC
CAL
VOLTAGE
Q OFFSET
DAC
DAC
Q GAIN
ALC
HOLD
DETECTOR
SHAPING
ALC REF
DAC
BURST
MODULATOR
DRIVER
FEED FORWARD AM
HOLD ALC
EXT
I INPUT
EXT
Q INPUT
I OFFSET
DAC
DAC
I GAIN
CAL
VOLTAGE
/RPP
5dB STEP
ATTENUATOR
RPP
DUAL ARBITRARY WAVEFORM GENERATOR BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
ARB_REF
CLOCK IN
DATA IN
SYNC IN
PATTERN
TRG
REFERENCE
PLL_CLOCK
SOCLK 1
SOCLK 0
DATA
SWITCH
EXT_CLK
EXT_DATA
EXT_SYNC
PATTERN_TRG
DSP
RAM
MEMORY
POL
LATCH
I/O DATA BUS
PLL_ON
SOCLK 1
SOCLK 0
POL_LATCH
EVENT 1 OUT
EVENT 2 OUT
NSGEND
SQADV
WFCNT
CONTROL
LOGIC
DATA
SEQUENCER
RAM
MEMORY
RAM
DATA
RAM
I/O DATA BUS
Q_OUT
BURST
Q
I
Q
DAC
I
DAC
BURST_PULSE
ALC_REF
IN_BAND_AM
I_OUT
LIN_BURST
LOG_BURST
LIN_AM_MOD
PULSE MOD
sk777b
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UND)
ESG-D SERIES RF BLOCK DIAGRAM
(OPTION UN7, UN8/UN9, 300)
1 GHz REF
B OUTPUT BOARD
LF OUT
EXT 1
INPUT
EXT 2
INPUT
EXT REF
A SYNTHESIZER BOARD
.5-1 GHz
VARIABLE
MODULUS
PRESCALER
FRACTIONAL
DIVIDE
F
f
Om
/
d/dt
FM
10 MHz SYNTH
D REFERENCE BOARD
10 MHz BW
10 MHz PLL
PLL
1 GHz PLL
PLL
5 MHz
2
FM_MOD
LIN_AM_MOD
PULSE MOD
10 MHz
SYNTH
10 MHz
OUT
1 GHz
REF
X2
X2
2
10 MHz DIG
EXT 13 MHz
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIGGER
EVENT 1
EVENT 2
AUX
OUT
(COHERENT
CARRIER)
.25-4 GHz
VBLO
DAC
IQ MODULATOR
90
QUAD
DAC
I OFFSET
DAC
DAC
EXT
I INPUT
EXT
Q INPUT
I GAIN
CAL
VOLTAGE
E BASEBAND GENERATOR BOARD
MASTER
CLOCK-PLL
MPU
GLOBAL CLOCK INPUTS
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN8=1M
UN8&UN9=8M
EVENT1_OUT
USER_DATA_EN
PLL_LCK_SIG
MASTER_CLK
BBG_BIT_CCK
SUB_I_CLK
MPU BUS
DATA
GENERATION
CONTROL
BASEBAND
GEN. I/O
FPGA
FPGA
FPGA
FPGA BUS
DAC
DAC
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
F DATA GENERATOR BOARD
0
CAL
VOLTAGE
BURST MOD
SWITCH &
FILTERS
BURST_PULSE
Q OFFSET
DAC
DAC
Q GAIN
BURST_ENVELOPE
INT_ Q_MOD
INT_ I_MOD
LIN_AM_MOD
ALC
MODULATOR
ALC
MODULATOR
DRIVER
FEED FORWARD AM
LIN_BURST
PULSE_MOD
BURST
MODULATOR
BURST
MODULATOR
DRIVER
LOG_BURST
.75-1 GHz
.25-4 GHz
ALC
HOLD
HOLD ALC
BURST
ALC_REF
IN_BAND_AM
OPTION 300
DEMODULATOR
CLOCK
DATA
GAIN
.0-.25 GHz
C ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
FPGA
DETECTOR
SHAPING
INTERFACE
SWITCH
DETECTOR
PLL
ALC
FPGA
DAC
50
ALC REF
CLK
MEMORY
DSP
CLK
G BERT MEASURMENT BOARD
BERT
DATA IN
BERT
CLK IN
BERT
GATE IN
INPUT
BERT ASIC
DSP
BER
CALCULATION
12
RPP
ADC
26 MHz REF
BER
SYNC LOSS
BER
NO DATA
BER
ERR OUT
BER
TEST OUT
BER
MEAS END
DAC
DOWN CONVERTER
IF
321.4
MHz
F
f
sk7110b
ESG-D SERIES RF BLOCK DIAGRAM (OPTION UN7, UN8/UN9, 300 )
ESG-AP SERIES RF BLOCK DIAGRAM (STANDARD &1E6)
A FRAC-N (PART OF FRAC-N/DIVIDER)
10 MHz
SYNTH
FM_MOD
Paren/Tessera
Frac-N
D REFERENCE
LF OUT
10 MHz BW
400-1000
MHz
B YO DRIVER
J3
J4
PRETUNE
FM
CROSS
OVER
DAC
<115 Hz
SCALING
-15V
P/O
P/O
F OUTPUT
1 GHz REF
E DIVIDER (PART OF FRAC-N DIVIDER)
.75-1 GHz
YO
J1
FM
COIL
J1
MAIN
COIL
RF OUT TO
FRAC-N/DIVIDER
J7
4-8 GHz
J8
RF OUT TO
SAMPLER
2-4 GHz
1-2 GHz
2
.5-1 GHz
222
.25-4 GHz
.25-.5 GHz
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
I GAIN
ALC
MODULATOR
90
0
Q OFFSET
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
CAL
VOLTAGE
DAC
Q GAIN
CAL
VOLTAGE
LIN_AM_MOD
FEED FORWARD AM
BURST
MODULATOR
DRIVER
.25-4 GHz
HOLD ALC
.0-.25 GHz
ALC
HOLD
ALC_REF
IN_BAND_AM
ALC
DETECTOR
DETECTOR
SHAPING
DAC
50
ALC REF
PULSE
INPUT
G PULSE MOD
H ATTENUATOR /RPP
5dB STEP
ATTENUATOR
RPP
RF OUTPUT
EXT 1
INPUT
EXT 2
INPUT
EXT 10 MHz
INPUT
10 MHz
PLL
VCO
1 GHz
PLL
100
LIN_AM_MOD
PULSE MOD
1 GHz
J3
1 GHz In
10 MHz
SYNTH
10 MHz
OUT
10 MHz
CLK
1 GHZ
REF
FRAC-N
J1
J6
C SAMPLER
750 MHz
4
PROGRAMMABLE
DIVIDER
750 MHz
256
M
DATA
M
6
4 < M < 51
- -
cw
fm
PULSE MOD
2P
F
+ / -
¦
P = 8, 9, or 10
cw
fm
750 MHz
30-70 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
f
s
f = N * f + f
yos if
f
if
LO
5 < N < 9
- -
F
¦
IF
S
RF
J3
f
yo
sk781b
ESG-AP SERIES RF BLOCK DIAGRAM (STANDARD & 1E6)
ESG-DP SERIES RF BLOCK DIAGRAM
A FRAC-N (PART OF FRAC-N/DIVIDER)
Paren/Tessera
Frac-N
10 MHz BW
400-1000
MHz
LF OUT
10 MHz
SYNTH
FM_MOD
D REFERENCE
B YO DRIVER
J3
J4
PRETUNE
FM
CROSS
OVER
DAC
<115 Hz
SCALING
-15V
P/O
P/O
F OUTPUT
1 GHz REF
E DIVIDER (PART OF FRAC-N DIVIDER)
.75-1 GHz
YO
J1
FM
COIL
J1
MAIN
COIL
RF OUT TO
FRAC-N/DIVIDER
J7
4-8 GHz
J8
RF OUT TO
SAMPLER
2-4 GHz
1-2 GHz
.5-1 GHz
2
222
.25-.5 GHz
.25-4 GHz
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
I GAIN
ALC
MODULATOR
90
0
Q OFFSET
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
CAL
VOLTAGE
DAC
Q GAIN
CAL
VOLTAGE
LIN_AM_MOD
FEED FORWARD AM
BURST
MODULATOR
DRIVER
.25-4 GHz
HOLD ALC
.0-.25 GHz
ALC
HOLD
ALC_REF
IN_BAND_AM
ALC
DETECTOR
DETECTOR
SHAPING
DAC
50
ALC REF
G ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
RF OUTPUT
EXT 1
INPUT
EXT 2
INPUT
EXT 10 MHz
INPUT
10 MHz
PLL
VCO
1 GHz
PLL
100
LIN_AM_MOD
PULSE MOD
1 GHz
J3
1 GHz In
10 MHz
SYNTH
10 MHz
OUT
10 MHz
CLK
1 GHZ
REF
FRAC-N
J1
C SAMPLER
J6
750 MHz
4
PROGRAMMABLE
DIVIDER
750 MHz
256
M
DATA
M
6
4 < M < 51
- -
cw
fm
PULSE MOD
2P
F
+ / -
¦
P = 8, 9, or 10
cw
fm
750 MHz
30-70 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
f
s
f = N * f + f
yos if
f
if
LO
5 < N < 9
- -
F
¦
IF
S
RF
J3
f
yo
sk767b
ESG-DP SERIES RF BLOCK DIAGRAM
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UN7)
A FRAC-N (PART OF FRAC-N/DIVIDER)
Paren/Tessera
Frac-N
LF OUT
10 MHz
SYNTH
FM_MOD
D REFERENCE
10 MHz BW
400-1000
MHz
B YO DRIVER
J3
J4
PRETUNE
FM
CROSS
OVER
DAC
<115 Hz
SCALING
-15V
P/O
P/O
F OUTPUT
1 GHz REF
E DIVIDER (PART OF FRAC-N DIVIDER)
.75-1 GHz
YO
J1
FM
COIL
J1
MAIN
COIL
RF OUT TO
FRAC-N/DIVIDER
J7
4-8 GHz
J8
RF OUT TO
SAMPLER
2-4 GHz
1-2 GHz
.5-1 GHz
2
222
.25-.5 GHz
.25-4 GHz
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
I GAIN
ALC
MODULATOR
90
0
Q OFFSET
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
CAL
VOLTAGE
DAC
Q GAIN
CAL
VOLTAGE
LIN_AM_MOD
FEED FORWARD AM
BURST
MODULATOR
DRIVER
.25-4 GHz
HOLD ALC
.0-.25 GHz
ALC
HOLD
ALC_REF
IN_BAND_AM
ALC
DETECTOR
DETECTOR
SHAPING
DAC
50
ALC REF
G ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
RF OUTPUT
EXT 1
INPUT
EXT 2
INPUT
EXT 10 MHz
INPUT
10 MHz
PLL
VCO
1 GHz
PLL
100
LIN_AM_MOD
PULSE MOD
BURST_PULSE
10 MHz SYNTH
10 MHz OUT
10 MHz CLK
1 GHZ REF
1 GHz
J3
FRAC-N
1 GHz In
J6
J1
C SAMPLER
750 MHz
4
PROGRAMMABLE
DIVIDER
750 MHz
256
M
DATA
M
6
4 < M < 51
- -
cw
fm
PULSE MOD
2P
F
+ / -
¦
P = 8, 9, or 10
cw
fm
750 MHz
30-70 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
f
s
f = N * f + f
yos if
f
if
LO
5 < N < 9
- -
F
¦
10 MHz DIG
EXT 13 MHz
IF
H BASEBAND GENERATOR BOARD
PLL_LCK_SIG
MASTER_CLK
BUF_DATA_IN
SYMBOL_SYNC
DATA
GENERATION
CONTROL
PLL_CLOCK
MASTER
CLOCK-PLL
DAC
DAC
INT_ Q_MOD
INT_ I_MOD
S
RF
J3
f
yo
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIG
EVENT 1
EVENT 2
USER_DATA
DATA
SWITCH
L DATA_CLK
BBG_BIT_CLK
SUB_I_COUNT
L_BURST
SCRAMBLE_RUN
SYMBOL_SYNC
BURST_GATE
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN3=1M
UN4=8M
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
BURST MOD
SWITCH & FILTERS
BURST_ENVELOPE
K BERT MEASURMENT BOARD
BERT
DATA IN
BERT
CLK IN
BERT
GATE IN
INPUT
BERT ASIC
DSP
BER
Calculation
BER
SYNC LOSS
BER
NO DATA
BER
ERR OUT
BER
TEST OUT
BER
MEAS END
sk782b
J DATA GENERATOR BOARD
BURST_PULSE
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UN7)
ESG-DP SERIES RF BLOCK DIAGRAM (OPTIONS UN8 or UN9)
A FRAC-N (PART OF FRAC-N/DIVIDER)
Paren/Tessera
Frac-N
10 MHz BW
LF OUT
10 MHz
SYNTH
FM_MOD
D REFERENCE
400-1000
MHz
B YO DRIVER
J3
J4
PRETUNE
FM
CROSS
OVER
DAC
<115 Hz
SCALING
-15V
P/O
P/O
F OUTPUT
1 GHz REF
E DIVIDER (PART OF FRAC-N DIVIDER)
.75-1 GHz
YO
J1
FM
COIL
J1
MAIN
COIL
RF OUT TO
FRAC-N/DIVIDER
J7
4-8 GHz
J8
RF OUT TO
SAMPLER
2-4 GHz
1-2 GHz
.5-1 GHz
2
222
.25-.5 GHz
.25-4 GHz
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
I GAIN
ALC
MODULATOR
90
0
Q OFFSET
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
CAL
VOLTAGE
DAC
Q GAIN
CAL
VOLTAGE
LIN_AM_MOD
FEED FORWARD AM
BURST
MODULATOR
DRIVER
.25-4 GHz
HOLD ALC
.0-.25 GHz
ALC
HOLD
ALC_REF
IN_BAND_AM
ALC
DETECTOR
DETECTOR
SHAPING
DAC
50
ALC REF
G ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
RF OUTPUT
EXT 1
INPUT
EXT 2
INPUT
EXT 10 MHz
INPUT
10 MHz
PLL
VCO
1 GHz
PLL
100
LIN_AM_MOD
PULSE MOD
BURST_PULSE
10 MHz SYNTH
10 MHz OUT
10 MHz CLK
1 GHZ REF
1 GHz
J3
J6
FRAC-N
J1
1 GHz In
C SAMPLER
750 MHz
4
PROGRAMMABLE
DIVIDER
750 MHz
256
M
DATA
M
6
4 < M < 51
- -
cw
fm
PULSE MOD
H BASEBAND GENERATOR BOARD
2P
F
+ / -
¦
P = 8, 9, or 10
cw
fm
750 MHz
30-70 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
f
s
f = N * f + f
yos if
f
if
LO
5 < N < 9
- -
F
¦
IF
10 MHz DIG
EXT 13 MHz
S
RF
J3
f
yo
DATA_CLOCK
DATA
EXT_SYNC
EXT_BURST
PATTERN
TRIGGER
EVENT 1
EVENT 2
INTERNAL DATA
GENERATOR
(PATTERN RAM)
UN8=1M
UN8&UN9=8M
MASTER
CLOCK-PLL
MPU
GLOBAL CLOCK INPUTS
EVENT1_OUT
USER_DATA_EN
PLL_LCK_SIG
MASTER_CLK
BBG_BIT_CCK
SUB_I_CLK
MPU BUS
DATA
GENERATION
CONTROL
BASEBAND
GEN. I/O
FPGA
FPGA
FPGA
FPGA BUS
DAC
DAC
CONTROL
BURST & DELAY
BURST_PLS
-1V_REF
BURST MOD
SWITCH &
FILTERS
INT_ Q_MOD
INT_ I_MOD
BURST_PULSE
J DATA GENERATOR BOARD
BURST_PULSE
sk783b
ESG-DP SERIES RF BLOCK DIAGRAM (OPTIONS UN8 or UN9)
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UND)
A FRAC-N (PART OF FRAC-N/DIVIDER)
Paren/Tessera
Frac-N
LF OUT
10 MHz
SYNTH
FM_MOD
D REFERENCE
10 MHz BW
400-1000
MHz
B YO DRIVER
J3
J4
PRETUNE
FM
CROSS
OVER
DAC
<115 Hz
SCALING
-15V
P/O
P/O
F OUTPUT
1 GHz REF
E DIVIDER (PART OF FRAC-N DIVIDER)
.75-1 GHz
YO
J1
FM
COIL
J1
MAIN
COIL
RF OUT TO
FRAC-N/DIVIDER
J7
4-8 GHz
J8
RF OUT TO
SAMPLER
2-4 GHz
1-2 GHz
.5-1 GHz
2
222
.25-.5 GHz
.25-4 GHz
AUX
OUT
(Coherent
Carrier)
EXT
I INPUT
EXT
Q INPUT
VBLO
DAC
IQ MODULATOR
QUAD
DAC
I OFFSET
DAC
DAC
I GAIN
ALC
MODULATOR
90
0
Q OFFSET
ALC
MODULATOR
DRIVER
BURST
MODULATOR
DAC
FEED FORWARD AM
LIN_BURST
BURST
MODULATOR
DRIVER
LOG_BURST
CAL
VOLTAGE
DAC
Q GAIN
CAL
VOLTAGE
LIN_AM_MOD
.25-4 GHz
HOLD ALC
.0-.25 GHz
ALC
HOLD
ALC_REF
IN_BAND_AM
ALC
DETECTOR
DETECTOR
SHAPING
DAC
50
ALC REF
G ATTENUATOR
/RPP
5dB STEP
ATTENUATOR
RPP
RF OUTPUT
EXT 1
INPUT
EXT 2
INPUT
EXT 10 MHz
INPUT
10 MHz
PLL
VCO
1 GHz
PLL
100
LIN_AM_MOD
PULSE MOD
BURST_PULSE
10 MHz
SYNTH
10 MHz
OUT
10 MHz
CLK
1 GHZ
REF
1 GHz
J3
FRAC-N
1 GHz In
J6
J1
C SAMPLER
750 MHz
4
PROGRAMMABLE
DIVIDER
750 MHz
256
M
DATA
M
6
4 < M < 51
- -
cw
fm
PULSE MOD
2P
F
+ / -
¦
P = 8, 9, or 10
cw
fm
750 MHz
30-70 MHz
600-735 MHz
765-900 MHz
2.93 MHz Steps
f
s
f = N * f + f
yos if
f
if
LO
5 < N < 9
- -
F
¦
ARB_REF
IF
S
RF
J3
f
yo
CLOCK IN
DATA IN
SYNC IN
PATTERN
TRG
H DUAL ARBITRARY WAVEFORM GENERATOR BOARD
DSP
RAM
I/O DATA BUS
PLL_ON
SOCLK 1
SOCLK 0
POL_LATCH
EVENT 1 OUT
EVENT 2 OUT
NSGEND
SQADV
WFCNT
CONTROL
LOGIC
DATA
SEQUENCER
RAM
MEMORY
Q
RAM
DATA
I
RAM
I/O DATA BUS
Q
DAC
I
DAC
REFERENCE
PLL_CLOCK
SOCLK 1
SOCLK 0
DATA
SWITCH
EXT_CLK
EXT_DATA
EXT_SYNC
PATTERN_TRG
MEMORY
POL
LATCH
Q_OUT
I_OUT
sk784b
BURST_PULSE
ESG-DP SERIES RF BLOCK DIAGRAM (OPTION UND)
ESG Family Signal Generators
2Assembly-Level Troubleshooting with
Block Diagrams
This chapter provides the block diagrams and information necessary for you to test and
troubleshoot the major assemblies of your signal generator.
Service Guide2-1
Assembly-Level Troubleshooting with Block DiagramsESG Family Signal Generators
Before You Begin Troubleshooting
Before You Begin Troubleshooting
Be sure to review the warning and caution statements described in Chapter 7 prior to
troubleshooting your signal generator.
Using this Chapter with Service Software
Some block diagrams in this chapter are accompanied by a table for use with the
automated service software that came with your signal generator. These tables list the
signal generator’s test conditions and the expected ABUS node voltages. The service
software has a utility program which measures and displays the node voltages for each
test. Refer to your signal generator’s calibration guide for information on using the
software.
The block diagrams and ABUS node tables are arranged in the following order:
A7 DBMIC BASEBAND GENERATOR BLOCK DIAGRAM (OPTIONS UN8 and UN9)
REFERENCE
P1-84
FROM MOTHERBOARD
/CPU
13 MHz
10 MHz DIG
J3
P403
REF SELECT
DIVIDE
GENERATOR INTERFACE
P3-6
P3-8
P3-10
P3-12
P3-14
P3-18
P3-20
P1-85
P1-49
P1-100
P1-50
P2-6
P2-4
P10-8,9,
10,11,12,
13,14,15
P6-12,13,
14,15,16,
17,18,19
BURST_GATELINT_CLK_EN
ADJ_TSLEXT_CLK_EN
EXT_DATALBBG_EN
EXT_SYNC
EXT_CLK
BBG_INT_CLK
BBG_EN
BBG_TRIG_INT
DATA
SYNC
CLK
ALT_PWR_IN
PATTERN_TRG
I_DIRECT
Q_DIRECT
6
8
10
12
14
18
20
BURST MOD
MASTER CLOCK PLL
BURST_PLS
CONTROL
LOGIC
15
ENVL_LATCH
LATCH_DATA
BURST_TC
MASTER_CLK
L_BURST
+10V_REF
ALC_HOLD_DIR
BURST_PULSE_DIR
ALT_PWR_DIR
ADJ_TS_PWR_IN
BURST
ENVELOPE
CONTROL
&
RAM
15
ENVELOPE
DATA
DAC_EN
LOOP FILTER
&
LEAD/LAG
DIG_BUS_INT
(PLL UNLOCKED)
PLL_T UNE
ABUS
PLL T UNE
60 T O 120 MHz
VCO
VCO
ENABLE
PLL
DIVIDERS
30 T O
60 MHz
MASTER CLOCK
P1-35
PLL LOCK SIG
PLL CLK
&
PLL REF
LCLK
ABUS
F
REF
DIGITAL MODULATOR IC
BURST
ABUS
BURST MOD
SWITCH
AND
FILTERS
BURST_ENVELOPE
BURST_PULSE
INTL_ALC_HOLD
L_DCC_ALT_PWR_SEL
P1-57
P1-30
P1-31
P1-80
Q DATA
PLL_CLOCK
BBG_BIT_CLK
16
EXT_BURST
2
BURST_GATE
ADJ_TS_PWR_IN
L_BURST
RC TIME
CONSTANT
DATA
ABUS
RC TIME
CONSTANT
BUFFERED_DATA_IN
SYMBOL_SYNC
P3-16
P2-2
FIR
PRE-MOD
FILTER
DATA/SYMBOL
GENERATOR
DIGITAL
INTERPOLATOR
GENERATION
14
CLK_OUT
DATA_OUT
SYNC_OUT
LATCH DATA BUS
DATA_EN_OUT
EVENT1_OUT
I DATA
GENERATION
14
P2-14
P2-12
P2-16
P2-10
P2-8
Q
DAC
ADJ
DAC
DAC
I
14 MHz
Q
OFFSET ADJUST
Q
GAIN ADJUST
I
GAIN ADJUST
I
OFFSET ADJUST
14 MHz
RECONSTRUCTION
FILTER
RECONSTRUCTION
FILTER
Q_OFFSET
I_OFFSET
ABUS
J2
Q_OUT
P1-53
AUD 2
P1-4
J1
I_OUT
P1-2
AUD 1
P1-55
P1-6
POWER SUPPLY INPUTS
P1-9
P1-14,64
+10V
REF
P1-16
P1-17,66,67
P1-12
P1-62
P1-13,63
P1-1,7,54,56
P1-22,28,34,
40,46,69,75,
81,87,93 ,99
REG
3V
DIGITAL INTERFACE
P1-33
P1-82
P1-83
P1-32
P1-24
P1-74
P1-25
P1-26
P1-76
P1-27
P1-77
P1-78
P1-29
P1-79
P1-36
P1-19
P1-20
P1-70
P1-21
P1-71
P1-72
P1-23
P1-73
EXT SELECT
L EXT STROBE
EXT RD L WR
EXT RE SET
IAB0
IAB1
IAB2
IAB3
IAB4
IAB5
IAB6
IAB7
IAB8
IAB9
IAB10
EXT_DO
EXT_D1
EXT_D2
EXT_D3
EXT_D4
EXT_D5
EXT_D6
EXT_D7
SELECT
STROBE
READ/LWRITE
RESET
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
D0
D1
D2
D3
D4
D5
D6
D7
+10 VREF
CLK
SELECT
DATA
DIG_ BUS_ INT
(PLL UNLOCKED)
+32V
+15V
+5VA
+3.3VF
-5.2V
-5V
-15V
ANALOG
COMMON
DIGITAL
COMMON
EEPROM
CONTROL
LOGIC
LATCHED
ADDRESS
LATCHED
DATA
sk758b
A7 DBMIC BASEBAND GENERATOR BLOCK DIAGRAM (OPTIONS UN8 and UN9)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A8 Data Generator Block Diagram (Options UN3 & UN4)
A8 Data Generator Block Diagram
(Options UN3 & UN4)
Service Guide2-13
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A8 Data Generator - Rev. A & B Block Diagram (Options UN8 & UN9)
A8 Data Generator - Rev. A & B Block Diagram
(Options UN8 & UN9)
Service Guide2-15
A8 FLEX GENERATOR BLOCK DIAGRAM
REV. C & D (OPTION UN8 & UN9)
Burst Pulse
Intl ACL Hold
L DCC Alt Pwr Sel
P1-30
P1-31
P1-80
P1
Motherboard
Digital Card Cage
Connector
POWER SUPPLY INPUTS
P1-14, 64
P1-16, 17, 66, 67
TP100
Control
Data
Address
3.3V
CPU BUS
+15VF
+5VD
MPU
14.7456 MHz
Configuration
Flash 4MB
Boot ROM
Microprocessor
+3.3V to +5V
Conversion
RxTx
UART
162550
Identification
Clock
DRAM
4MB
CPU
Interface
Control
Board
EEPROM
MPU Clock
Configuration "A"
Configuration "B"
Configuration "C"
IRQ
and
Status
Symbol Sync OutSymbol Sync Out
Clock OutClock Out
Data OutData Out
Event 2
Event 1
Ext Alt Power
Ext Pattern Trigger
Data Configuration
Field Programmable
Gate Array "C"
External RAM
32K X 8 X 2 pages
FPGA-to-FPGA BUS
MPU BUS
Data Generator
RAM
8MB X 8
Data Configuration
Field Programmable
Gate Array "B"
Data Configuration
Field Programmable
Gate Array "A"
External RAM
32K X 8 X 2 pages
Global Clock
&
Global Input Mux
Global Clocks and Inputs
Baseband and External I/O
Ext Burst Gate
I Data 0
I Data 1
I Data 2
I Data 3
Q Data 0
Q Data 1
Q Data 2
Q Data 3
Burst Gate
Alt Power
Data
Ext Symbol Sync
Ext Clock
Int/Ext Clock Select
BB Gen Enable
Ext Data
Ext Clock
Ext Symbol Sync
Trigger
10 MHz Reference
P2-16P2-16
P2-14P2-14
P2-12P2-12
P2-10
P2- 8
P2- 6
P2- 4
P2- 2
P4- 2
P4- 4
P4- 6
P4- 8
P4-10
P4-12
P4-14
P4-16
P3- 6
P3- 8
P3-10
P3-12
P3-14
P3-18
P3-20
P1-16Bit Clock
P3-2Sub I Clock
P1-49
P1-50
P3-100
P3-85
P3-84
sk786b
P1-1, 7, 54, 56
P1-22, 28, 34,
40, 46, 69, 75,
81, 87, 93, 99
Analog
Common
Digital
Common
A8 FLEX GENERATOR BLOCK DIAGRAM
REV. C & D (OPTION UN8 & UN9)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A9 Output ABUS Nodes (ESG-A Series)
A9 Output ABUS Nodes (ESG-A Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
A9 Output ABUS Nodes (ESG-A Series) (1 of 2)
Node Voltages (Corrected Values in Vdc)
Test Conditions
PTAT
ALC_DET
−0.02
POW_REF_1
b
≈5
b
≈5
POW_REF_2
c
≈ 5
c
≈ 5
LOOP_INT
0.3 to
1.7
≈−10≈ 8.5 to
≈ 8.5 to
9.9
9.9
PRESET; 0 dBm; RF On; No Modulation
PRESET; 0 dBm; RF Off; No Modulation
ALC_MOD
a
≈ 0.7
d
≈ 0.1
BURST_MOD
≈ 19−0.23 to
≈ 190.0
PRESET; 20 dBm; RF On (Unleveled)≈ 20≈ 19≈−0.5≈ 2.3≈ 4.1≈ 12≈ 8.5 to
9.9
Frequency Set to heterodyne Band;
PRESET; Freq ≤ 249.9 MHz; 0 dBm;
RF On; No Modulation
+5.0 Vdc applied to Q INPUT:
PRESET; 0 dBm; RF On; I/Q On; I/Q
Source EXT I/Q; I Input =No Connection;
Burst Envelope On; If −0.5Vdc is applied
to Q INPUT, the Q node changes to
negative voltage
+1 Vdc Applied to EXT 1 INPUT:
PRESET; 0 dBm; RF On; AM On;
AM Depth 100%; AM Source Ext 1 DC
a. If board E4400-60038 then Abus ≈ 0.3.
If board E4400-60141 then Abus ≈ 1.3.
b. If Option UNB then Abus ≈ 3.9.
c. If Option UNB then Abus ≈ 4.2.
d. If board E4400-60141 then Abus ≈ 1.3.
≈ 0.2 to
0.5
≈ 0.6
(20 w/
no Q
Input)
≈ 1≈ 19≈ 0
≈ 194.1 to
4.8
≈ 4.8 to
5.6
≈−0.08
to −0.2
(≈ 0.1
w/ no Q
Input)
≈ 4.3 to
5.0
≈ 4.5
≈ 4.6
≈ 4.3 to
5.0
b
≈ 4.8
b
≈ 4.8
≈ 0.0≈ 8.5 to
c
≈−0.2
to 0.6
(≈ 12 w/
no Q
Input)
c
9.9
≈ 8.5 to
9.9
≈ 8.5 to
9.9
Service Guide2-19
Assembly-Level Troubleshooting with Block DiagramsESG Family Signal Generators
A9 Output ABUS Nodes (ESG-A Series)
A9 Output ABUS Nodes (ESG-A Series) (2 of 2)
Node Voltages (Corrected Values in Vdc)
Test Conditions
I
PRESET; 0 dBm; RF On; No Modulation≈ 0.7≈ 0
PRESET; 0 dBm; RF Off; No Modulation≈ 0.7≈ 0
PRESET; 20 dBm; RF On (Unleveled)≈ 0.7≈ 0
Q
PRE_LEVEL
a
≈ 2.1
d
≈ 2.1
a
≈ 2.1
QUAD
≈−1.8−0.22
≈−1.8−0.22
≈−1.8
b
to
−0.05
b
to
−0.05
−0.3 to
−0.19
GND
GAIN_DET
0.0−0.52
0.0≈ −0.52
b
0.0≈ 2.3
REF_AM
c
to
0.3
c
to
0.3
Frequency Set to heterodyne Band;
PRESET; Freq ≤ 249.9 MHz; 0 dBm;
RF On; No Modulation
+5.0 Vdc applied to Q INPUT:
PRESET; 0 dBm; RF On; I/Q On; I/Q
Source EXT I/Q; I Input =No Connection;
Burst Envelope On; If −0.5Vdc is applied
to Q INPUT, the Q node changes to
negative voltage
+1 Vdc Applied to EXT 1 INPUT:
PRESET; 0 dBm; RF On; AM On;
AM Depth 100%; AM Source Ext 1 DC
a. If board E4400-60155, 60141 or 60038 then Abus ≈ 3.
b. If board E4400-60038 then Abus ≈ 1.2.
c. If Option UNB then Abus ≈ 0.8.
d. If board E4400-60038 then Abus ≈ 5.0.
If board E4400-60155 or 60141 then Abus ≈ 3.
e. If board E4400-60155 or 60141 then Abus ≈ 4.
f. If board E4400-60155 or 60141 then Abus ≈ 3.
g. If Option UNB then Abus ≈ 1.4.
≈ 0.44≈ 0
≈ 0.0≈ 1.1
≈ 0.7≈ 0
≈ 2
≈ 2
≈ 2.1
e
f
≈−3
≈−1.8≈0.6
a
≈−1.8≈ −0.20.0
≈−0.04
(0.0 w/
no Q
Input)
b
0.0−0.1 to
0.00.2 to
0.6
0.9
≈ 0.9
g
2-20Service Guide
A9 OUTPUT BLOCK DIAGRAM (ESG-A SERIES)
250 to 4000 MHz
RF IN
>+10 dBm
FROM:
SYNTHESIZER
ALC MOD DRIVE
CLOSED =
RF PATH
PRELEVEL
ABUS
PRELEVEL DET
2400-4000MHz
2400 MHZ LPF
1550-2400
1550 MHZ LPF
J4
1000 MHZ LPF
628 MHZ LPF
396 MHZ LPF
1000-1550
628-1000
396-628
256-396
250 MHz TO 4000 MHz
0 dBm +/- 5dB
BURST MOD
DRIVE
PRELEVEL REF
DAC
ALC MOD
ALC MOD
DRIVE
+
GAIN ADJ DET
1 GHz REFERENCE
FROM: REFERENCE
BURST MOD
P1-19
ASSY P1-19
PRELEVEL MOD DRIVE
P3-4
TO: SYNTHESIZER P3-17
F >250 MHz
F < 250 MHz
700 - 1050 MHz
BPF
1GHZ
MIXER
300 MHz
LPF
LO
F >250 MHz
F <250 MHz
DET
VOLTAGE
DET BW
SEL
.250 TO 4000 MHz
MAX POWER >17 dBm
TO: STEP ATTENUATOR
ASSY J2
ALC DETECTOR
VOLTAGE
J6
RF OUT
ALC REFERENCE
DET OFFSET
DET
ALC REF
DAC
ALT ALC REF
DAC
DAC
ALC DET
ABUS
ALC REF
SELECT
CLOSED=
OPEN LOOP
BULK R
ADJUSTMENT
LOG
AMP
PWR REF
OPEN=
OPEN LOOP
IN BAND AM
ABUS
LOG DET
REFERENCE + AM
REF + AM
LOG OFFSET
REF AM
ABUS
DAC
OPEN =
HOLD ALT INT
P2-10
RF OFF MAIN INT
OPEN =
HOLD MAIN INT
CLOSED =
RF OFF ALT INT
L ALT PWR SEL
+V
BW SELECT
+
_
BW SELECT
+
_
ALT POWER
SELECT LOGIC
ALC UNLEVELED
DETECTOR
ALC MOD BIAS
L_UNLEVELED
DAC
LOOP INT
ABUS
+V
OPEN =
OPEN LOOP
CLOSED =
RF OFF (ALC MOD)
-15V
ALT POWER SELECT
ALC REF SELECT
ALC MOD
ALC MOD
DRIVER
ABUS
ALC
MOD
DRIVE
P2-6,21
P2-5,20
P2-14,29
P2-3,18
P2-1,17
P2-1,16
P2-15,30
CLK OUT P2-24
DATA P2-11
ENABLE/INTERRUPT
P2-25
POWER SUPPLIES INPUTS
+10V REG
FILTER
FILTER
FILTER
FILTER
FILTER
ABUS
+15VF
+9VF
+5VF
-6VF
-15VF
GND
ANALOG COMMON
DIGITAL COMMON
DIGITAL INTERFACE
SERIAL I/O
CLK
DATA
ENABLE/INTRPT
+5V
+5V
L UNLEVELED
+5V
INT 1
INT2
INT3
INT4 (Serial Data)
+10V
8.5 TO 9.9V
TEMPERATURE
COMPENSATION
POWER SUPPLY
CLK
SELECT
DATA
PTAT
ABUS
-PTAT
ABUS
P1-4
DIGITAL
CONTROL
EEPROM
MUX
+PTAT
P1-15
ALC MOD 1
BURST MOD
LOOP INT
REF PLUS AM
PRELEVEL DRIVE
ALC DET
PWR REF
+PTAT
LIN_AM_ MOD
P1-2
FROM: REFERENCE
ASSY
P3-17
AM INPUT
AMP
LOG
P1-17
P1-6
EN LIN AM
BURST MOD DRIVE
FADE ENVELOPE
(NOT USED)
BURST ENVELOPE
(NOT USED)
EN LIN BURST
EN LOG BURST
FEED FORWARD AM
REF
L RF OFF (BURST MOD)
FROM: REFERENCE ASSY
P3-7
BURST GAIN
DAC
BURST MOD OFFSET
P2-23
BURST EN
DAC
BURST MOD BIAS
PULSE MOD
REF + AM
DAC
BURST MOD
ABUS
BURST
MOD
DRIVER
&
BURST
MOD
DRIVE
CLOSED =
RF OFF
(BURST MOD)
-6V
DEEP AM LEVEL DETECTOR
P2-22
ALC HOLD
L ALC HOLD
L HOLD ALC
L RF OFF ALC MOD
DEEP AM MOD
&
ALT POWER SELECT
FEED FORWARD AM
HOLD MAIN
INT
HOLD ALT
INT
sk785b
A9 OUTPUT BLOCK DIAGRAM (ESG-A SERIES)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A9 Output ABUS Nodes (ESG-D Series)
A9 Output ABUS Nodes (ESG-D Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
A9 Output ABUS Nodes (ESG-D Series) (1 of 2)
Node Voltages (Corrected Values in Vdc)
Test Conditions
PTAT
ALC_DET
−0.02
POW_REF_1
b
≈5
b
≈5
POW_REF_2
c
≈ 5
c
≈ 5
LOOP_INT
0.3 to
1.7
≈−10≈ 8.5 to
≈ 8.5 to
9.9
9.9
PRESET; 0 dBm; RF On; No Modulation
PRESET; 0 dBm; RF Off; No Modulation
ALC_MOD
a
≈ 0.7
d
≈ 0.1
BURST_MOD
≈ 19−0.23 to
≈ 190.0
PRESET; 20 dBm; RF On (Unleveled)≈ 20≈ 19≈−0.5≈ 2.3≈ 4.1≈ 12≈ 8.5 to
9.9
Frequency Set to heterodyne Band;
PRESET; Freq ≤ 249.9 MHz; 0 dBm;
RF On; No Modulation
+5.0 Vdc applied to Q INPUT:
PRESET; 0 dBm; RF On; I/Q On; I/Q
Source EXT I/Q; I Input =No Connection;
Burst Envelope On; If −0.5Vdc is applied
to Q INPUT, the Q node changes to
negative voltage
+1 Vdc Applied to EXT 1 INPUT:
PRESET; 0 dBm; RF On; AM On;
AM Depth 100%; AM Source Ext 1 DC
a. If board E4400-60038 then Abus ≈ 0.3.
If board E4400-60141 then Abus ≈ 1.3.
b. If Option UNB then Abus ≈ 3.9.
c. If Option UNB then Abus ≈ 4.2.
d. If board E4400-60141 then Abus ≈ 1.3.
≈ 0.2 to
0.5
≈ 0.6
(20 w/
no Q
Input)
≈ 1≈ 19≈ 0
≈ 194.1 to
4.8
≈ 4.8 to
5.6
≈−0.08
to −0.2
(≈ 0.1
w/ no Q
Input)
≈ 4.3 to
5.0
≈ 4.5
≈ 4.6
≈ 4.3 το
5.0
b
≈ 4.8
b
≈ 4.8
≈ 0.0≈ 8.5 to
c
≈−0.2
to 0.6
(≈ 12 w/
no Q
Input)
c
≈ 8.5 to
9.9
9.9
≈ 8.5 to
9.9
Service Guide2-23
Assembly-Level Troubleshooting with Block DiagramsESG Family Signal Generators
A9 Output ABUS Nodes (ESG-D Series)
A9 Output ABUS Nodes (ESG-D Series) (2 of 2)=
Node Voltages (Corrected Values in Vdc)
Test Conditions
I
PRESET; 0 dBm; RF On; No Modulation≈ 0.7≈ 0
PRESET; 0 dBm; RF Off; No Modulation≈ 0.7≈ 0
PRESET; 20 dBm; RF On (Unleveled)≈ 0.7≈ 0
Frequency Set to heterodyne Band;
PRESET; Freq ≤ 249.9 MHz; 0 dBm;
RF On; No Modulation
+5.0 Vdc applied to Q INPUT:
PRESET; 0 dBm; RF On; I/Q On; I/Q
Source EXT I/Q; I Input =No Connection;
Burst Envelope On; If −0.5Vdc is applied
to Q INPUT, the Q node changes to
negative voltage
+1 Vdc Applied to EXT 1 INPUT:
PRESET; 0 dBm; RF On; AM On;
AM Depth 100%; AM Source Ext 1 DC
≈ 0.44≈ 0
≈ 0.0≈ 1.1
≈ 0.7≈ 0
Q
PRE_LEVEL
a
≈ 2.1
d
≈ 2.1
a
≈ 2.1
e
≈ 2
f
≈ 2
a
≈ 2.1
QUAD
GAIN_DET
≈−1.8−0.22
≈−1.8−0.22
≈−1.8
≈−3
≈−1.8≈0.6
≈−1.8≈ −0.20.0
b
to
−0.05
b
to
−0.05
−0.3 to
−0.19
≈−0.04
(0.0 w/
no Q
Input)
0.0−0.52
0.0≈ −0.52
b
0.0≈ 2.3
b
0.0−0.1 to
0.00.2 to
GND
REF_AM
c
to
0.3
c
to
0.3
0.6
0.9
g
≈ 0.9
a. If board E4400-60155, 60141 or 60038 then Abus ≈ 3.
b. If board E4400-60038 then Abus ≈ 1.2.
c. If Option UNB then Abus ≈0.8.
d. If board E4400-60038 then Abus ≈ 5.0.
If board E4400-60155 or 60141 then Abus ≈ 3.
e. If board E4400-60155 or 60141 then Abus ≈ 4.
f. If board E4400-60155 or 60141 then Abus ≈ 3.
g. If Option UNB then Abus ≈ 1.4.
2-24Service Guide
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A9 Output ABUS Nodes (ESG-AP, & ESG-DP Series)
A9 Output ABUS Nodes
(ESG-AP, & ESG-DP Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
ALC MOD 1
BURST MOD
LOOP INT
REF PLUS AM
PRELEVEL DRIVE
QUAD LOOP
GAIN ADJUST DET
I
Q
ALC DET
PWR REF
+PTAT
ASSY
2400-4000MHz
2400 MHZ LPF
1550-2400
1550 MHZ LPF
1000 MHZ LPF
628 MHZ LPF
396 MHZ LPF
EXT I MOD
P3-19
FROM: I INPUT
EXT Q MOD
P3-8
FROM: Q INPUT
1000-1550
628-1000
396-628
256-396
FROM: REFERENCE
ASSY
P3-6
250 MHz TO 4000 MHz
0 dBm + -5dB
I MOD DRIVE
P3-15
CAL
VOLTAGES
Q MOD DRIVE
CAL
VOLTAGES
BURST MOD
DRIVE
INT_I_MOD
EXT_I_MOD
EXT_Q_MOD
INT_Q_MOD
EXT_Q_MOD
EXT_I_MOD
GAIN DETECTOR
ABUS
ALC MOD
I MOD SELECT
Q MOD SELECT
ALC MOD
DRIVE
GAIN ADJ DET
BURST MOD
1 GHz REFERENCE
FROM: REFERENCE
I OFFSET
DAC
I GAIN
REF
DAC
Q OFFSET
DAC
Q GAIN
REF
DAC
P1-19
ASSY P1-19
F >250 MHz
F < 250 MHz
700 - 1050 MHz
BPF
MIXER
1GHZ
I
STEP
ATTENUATOR
Q
STEP
ATTENUATOR
300 MHz
LPF
LO
F >250 MHz
F <250 MHz
ABUS
ABUS
I MOD DRIVE
Q MOD DRIVE
DET
VOLTAGE
DET BW
SEL
.250 TO 4000 MHz
MAX POWER >17 dBm
TO: STEP ATTENUATOR
ASSY J2
LIN_AM_ MOD
P1-2
FROM: REFERENCE
ASSY
P3-17
ALC DETECTOR
J6
RF OUT
ALC REFERENCE
AM INPUT
AMP
LOG
P1-17
P1-6
FROM: BASEBAND
GENERATOR ASSY
P301-57
DET
VOLTAGE
ALC REF
DAC
ALT ALC REF
DAC
DET OFFSET
DAC
ALC DET
ABUS
CLOSED=
OPEN LOOP
ALC REF
SELECT
EN LIN AM
BURST MOD DRIVE
FADE ENVELOPE
(NOT USED)
BURST ENVELOPE
BULK R
ADJUSTMENT
LOG
AMP
PWR REF
OPEN=
OPEN LOOP
IN BAND AM
EN LIN BURST
ABUS
EN LOG BURST
LOG DET
REFERENCE + AM
FROM: REFERENCE ASSY
P3-7
REF AM
REF + AM
LOG OFFSET
DAC
L RF OFF (BURST MOD)
ABUS
FEED FORWARD AM
BURST GAIN
REF
DAC
P2-23
BURST EN
BURST MOD OFFSET
DAC
BURST MOD BIAS
DAC
PULSE MOD
REF + AM
BURST MOD
ABUS
BURST
MOD
DRIVER
&
ALC MOD DRIVE
OPEN =
HOLD MAIN INT
OPEN =
HOLD ALT INT
P2-10
FROM: BASEBAND GENERATOR
ASSY P301-80
BURST
MOD
DRIVE
CLOSED =
RF OFF
(BURST MOD)
-6V
DEEP AM LEVEL DETECTOR
CLOSED =
RF OFF MAIN INT
CLOSED =
RF OFF ALT INT
L ALT PWR SEL
P2-22
+V
BW SELECT
+
_
BW SELECT
+
_
ALC HOLD
FROM: BASEBAND
GENERATOR ASSY
P301-31
L ALC HOLD
L HOLD ALC
L RF OFF ALC MOD
DEEP AM MOD
+V
ALT POWER
SELECT LOGIC
&
ALT POWER SELECT
LOOP INT
ABUS
CLOSED =
RF OFF (ALC MOD)
ALT POWER SELECT
ALC REF SELECT
HOLD MAIN
INT
HOLD ALT
INT
ALC UNLEVELED
DETECTOR
ALC MOD BIAS
DAC
OPEN =
OPEN LOOP
-15V
FEED FORWARD AM
ALC MOD
ALC MOD
DRIVER
L_UNLEVELED
ABUS
ALC
MOD
DRIVE
sk772b
A9 OUTPUT BLOCK DIAGRAM
(ESG-D, ESG-DP, & ESG-DP SERIES)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A11 Reference ABUS Nodes (ESG-A & ESG-D Series)
A11 Reference ABUS Nodes
(ESG-A & ESG-D Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
A11 Reference ABUS Nodes (ESG-A & ESG-D Series)
Node Voltages (Corrected Values in Vdc)
Test Conditions
VTUNE
MOD1_OUT
PRESET; No Modulation0.000.002 to 4< 0.5< 0.50.000.0< 0.3
Frequency Set to Heterodyne Band:
PRESET; Freq ≤ 249.9 MHz;
No Modulation
+1 Vdc Applied to EXT 1 INPUT:
PRESET; FM On; FM Source Ext 1 DC
+1 Vdc Applied to EXT 2 INPUT:
PRESET; FM On; FM Source Ext 2 DC
1 Vpp @ 1 kHz Applied to EXT 1 INPUT:
PRESET; FM On; FM Source Ext 1 AC
1 Vpp @ 1 kHz Applied to EXT 2 INPUT:
PRESET; FM On; FM Source Ext 2 AC
+1 Vdc Applied to EXT 1 INPUT:
PRESET; AM On; AM Depth 100%;
AM Source Ext 1 DC
+1 Vdc Applied to EXT 2 INPUT:
PRESET; AM On; AM Depth 100%;
AM Source Ext 2 DC
1 Vpp @ 1 kHz Applied to EXT 1 INPUT:
PRESET; AM On; AM Depth 100%;
AM Source Ext 1 AC
≈−1.90.002 to 4< 0.5< 0.50.0≈ 2.2
≈ 00.002 to 4≈ 7.5< 0.50.0≈0
≈−1.90.002 to 4< 0.5< 0.5≈ 2.00.0
≈ 00.002 to 4≈ 7.5< 0.5≈ 00.0
0.00≈−1.92 to 4< 0.5< 0.50.0≈ 2.2
0.00≈ 02 to 4< 0.5≈ 7.50.0≈ 0
0.00≈−1.92 to 4< 0.5< 0.5≈ 2.00.0
MOD2_OUT
2 to 4> 0.15
MOD1_PK
MOD2_PK
LIN_AM
1GHZ_DET
FM_MOD
1 Vpp @ 1 kHz Applied to EXT 2 INPUT:
PRESET; AM On; AM Depth 100%;
AM Source Ext 2 AC
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A11 Reference ABUS Nodes (ESG-AP & ESG-DP Series)
A11 Reference ABUS Nodes
(ESG-AP & ESG-DP Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
A12 Synthesizer/Doubler ABUS Nodes
Node Voltages (Corrected Values in Vdc)
Test Conditions
F2
RF_OUT
TUNE
LOOP
10V
FM
PRESET; Freq 500.000001 MHz;
No Modulation
PRESET; Freq 750 MHz; No Modulation≈5.5−0.4 to
PRESET; Freq 1000 MHz; No Modulation≈ 7.2−0.4 to
+1 Vdc Applied to EXT 1 INPUT:
PRESET; FM On; FM Source Ext 1 DC
+1 Vdc Applied to EXT 1 INPUT:
PRESET; Freq < 250 MHz; FM On; FM
Source Ext 1 DC
≈ 4−0.4 to
−0.7
−0.7
−0.7
3.0 to 4.8≈−0.69.9 to
10.1
10.2 to
12.8
17.7 to
23.2
≈−1.59.9 to
10.1
≈−5.59.9 to
10.1
< 0.2
< 0.2
< 0.2
≈−2.0
≈−2.0
Service Guide2-37
ESG-D SERIES MODULATION AND SIGNAL INTERCONNECTS (2 of 2)
P2-2
PATTERN_TRIG
P2-4
ALT_PWR_IN
P2-6
EVENT (1) OUT
P2-8
USER_DATA_EN
P2-10
P2-1,3,5,7
9,11,13,15
10K
EXT_DATA
P1-49
CLOCK
P1-50
SYNC
P1-100
100pf
BERT BOARD
P1-1
BERT BOARD
P2-1
BERT BOARD
P3-1
BER CLK IN
(RP)
BER DATA IN
(RP)
BER GATE IN
(RP)
DOWN CONV
V1-1
DOWN CONV
V1-3
BER SYNC LOSS
(RP)
BER NO DATA
(RP)
BER MEAS END
(RP)
BER ERROR OUT
(RP)
BER TEST OUT
(RP)
PATTERN TRIG IN
(RP)
EVENT 1
(RP)
EVENT 2
(RP)
DATA OUT
(RP)
DATA CLK OUT
(RP)
SYMBOL SYNC OUT
(RP)
J1-J4, 49
J1-J4, 50
J1-J4, 85
J1-J4, 100
OPTION 300
DEMODULATOR
J
CLOCK
P10-1
DATA
P9-1
GATE
P8-1
EXT_CLOCK
P13-1
EXT_DATA
P12-1
EXT_GATE
P11-1
IF IN
P16-1
FREQ_REF
P7-1
SYNC_LOSS_IN
P5-2
NO_DATA_IN
P15-4
MES_END_IN
P5-6
ERR_IN
P5-8
TEST_IN
SPR_FUZZY_INO
P3-4
SPR_FUZZY_INO
P3-16
SPR_FUZZY_INO
P3-22
PATTERN_TRIG_IN
P2-4
EVENT_1
P2-8
EVENT_2
P2-10
DATA_IN
P2-12
DATA_CLK_IN
P2-14
SYMBOL_SYNC_IN
P2-16
P2-1, 3, 5, 7, 9, 11, 13, 15
EXT_DATA_IN
P1-49
EXT_CLK_IN
P1-50
BBG_TRIG_INT
P1-85
EXT_SYNC_IN
P1-100
sk792b
ESG-D SERIES MODULATION AND SIGNAL INTERCONNECTS (2 of 2)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A14 CPU/Motherboard ABUS Nodes
A14 CPU/Motherboard ABUS Nodes
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
A14 CPU/Motherboard ABUS Nodes
Node Voltages (Corrected Values in Vdc)
Test Conditions
≈7
LCD
INT_MOD
a
0.0010−6.0−5.29.00.00
P10V_REF
DISP
PRESET;
PRESET; Vary Display Brightness 1 to50−0.4to
−1.3
a. Approximately −5.3 V if jumpers for P104, P105, and P106 are set to negative position.
M6V
M5V
P9V
ACOM
Service Guide2-41
A14 CPU/MOTHERBOARD BLOCK DIAGRAM (1 OF 2)
CPU CLOCK
32.77 kHz
CLOCK
L PRESET
L HALT
SERIAL INTERFACE
FROM: AUXILIARY
INTERFACE
RECV
J8-2
CTS
J8-8
XMIT
J8-3
RTS
J8-7
+5V
J8-4
J8-5
(EXTERNAL)
+5V
RS-232
SERIAL
INTERFACE
L SERIAL I/O INT
NOT USED
L HP-IB INT
L RPG INT
NOT USED
L KEY INT
NOT USED
10 MHz DIG
COUNTER
CPU TRIG INT
L DSP INT
DIG BUS INT 1
DIG BUS INT 2
DIG BUS INT 3
DIG BUS INT 4
PULSE INT
L RPP INT
CTS
FLASH PROGRAM
VOLTAGE
+15V
ENABLE
FLASH
INTERNAL
DATA BUS
PROGRAM
INT ADDR
BUS
INTERNAL
DATA BUS
VOLTAGE
REG
SWITCH & LEDS
CPU
RXD
TXD
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
TP CLK
TPU0
TPU1
TPU2
TPU3
TPU4
TPU5
TPU6
TPU7
TPU8
TPU10
PROGRAM = +12V
TP303
SELF TEST
LEDS
CONFIG
SWITCH
FLASH
VPP
CPU INTERFACE
ADDRESS BUS
CPU DATA BUS
SERIAL I/O BUS
ADDRESS
BUFFERS
BOOT
ROM
DATA
BUFFERS
CPU DATA BUS
BUS
CONTROL
HP- IB INTERFACE
L HP-IB INT
MEM ADDR
BUS
INT ADDR
BUS
MEM DATA
BUS
INTERNAL DATA
BUS
INT CONT
BUS
INT ADDR
BUS
INTERNAL
DATA BUS
HP-IB
INTERFACE
MEMORY
MEM ADDR
BUS
MEM DATA
BUS
MEM ADDR
BUS
MEM DATA
BUS
MEM ADDR
BUS
MEM DATA
BUS
MEM ADDR
BUS
MEM DATA
BUS
LATN
LEOI
LSRQ
LREN
LIFC
LDAV
NDAC
NRFD
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
FLASH
MEMORY
1M X 32
EEROM
64K X 8
NONVOLATILE
RAM
128K X 16
RAM
512 X 16
J7-11
J7-5
J7-10
J7-17
J7-9
J7-6
J7-8
TO:
HP-IB
J7-7
J7-1
J7-2
J7-3
J7-4
J7-13
J7-14
J7-15
J7-16
SERIAL INTERFACE
(INTERNAL)
SERIAL I/O
BUS
INTERNAL
DATA BUS
L SERIAL
I/O INT
INT_I_MOD
P102
INT_I_MOD
P103
TRIGGER I/O
J11
TRIGGER
IN
CPU TRIG OUT
DCC TRIG OUT
DSP TRIG OUT
10 MHz IN/OUT
10 MHz
IN
FROM:
DAUGHTER
BOARD
SERIAL I/O
INTERFACE
J12
SYNTH ENABLE
OUTPUT ENABLE
ATTEN ENABLE
ATTEN CLK
ATTEN DATA
SPARE_I_DATA
SPARE_I_EN
TRIG
ENABLE
TRIG
ENABLE
J13
REF ENABLE
REF CLK
REF DATA
SNTH CLK
SYNTH DATA
OUTPUT CLK
OUTPUT DATA
INT_I_MOD1
INT_Q_MOD1
-15V
+5.2VD
TO:
DAUGHTER
BOARD
10 MHz
OUT
TO: DAUGHTER
BOARD
J5-24
J5-21
J5-18
J5-26
J5-23
J5-20
J5-76
J5-73
J5-70
J5-44
J5-45
J18
2
3
4
7
8
CPU TRIG INT
DCC TRIG INT
TRIG INT
J10
TRIGGER
OUT
TO PULSE
MODULATOR
OPTION 1E6
ATTENUATOR & RPP
INTERFACE
ATTEN
SENSE
HF
ATTEN
L DCC ALT
PWR SEL
TRIG INT
INTERNAL DATA BUS
L RPP INT
L RPP RESET
CONTROL
+15V
+12.5V
+5.2V
-12.5V
ACOM
EXT. DATA & CLOCK IN
P5
P6
P7
L = LF ATTEN
L=HF ATTEN
ELEC.
ATTEN_405_5
ATTEN_5A_10
ATTEN_10A_40
ATTEN_10B_20
ATTEN_40A_60
ATTEN_5B_XX
ATTEN_20_XX
ATEN XX
ATTEN ENABLE
ATTEN CLK
ATTEN DATA
L RPP INT
L RPP RESET
JI-49
J2-49
DATA
J3-49
J4-49
JI-50
CLOCK
J2-50
J3-50
J4-50
JI-100
J2-100
SYMB_SYNC
J3-100
J4-100
MECH.
J14-20
J14-19
J14-18
J14-16
J15-2
J14-12
J15-1
J14-1
J14-14
J15-3
J14-15
J15-5
J14-13
J15-4
J14-8
J14-17
J14-11
J14-10
J14-9
J14-7
J14-6
J14-5
J14-4
J14-3
J14-2
ANALOG TO DIGITAL CONVERTER (ADC)
TP703
ABUS
ABUS RTN
TP702
+
DIGITAL SIGNAL PROCESSOR (DSP)
16 MHz
CLOCK
DSP/CPU
+5V
INTERFACE
ADC
DSP DATA BUS
TRIG INT
SERIAL INTERFACE
INTERNAL DATA BUS
INT ADDR BUS
ADC IN
TP704
SWEEP RAMP
BUF ABUS
+10V REF
RESET
BUF ABUS
DAC
DIGITAL
SIGNAL
PROCESSOR
SWEEP RAMP
A BUS
TP701
CLK OUT
DSP ADDR BUS
INTERNAL MODULATION DAC
SERIAL INTERFACE
J9
SWEEP
OUT
L DSP INT
DSP TRIG
OUT
DAC
TP705
DSP RAM
DSP ADDR BUS
DSP DATA BUS
+
DSP
RAM
32K X 8
TP706
INT MOD
ABUS
TO: DAUGHTER
BOARD
sk789b
A14 CPU/MOTHERBOARD BLOCK DIAGRAM (1 0F 2)
A14 CPU/MOTHERBOARD BLOCK DIAGRAM (2 OF 2)
LCD CONTROLLER
14.32 MHz
CLOCK
LCD DATA
CPU DATA BUS
BUFFER
LCD DRIVER VOLTAGE
(CONTRAST)
+10 VREF
INTERNAL DATA BUS
DAC
LCD BRIGHTNESS DRIVER
(FLUORESCENT)
DISPLAY ENABLED
+10 VREF
INTERNAL DATA BUS
OPEN=
DAC
RESET
LCD DATA BUS
MEM ADDR BUS
VARIABLE
POWER
SUPPLY
+5V
LCD
CONTROLLER
POLARITY
CONTROL JUMPERS
P104, 5, 6
CLOSED=
DISPLAY ENABLED
+
DISPLAY
ENABLE
+5VJ21-5
SHIFT
CLOCK
TO LCD DISPLAY
FLM
LP
P0
P1
P2
P3
P4
P5
P6
P7
LCD RAM INTERFACE
TP601
VLCD
ABUS
VDISP
ABUS
TP602
J21-4
J21-3
J21-1
J21-2
J21-11
J21-10
J21-9
J21-8
J21-15
J21-14
J21-13
J21-12
+5V
LCD RAM
256K X 16
J21-7
TO: LCD
J19-1
J19-2
J19-3
TO: LCD
KEYBOARD DECODER
J20-1
J20-3
J20-5
J20-7
J20-9
J20-11
J20-13
J20-15
FROM FRONT PANEL
KEYCOL 0
KEYCOL 1
KEYCOL 2
KEYCOL 3
KEYCOL 4
KEYCOL 5
KEYCOL 6
KEYCOL 7
INTERNAL DATA BUS
POWER ON
J20-20
FROM FRONT PANEL
ON/OFF SW
+15V STBY
RPG DECODER
FROM RPG
J20-14
J20-10
RPG A
RPG B
KEYBOARD
COLUMN
DECODER
KEYBOARD
ROW
LATCH
POWER
SWITCH
LATCH
RPG
DECODER
INTERNAL DATA BUS
KEYROW 0
KEYROW 1
KEYROW 2
KEYROW 3
KEYROW 4
KEYROW 5
KEYROW 6
KEYROW 7
L PWRON
PWR GREEN
STBY YELLOW
+5V
L RPG INT
INTERNAL DATA BUS
L KEY INT
TO FRONT PANEL
J20-17
J20-19
J20-21
J20-23
J20-25
J20-26
J20-24
J2-22
J6-1
TO PWR SUPPLY
J20-2
J20-4
J20-12
TO RPG
TO: FRONT
PANEL
POWER SUPPLY INPUTS
J6-17
FROM POWER SUPPLY
J6-20
J6-19
J6-2,3,
12,13
J6-18
+15V STANDBY
TP502
+15V
TP502
+12V
SUPPLY
+5.2V
FILTERING
TP502
-15V
SWITCHING POWER SUPPLIES
TP504
SWITCHING
+12V
+5.2VD
SUPPLY
NEGATIVE
SWITCHING
SUPPLIES
M5V
ABUS
M6V
ABUS
POWER RESET
POWER
RESET
+5.2VD
+5.2VD
J29-1
SENSE
LOW RESET
DS502
TP509
TP508
+15V STBY
+15V
+12V
TP506
DS502
-15V
+32V
DS503-H
-5.2V
DS503-G
-6V
L PRESET
L HALT
L STANDBY
+5.2VD
+5.2V
POWER SUPPLY REGULATORS
TP510
+15V
+15V
+10VREF
-15V
+12.5V
REG
TP501
+10V
REG
TP507
+9V
REG
DS504
DS505
-12.5V
REG
POWER SUPPLY DIAGNOSTICS
+32V
+15V
+12V
-15V
+5.2VD
POWER
SUPPLY
DIAGNOSTICS
DS503-A
LOW=+32V OK
LOW=+15V OK
LOW=+12V OK
LOW=-15V OK
NONVOLATILE MEMORY POWER
+15V STANDBY
+5.2VD
+5.1V
V BAT
SELECT
+3V
BT1
DS504
P10V_REF
ABUS
P9V
ABUS
TP511
VBAT
+12.5V
+10VREF
+9V
+12.5V
DS503-EDS503-BDS503-DDS503-C
FAN POWER SUPPLY
+12V
FAN+
+12V
FAN+
+5.2VD
J16-1
J16-2
J17-1
J17-2
INT ADDR BUS
INT DATA BUS
CONTROL BUS
DIGITAL CARD CAGE CONNECTIONSDAUGHTER BOARD CONNECTIONS
CPU INTERFACE
MNEMONIC
EXT D0
EXT D1
EXT D2
EXT D3
EXT D4
EXT D5
EXT D6
EXT D7
EXT RESET
EXT RD L WR
EXT L STROBE
EXT SELECT 1
EXT SELECT 2
EXT SELECT 3
EXT SELECT 4
DIG BUS INT 1
DIG BUS INT 2
DIG BUS INT 3
DIG BUS INT 4
IAB1
IAB2
IAB3
IAB4
IAB5
IAB6
IAB7
IAB8
IAB9
IAB10
J1 J2 J3 J4
24
242424IAB0
74747474
25252525
26262626
76767676
27272727
77777777
78787878
29292929
79797979
36363636
19191919
20202020
70707070
21212121
71717171
72727272
23232323
73737373
32
83
82
33
33
33
35
35
35
POWER SUPPLIES
MNEMONIC J1 J2 J3 J4
9999
+32V
14,64 14,64 14,64 14,64
+15V
15,65 15,65 15,65 15,65
+12V
16,17 16,17 16,17 16,17
+5.2V
66,67 66,67 66,67 66,67
12,62 12,62 12,62 12,62
-5.2V
13,63 13,63 13,63 13,63
-15V
22,28 22,28 22,28 22,28
DCOM
34,40 34,40 34,40 34,40
46,69 46,69 46,69 46,69
75,81 75,81 75,81 75,81
87,93 87,93 87,93 87,93
99999999
1,7 1,7 1,7 1,7
ACOM
54,56 54,56 54,56 54,56
CPU INTERFACE
MNEMONIC
10 MHz DIG
ABUS RTN
ALC GND
L ALC HOLD
AUD 1 (NOT USED)
AUD 2 (NOT USED)
BURST ENVELOPE
BURST PULSE
COUNTER
L DCC ALT PWR SEL
DCC TRIG OUT
DCC TRIG INT
FADE ENVELOPE
33
35
FM D10
FM D11
FM D12
FM D13
FM D14
FM D15
INT I MOD
INT I/Q MOD RTN
INT Q MOD
MOD STROB
PAREN SYNC
SWP READY
SWP STATUS
SWP RUN
J1 J2 J3 J4
59595959
+PTAT
84848484
4444
ABUS
5555
8888
31313131
6666
55555555
57575757
30303030
86868686
80808080
18181818
85858585
58585858
47474747
FM D0
91919191
FM D1
95959595
FM D2
90909090
FM D3
96969696
FM D4
41414141
FM D5
89898989
FM D6
45454545
FM D7
39393939
FM D8
94949494
FM D9
88888888
37373737
92929292
43434343
38383838
44444444
2222
3,52 3,52 3,52 3,52
53535353
97979797
42424242
48484848
98989898
49494949
SERIAL I/OSIGNALS
MNEMONICJ5
REF DATA
REF CLK
REF ENABLE
SYNTH DATA
SYNTH CLK
SYNTH ENABLE
OUTPUT DATA
OUTPUT CLK
OUTPUT ENABLE
18
21
24
20
23
26
70
73
76
POWER SUPPLIES
MNEMONICJ5
83
+32V
32,82
+15V
+9V
+5.2V
-5.2V
-6V
-15V
ACOM
33
34,84
30,31
80,81
35,85
37,87
36,86
4,10
16,22
28,51
57,63
69,75
43,47
49,96
+15V STBY
DCOM
MNEMONIC J5
10 MHz IN
10 MHz OUT
10 MHz RTN
ABUS RTN
ALC GND
L ALC HOLD
L ALT PWR SEL
AUD 1 (NOT USED)
AUD 2 (NOT USED)
BURST ENVELOPE
BURST PULSE
COUNTER
FADE ENVELOPE
INT I MOD
INT I/Q MOD RTN
INT Q MOD
MOD STROB
PAREN SYNC
SWP READY
SWP STATUS
SWP RUN
+PTAT
ABUS
FM D0
FM D1
FM D2
FM D3
FM D4
FM D5
FM D6
FM D7
FM D8
FM D9
FM D10
FM D11
FM D12
FM D13
FM D14
FM D15
INT MOD
40
97
99
98,100
93
92
91
17
29
48
46
42
79
15
41
55
60
56
11
5
61
62
6
12
7
13
14
59
8
64
58
50
44
45,94
95
54
9
3
53
2
sk790b
J29-2
JUMPER ACROSS
PINS TO RESET
A14 CPU/MOTHERBOARD BLOCK DIAGRAM (2 OF 2)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A20 Downconvertor Block Diagram (Option 300)
A20 Downconvertor Block Diagram (Option 300)
Service Guide2-47
A21 DEMODULATOR BLOCK DIAGRAM
(OPTION 300)
P16
Down Converter
IF IN
DAC
FIFO
ADC
TRIGGER
PULSE
DELAY
SERIAL
EPROM
P1-24,25,26,27,29,36,74,76,77,78,79
P1-20,21,23,79,71,72,73
P1-33
P1-83
P1-32
P1-82
P1-35
P1-49
P1-50
P1-100
P1-85
P1-84
+15V F 1
+5V REG
+15V F 2
-15V F
+15V
+5V A
-5V A
REG
REG
REG
REG
REG
+12.3V
-5V REG
+2.5V
+3.3V
+15V
P1-14
+15V
P1-64
-15V
P1-13,63
-15V
P1-16,17,66
+5V
P1-67
-5V
P1-12,62
IAB 10-0
D7-0
SEL n
R/WEn
RSTn
STRBn
Dig_BUS_INTn
DATA
DATA Clock
Symbol Sync
TRIGGER
10 MHz
Filter
Filter
Filter
Filter
Filter
Filter
P1
FPGA
DIG_BUS_INT1
D_RCV_TRG
16 BTT CLK (4.333 MHz)
TST BUS
I/O BUS
FPGA
DATA BUS
PATTERN TRIG IN (FRAME TRIG IN)
DATA I N
DATA CLOCK IN
SYMB SYNC IN
EVENT 1, 2
P2
Rear Panel
P6
VCXO_IN
SYNC LOSS
NO DATA
MEAS END
Err OUT
TEST IN
BIT CLOCK IN
SPR FUZZY IN0
SPR FUZZY IN1
SUB_BIT OUT
Clock
DATA
GATE
EXT Clock
EXT DATA
EXT GATE
FREQ REF
PLL
26 MHz
12
Clock
SRAM
80 MHz
INTERFACE
256k x 32
SYNC
FLASH
128 x 32
FLASH
256 x 32
DATA_X1
DATA_R1
DSP_TCLK0
DSP_INTn
DSP
DSP Emul
30 MHz
Clock
P3
2
4
6
8
TRIGGER/GATE
10
16
4
BBG
22
2
P10
P9
P8
P13
P12
P11
P7
DOWN
CONVERTER
POWER SUPPLY INPUTS
sk7106b
A21 DEMODULATOR BLOCK DIAGRAM
(OPTION 300)
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A23 Sampler ABUS Nodes (ESG-AP & ESG-DP Series)
A23 Sampler ABUS Nodes (ESG-AP & ESG-DP Series)
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
ESG Family Signal GeneratorsAssembly-Level Troubleshooting with Block Diagrams
A24 Frac-N/Divider ABUS Nodes (ESG-AP & ESG-DP Series
A24 Frac-N/Divider ABUS Nodes (ESG-AP & ESG-DP
Series
NOTEThe node voltages given in the following table are approximate values based
on a sample of signal generators. Your signal generator may not reflect these
exact values. Additionally, the resolution of these values varies from node to
node. As a guideline, interpret your measurements based on the number of
decimal places shown for the expected voltage.
ESG-D SERIES MODULATION AND SIGNAL INTERCONNECTS (2 of 2)
ESG Family Signal Generators
3Replaceable Parts
(ESG-A and ESG-D Series)
This chapter provides important ordering information and lists the part numbers for the
various replaceable parts, kits, and accessories available for your signal generator. This
chapter is also useful for locating and identifying assemblies and cables.
Service Guide3-1
Replaceable Parts (ESG-A and ESG-D Series)ESG Family Signal Generators
Ordering Information
Ordering Information
To order a part listed in the replaceable parts lists, do the following:
1. Determine the part number.
2. Determine the quantity required.
3. Mail this information to the nearest Agilent Technologies office or, in the U.S., call the
hotline number listed in the following section.
To order a part not listed in the replaceable parts lists, mail the following information to
the nearest Agilent Technologies office or, in the U.S., call the hotline number listed in the
following section.
1. the instrument model number
2. the serial number and options, if any (see rear panel)
3. a description of the part
4. a description of the part’s function
5. the quantity required
Call (800) 227-8164 to Order Parts Fast (U.S. Only)
When you have gathered the information required to place an order, contact Agilent
Technologies’ direct ordering team by calling the toll-free hotline number shown above.
Orders may be placed Monday through Friday, 6 AM to 5 PM (Pacific Stand ard Time).
The parts specialists have direct on-line access to replacement part s inventory
corresponding to the replaceable parts lists in this manual. Four day delivery time is
standard; there is a charge for hotline one-day delivery.
This information applies to the United States only. Outside the United States, you must
contact the nearest Agilent Technologies sales and service office. (Refer to Table 1-1 on
page 1-9.)
3-2
Service Guide
ESG Family Signal Generators Replaceable Parts (ESG-A and ESG-D Series)
Save Money with Rebuilt-Exchange Assemblies
Save Money with Rebuilt-Exchange Assemblies
Under the rebuilt-exchange assembly program, certain factory-repaired and tested
assemblies are available on a trade-in basis. These assemblies cost less than a new
assembly, and meet all factory specifications required of a new assembly.
The defective assembly must be returned for credit under the terms of the
rebuilt-exchange assembly program. The figure below illustrates the assembly exchange
procedure in flowchart format.
Assembly Exchange Procedure
Service Guide3-3
Replaceable Parts (ESG-A and ESG-D Series)ESG Family Signal Generators
Save Money with Rebuilt-Exchange Assemblies
Shipping the Defective Assembly Back to Agilent Technologies
1. When you receive the rebuilt assembly, be careful not to d amage the box in whic h it w as
shipped. You will use that box to return the defective assembly. The box you receive
should contain the following:
• the rebuilt assembly
• an exchange assembly failure report
• a return address label
2. Complete the failure report.
3. Place the failure report and the defective assembly in the box. Be sure to remove the
enclosed return addres s label.
4. Seal the box with tape.
If you are inside the United States, stick the preprinted retur n address label over the
label that is already on the box and return the box to Agilent Technologies. (Agilent
Technologies pays postage on boxes mailed within the United States.)
If you are outside the USA, do not use the retur n address label; instea d, address the bo x
to the nearest Agilent Technologies sales and service office. (Refer to Table 1-1 on
page 1-9.)
3-4
Service Guide
ESG Family Signal Generators Replaceable Parts (ESG-A and ESG-D Series)
Abbreviations Used in Part Descriptions
Abbreviations Used in Part Descriptions
This section defines the referenc e desi gnator s , abbr eviations, and option numbers t hat ar e
used in the part descriptions throughout this chapter.
Reference Designations
Abbreviations
Reference
Designator
Aassembly
ATattenuator
Bfan
DSlamp
Jelectrical co nn ector; jack
Pelectri cal connector; plu g
Wcable; transmission path; wire
AbbreviationDefinition
Assyassembly
Bdboard
BCberyllium
BNbuttonhead (screws)
CPUcentral processing unit
Definition
CWconical washer (screws)
CYc opper
Ddiameter
ESDelectrostatic discharge
EXTexternal
FLflathead (screws)
Ftfeet
Hexhexagonal
GPIBgeneral purpose i nt erface bus
HXhexagonal recess (screws)
Iin-phase
IDinside diameter
Llength
Service Guide3-5
Replaceable Parts (ESG-A and ESG-D Series)ESG Family Signal Generators
Abbreviations Used in Part Descriptions
AbbreviationDefinition
LFlow frequency
Mmeters or metric hardware
ODoutside diameter
PCpatch lock (screws) or printed circuit
PNpanhead (screws)
Qquadrature
Qtyquantity
REFreference
RFradio frequency
RFIradio frequency interference
RPPreverse power protection
SHsocket head cap (screws)
SMAsubminiature type-A
UN7
1E5Precision Frequency Reference
1E6High Performance Pulse Input
1EMRear Panel Connections
UN3Baseband Generator - 1 Meg
UN4Baseband Generator - 8 Meg
UN7Bit Error Rate Test
UN8Real-Time I/Q Baseband Generator - 1 Meg
UN9Adds 7 Meg RAM to UN8
UNAAlternate Timeslot Power
3-6
UNBHigh Power with Mechanical Attenuator
UNDDual Arbitrary Waveform Generator
Service Guide
ESG Family Signal Generators Replaceable Parts (ESG-A and ESG-D Series)
Major Assemblies
Major Assemblies
This section lists part numbers for the major assemblies in your signal generator. The
following instrument views are provided to help you locate specific assemblies.
• “Top View” on page 3-8
• “Top View (ESG-D Series - Option 300)” on page 3-10
• “Right Side Assemblies” on page 3-12
• “Disassembled Front Panel View” on page 3-13
• “Inside Rear Panel View” on page 3-14
Service Guide3-7
Replaceable Parts (ESG-A and ESG-D Series)ESG Family Signal Generators
Major Assemblies
A8E4400-601541Bd Assy-Flex Data Generator, 1 Meg (Option UN8)
A8E4400-69154Exchange Bd Assy-Flex Data Generator, 1 Meg (Option UN8)
A8E4400-601951Bd Assy-Flex Data Generator, 8 Meg (Option UN8+UN9)
A8E4400-69195Exchange Bd Assy-Flex Data Generator, 8 Meg (Option UN8+UN9)
A14E4400-602201Replacement Kit-CPU/Motherboard (serial no. prefixes < US3934/GB3934)
A14E4400-602251Replacement Kit-CPU/Motherboard (serial no. prefixes ≥ US3934/GB3934)
A14BT11420-03381Battery -Lithium
AT1E4400-600421Assy-Electronic Attenuator/RPP (Option UNA) replaced by E4400-60681
AT1E4400-606801Assy-Electronic Attenuator/RPP
Part NumberQtyDescription
(Options UN8 or UN8+UN9)
AT1E4400-606811Assy-Electronic Attenuator/RPP upgrade kit (for E4400-60042 and
E4400-6205)
A20E4400-602001Bd Assy-Downconvertor
A20E4400-692001Exchange Bd Assy-Downconvertor
A21E4400-602411Bd Assy-Demodulator
A21E4400-69199Exchange Assy-Demodulator
B1E4400-602181Assy-Fan, Small
B2E4400-600621Kit-Fan, Large (includes 2 foam strips)
3-10
Service Guide
ESG Family Signal Generators Replaceable Parts (ESG-A and ESG-D Series)
Major Assemblies
Figure 3-2Top View (ESG-D Series - Option 300)
Service Guide3-11
Replaceable Parts (ESG-A and ESG-D Series)ESG Family Signal Generators
Major Assemblies
Right Side Assemblies
Refer to Table 3-3 and Figure 3-3.
Table 3-3Replaceable Assemblies, Right Side
Reference
Designator
A9E4400-600381Bd Assy-Output (ESG-A series with serial no. prefixes
A9E4400-690381Exchange Bd Assy-Output (ESG-A series with serial no. prefixes
A9E4400-600031Bd Assy-Output (ESG-A series with serial no. prefix US3927/GB3927)
A9E4400-690031Exchange Bd Assy-Output (ESG-A series with serial no. prefix