The Z86318 is a member of the Z8
microcontrollers. This device offers on-board pull-up and
pull-down resistors (ROM mask-option programmable on a
nibble basis), a scalable trip-point buffer to accommodate
opto-transistor outputs, and high drive ports capable of up
to 20 mA current sinking per pin (3 pins maximum).
The Z86318 features I/O Ports (IOL = 20 mA at VOL =
0.8V, 3 pins max.) to provide increased current sinking capabilities. These devices also offer users a selection of
ROM mask options, which include a permanently enabled
Watch-Dog Timer that ensures operational reliability
across a broad range of application environments.
For applications requiring powerful I/O capabilities, the
Z86318 provides dedicated input and output lines that are
grouped into three ports. These ports can be configured by
means of ROM mask options (nibble-programmable) as
pull ups, pull downs, or neither. There are two basic address spaces available. Program Memory, and 124 bytes
of general-purpose registers.
On-Chip Oscillator (Crystal, Ceramic Resonator,
LC, or External Clock Drive)
■
Fast Instruction Pointer: 1.5 µ s @ 4 MHz
■
ESD Protection Circuitry
The Z86318 devices provide two on-chip 8-bit programmable counter/timers with a large number of user-selectable
modes. Each counter/timer is driven by its own 6-bit programmable prescaler. The Z86318 counter/timers off-load
system real-time tasks such as counting/timing and input/output data communications for increased system efficiency.
Notes: All Signals with a preceding front slash, “/”, are ac-
tive Low, e.g.; B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Power connections follow conventional descriptions below:
ConnectionCircuitDevice
PowerVCCVDD
GroundGNDVSS
IT
M
ICROCONTROLLER
1
DS96KEY0103 (8/96)
P R E L I M I N A R Y
1
2
Z86318
®
Z8
MCU 8-Bit Microcontroller
GENERAL DESCRIPTION (Continued)
Input
Port 3
Counter/
Timers (2)
Interrupt
Control
VSSXTALVDD
ALU
FLAG
Register
Pointer
Register File
144 x 8-Bit
Machine
Timing & Inst.
Control
Prg. Memory
3072 x 8-Bit (318)
2048 x 8-Bit (319)
Program
Counter
Port 2
I/O
(Bit Programmable)
Port 0
I/O
Figure 1. Z86318 Functional Block Diagram
P R E L I M I N A R Y
1
PIN DESCRIPTIONS
®
Z8
MCU 8-Bit Microcontroller
Z86318
P24
P25
P26
P27
VDD
XTAL2
XTAL1
P31
P32
1
2
3
4
Z86318
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P23
P22
P21
P20
VSS
P02
P01
P00
P33
Figure 2. Z86318 18-Pin DIP/SOIC
Pin Configuration
ABSOLUTE MAXIMUM RATINGS
Sym.ParameterMin.Max.Units
V
T
T
Note:
*Voltages on all pins with respect to Ground.
†See Ordering Information.
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
P R E L I M I N A R Y
3
Z86318
®
Z8
MCU 8-Bit Microcontroller
STANDARD TEST CONDITIONS
4
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground.Positive current flows into the referenced pin (Figure 3).
CAPACITANCE
TA = GND = 0V, f = 1.0 MHz, unmeasured pins returned to Ground.
and Fall Times
3TwCInput Clock Width6.0V475100ns[1]
4TwTinLTimer Input Low Width6.0V7070ns[1]
5TwTinHTimer Input High Width6.0V2.5TpC2.5TpC[1]
6TpTinTimer Input Period6.0V4TpC4TpC[1]
7TrTin,
TtTin
8TwILInt. Request Input
Timer Input Rise
and Fall Timer
6.0V100100ns[1]
6.0V7070ns[1,2]
Low Time
9TwIHInt. Request Input
6.0V2.5TpC2.5TpC[1,2]
High Time
10T wdtWatch-Dog Timer6.0V2424ms
11T
Notes:
1. Timing Reference uses 0.9 VDD for a logic 1 and 0.1 VDD for a logic 0.
2. Interrupt request through Port 3 (P33-P31).
POR
Power-On Reset Time6.0V66ms[1]
8P R E L I M I N A R Y
1
PIN FUNCTIONS
Z86318
Z8® MCU 8-Bit Microcontroller
XTAL1, XTAL2. Crystal in, crystal out (time-based input
and output, respectively). These pins connect a parallelresonant crystal, LC, or an external single-phase clock (4
MHz Max.) to the on-chip clock oscillator and buffer. Note:
XTAL1 has a pull-down resistor.
/OEN
Port 0 (P02-P00). Port 0 is a 3-bit, I/O programmable, bidirectional, CMOS-compatible I/O port. These three I/O
lines can be configured under software control to be input
or output (see Figure 5). When Port 0 is configured as an
input port, all lines have the capability to be globally configured (ROM mask option) for a 100K pull-down or pull-up
resistor. The pull-up/pull-down resistor can be disabled as
well. (No current is drawn if disabled.) Graphs showing
current versus pin voltage are shown in Figures 6 and 7.
Pull-Up
Enable
Pad
Out
In
Pull-Down
Enable
Figure 5. Port 0 Configuration
P R E L I M I N A R Y9
Z86318
Z8® MCU 8-Bit Microcontroller
PIN FUNCTIONS (Continued)
Figure 6. Typical Current Versus Pin Voltage Values
10P R E L I M I N A R Y
Z86318
1
Z8® MCU 8-Bit Microcontroller
Figure 7. Typical Current Versus Pin Voltage Values
P R E L I M I N A R Y11
Z86318
Z8® MCU 8-Bit Microcontroller
PIN FUNCTIONS (Continued)
Port 2 (P27-P20). Port 2 is an 8-bit, bit-programmable, bi-
directional, CMOS-compatible I/O port. P23-P20 can be
configured under software control to be input or output, independently. Note: Bits D3 and D4 of POIM register must
be set to 0. Bits programmed as outputs may be globally
programmed as either push-pull or open-drain via bit D0,
P3M register. P20 and P21 can be configured with a ROM
mask option for 10 Kohm pull-up/pull-down, or none. P22
and P23 can be configured with a ROM mask option for
100 Kohm pull-up/pull-down, or none (Figure 8). No cur-
/Open-Drain
/OEN
rent is drawn if pull-up/pull-down is disabled. Note: P23-20
are configured for pull-up/pull-down/none globally.
P24-P27 can be configured as a voltage divider. The voltage divider consists of an internal 25K pull-up resistor (Figure 9), and a 7.5K pull-down resistor. The zero trip-point input levels on P24-P27 are adjusted for connection to the
emitters of opto-transistors and switch at a voltage level of
0.4 VDD. All four of the voltage dividers are globally configured as enabled or disabled.
Pull-Up
Enable
Out
In
Pull-Down
Enable
Note: P20, P21: 10K Pull-Up/Down or none.
P22, P23: 100K Pull-Up/Down or none.
P23-20 are globally selected for Pull-Up/Down or none.
Figure 8. Port 2 P20-P23 Configuration
Pad
12P R E L I M I N A R Y
Z86318
1
Z8® MCU 8-Bit Microcontroller
Divenb
/Open-Drain
/OE
Out
In
Resistance Tolerance (0 - +40°C)
Typ.
7.5K8.9K
25K30K
Pull-Down
Pull-Up
Min.Max.
5.2K
18K
25K
7.5K
Pad
0.4 VDD
Trip Point Buffer
Figure 9. Port 2 P27-P24 Configuration
Port 3 (P33, P32, P31). Port 3 is a 3-bit, CMOS-compati-
ble port with three fixed input lines (P33–P31). These three
lines can also be used as the interrupt sources IRQ2,
IRQ1, and IRQ0. P31 can also be configured as a timer input.
All three lines can be configured globally by means of ma
ROM mask option for a 100 Kohm pull-up or pull-down resistor (Figure 10), or no pull-up/pull-down. No current is
drawn if pull-up/pull-down is disabled.
P R E L I M I N A R Y13
Z86318
Z8® MCU 8-Bit Microcontroller
PIN FUNCTIONS (Continued)
Pad
P31
Pull-Up
Enable
Data Latch
IRQ2, TIN
Pull-Down
/Enable
Pad
Pad
P32
P33
Pull-Down
/Enable
Pull-Up
Enable
Pull-Down
/Enable
Pull-Up
Enable
Data Latch
Data Latch
IRQ1
Figure 10. Port 3 P31-P33 Configuration
14P R E L I M I N A R Y
Z86318
1
Z8® MCU 8-Bit Microcontroller
The Z86318 MCU incorporates the following special features to enhance the Z8® architectural core for use in
mouse and trackball applications.
Reset. The Z86318 is reset in one of the following conditions: 1) Power-On Reset (POR), 2) Watch-Dog Timer
(WDT) Mode, 3) Stop-Mode Recovery source, and 4) LowVoltage Recovery. Other sources of Reset, ports are configured in an input mode, asynchronous of the clock. However, a clock is required to generate the internal reset that
resets the internal registers.
Auto POR circuitry is built into the Z86318, eliminating the
need for an external reset circuit to reset on power-on.
Table 2. Z86318 Control Registers
Reset Values
Addr.Reg.D7 D6 D5 D4 D3 D2 D1 D0 Comments
F1 TMR00000000
F2 T1UUUUUUUU
F3PRE1 UUUUUU00
F4 T0UUUUUUUU
F5PRE0 UUUUUUU0
F6*P2M 11111111Inputs after
A reset after a Low on P27 to exit STOP mode may
affect device reliability.
Program Memory. The Z86318 device can address up to
3 KB of internal program memory (Figure 11). The first 12
bytes of Program Memory are reserved for the interrupt
vectors. These locations contain four 16-bit vectors that
correspond to the four available interrupts. Bytes 0-3064
are programmed on-chip by means of a ROM mask option.
3064
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
IRQ5
IRQ5
IRQ4
IRQ4
Reserved
Reserved
IRQ2
IRQ2
IRQ1
IRQ1
Reserved
Reserved
Figure 11. Program Memory Map
P R E L I M I N A R Y15
Z86318
Z8® MCU 8-Bit Microcontroller
FUNCTIONAL DESCRIPTION
Register File. The Register File consists of three I/O port
registers, 124 general-purpose registers, and 15 control
and status registers, R0-R3, R4-R127 and R241-R255, respectively (see Figure 12). The Z86318 instructions can
access registers directly or indirectly via an 8-bit address
field. This allows short, 4-bit register addressing using the
Register Pointer.
In the 4-bit mode, the register file is divided into eight
working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group (Figures 13 and
All addresses are in Hexadecimal
U = Unknown
* Will not be reset with a Stop-Mode Recovery
P3
P2
Reserved
P0
D5 D4
U
U
U
U
U
0
U
0
0
U
0
0
1
UUUUU
UUUUUUUU
UUU
UUUUUUU
0
U
U
U
0
0
0
U
U
U
U
U
U
0
0
0
U
U
U
0
1
0
0
0
0
1
1
1
UUUUU
000000
0
RESET CONDITION
00 00UU
UUUUUU
UU
UUU
UUU
D3 D2 D1
U
U
U
U
0
0
U
U
U
U
0
0
U
U
1
1
0
0
1
1
UU
D0
U
U
U
U
0
0
U
U
U
U
0
0
U
U
0
1
0
0
1
1
U
U
UU
UU
Figure 14. Register File Architecture
ROM Protect. A ROM Protect feature prevents “dumping”
of the ROM contents without inhibiting execution of LDC,
LDCI, LDE, and LDEI instructions. This feature is maskprogrammable.
Stack Pointer. The Z86318 features an 8-bit Stack Pointer (R255) used for the internal stack that resides within the
124 general-purpose registers.
Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler can be driven
by internal or external clock sources, however, the T0 can
be driven by the internal clock source only (see Figure 15).
The 6-bit prescalers can divide the input frequency of the
clock source by any integer number from 1 to 64. Each
prescaler drives its counter, which decrements the value
(1 to 256) that has been loaded into the counter. When
both counter and prescaler reach the end of count, a timer
interrupt request IRQ4 (T0) or IRQ5 (T1) is generated.
P R E L I M I N A R Y17
Z86318
Z8® MCU 8-Bit Microcontroller
FUNCTIONAL DESCRIPTION (Continued)
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters can
also be programmed to stop upon reaching zero (single
pass mode) or to automatically reload the initial value and
continue counting (modulo-n continuous mode).
The counters, but not the prescalers, may be read at any
time without disturbing their value or count mode. The
WriteWriteRead
PRE0
Initial Value
Register
OSC
6-Bit
÷4
Internal
Clock
External Clock
Down
Counter
clock source for T1 is user-definable and can be either the
internal microprocessor clock divided by four, or an external signal input via Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a
trigger input that is retriggerable or not retriggerable, or as
a gate input for the internal clock.
Internal Data Bus
T0
Initial Value
Register
8-Bit
Down
Counter
T0
Current Value
Register
IRQ4
Clock
Logic
T P31
IN
÷4
Internal Clock
Gated Clock
Triggered Clock
Write
6-Bit
Down
Counter
PRE1
Initial Value
Register
Write
8-Bit
Down
Counter
T1
Initial Value
Register
Internal Data Bus
Figure 15. Counter/Timers Block Diagram
IRQ5
T1
Current Value
Register
Read
18P R E L I M I N A R Y
Z86318
1
Z8® MCU 8-Bit Microcontroller
Interrupts. The Z86318 features four interrupts from four
different sources. These interrupts are maskable and prioritized (Figure 16). The four sources are divided as follows: the falling edge of P31, P33, and the two counter/timers. The Interrupt Mask Register globally or individually
enables or disables the four interrupt requests (Table 4).
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z86318 interrupts are vectored through locations in program memory.
When an interrupt machine cycle is activated, an interrupt
request is granted. This disables all subsequent interrupts,
saves the Program Counter and Status Flags, and then
branches to the program memory vector location reserved
for that interrupt. This memory location and the next byte
contain the 16-bit starting address of the Interrupt Service
Routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the Interrupt Request Register is polled to
determine which of the interrupt requests needs service.
F = Falling edge triggered
R = Rising edge triggered
IRQ0 - IRQ5
IRQ
Global
Interrupt
Enable
Interrupt
Request
Figure 16. Interrupt Block Diagram
Clock. The Z86318 on-chip oscillator has a parallel-reso-
nant amplifier for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input,
XTAL2 = Output). The crystal should be AT cut, 4 MHz
max, with a series resistance (RS) less than or equal to
100 Ohms.
IMR
6
IPR
Priority
Logic
Vector Select
The crystal should be connected across XTAL1 and
XTAL2 using the recommended capacitors (capacitance is
between 10 pF to 250 pF and is specified by the crystal
manufacturer, ceramic resonator and PCB layout) from
each pin to ground (see Figure 17).
P R E L I M I N A R Y19
Z86318
Z8® MCU 8-Bit Microcontroller
FUNCTIONAL DESCRIPTION (Continued)
XTAL1
C1
C1
XTAL2
C2
C2
Ceramic
Resonator
or Crystal
Figure 17. Oscillator Configuration
HALT Mode. This instruction turns off the internal CPU
clock but not the on-chip oscillation circuit. The
counter/timers and external interrupts IRQ1 and IRQ2 remain active. The device can be recovered by interrupts, either externally or internally generated. An interrupt request
must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the
instruction after the HALT. The HALT mode may also be
exited via POR/RESET activation or a WDT time-out. In
this case, the program execution begins at location
000CH. The WDH instruction is used to enable the WatchDog Timer in HALT mode.
STOP Mode. This instruction turns off the internal clock
and reduces the standby current. The STOP mode can be
released by the following methods: 1) Power-On Reset
(POR) and 2) P27 is configured as an input line when the
device executes the STOP instruction. A low input condition on P27 that meets a minimum pulse width (TWSM) releases the STOP mode. Note: WDT is disabled in STOP
mode.
XTAL1
XTAL1
L
XTAL2
LC Clock
In order to enter STOP (or HALT) mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute
a NOP (opcode=FFH) immediately before the appropriate
sleep instruction, such as the following:
FFNOP; clear the pipeline
6FSTOP; enter the STOP
FFNOP; clear the pipeline
7FHALT; enter the HALT
In STOP or HALT mode, the value of each output line prior
to the HALT or STOP instruction is retained during execution.
External Clock
XTAL2
mode
or
mode
Upon reset, program execution begins at location 000C
(hex). However, when P27 is used to release the STOP
mode, the I/O port mode registers are not reconfigured to
their default power-on conditions. This prevents any I/O,
configured as an output when the STOP instruction was
executed, from glitching to an unknown state. To use the
P27 release approach with STOP mode, use the following
instruction:
LDP2M, #1XXX XXXXB(X = user's choice)
NOP
STOP
20P R E L I M I N A R Y
Z86318
1
Z8® MCU 8-Bit Microcontroller
Watch-Dog Timer (WDT). The WDT is initially enabled by
executing the WDT instruction and it is refreshed by subsequent WDT instruction executions. Note: Once the WDT
has been enabled, it cannot be disabled. The time-out period of the WDT is 24 ms. The WDT instruction affects the
Zero (Z), Sign (S), and Overflow (V) flags. The WDT can
be permanently enabled (ROM mask option) upon MCU
power-up.
Opcode WDT (5FH). Execution of WDT clears the WDT
counter. This must be done at least every 24 ms, otherwise, the WDT times out and generates a reset. This generated reset is the same as a power-on reset of 6.0 ms,
plus 18 clock cycles.
Vcc
(Volts)
2.80
2.75
2.70
Low-Voltage Protection (VLV). The device will function
normally between 6.0V and 4.0V under all specified conditions. Below 4.0V, the device is still internally functional until the Low Voltage trip point (VLV) is reached; however, it
is not guaranteed to meet all AC and DC Characteristics.
When the supply voltage drops below VLV, an automatic
hardware reset occurs, re-initializing the Z86318. The
Low-Voltage Protection feature may be selected as a
ROM mask option.
The actual VLV is a function of temperature, operating frequency and process parameters. A typical example of the
trip-point function at ambient temperature for a fre-