XILINX XC 95144XL TQ100 Datasheet

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DS056 (v1.9) March 22, 2006

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Features

• 5 ns pin-to-pin logic delays

• System frequency up to 178 MHz

• 144 macrocells with 3,200 usable gates

• Available in small footprint packages

- 100-pin TQFP (81 user I/O pins)

- 144-pin TQFP (117 user I/O pins)

- 144-CSP (117 user I/O pins)

- Pb-free available for all packages

• Optimized for high-performance 3.3V systems

- Low power operation

- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals

- 3.3V or 2.5V output capability

- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology

• Advanced system features

- In-system programmable

- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with
individual product-term allocation

- Local clock inversion with three global and one
product-term clocks

- Individual output enable per output pin with local
inversion

- Input hysteresis on all user and boundary-scan pin
inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase
cycles

- 20 year data retention

- ESD protection exceeding 2,000V

• Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package

Description

The XC95144XL is a 3.3V CPLD targeted for high-perfor­mance, low-voltage applications in leading-edge communi­cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.

XC95144XL High Performance
CPLD

Product Specification

Power Estimation

Power dissipation in CPLDs can vary substantially depend­ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi­tion, unused product-terms and macrocells are automati­cally deactivated by the software to further conserve power.

For a general estimate of I
used:

(mA) = MCHS(0.175*PT

I

CC

+ 0.272) + 0.04 * MC

where:

MC

= # macrocells in high-speed configuration

HS

PT

= average number of high-speed product terms

HS

per macrocell

= # macrocells in low power configuration

MC

LP

PT

= average number of low power product terms per

LP

macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock

(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
value varies with the design application and should be veri­fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL

CPLD Power.”

250

200

150

(mA)

CC

100

Typical I

50

0

High Performance

P

Low

50 150

Figure 1: Typical ICC vs. Frequency for XC95144XL

, the following equation may be

CC

+ 0.345) + MCLP(0.052*PTLP

HS

(MCHS +MCLP)* f

TOG

178 MHz

104 MHz

r

owe

100 200

Clock Frequency (MHz)

CC

© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS056 (v1.9) March 22, 2006 www.xilinx.com 1

Product Specification

XC95144XL High Performance CPLD

R

JTAG Port

I/O/GCK

I/O/GSR

I/O/GTS

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

3

1

JTAG

Controller

In-System Programming Controller

54

18

Function

Block 1

Macrocells

1 to 18

54

18

Function

Block 2

Macrocells

I/O

1 to 18

Blocks

54

18

Function

Block 3

Macrocells

Fast CONNECT II Switch Matrix

1 to 18

3

1

18

4

54

Function

Block 4

Macrocells

1 to 18

54

18

Function

Block 8

Macrocells

1 to 18

DS056_02_101300

Figure 2: XC95144XL Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

2 www.xilinx.com DS056 (v1.9) March 22, 2006

Product Specification

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XC95144XL High Performance CPLD

Absolute Maximum Ratings

(2)

Symbol Description Value Units

V

CC

V

IN

V

TS

T

STG

T

J

Notes:

1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed V

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.

Supply voltage relative to GND –0.5 to 4.0 V

Input voltage relative to GND

Voltage applied to 3-state output

Storage temperature (ambient)

Junction temperature +150

(1)

(3)

(1)

CCINT

by 4.0V.

–0.5 to 5.5 V

–0.5 to 5.5 V

–65 to +150

o

o

C

C

Recommended Operation Conditions

Symbol Parameter Min Max Units

V

CCINT

V

CCIO

V

V

V

IL

IH

O

Supply voltage for internal logic
and input buffers

Commercial TA = 0oC to 70oC3.0 3.6 V

Industrial T

= –40oC to +85oC3.0 3.6 V

A

Supply voltage for output drivers for 3.3V operation 3.0 3.6 V

Supply voltage for output drivers for 2.5V operation 2.3 2.7 V

Low-level input voltage 0 0.80 V

High-level input voltage 2.0 5.5 V

Output voltage 0 V

CCIO

V

Quality and Reliability Characteristics

Symbol Parameter Min Max Units

V

T

N

ESD

DR

PE

Data Retention 20 - Years

Program/Erase Cycles (Endurance) 10,000 - Cycles

Electrostatic Discharge (ESD) 2,000 - Volts

DC Characteristic Over Recommended Operating Conditions

Symbol Parameter Test Conditions Min Max Units

V

OH

V

OL

I

IL

I

IH

Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V

Output high voltage for 2.5V outputs I

= –500 μA90% V

OH

CCIO

-V

Output low voltage for 3.3V outputs IOL = 8.0 mA - 0.4 V

Output low voltage for 2.5V outputs I

Input leakage current VCC = Max; VIN = GND or V

I/O high-Z leakage current VCC = Max; VIN = GND or V

= 500 μA-0.4V

OL

CC

CC

-±10μA

-±10μA

DS056 (v1.9) March 22, 2006 www.xilinx.com 3

Product Specification

XC95144XL High Performance CPLD

Symbol Parameter Test Conditions Min Max Units

C

I

I

CC

IH

IN

I/O high-Z leakage current VCC = Max; V

V

= GND or 3.6V

IN

V

Min < VIN < 5.5V - ±50 μA

CC

CCIO

= Max;

-±10μA

I/O capacitance VIN = GND; f = 1.0 MHz - 10 pF

Operating supply current

VIN = GND, No load; f = 1.0 MHz 45 (Typical) mA

(low power mode, active)

AC Characteristics

XC95144XL-5 XC95144XL-7 XC95144XL-10

Symbol Parameter

T

PD

T

SU

T

H

T

CO

f

SYSTEM

T

PSU

T

PH

T

PCO

T

OE

T

OD

T

POE

T

POD

T

AO

T

PAO

T

WLH

T

APRPW

T

PLH

I/O to output valid - 5.0 - 7.5 - 10.0 ns

I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns

I/O hold time after GCK 0 - 0 - 0 - ns

GCK to output valid - 3.5 - 4.5 - 5.8 ns

Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz

I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns

I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns

P-term clock output valid - 5.5 - 7.7 - 10.2 ns

GTS to output valid - 4.0 - 5.0 - 7.0 ns

GTS to output disable - 4.0 - 5.0 - 7.0 ns

Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns

Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns

GSR to output valid - 10.0 - 12.0 - 14.5 ns

P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns

GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns

Asynchronous preset/reset pulse width

5.0 - 6.5 - 7.0 - ns

(High or Low)

P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns

R

UnitsMin Max Min Max Min Max

V

TEST

R

Device Output

1

C

R

2

L

Output Type V

V

CCIO

3.3V

2.5V

TEST

3.3V

2.5V

R

1

320 Ω

250 Ω

R

2

360 Ω

660 Ω

C

L

35 pF

35 pF

DS058_03_081500

Figure 3: AC Load Circuit

4 www.xilinx.com DS056 (v1.9) March 22, 2006

Product Specification