Xilinx XAPP721 User Manual

Application Note: Virtex-4 Series

March 2006 Memory Interfaces Solution Guide 55

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High-Performance DDR2 SDRAM
Interface Data Capture Using ISERDES

XAPP721 (v1.3) February 2, 2006

Summary This application note describes a data capture technique for a high-performance DDR2

SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output
Serializer/Deserializer (OSERDES) features available in every Virtex™-4 I/O. This technique
can be used for memory interfaces with frequencies of 267 MHz (533 Mb/s) and above.

Introduction A DDR2 SDRAM interface is source-synchronous where the read data and read strobe are

transmitted edge-aligned. To capture this transmitted data using Virtex-4 FPGAs, either the
strobe or the data can be delayed. In this design, the read data is captured in the delayed
strobe domain and recaptured in the FPGA clock domain in the ISERDES. The received serial,
double data rate (DDR) read data is converted to 4-bit parallel single data rate (SDR) data at
half the frequency of the interface using the ISERDES. The differential strobe is placed on a
clock-capable IO pair in order to access the BUFIO clock resource. The BUFIO clocking
resource routes the delayed read DQS to its associated data ISERDES clock inputs. The write
data and strobe transmitted by the FPGA use the OSERDES. The OSERDES converts 4-bit
parallel data at half the frequency of the interface to DDR data at the interface frequency. The
controller, datapath, user interface, and all other FPGA slice logic are clocked at half the
frequency of the interface, resulting in improved design margin at frequencies of 267 MHz and
above.

and OSERDES

Author: Maria George

Clocking
Scheme

The clocking scheme for this design includes one digital clock manager (DCM) and two phase­matched clock dividers (PMCDs) as shown in Figure 1. The controller is clocked at half the
frequency of the interface using CLKdiv_0. Therefore, the address, bank address, and
command signals (RAS_L, CAS_L, and WE_L) are asserted for two clock cycles (known as
"2T" timing), of the fast memory interface clock. The control signals (CS_L, CKE, and ODT) are
twice the rate (DDR) of the half frequency clock CLKdiv_0, ensuring that the control signals are
asserted for just one clock cycle of the fast memory interface clock. The clock is forwarded to
the external memory device using the Output Dual Data Rate (ODDR) flip-flops in the Virtex-4
I/O. This forwarded clock is 180 degrees out of phase with CLKfast_0. Figure 2 shows the
command and control timing diagram.

© 2005 – 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.

All other trademarks are the property of their respective owners.

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56 Memory Interfaces Solution Guide March 2006

Write Datapath

CLKfast Input

System Reset*

CLKIN

RST

CLKFB

DCM

CLK0

LOCKED

CLK90

*

PMCD#1

CLKA

RST

CLKFB

CLKA1

CLKA1D2

CLKfast_0

CLKdiv_0

PMCD#2

CLKA

CLKA1

CLKB

*

RST

CLKA1D2

CLKFB

CLKfast_90

CLKdiv_90

x702_04_051105

Figure 1: Clocking Scheme for the High-Performance Memory Interface Design

CLKdiv_0

CLKfast_0

Memory Device
Clock

Command WRITE IDLE

Control (CS_L)

X721_02_080205

Figure 2: Command and Control Timing

Write Datapath The write datapath uses the built-in OSERDES available in every Virtex-4 I/O. The OSERDES

transmits the data (DQ) and strobe (DQS) signals. The memory specification requires DQS to
be transmitted center-aligned with DQ. The strobe (DQS) forwarded to the memory is
180 degrees out of phase with CLKfast_0. Therefore, the write data transmitted using
OSERDES must be clocked by CLKfast_90 and CLKdiv_90 as shown in Figure 3. The timing
diagram for write DQS and DQ is shown in Figure 4.

Write Datapath

March 2006 Memory Interfaces Solution Guide 57

Write

Data

Words

0-3

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D1

DQ

D2

D3

D4

OSERDES

CLKDIV CLK

CLKdiv_90

CLKfast_90

IOB ChipSyncTM Circuit

Figure 3: Write Data Transmitted Using OSERDES

CLKfast_0

CLKfast_90

Clock Forwarded
to Memory Device

Command WRITE IDLE

Control (CS_L)

Strobe (DQS)

X721_03_080305

Data (DQ), OSERDES Output

D0 D1 D2 D3

X721_04_120505

Figure 4: Write Strobe (DQS) and Data (DQ) Timing for a Write Latency of Four

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58 Memory Interfaces Solution Guide March 2006

Write Timing Analysis

Ta bl e 1 shows the write timing analysis for an interface at 333 MHz (667 Mb/s).

Ta b l e 1 : Write Timing Analysis at 333 MHz

Write Datapath

Uncertainty Parameters Value

T

CLOCK

T

MEMORY_DLL_DUTY_CYCLE_DIST

T

DATA_PERIOD

T

SETUP

T

HOLD

T

PACKAGE_SKEW

T

JITTER

T

CLOCK_SKEW-MAX

T

CLOCK_OUT_PHASE

Uncertainties

before DQS

Uncertainties

after DQS

Meaning

3000 Clock period.

150 150 150 Duty-cycle distortion from memory DLL is

subtracted from clock phase (equal to half
the clock period) to determine
T

DATA_PERIOD.

1350 Data period is half the clock period with 10%

duty-cycle distortion subtracted from it.

100 100 0 Specified by memory vendor.

175 0 175 Specified by memory vendor.

30 30 30 PCB trace delays for DQS and its

associated DQ bits are adjusted to account
for package skew. The listed value
represents dielectric constant variations.

50 50 50 Same DCM used to generate DQS and DQ.

50 50 50 Global Clock Tree skew.

140 140 140 Phase offset error between different clock

outputs of the same DCM.

T

PCB_LAYOUT_SKEW

50 50 50 Skew between data lines and the

associated strobe on the board.

Total Uncertainties 420 495

Start and End of Valid Window 420 855

Final Window 435 Final window equals 855 – 420.

Notes:

1. Skew between output flip-flops and output buffers in the same bank is considered to be minimal over voltage and temperature.