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Revision History
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The following table shows the revision history for this document.
DateVersionRevision
06/24/091.0Initial Xilinx release.
08/11/092.0Chapter 2:
• Added new sections: Using TXOUTCLK to Drive the GTX TX, page 131, GTX TX Reset in
Response to Completion of Configuration, page 139, GTX TX Reset in Response to
GTXTXRESET Pulse, page 139, GTX TX Component-Level Resets, page 140, After Powerup and Configuration, page 142, After Turning on a Reference Clock to the TX PLL,
page 142, After Changing the Reference Clock to the TX PLL, page 142, After
Assertion/Deassertion of TXPOWERDOWN, page 142, TX Rate Change with the TX
Buffer Enabled, page 142, TX Rate Change with the TX Buffer Bypassed, page 142, TX
Parallel Clock Source Reset, page 142, TX Phase Alignment after Rate Change Use Mode,
page 159, and Rate Change Use Mode for PCI Express 2.0 Operation, page 171.
• Added the RXPLLREFSELDY[2:0] port to Table 2-4, page 106.
• Replaced first sentence of Single External Reference Clock Use Model, page 108.
• Added new section Multiple External Reference Clocks Use Model, page 110.
• Revised PLL nominal operating range and added Tab l e 2-6 , pag e 11 3 .
• Added the PMA_COM_CFG attribute to Tabl e 2 -9, p age 115 .
•Replaced Table 2-10, page 117.
• Added PCI Express mode power conditions to bulleted list in Power-Down Features for
PCI Express Operation, page 123.
• Added note 1 to Table 2-10, page 117 on P1 and P2 power state support.
•In Dynamic Reconfiguration Port, page 125, revised occurrences of DO to DRPDO.
•In Table 2-18, page 126, changed the bus width of the DRP address bus to DADDR[7:0].
Chapter 3:
• Renamed TX Clock Divider Control block to TX Fabric Clock Output Control.
• Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 3-3, page 129.
• In the Functional Description of TX Initialization, page 136, revised #2 and added #3.
Added Figure 3-8, page 137 showing the GTX TX reset hierarchy.
• Revised the GTXTEST[12:0] and GTXTXRESET descriptions in Table 3-7, page 138.
• Revised Ease of Use and TX Lane-to-Lane Deskew rows in Table 3-15, page 153.
• Revised the TXDLYALIGNDISABLE, TXDLYALIGNMONITOR[7:0], and TXOUTCLK
descriptions in Table 3-18, page 155.
• Revised steps 2, 5, and 9 in Using t
page 158.
• Changed the width of TXDLYALIGNRESET in Figure 3-21, page 159 to 16 TXUSRCLK2
cycles and revised caption.
• Revised paragraph under Figure 3-23, page 160 on making phase alignment effective.
•In Serial Clock Divider, page 168, provided more details on using the D divider in fixed
line rate and multiple line rate applications.
•In Table 3-28, page 168, removed TXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
•In Table 3-29, page 169, added the GTXTEST[1] port and revised the clock domain and
description of TXRATEDONE.
•In Table 3-30, page 170, revised the description of TRANS_TIME_RATE.
• Revised PCI Express Clocking Use Mode, page 170 and added Figure 3-29, page 171 and
Figure 3-30, page 172.
he TX Phase-Alignment Circuit to Bypass the Buffer,
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DateVersionRevision
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08/11/09
(Cont’d)
2.0Chapter 3 (Cont’d):
• Changed the widths of TXPREEMPHASIS, TXDIFFCTRL, and TXPOSTEMPHASIS in
Figure 3-31, page 173.
• Revised description of RXPOWERDOWN and TXPOWERDOWN in Table 3-33, page 179.
• Added note to the Functional Description of TX Out-of-Band Signaling, page 180.
•In Table 3-34, page 181, changed TXELECIDLE to one bit and added COMFINISH.
• Updated descriptions of TXELECIDLE and TXPOWERDOWN ports in Table 3-34,
page 181
Chapter 4:
• Added new sections GTX RX Reset in Response to Completion of Configuration, page 263,
GTX RX Reset in Response to GTXRXRESET Pulse, page 263, Link Idle Reset Support,
page 264, GTX RX Component-Level Resets, page 264, After Power-up and Configuration,
page 266, After Turning on a Reference Clock to RX PLL, page 266, After Changing the
Reference Clock to RX PLL, page 267, After Assertion/Deassertion of RXPOWERDOWN,
page 267, RX Rate Change with RX Elastic Buffer Enabled, page 267, RX Rate Change with
RX Elastic Buffer Bypassed, page 267, RX Parallel Clock Source Reset, page 267, After
Remote Power-Up, page 267, Electrical Idle Reset, page 267, After Connecting RXN/RXP,
page 268, After an RX Elastic Buffer Error, page 268, Before Channel Bonding, page 268,
After Changing Channel Bonding Mode on the Fly, page 268, After a PRBS Error, page 268,
After an Oversampler Error, page 268, and After Comma Realignment, page 269.
• Revised captions for Figure 4-9, page 194 and Figure 4-10, page 195.
•In Tab l e 4-2 , pag e 1 85, added sentence about system evaluation purposes to the
de
scriptions of TERMINATION_CTRL[4:0] and TERMINATION_OVRD.
• Added GATERXELECIDLE and IGNORESIGDET ports to Table 4-9, page 192.
•Added Figure 4-8, page 193.
•In Serial Clock Divider, page 208, provided more details on using the D divider in fixed
line rate and multiple line rate applications.
•In Table 4-23, page 208, removed RXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
•In Table 4-24, page 209, revised the clock domain and description of RXRATEDONE.
•In Table 4-25, page 209, revised the description of TRANS_TIME_RATE.
• Added RX decoder port and attribute tables (Table 4-38, page 230 and Table 4-39, page 231,
respectively).
• Changed description of RXDLYALIGNMONITOR[7:0] to reserved in Table 4-40, page 233.
• Moved description of RX CDR lock to RX CDR, page 204.
• Revised descriptions of CLK_COR_ADJ_LEN, CLK_COR_DET_LEN,
CLK_COR_MAX_LAT, and CLK_CORRECT_USE attributes in Table 4-47, page 242.
• In the Functional Description of RX Initialization, page 261, revised #2 and added #3.
Added Figure 4-49, page 261 showing the GTX receiver reset hierarchy.
•In Table 4-52, page 261, revised the GTXTEST[12:0] description and added the
PRBSCNTRESET port.
• Added the RX_EN_REALIGN_RESET_BUF2 attribute to Table 4-53, page 262.
• Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 4-58, page 270.
Appendix B:
• Added new appendix.
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DateVersionRevision
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01/19/102.1Updated width of TXBUFSTATUS port in Ta bl e 1 -1. Updated Figure 1-4. Updated description
of SIM_GTXRESET_SPEEDUP in Tab le 1 -2 . Added GTXE1_X0Y1 location for LX75T to
Figure 1-9.
Added new section Reference Clock Input Structure, page 101. Added note after Figure 2-4,
Figure 2-5, Figure 2-6, and Figure 2-7. Updated PLL nominal operation range in Functional
Description. Removed Line Rate Range column and added -1 Line Rate Range and -2/-3 Line
Rate Range columns to Ta bl e 2 -6 . Added note after Figure 2-9. Added description of N1
divider setting after Ta bl e 2 -7 . Updated entries in and removed REFCLK Max and Min
columns from Ta bl e 2 -1 0. Removed Power Down Transition Times section. Updated
Description column of Ta bl e 2 -1 0.
Moved Ports and Attributes, page 130 before Using TXOUTCLK to Drive the GTX TX,
page 131. Updated Using TXOUTCLK to Drive the GTX TX, page 131. Added guideline for
asynchronous GTXTXRESET pulse width in GTX TX Reset in Response to GTXTXRESET
Pulse, page 139. Added TXDLYALIGNMONENB and updated descriptions of
TXDLYALIGNRESET, TXOUTCLK, and TXPMASETPHASE to Tab le 3 -1 8. Updated steps 1d
and 6 in Using the TX Phase-Alignment Circuit to Bypass the Buffer, page 158. Updated TX
Oversampling, page 166. In Ta bl e 3 - 26 , removed PMA_RX_CFG, updated description of
TX_OVERSAMPLE_MODE, and added TXPLL_DIVSEL_OUT. Added note 5 to Figure 3-28.
Updated line rate ranges in Ta bl e 3 -2 8. Changed IBUFDS to IBUFDS_GTXE1 in Figure 3-29
and added a note after the figure. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
description of TXDEEMPH in Ta bl e 3- 31 . Changed PCI Express version from 3.0 to 2.0 in note
for Ta bl e 3- 31 . Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in descriptions of
TX_DEEMPH_0/1 in Tab le 3 -3 2. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
PCIe Mode, page 178 and Customizable User Presets, page 178.
Added note after Figure 4-2 and Tab l e 4 -3 . Updated Ta bl e 4 -5 and Tabl e 4 -7 . Added
OOBDETECT_THRESHOLD_0/1 to and updated description of SATA_IDLE_VAL in
Ta bl e 4 - 10 .
Figure 4-12. Updated descriptions of DFECLKDLYADJ, DFECLKDLYADJMON, and
DFEDLYOVRD in Ta b le 4 -1 1. Updated descriptions of DFE_CAL_TIME, DFE_CFG, and
RX_EN_IDLE_HOLD_DFE attributes in Ta bl e 4 -1 2. Renamed RX Clock Divider Control
section as RX Fabric Clock Output Control, page 207. Updated MGTREFCLKFAB[1] bit in
and added note 4 to Figure 4-15. Updated line rate ranges in Tab le 4- 23 . Updated RX Margin
Analysis, page 210. Added DFEEYEDACMON port to Tab le 4 -2 6. Replaced
INTDATAWIDTH with R X _ D ATA _W I DTH in and added note to Figure 4-19. Changed
RXOVERSAMPLER to RXOVERSAMPLEERR in Tab l e 4 -2 9 . Updated description of
RX_OVERSAMPLE_MODE in and added RXPLL_DIVSEL_OUT to Tab l e 4 -3 0 . Swapped the
order of the SIPO and Polarity Inversion blocks in Figure 4-20. Updated descriptions of
RX_PRBS_ERR_CNT and RXPRBSERR_LOOPBACK attributes in Tab le 4 -3 2. Replaced
GTXRESET with GTXRXRESET in Use Models, page 216. Changed PCOMMA_ALIGN and
MCOMMA_ALIGN to PCOMMA_DETECT and MCOMMA_DETECT, respectively, in
Alignment Status Signals, page 219 and Ta b le 4 -3 4 . Updated RX Buffer Bypass, page 231 with
restrictions on RX buffer bypass operation. Updated descriptions of
CHAN_BOND_1/2_MAX_SKEW a nd CHAN_BOND_SEQ_LEN attribute in Ta bl e 4 - 49 .
Added guideline for asynchronous GTXTXRESET pulse width in GTX RX Reset in Response
to GTXRXRESET Pulse, page 263. Added description of power supply regulators for
MGTAVCC and VCCINT in Overview, page 283.
In Tab le B -1 , changed attribute encoding 3 in attribute bits 1:0 of DADDRs 7h, 12h, and 13h
to Reserved.
02/23/102.2Updated descriptions of RXDLYALIGNOVERRIDE in Tab le 4 -4 0 and
RX_DLYALIGN_OVRDSETTING in Ta bl e 4 - 41 . Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer, page 235, including Note 2 in Notes for Figure 4-32.. Updated
Figure 4-33.
Updated descriptions of DFETAPOVRD and DFEDLYOVRD ports after
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DateVersionRevision
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05/24/102.3Added description of buffer bypass mode to Multiple External Reference Clocks Use Model.
Added Power-Down Requirements for TX and RX Buffer Bypass.
Added description of TX buffer bypass to Functional Description, page 136 and Functional
Description, page 155.
Added description of RX buffer bypass to Functional Description, page 231. Updated
Functional Description, page 261 with description of buffer bypass mode. Removed
GTXTEST[12:0] from Tabl e 4 -5 2.
Updated Managing Unused GTX Transceivers. Replaced “group” with “bank” in Ta bl e 5-1 ,
Analog Power Supply Pins, and Partially Unused Quad Column. Added Note 2 to Ta bl e 5- 3
and Tab le 5 -4 . Added note about buffer bypass mode to Reference Clock Checklist. Added
Reference Clock Toggling.
10/01/102.4Updated Functional Description, GTX TX Reset in Response to Completion of Configuration,
and GTX TX Reset in Response to GTXTXRESET Pulse.
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DateVersionRevision
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01/17/112.5Replaced PMA_COM_CFG with PMA_CFG in Ta bl e 2- 9. Replaced RXRATE with
RXRATE[1:0] in Chapter 4, Receiver. Added note before
TXDLYALIGNMONENB, RXDLYALIGNMONENB, PMA_RXSYNC_CFG,
TXDRIVE_LOOPBACK_HIZ, and TXDRIVE_LOOPBACK_PD to Ta bl e 1 -1. In Ta bl e 1 -1 ,
moved RX_PRBS_ERR_CNT from RX Pattern Checker to Status Registers (Read Only)
section. Added FF1154 Package Placement Diagrams, FF1155 Package Placement
Diagrams, FF1923 Package Placement Diagrams, and FF1924 Package Placement
Diagrams.
Updated Figure 2-1. Added RX_CLK25_DIVIDER and TX_CLK25_DIVIDER to Tab l e 2 -9 and
Tab le 1 -1 . Updated description of TXPDOWNASYNCH in Tab le 2 -11. Added BGTEST_CFG,
BIAS_CFG, and PMA_TX_CFG to Ta bl e 2 -1 2 and
ACJTAG. Updated Ta bl e 3 -1 0. Updated descriptions of TXDIFFCTRL[3:0],
TXPDOWNASYNCH, TXPOSTEMPHASIS[4:0], and TXPREEMPHASIS[3:0] in Ta b le 3 -3 1 .
Updated description of TXPOWERDOWN[1:0] in Tab le 3 -3 4.
Updated description of IGNORESIGDET and changed direction of RXVALID from In to Out
in Tab l e 4 -9 . Updated OOBDETECT_THRESHOLD attribute in Tab l e 4 -1 0 . Added Use Mode
– Fixed Tap Mode and Use Mode – Auto-To-Fix and Use Mode – Auto. Updated descriptions
of PMA_RX_CFG, RX_EN_IDLE_HOLD_CDR, RX_EN_IDLE_RESET_FR, and
RX_EN_IDLE_RESET_PH in Ta bl e 4 - 22 . Updated Eye Outline Scan Mode. Updated
description of RX_EYE_OFFSET in Ta bl e 4 - 27 . Updated description of PMA_RX_CFG in
Ta bl e 4 - 30 . Updated Figure 4-26. Added Manual Alignment, including Figure 4-27. Removed
RX_PRBS_ERR_CNT from Tab le 4 -3 2 and added it to Ta bl e 4 -3 3. Added RXSLIDE to
Ta bl e 4 - 34 and
MCOMMA_10B_VALUE, MCOMMA_DETECT, PCOMMA_10B_VALUE,
PCOMMA_DETECT, SHOW_REALIGN_COMMA, RX_SLIDE_MODE, and
RX_SLIDE_AUTO_WAIT to Ta b le 4 -3 5 and
of RX_LOS_THRESHOLD in Functional Description, page 226. Changed RX_DATA_WIDTH
attribute type in Ta bl e 4 - 39 . Added RXDLYALIGNMONENB to Tab le 4 - 40 . Added
PMA_RXSYNC_CFG to Ta bl e 4 -4 1. Changed direction of RXDATA[31:0] port from In to Out
in Tab le 4 -4 0.
Updated Common Package Power Plane Prioritization. Added Hot Swapping Devices.
Updated 2Ah and 47h rows of Ta ble B -1 . Added Tab le B -2 .
Added Appendix C, Low Latency Design.
Updated POWER_SAVE description in Ta ble 2 -1 2, Ta bl e 3 -1 9, and Ta bl e 4 -4 1. Updated
embedded table title of TXPOSTEMPHASIS[4:0] port in Tab le 3 - 31 . Updated description
of “From TX Parallel Data” in Figure 4-1 and Figure C-3. Updated Tab le 4 -2 . Updated
Use Mode – Auto-To-Fix and Use Mode – Auto. Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer. Updated Figure 4-32 and Figure 4-34. Updated DADDR in
Tab le B -1.
Per XCN11009: Virtex-6: Data-Sheet, User Guides and JTAG ID Updates: Updated TX Buffer
Bypass: TX delay aligner bypassed, additional requirements on interconnect logic clocking
use model; Updated RX Buffer Bypass: RX delay aligner bypassed for lower line rates, higher
line rate support is an advanced feature.
Tab le 1 -1 . Updated description of ALIGN_COMMA_WORD, and added
Tab le 1 -1 . Updated Figure 4-28 and description
Tab le 1 -1 . Added
Tab le 1 -1 . Added Tab le 2 -1 7. Added
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UG366 (v2.5) January 17, 2011
About This Guide
www.BDTIC.com/XILINX
This document shows how to use the GTX transceivers in Virtex®-6 FPGAs. In this
document:
•Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver.
•GTXE1 is the name of the instantiation primitive that instantiates one Virtex-6 FPGA
GTX transceiver.
•A Quad or Q is a cluster or set of four GTX transceivers that share two differential
reference clock pin pairs and analog supply pins.
Guide Contents
This manual contains the following chapters:
•Chapter 1, Transceiver and Tool Overview
•Chapter 2, Shared Transceiver Features
•Chapter 3, Transmitter
•Chapter 4, Receiver
•Chapter 5, Board Design Guidelines
•Appendix A, 8B/10B Valid Characters
•Appendix B, DRP Address Map of the GTX Transceiver
•Appendix C, Low Latency Design
Preface
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/
•Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
•Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
•Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-6 FPGA GTX Transceivers User Guidewww.xilinx.com17
UG366 (v2.5) January 17, 2011
products/virtex6.
Preface: About This Guide
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•Virtex-6 FPGA Configuration User Guide
•Virtex-6 FPGA SelectIO Resources User Guide
•Virtex-6 FPGA Clocking Resources User Guide
•Virtex-6 FPGA Memory Resources User Guide
•Virtex-6 FPGA Configurable Logic Block User Guide
•Virtex-6 FPGA DSP48E1 Slice User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
This guide describes the SelectIO™ resources available in all Virtex-6 devices.
This guide describes the clocking resources available in all Virtex-6 devices, including
the MMCM and PLLs.
The functionality of the block RAM and FIFO are described in this user guide.
This guide describes the capabilities of the configurable logic blocks (CLBs) available
in all Virtex-6 devices.
This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and
provides configuration examples.
•Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in all Virtex-6 FPGAs except the XC6VLX760.
•Virtex-6 FPGA System Monitor User Guide
The System Monitor functionality available in all Virtex-6 devices is outlined in this
guide.
•Virtex-6 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers,
with a focus on strategies for making design decisions at the PCB and interface level.
Additional Resources
To find additional documentation, see the Xilinx website at:
18www.xilinx.comVirtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Transceiver and Tool Overview
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Overview
The Virtex®-6 FPGA GTX transceiver is a power-efficient transceiver. The GTX transceiver
is highly configurable and tightly integrated with the programmable logic resources of the
FPGA. It provides the following features to support a wide variety of applications:
•Current Mode Logic (CML) serial drivers/buffers with configurable termination,
voltage swing
•Programmable TX pre-emphasis/post-emphasis, RX equalization, and linear and
decision feedback equalization (DFE) for optimized signal integrity.
•Line rates from 600 Mb/s to 6.6 Gb/s, with optional 5X digital oversampling required
for rates between 480 Mb/s and 600 Mb/s.
•Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel
bonding, and clock correction.
•Fixed latency modes for minimized, deterministic datapath latency.
•Beacon signaling for PCI Express® designs and Out-of-Band signaling including
COM signal support for SATA designs.
•RX/TX Gearbox provides header insertion and extraction support for 64B/66B and
64B/67B (Interlaken) protocols.
•Receiver eye scan
Horizontal eye scan in the time domain for testing purposes
Chapter 1
The first-time user is recommended to read High-Speed Serial I/O Made Simple[Ref 1], which
discusses high-speed serial transceiver technology and its applications. The
CORE Generator™ tool includes a Wizard to automatically configure GTX transceivers to
support configurations for different protocols or perform custom configuration (see
Virtex-6 FPGA GTX Transceiver Wizard). The GTX transceiver offers a data rate range and
features that allow physical layer support for various protocols.
Figure 1-1 illustrates a block view of the Virtex-6 FPGA GTX transceiver.
Virtex-6 FPGA GTX Transceivers User Guidewww.xilinx.com19
Details about the different functional blocks of the transmitter and receiver including their
use models are described in Chapter 3, Transmitter, and Chapter 4, Receiver.
Figure 1-2 shows the GTX transceiver placement in an example Virtex-6 device
(XC6VLX75T).
Additional information on the functional blocks in Figure 1-2 is available in the following
locations:
20www.xilinx.comVirtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Overview
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•The Virtex-6 FPGA Configuration User Guide provides more information on the
Configuration and Clock, MMCM, and I/O blocks.
•The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailed
information on the Ethernet MAC.
Figure 1-2 illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T
FPGA.
X-Ref Target - Figure 1-2
Virtex-6 FPGA (XC6VLX75T)
GTXE1
Column
GTXE1_
X0Y11
MMCM
Ethernet
MAC
GTXE1_
X0Y10
I/O
Column
I/O
Column
Configuration
MMCM
MMCM
I/O
Column
Ethernet
MAC
Integrated
Block for
PCI Express
Operation
Ethernet
MAC
Ethernet
MAC
GTXE1_
X0Y9
GTXE1_
X0Y8
GTXE1_
X0Y7
GTXE1_
X0Y6
GTXE1_
X0Y5
GTXE1_
X0Y4
GTXE1_
X0Y3
GTXE1_
X0Y2
GTXE1_
X0Y1
GTXE1_
X0Y0
Figure 1-2: GTX Transceiver Inside the Virtex-6 XC6VLX75T FPGA
GTX transceivers are clustered together in a set of four called a Quad or Q. Figure 1-3
illustrates the clustering of four GTX transceivers to a Quad. Refer to Implementation,
page 41 for placement information and the mapping of each transceiver into a specific
Quad.
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UG366_c1_02_051509
Chapter 1: Transceiver and Tool Overview
From/To Adjacent Quad
From/To Adjacent Quad
UG366_c1_03_051509
TX-P2S
RX0
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX0
TX-P2S
RX1
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX1
TX-P2S
RX2
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX2
TX-P2S
RX3
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX3
MGTREFCLK0
MGTREFCLK1
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X-Ref Target - Figure 1-3
Figure 1-3: Quad Configuration
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UG366 (v2.5) January 17, 2011
This cluster of four GTX transceivers share two differential reference clock pin pairs and
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clock routing. Chapter 2, Shared Transceiver Features, discusses details about reference
clock sources and the routing.
Port and Attribute Summary
The ports and attributes are grouped in tables for each functionality group (e.g., reference
clock selection). If a port or attribute appears in multiple chapters, it is listed in the group
of its first appearance. Ta bl e 1 -1 summarizes the ports and attributes according to
functionality group.
Port and Attribute Summary
Note:
are present in the instantiation primitive or are listed in Appendix B, DRP Address Map of the GTX
Transceiver but not in Ta bl e 1 - 1 .
Table 1-1: Port and Attribute Summary
Ta bl e 1 - 1 lists all the ports and attributes covered in this user guide. Some ports or attributes
The Virtex-6 FPGA GTX Transceiver Wizard is the preferred tool to generate a wrapper to
instantiate a GTX transceiver primitive called GTXE1. The Wizard can be found in the
CORE Generator tool. Be sure to download the most up-to-date IP Update before using the
Wizard. Details on how to use this Wizard can be found in Virtex-6 FPGA GTX Transceiver Getting Started Guide.
1.Start the CORE Generator tool.
2.Locate the GTX Transceiver Wizard in the taxonomy tree under:
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/FPGA Features & Design/IO Interfaces
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See Figure 1-4.
X-Ref Target - Figure 1-4
Simulation
Simulation
Functional Description
Figure 1-4: Virtex-6 FPGA GTX Transceiver Wizard
3.Double-click V6 GTX Wizard to launch the Wizard.
Simulations using GTX transceivers have specific prerequisites that the simulation
environment and the test bench must fulfill.
The Synthesis and Simulation Design Guide explains how to set up the simulation
environment for supported simulators depending on the used Hardware Description
Language (HDL). This design guide can be downloaded from the Xilinx website.
The prerequisites for simulating a design with GTX transceivers are:
•Simulator with support for SecureIP models, which are encrypted versions of the
Verilog HDL used for implementation of the modeled block.
SecureIP is a new IP encryption methodology. To support SecureIP models, a Verilog
LRM - IEEE Std 1364-2005 encryption compliant simulator is required.
•Mixed-language simulator for VHDL simulation.
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SecureIP models use a Verilog standard. To use them in a VHDL design, a mixedlanguage simulator is required. The simulator must be capable of simulating VHDL
and Verilog simultaneously.
•Installed GTX SecureIP model.
•Correct setup of the simulator for SecureIP use (initialization file, environment
variable(s)).
•Running COMPXLIB (which compiles the simulation libraries (e.g. UNISIM,
SIMPRIMS, etc.) in the correct order.
•Correct simulator resolution (Verilog)
•The user guide of the simulator and the Synthesis and Simulation Design Guide provide
a detailed list of settings for SecureIP support.
Ports and Attributes
There are no simulation-only ports.
The GTXE1 primitive has attributes intended only for simulation. Ta b le 1 - 2 lists the
simulation-only attributes of the GTXE1 primitive. The names of these attributes start with
SIM_.
Table 1-2:
SIM_GTXRESET_SPEEDUPIntegerThis attribute shortens the time it takes to finish the GTXRXRESET
SIM_RECEIVER_DETECT_PASSBooleanThis attribute simulates the TXDETECTRX feature in the
GTXE1 Simulation-Only Attributes
AttributeTypeDescription
and GTXTXRESET sequence and lock the TX PMA PLL and RX
PMA PLL during simulation.
0: The GTXRXRESET and GTXTXRESET sequence is simulated
with its original duration (standard initialization is
approximately 160 µs).
1: Shorten the GTXRXRESET and GTXTXRESET cycle time (fast
initialization is approximately 300 ns).
GTX
transceiver.
TRUE: Simulates an RX connection to the TX serial ports.
TXDETECTRX initiates receiver detection, and
RXSTATUS[2:0] = 011 reports that an RX port is connected.
FALSE (default): Simulates a disconnected TX port.
TXDETECTRX initiates receiver detection, and
RXSTATUS[2:0] = 000 reports that an RX port is not connected.
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Table 1-2:
SIM_RXREFCLK_SOURCE3-Bit Binary This attribute selects the reference clock source used to drive the RX
SIM_TX_ELEC_IDLE_LEVEL1-Bit Binary This attribute sets the value of TXN and TXP during simulation of
GTXE1 Simulation-Only Attributes
AttributeTypeDescription
(Cont’d)
PMA PLL in simulation for designs where the RX PMA PLL is
always driven by the same reference clock source. The
RXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
RXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKRX[0] port as the source
001: Selects the MGTREFCLKRX[1] port as the source
010: Selects the NORTHREFCLKRX[0] port as the source
011: Selects the NORTHREFCLKRX[1] port as the source
100: Selects the SOUTHREFCLKRX[0] port as the source
101: Selects the SOUTHREFCLKRX[1] port as the source
110: Reserved
111: Selects a clock from the FPGA logic which can be either port
GREFCLKRX or PERFCLKRX as the source
electrical idle. This attribute can be set to 0, 1, x, or z. The default for
this attribute is x.
SIM_TXREFCLK_SOURCE3-Bit Binary This attribute selects the reference clock source used to drive the TX
PMA PLL in simulation for designs where the TX PMA PLL is
always driven by the same reference clock source. The
TXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
TXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKTX[0] port as the source
001: Selects the MGTREFCLKTX[1] port as the source
010: Selects the NORTHREFCLKTX[0] port as the source
011: Selects the NORTHREFCLKTX[1] port as the source
100: Selects the SOUTHREFCLKTX[0] port as the source
101: Selects the SOUTHREFCLKTX[1] port as the source
110: Selects the RX recovered clock from the RX channel as the
source
111: Selects a clock from the FPGA logic that can be either the
GREFCLKTX or the PERFCLKTX port as the source
SIM_VERSIONRealThis attribute selects the simulation version to match different
steppings of silicon. The default for this attribute is 1.0.
SIM_GTXRESET_SPEEDUP
The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of
the TX PMA PLL and the RX PMA PLL.
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t
USRCLKstabletGTXRESETsequencetlocktimeMMCM
+
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If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks
occasionally flatline while the GTX transceiver is locking. If an MMCM is used to divide
TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTX
transceiver and the MMCM have locked. Equation 1-1 provides an estimate of the time
required before a stable source from TXOUTCLK or RXRECCLK is available in simulation,
including the time required for any MMCMs used.
If the MMCM is not used, the term can be removed from the lock time equation.
SIM_RECEIVER_DETECT_PASS
The GTX transceiver includes a TXDETECTRX feature that allows the transmitter to detect
whether its serial ports are currently connected to a receiver by measuring rise time on the
TXP/TXN differential pin pair (see TX Receiver Detect Support for PCI Express Designs,
page 179).
The GTXE1 SecureIP model includes an attribute for simulating TXDETECTRX called
SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for
the GTX transceiver without modeling the measurement of rise time on the TXP/TXN
differential pin pair.
By default, SIM_RECEIVER_DETECT_PASS is set to FALSE. When FALSE, the attribute
models a disconnected receiver and TXDETECTRX operations indicate a receiver is
disconnected. To model a connected receiver, SIM_RECEIVER_DETECT_PASS for the
transceiver is set to TRUE.
Equation 1-1
SIM_RXREFCLK_SOURCE
The GTXE1 SecureIP model includes an attribute to select the reference clock source used
to drive the RX PMA PLL in simulation called SIM_RXREFCLK_SOURCE. This attribute is
to be used in designs where the RX PMA PLL’s clock input is always driven by the same
reference clock source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic. Tab le 1 -2 shows the possible settings for this attribute.
For multi-rate designs requiring the reference clock source driving the RX PMA PLL to be
changed on the fly, the RXPLLREFSELDY port is used to dynamically select the reference
clock source instead.
SIM_TXREFCLK_SOURCE
The GTXE1 SecureIP model includes an attribute to select the reference clock source used to
drive the TX PMA PLL in simulation called SIM_TXREFCLK_SOURCE. This attribute is to be
used in designs where the TX PMA PLL’s clock input is always driven by the same reference clock
source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic. Tab le 1 -2 shows the possible settings for this attribute.
For multi-rate designs requiring the reference clock source driving the TX PMA PLL to be
changed on the fly, the TXPLLREFSELDY port is used to dynamically select the reference
clock source instead.
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SIM_VERSION
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The SIM_VERSION attribute selects the simulation version to match different steppings of
silicon. The default for this attribute is 1.0.
SIM_TX_ELEC_IDLE_LEVEL
The SIM_TX_ELEC_IDLE_LEVEL attribute sets the value of the transceiver’s differential
transmitter output pair TXN and TXP during simulation of electrical idle. This attribute
can be set to 0, 1, x, or z. The default for this attribute is x.
Implementation
Functional Description
This section provides the information needed to map Virtex-6 FPGA GTX transceivers
instantiated in a design to device resources, including:
•The location of the GTX transceiver on the available device and package
•The pad numbers of external signals associated with each GTX transceiver.
•How GTX transceiver and clocking resources instantiated in a design are mapped to
Implementation
combinations.
available locations with a user constraints file (UCF).
It is a common practice to define the location of GTX transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.
While this section describes how to instantiate GTX clocking components, the details of the
different GTX transceiver clocking options are discussed in Reference Clock Selection,
page 102.
The position of the GTX transceiver is specified by an XY coordinate system that describes
the column number and its relative position within that column. In current members of the
Virtex-6 family, all GTX transceivers are located in a single column along one side of the
die.
The transceiver with the coordinates “X0Y0” is for a given device/package combination
always located at the lowest position of the lowest available bank. For the combination of
a package with a large pin count (for example, 1759) and a smaller device (for example,
XC6VLX240T), transceivers at higher or lower banks are not available.
There are two ways to create a UCF for designs that utilize the GTX transceiver. The
preferred method is to use the Virtex-6 FPGA GTX Transceiver Wizard (see Virtex-6 FPGA
that configure the transceivers and contain placeholders for GTX placement information.
The UCFs generated by the Wizard can then be edited to customize operating parameters
and placement information for the application.
The second approach is to create the UCF by hand. When using this approach, the designer
must enter both configuration attributes that control transceiver operation as well as tile
location parameters. Care must be taken to ensure that all of the parameters needed to
configure the GTX transceiver are correctly entered.
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LX75T: GTXE1_X0Y7
LX130T: GTXE1_X0Y15
LX75T: GTXE1_X0Y6
LX130T: GTXE1_X0Y14
QUAD_115
LX75T: GTXE1_X0Y5
LX130T: GTXE1_X0Y13
LX75T: GTXE1_X0Y4
LX130T: GTXE1_X0Y12
B1
B2
D1
D2
C3
C4
F1
F2
J4
J3
L4
L3
E3
E4
H1
H2
G3
G4
K1
K2
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
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Figure 1-5, page 42 through Figure 1-23, page 60 provide the GTX transceiver position
information for all available device and package combinations along with the pad
numbers for the external signals associated with each GTX transceiver.
FF484 Package Placement Diagrams
Figure 1-5 through Figure 1-6 show the placement diagrams for the FF484 package.
X-Ref Target - Figure 1-5
Figure 1-5: Placement Diagram for the FF484 Package (1 of 2)
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X-Ref Target - Figure 1-6
LX75T: GTXE1_X0Y3
LX130T: GTXE1_X0Y11
LX75T: GTXE1_X0Y2
LX130T: GTXE1_X0Y10
QUAD_114
LX75T: GTXE1_X0Y1
LX130T: GTXE1_X0Y9
LX75T: GTXE1_X0Y0
LX130T: GTXE1_X0Y8
W3
W4
M1
M2
Y1
Y2
P1
P2
R4
R3
U4
U3
AA3
AA4
T1
T2
AB1
AB2
V1
V2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
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Implementation
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Figure 1-6: Placement Diagram for the FF484 Package (2 of 2)