Virtex-6 FPGA
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GTX Transceivers
User Guide
UG366 (v2.5) January 17, 2011
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com UG366 (v2.5) January 17, 2011
Revision History
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The following table shows the revision history for this document.
Date Version Revision
06/24/09 1.0 Initial Xilinx release.
08/11/09 2.0 Chapter 2:
• Added new sections: Using TXOUTCLK to Drive the GTX TX, page 131, GTX TX Reset in
Response to Completion of Configuration, page 139, GTX TX Reset in Response to
GTXTXRESET Pulse, page 139, GTX TX Component-Level Resets, page 140, After Powerup and Configuration, page 142, After Turning on a Reference Clock to the TX PLL,
page 142, After Changing the Reference Clock to the TX PLL, page 142, After
Assertion/Deassertion of TXPOWERDOWN, page 142, TX Rate Change with the TX
Buffer Enabled, page 142, TX Rate Change with the TX Buffer Bypassed, page 142, TX
Parallel Clock Source Reset, page 142, TX Phase Alignment after Rate Change Use Mode,
page 159, and Rate Change Use Mode for PCI Express 2.0 Operation, page 171.
• Added the RXPLLREFSELDY[2:0] port to Table 2-4, page 106.
• Replaced first sentence of Single External Reference Clock Use Model, page 108.
• Added new section Multiple External Reference Clocks Use Model, page 110.
• Revised PLL nominal operating range and added Tab l e 2-6 , pag e 11 3 .
• Added the PMA_COM_CFG attribute to Tabl e 2 -9, p age 115 .
•Replaced Table 2-10, page 117.
• Added PCI Express mode power conditions to bulleted list in Power-Down Features for
PCI Express Operation, page 123.
• Added note 1 to Table 2-10, page 117 on P1 and P2 power state support.
•In Dynamic Reconfiguration Port, page 125, revised occurrences of DO to DRPDO.
•In Table 2-18, page 126, changed the bus width of the DRP address bus to DADDR[7:0].
Chapter 3:
• Renamed TX Clock Divider Control block to TX Fabric Clock Output Control.
• Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 3-3, page 129.
• In the Functional Description of TX Initialization, page 136, revised #2 and added #3.
Added Figure 3-8, page 137 showing the GTX TX reset hierarchy.
• Revised the GTXTEST[12:0] and GTXTXRESET descriptions in Table 3-7, page 138.
• Revised Ease of Use and TX Lane-to-Lane Deskew rows in Table 3-15, page 153.
• Revised the TXDLYALIGNDISABLE, TXDLYALIGNMONITOR[7:0], and TXOUTCLK
descriptions in Table 3-18, page 155.
• Revised steps 2, 5, and 9 in Using t
page 158.
• Changed the width of TXDLYALIGNRESET in Figure 3-21, page 159 to 16 TXUSRCLK2
cycles and revised caption.
• Revised paragraph under Figure 3-23, page 160 on making phase alignment effective.
•In Serial Clock Divider, page 168, provided more details on using the D divider in fixed
line rate and multiple line rate applications.
•In Table 3-28, page 168, removed TXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
•In Table 3-29, page 169, added the GTXTEST[1] port and revised the clock domain and
description of TXRATEDONE.
•In Table 3-30, page 170, revised the description of TRANS_TIME_RATE.
• Revised PCI Express Clocking Use Mode, page 170 and added Figure 3-29, page 171 and
Figure 3-30, page 172.
he TX Phase-Alignment Circuit to Bypass the Buffer,
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Date Version Revision
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08/11/09
(Cont’d)
2.0 Chapter 3 (Cont’d):
• Changed the widths of TXPREEMPHASIS, TXDIFFCTRL, and TXPOSTEMPHASIS in
Figure 3-31, page 173.
• Revised description of RXPOWERDOWN and TXPOWERDOWN in Table 3-33, page 179.
• Added note to the Functional Description of TX Out-of-Band Signaling, page 180.
•In Table 3-34, page 181, changed TXELECIDLE to one bit and added COMFINISH.
• Updated descriptions of TXELECIDLE and TXPOWERDOWN ports in Table 3-34,
page 181
Chapter 4:
• Added new sections GTX RX Reset in Response to Completion of Configuration, page 263,
GTX RX Reset in Response to GTXRXRESET Pulse, page 263, Link Idle Reset Support,
page 264, GTX RX Component-Level Resets, page 264, After Power-up and Configuration,
page 266, After Turning on a Reference Clock to RX PLL, page 266, After Changing the
Reference Clock to RX PLL, page 267, After Assertion/Deassertion of RXPOWERDOWN,
page 267, RX Rate Change with RX Elastic Buffer Enabled, page 267, RX Rate Change with
RX Elastic Buffer Bypassed, page 267, RX Parallel Clock Source Reset, page 267, After
Remote Power-Up, page 267, Electrical Idle Reset, page 267, After Connecting RXN/RXP,
page 268, After an RX Elastic Buffer Error, page 268, Before Channel Bonding, page 268,
After Changing Channel Bonding Mode on the Fly, page 268, After a PRBS Error, page 268,
After an Oversampler Error, page 268, and After Comma Realignment, page 269.
• Added ESD Diodes label to Figure 4-2, page 184, Figure 4-3, page 187, Figure 4-4,
page 188, Figure 4-5, page 189, Figure 4-6, page 190, and Figure 4-7, page 191.
• Revised captions for Figure 4-9, page 194 and Figure 4-10, page 195.
•In Tab l e 4-2 , pag e 1 85, added sentence about system evaluation purposes to the
de
scriptions of TERMINATION_CTRL[4:0] and TERMINATION_OVRD.
• Added GATERXELECIDLE and IGNORESIGDET ports to Table 4-9, page 192.
•Added Figure 4-8, page 193.
•In Serial Clock Divider, page 208, provided more details on using the D divider in fixed
line rate and multiple line rate applications.
•In Table 4-23, page 208, removed RXPLL_DIVSEL_OUT = Ignored from all rows in the
Dynamic Control via Ports column.
•In Table 4-24, page 209, revised the clock domain and description of RXRATEDONE.
•In Table 4-25, page 209, revised the description of TRANS_TIME_RATE.
• Added RX decoder port and attribute tables (Table 4-38, page 230 and Table 4-39, page 231,
respectively).
• Changed description of RXDLYALIGNMONITOR[7:0] to reserved in Table 4-40, page 233.
• Moved description of RX CDR lock to RX CDR, page 204.
• Revised descriptions of CLK_COR_ADJ_LEN, CLK_COR_DET_LEN,
CLK_COR_MAX_LAT, and CLK_CORRECT_USE attributes in Table 4-47, page 242.
• In the Functional Description of RX Initialization, page 261, revised #2 and added #3.
Added Figure 4-49, page 261 showing the GTX receiver reset hierarchy.
•In Table 4-52, page 261, revised the GTXTEST[12:0] description and added the
PRBSCNTRESET port.
• Added the RX_EN_REALIGN_RESET_BUF2 attribute to Table 4-53, page 262.
• Revised “GTX Lanes in Channel” values for 2-byte and 4-byte rows in Table 4-58, page 270.
Appendix B:
• Added new appendix.
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Date Version Revision
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01/19/10 2.1 Updated width of TXBUFSTATUS port in Ta bl e 1 -1. Updated Figure 1-4. Updated description
of SIM_GTXRESET_SPEEDUP in Tab le 1 -2 . Added GTXE1_X0Y1 location for LX75T to
Figure 1-9.
Added new section Reference Clock Input Structure, page 101. Added note after Figure 2-4,
Figure 2-5, Figure 2-6, and Figure 2-7. Updated PLL nominal operation range in Functional
Description. Removed Line Rate Range column and added -1 Line Rate Range and -2/-3 Line
Rate Range columns to Ta bl e 2 -6 . Added note after Figure 2-9. Added description of N1
divider setting after Ta bl e 2 -7 . Updated entries in and removed REFCLK Max and Min
columns from Ta bl e 2 -1 0. Removed Power Down Transition Times section. Updated
Description column of Ta bl e 2 -1 0.
Moved Ports and Attributes, page 130 before Using TXOUTCLK to Drive the GTX TX,
page 131. Updated Using TXOUTCLK to Drive the GTX TX, page 131. Added guideline for
asynchronous GTXTXRESET pulse width in GTX TX Reset in Response to GTXTXRESET
Pulse, page 139. Added TXDLYALIGNMONENB and updated descriptions of
TXDLYALIGNRESET, TXOUTCLK, and TXPMASETPHASE to Tab le 3 -1 8. Updated steps 1d
and 6 in Using the TX Phase-Alignment Circuit to Bypass the Buffer, page 158. Updated TX
Oversampling, page 166. In Ta bl e 3 - 26 , removed PMA_RX_CFG, updated description of
TX_OVERSAMPLE_MODE, and added TXPLL_DIVSEL_OUT. Added note 5 to Figure 3-28.
Updated line rate ranges in Ta bl e 3 -2 8. Changed IBUFDS to IBUFDS_GTXE1 in Figure 3-29
and added a note after the figure. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
description of TXDEEMPH in Ta bl e 3- 31 . Changed PCI Express version from 3.0 to 2.0 in note
for Ta bl e 3- 31 . Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in descriptions of
TX_DEEMPH_0/1 in Tab le 3 -3 2. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
PCIe Mode, page 178 and Customizable User Presets, page 178.
Added note after Figure 4-2 and Tab l e 4 -3 . Updated Ta bl e 4 -5 and Tabl e 4 -7 . Added
OOBDETECT_THRESHOLD_0/1 to and updated description of SATA_IDLE_VAL in
Ta bl e 4 - 10 .
Figure 4-12. Updated descriptions of DFECLKDLYADJ, DFECLKDLYADJMON, and
DFEDLYOVRD in Ta b le 4 -1 1. Updated descriptions of DFE_CAL_TIME, DFE_CFG, and
RX_EN_IDLE_HOLD_DFE attributes in Ta bl e 4 -1 2. Renamed RX Clock Divider Control
section as RX Fabric Clock Output Control, page 207. Updated MGTREFCLKFAB[1] bit in
and added note 4 to Figure 4-15. Updated line rate ranges in Tab le 4- 23 . Updated RX Margin
Analysis, page 210. Added DFEEYEDACMON port to Tab le 4 -2 6. Replaced
INTDATAWIDTH with R X _ D ATA _W I DTH in and added note to Figure 4-19. Changed
RXOVERSAMPLER to RXOVERSAMPLEERR in Tab l e 4 -2 9 . Updated description of
RX_OVERSAMPLE_MODE in and added RXPLL_DIVSEL_OUT to Tab l e 4 -3 0 . Swapped the
order of the SIPO and Polarity Inversion blocks in Figure 4-20. Updated descriptions of
RX_PRBS_ERR_CNT and RXPRBSERR_LOOPBACK attributes in Tab le 4 -3 2. Replaced
GTXRESET with GTXRXRESET in Use Models, page 216. Changed PCOMMA_ALIGN and
MCOMMA_ALIGN to PCOMMA_DETECT and MCOMMA_DETECT, respectively, in
Alignment Status Signals, page 219 and Ta b le 4 -3 4 . Updated RX Buffer Bypass, page 231 with
restrictions on RX buffer bypass operation. Updated descriptions of
CHAN_BOND_1/2_MAX_SKEW a nd CHAN_BOND_SEQ_LEN attribute in Ta bl e 4 - 49 .
Added guideline for asynchronous GTXTXRESET pulse width in GTX RX Reset in Response
to GTXRXRESET Pulse, page 263. Added description of power supply regulators for
MGTAVCC and VCCINT in Overview, page 283.
In Tab le B -1 , changed attribute encoding 3 in attribute bits 1:0 of DADDRs 7h, 12h, and 13h
to Reserved.
02/23/10 2.2 Updated descriptions of RXDLYALIGNOVERRIDE in Tab le 4 -4 0 and
RX_DLYALIGN_OVRDSETTING in Ta bl e 4 - 41 . Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer, page 235, including Note 2 in Notes for Figure 4-32.. Updated
Figure 4-33.
Updated descriptions of DFETAPOVRD and DFEDLYOVRD ports after
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Date Version Revision
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05/24/10 2.3 Added description of buffer bypass mode to Multiple External Reference Clocks Use Model.
Added Power-Down Requirements for TX and RX Buffer Bypass.
Added description of TX buffer bypass to Functional Description, page 136 and Functional
Description, page 155.
Added description of RX buffer bypass to Functional Description, page 231. Updated
Functional Description, page 261 with description of buffer bypass mode. Removed
GTXTEST[12:0] from Tabl e 4 -5 2.
Updated Managing Unused GTX Transceivers. Replaced “group” with “bank” in Ta bl e 5-1 ,
Analog Power Supply Pins, and Partially Unused Quad Column. Added Note 2 to Ta bl e 5- 3
and Tab le 5 -4 . Added note about buffer bypass mode to Reference Clock Checklist. Added
Reference Clock Toggling.
10/01/10 2.4 Updated Functional Description, GTX TX Reset in Response to Completion of Configuration,
and GTX TX Reset in Response to GTXTXRESET Pulse.
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Date Version Revision
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01/17/11 2.5 Replaced PMA_COM_CFG with PMA_CFG in Ta bl e 2- 9. Replaced RXRATE with
RXRATE[1:0] in Chapter 4, Receiver. Added note before
TXDLYALIGNMONENB, RXDLYALIGNMONENB, PMA_RXSYNC_CFG,
TXDRIVE_LOOPBACK_HIZ, and TXDRIVE_LOOPBACK_PD to Ta bl e 1 -1. In Ta bl e 1 -1 ,
moved RX_PRBS_ERR_CNT from RX Pattern Checker to Status Registers (Read Only)
section. Added FF1154 Package Placement Diagrams, FF1155 Package Placement
Diagrams, FF1923 Package Placement Diagrams, and FF1924 Package Placement
Diagrams.
Updated Figure 2-1. Added RX_CLK25_DIVIDER and TX_CLK25_DIVIDER to Tab l e 2 -9 and
Tab le 1 -1 . Updated description of TXPDOWNASYNCH in Tab le 2 -11. Added BGTEST_CFG,
BIAS_CFG, and PMA_TX_CFG to Ta bl e 2 -1 2 and
ACJTAG. Updated Ta bl e 3 -1 0. Updated descriptions of TXDIFFCTRL[3:0],
TXPDOWNASYNCH, TXPOSTEMPHASIS[4:0], and TXPREEMPHASIS[3:0] in Ta b le 3 -3 1 .
Updated description of TXPOWERDOWN[1:0] in Tab le 3 -3 4.
Updated description of IGNORESIGDET and changed direction of RXVALID from In to Out
in Tab l e 4 -9 . Updated OOBDETECT_THRESHOLD attribute in Tab l e 4 -1 0 . Added Use Mode
– Fixed Tap Mode and Use Mode – Auto-To-Fix and Use Mode – Auto. Updated descriptions
of PMA_RX_CFG, RX_EN_IDLE_HOLD_CDR, RX_EN_IDLE_RESET_FR, and
RX_EN_IDLE_RESET_PH in Ta bl e 4 - 22 . Updated Eye Outline Scan Mode. Updated
description of RX_EYE_OFFSET in Ta bl e 4 - 27 . Updated description of PMA_RX_CFG in
Ta bl e 4 - 30 . Updated Figure 4-26. Added Manual Alignment, including Figure 4-27. Removed
RX_PRBS_ERR_CNT from Tab le 4 -3 2 and added it to Ta bl e 4 -3 3. Added RXSLIDE to
Ta bl e 4 - 34 and
MCOMMA_10B_VALUE, MCOMMA_DETECT, PCOMMA_10B_VALUE,
PCOMMA_DETECT, SHOW_REALIGN_COMMA, RX_SLIDE_MODE, and
RX_SLIDE_AUTO_WAIT to Ta b le 4 -3 5 and
of RX_LOS_THRESHOLD in Functional Description, page 226. Changed RX_DATA_WIDTH
attribute type in Ta bl e 4 - 39 . Added RXDLYALIGNMONENB to Tab le 4 - 40 . Added
PMA_RXSYNC_CFG to Ta bl e 4 -4 1. Changed direction of RXDATA[31:0] port from In to Out
in Tab le 4 -4 0.
Updated Common Package Power Plane Prioritization. Added Hot Swapping Devices.
Updated 2Ah and 47h rows of Ta ble B -1 . Added Tab le B -2 .
Added Appendix C, Low Latency Design.
Updated POWER_SAVE description in Ta ble 2 -1 2, Ta bl e 3 -1 9, and Ta bl e 4 -4 1. Updated
embedded table title of TXPOSTEMPHASIS[4:0] port in Tab le 3 - 31 . Updated description
of “From TX Parallel Data” in Figure 4-1 and Figure C-3. Updated Tab le 4 -2 . Updated
Use Mode – Auto-To-Fix and Use Mode – Auto. Updated Using the RX Phase Alignment
Circuit to Bypass the Buffer. Updated Figure 4-32 and Figure 4-34. Updated DADDR in
Tab le B -1.
Per XCN11009: Virtex-6: Data-Sheet, User Guides and JTAG ID Updates: Updated TX Buffer
Bypass: TX delay aligner bypassed, additional requirements on interconnect logic clocking
use model; Updated RX Buffer Bypass: RX delay aligner bypassed for lower line rates, higher
line rate support is an advanced feature.
Tab le 1 -1 . Updated description of ALIGN_COMMA_WORD, and added
Tab le 1 -1 . Updated Figure 4-28 and description
Tab le 1 -1 . Added
Tab le 1 -1 . Added Tab le 2 -1 7. Added
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Table of Contents
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Additional References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 1: Transceiver and Tool Overview
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port and Attribute Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Virtex-6 FPGA GTX Transceiver Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SIM_GTXRESET_SPEEDUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SIM_RECEIVER_DETECT_PASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SIM_RXREFCLK_SOURCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SIM_TXREFCLK_SOURCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SIM_VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SIM_TX_ELEC_IDLE_LEVEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FF484 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
FF784 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
FF1156 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FF1759 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
FF1154 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
FF1155 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
FF1923 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FF1924 Package Placement Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 2: Shared Transceiver Features
Reference Clock Input Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Use Modes: Reference Clock Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Single External Reference Clock Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Multiple External Reference Clocks Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PLL Settings for Common Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Generic Power-Down Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
PLL Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TX and RX Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Power-Down Requirements for TX and RX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . 122
Power-Down Features for PCI Express Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ACJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Dynamic Reconfiguration Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 3: Transmitter
TX Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FPGA TX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Interface Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
TXUSRCLK and TXUSRCLK2 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Using TXOUTCLK to Drive the GTX TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
TXOUTCLK Driving a GTX TX in 2-Byte Mode (Single Lane) . . . . . . . . . . . . . . . . . . . 131
TXOUTCLK Driving a GTX TX in 4-Byte Mode (Single Lane) . . . . . . . . . . . . . . . . . . . 132
TXOUTCLK Driving a GTX TX in 1-Byte Mode (Single Lane) . . . . . . . . . . . . . . . . . . . 133
TXOUTCLK Driving More Than One GTX TX in 2-Byte Mode (Multiple Lanes). . . . . 133
TXOUTCLK Driving More Than One GTX TX in 4-Byte Mode (Multiple Lanes). . . . . 134
TXOUTCLK Driving More Than One GTX TX in 1-Byte Mode (Multiple Lanes). . . . . 135
TX Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
GTX TX Reset in Response to Completion of Configuration . . . . . . . . . . . . . . . . . . . 139
GTX TX Reset in Response to GTXTXRESET Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
GTX TX Component-Level Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
After Power-up and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
After Turning on a Reference Clock to the TX PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
After Changing the Reference Clock to the TX PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
After Assertion/Deassertion of TXPOWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
TX Rate Change with the TX Buffer Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
TX Rate Change with the TX Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
TX Parallel Clock Source Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
TX 8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
8B/10B Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
K Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Enabling and Disabling 8B/10B Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
TX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Enabling the TX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
TX Gearbox Bit and Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
TX Gearbox Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
External Sequence Counter Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Internal Sequence Counter Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Using the TX Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Using the TX Buffer for Oversampling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
TX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Using the TX Phase-Alignment Circuit to Bypass the Buffer . . . . . . . . . . . . . . . . . . . 158
TX Phase Alignment after Rate Change Use Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Using the TX Phase Alignment Circuit to Minimize TX Lane-to-Lane Skew . . . . . . 160
Transmit Fabric Clocking Use Model for TX Buffer Bypass . . . . . . . . . . . . . . . . . . . . 161
TX Pattern Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
TX Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Using TX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
TX Fabric Clock Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Parallel Clock Divider and Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
PCI Express Clocking Use Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Rate Change Use Mode for PCI Express 2.0 Operation . . . . . . . . . . . . . . . . . . . . . . . . 171
TX Configurable Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Use Modes – TX Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
PCIe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Customizable User Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Use Mode – Resistor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
TX Receiver Detect Support for PCI Express Designs . . . . . . . . . . . . . . . . . . . . . . . 179
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
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TX Out-of-Band Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Chapter 4: Receiver
RX Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
RX Analog Front End. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Use Modes – RX Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Use Mode – Resistor Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
RX Out-of-Band Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
RX Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Use Mode – Continuous Time RX Linear Equalizer Only . . . . . . . . . . . . . . . . . . . . . . 199
Use Mode – Fixed Tap Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Use Mode – Auto-To-Fix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Use Mode – Auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
RX CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
RX Fabric Clock Output Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Parallel Clock Divider and Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
RX Margin Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Horizontal Eye Margin Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Eye Outline Scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Using RX Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
RX Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Feature Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
RX Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
RX Byte and Word Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Enabling Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Configuring Comma Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
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Activating Comma Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
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Alignment Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Alignment Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Manual Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
RX Loss-of-Sync State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
RX 8B/10B Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8B/10B Decoder Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
RX Running Disparity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
RX Buffer Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Using the RX Phase Alignment Circuit to Bypass the Buffer . . . . . . . . . . . . . . . . . . . 235
RX Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Using the RX Elastic Buffer for Channel Bonding or Clock Correction. . . . . . . . . . . 240
RX Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Using RX Clock Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Enabling Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Setting RX Elastic Buffer Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Setting Clock Correction Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Clock Correction Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Monitoring Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
RX Channel Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Using RX Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Enabling Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Channel Bonding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Connecting Channel Bonding Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Setting Channel Bonding Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Setting the Maximum Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Precedence between Channel Bonding and Clock Correction . . . . . . . . . . . . . . . . . . . 255
RX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Enabling the RX Gearbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
RX Gearbox Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
RX Gearbox Block Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
RX Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
GTX RX Reset in Response to Completion of Configuration . . . . . . . . . . . . . . . . . . . 263
GTX RX Reset in Response to GTXRXRESET Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Link Idle Reset Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
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After Power-up and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
After Turning on a Reference Clock to RX PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
After Changing the Reference Clock to RX PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
After Assertion/Deassertion of RXPOWERDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
RX Rate Change with RX Elastic Buffer Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
RX Rate Change with RX Elastic Buffer Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
RX Parallel Clock Source Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
After Remote Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Electrical Idle Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
After Connecting RXN/RXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
After an RX Elastic Buffer Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Before Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
After Changing Channel Bonding Mode on the Fly . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
After a PRBS Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
After an Oversampler Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
After Comma Realignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
FPGA RX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Interface Width Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
RXUSRCLK and RXUSRCLK2 Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Ports and Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Chapter 5: Board Design Guidelines
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Pin Description and Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
GTX Transceiver Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Termination Resistor Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Managing Unused GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Analog Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Unused Quad Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Partially Unused Quad Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Partially Used Quad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Quad Usage Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Reference Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Reference Clock Checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
LVDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
AC Coupled Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Unused Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Reference Clock Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Reference Clock Toggling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Power Supply and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Power Supply Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Linear vs. Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Switching Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Power Supply Distribution Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Staged Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
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Power Supply Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
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Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Board Stackup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
GTX Transceiver Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Signal BGA Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Hot Swapping Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
SelectIO Usage Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Appendix A: 8B/10B Valid Characters
Appendix B: DRP Address Map of the GTX Transceiver
Appendix C: Low Latency Design
GTX TX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
GTX RX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
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About This Guide
www.BDTIC.com/XILINX
This document shows how to use the GTX transceivers in Virtex®-6 FPGAs. In this
document:
• Virtex-6 FPGA GTX transceiver is abbreviated as GTX transceiver.
• GTXE1 is the name of the instantiation primitive that instantiates one Virtex-6 FPGA
GTX transceiver.
•A Quad or Q is a cluster or set of four GTX transceivers that share two differential
reference clock pin pairs and analog supply pins.
Guide Contents
This manual contains the following chapters:
• Chapter 1, Transceiver and Tool Overview
• Chapter 2, Shared Transceiver Features
• Chapter 3, Transmitter
• Chapter 4, Receiver
• Chapter 5, Board Design Guidelines
• Appendix A, 8B/10B Valid Characters
• Appendix B, DRP Address Map of the GTX Transceiver
• Appendix C, Low Latency Design
Preface
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/
• Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
• Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
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products/virtex6.
Preface: About This Guide
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• Virtex-6 FPGA Configuration User Guide
• Virtex-6 FPGA SelectIO Resources User Guide
• Virtex-6 FPGA Clocking Resources User Guide
• Virtex-6 FPGA Memory Resources User Guide
• Virtex-6 FPGA Configurable Logic Block User Guide
• Virtex-6 FPGA DSP48E1 Slice User Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
This guide describes the SelectIO™ resources available in all Virtex-6 devices.
This guide describes the clocking resources available in all Virtex-6 devices, including
the MMCM and PLLs.
The functionality of the block RAM and FIFO are described in this user guide.
This guide describes the capabilities of the configurable logic blocks (CLBs) available
in all Virtex-6 devices.
This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and
provides configuration examples.
• Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in all Virtex-6 FPGAs except the XC6VLX760.
• Virtex-6 FPGA System Monitor User Guide
The System Monitor functionality available in all Virtex-6 devices is outlined in this
guide.
• Virtex-6 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-6 FPGA GTX transceivers,
with a focus on strategies for making design decisions at the PCB and interface level.
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support
Additional References
.
.
The following documents provide additional information useful to this document:
1. High-Speed Serial I/O Made Simple
http://www.xilinx.com/publications/books/serialio/index.htm
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Transceiver and Tool Overview
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Overview
The Virtex®-6 FPGA GTX transceiver is a power-efficient transceiver. The GTX transceiver
is highly configurable and tightly integrated with the programmable logic resources of the
FPGA. It provides the following features to support a wide variety of applications:
• Current Mode Logic (CML) serial drivers/buffers with configurable termination,
voltage swing
• Programmable TX pre-emphasis/post-emphasis, RX equalization, and linear and
decision feedback equalization (DFE) for optimized signal integrity.
• Line rates from 600 Mb/s to 6.6 Gb/s, with optional 5X digital oversampling required
for rates between 480 Mb/s and 600 Mb/s.
• Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channel
bonding, and clock correction.
• Fixed latency modes for minimized, deterministic datapath latency.
• Beacon signaling for PCI Express® designs and Out-of-Band signaling including
COM signal support for SATA designs.
• RX/TX Gearbox provides header insertion and extraction support for 64B/66B and
64B/67B (Interlaken) protocols.
• Receiver eye scan
Horizontal eye scan in the time domain for testing purposes
Chapter 1
The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref 1], which
discusses high-speed serial transceiver technology and its applications. The
CORE Generator™ tool includes a Wizard to automatically configure GTX transceivers to
support configurations for different protocols or perform custom configuration (see
Virtex-6 FPGA GTX Transceiver Wizard). The GTX transceiver offers a data rate range and
features that allow physical layer support for various protocols.
Figure 1-1 illustrates a block view of the Virtex-6 FPGA GTX transceiver.
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Chapter 1: Transceiver and Tool Overview
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X-Ref Target - Figure 1-1
TX
Gearbox
TX PIPE
Control
FPGA
TX
Interface
8B/
10B
TX
Driver
TX
OOB
and
PCIe
TX
Pre/
Post
emp
PISO
PLL
Polarity
Pattern
Generator
Phase
Adjust
FIFO &
Over-
sampling
PCIe
Beacon
SATA
OOB
TX-PMA TX-PCS
PLL
To RX Parallel
Data (Near-End
PCS Loopback)
Pattern
Checker
From RX Parallel Data
(Far-End PMA Loopback)
Loss of Sync
From RX Parallel Data
(Far-End PCS Loopback)
RX PIPE Control
RX Status Control
RX
Gearbox
FPGA
RX
Interface
RX
EQ
RX OOB
DFE
RX
CDR
SIPO
Polarity
Over-
sampling
Comma
Detect
and
Align
Elastic
Buffer
10B
/8B
RX-PMA RX-PCS
UG366_c1_01_051509
Figure 1-1: Virtex-6 FPGA GTX Transceiver Simplified Block Diagram
Details about the different functional blocks of the transmitter and receiver including their
use models are described in Chapter 3, Transmitter, and Chapter 4, Receiver.
Figure 1-2 shows the GTX transceiver placement in an example Virtex-6 device
(XC6VLX75T).
Additional information on the functional blocks in Figure 1-2 is available in the following
locations:
20 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Overview
www.BDTIC.com/XILINX
•The Virtex-6 FPGA Configuration User Guide provides more information on the
Configuration and Clock, MMCM, and I/O blocks.
•The Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailed
information on the Ethernet MAC.
Figure 1-2 illustrates the location of the GTX transceiver inside the Virtex-6 XC6VLX75T
FPGA.
X-Ref Target - Figure 1-2
Virtex-6 FPGA (XC6VLX75T)
GTXE1
Column
GTXE1_
X0Y11
MMCM
Ethernet
MAC
GTXE1_
X0Y10
I/O
Column
I/O
Column
Configuration
MMCM
MMCM
I/O
Column
Ethernet
MAC
Integrated
Block for
PCI Express
Operation
Ethernet
MAC
Ethernet
MAC
GTXE1_
X0Y9
GTXE1_
X0Y8
GTXE1_
X0Y7
GTXE1_
X0Y6
GTXE1_
X0Y5
GTXE1_
X0Y4
GTXE1_
X0Y3
GTXE1_
X0Y2
GTXE1_
X0Y1
GTXE1_
X0Y0
Figure 1-2: GTX Transceiver Inside the Virtex-6 XC6VLX75T FPGA
GTX transceivers are clustered together in a set of four called a Quad or Q. Figure 1-3
illustrates the clustering of four GTX transceivers to a Quad. Refer to Implementation,
page 41 for placement information and the mapping of each transceiver into a specific
Quad.
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 21
UG366 (v2.5) January 17, 2011
UG366_c1_02_051509
Chapter 1: Transceiver and Tool Overview
From/To Adjacent Quad
From/To Adjacent Quad
UG366_c1_03_051509
TX-P2S
RX0
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX0
TX-P2S
RX1
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX1
TX-P2S
RX2
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX2
TX-P2S
RX3
To FPGA Logic
CLKs TX PLLPCS
RX DFE, CDR, S2P
CLKs RX PLL
From FPGA Logic
TX3
MGTREFCLK0
MGTREFCLK1
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-3
Figure 1-3: Quad Configuration
22 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
This cluster of four GTX transceivers share two differential reference clock pin pairs and
www.BDTIC.com/XILINX
clock routing. Chapter 2, Shared Transceiver Features, discusses details about reference
clock sources and the routing.
Port and Attribute Summary
The ports and attributes are grouped in tables for each functionality group (e.g., reference
clock selection). If a port or attribute appears in multiple chapters, it is listed in the group
of its first appearance. Ta bl e 1 -1 summarizes the ports and attributes according to
functionality group.
Port and Attribute Summary
Note:
are present in the instantiation primitive or are listed in Appendix B, DRP Address Map of the GTX
Transceiver but not in Ta bl e 1 - 1 .
Table 1-1: Port and Attribute Summary
Ta bl e 1 - 1 lists all the ports and attributes covered in this user guide. Some ports or attributes
Port/Attribute Section, Page
Simulation
Attributes:
• SIM_GTXRESET_SPEEDUP
• SIM_RECEIVER_DETECT_PASS
• SIM_RXREFCLK_SOURCE
• SIM_TX_ELEC_IDLE_LEVEL
• SIM_TXREFCLK_SOURCE
• SIM_VERSION
Clocking
Ports:
• GREFCLKRX
• GREFCLKTX
• MGTREFCLKRX[1:0]
• MGTREFCLKTX[1:0]
• NORTHREFCLKRX[1:0]
• NORTHREFCLKTX[1:0]
• PERFCLKRX
• PERFCLKTX
• RXPLLREFSELDY[2:0]
• SOUTHREFCLKRX[1:0]
• SOUTHREFCLKTX[1:0]
• TXPLLREFSELDY[2:0]
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Attributes:
• PMA_CAS_CLK_EN
• SIM_RXREFCLK_SOURCE[2:0]
• SIM_TXREFCLK_SOURCE[2:0]
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UG366 (v2.5) January 17, 2011
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Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
PLL
Ports:
• PLLTXRESET
• PLLRXRESET
• TXPLLLKDET
• RXPLLLKDET
• TXPLLLKDETEN
• RXPLLLKDETEN
• TXPLLPOWERDOWN
• RXPLLPOWERDOWN
Attributes:
• PMA_CFG
• TX_CLK_SOURCE
• TX_TDCC_CFG
• TXPLL_COM_CFG
• RXPLL_COM_CFG
• TXPLL_CP_CFG
• RXPLL_CP_CFG
• TXPLL_DIVSEL_FB
• RXPLL_DIVSEL_FB
• TXPLL_DIVSEL_OUT
• RXPLL_DIVSEL_OUT
• TXPLL_DIVSEL_REF
• RXPLL_DIVSEL_REF
• TXPLL_DIVSEL45_FB
• RXPLL_DIVSEL45_FB
• TXPLL_LKDET_CFG
• RXPLL_LKDET_CFG
• TXPLL_SATA
• RX_CLK25_DIVIDER
• TX_CLK25_DIVIDER
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Power Down
Ports:
• RXPLLPOWERDOWN
• RXPOWERDOWN[1:0]
• TXPDOWNASYNCH
• TXPLLPOWERDOWN
• TXPOWERDOWN[1:0]
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Table 1-1: Port and Attribute Summary (Cont’d)
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Port/Attribute Section, Page
Attributes:
• BGTEST_CFG
• BIAS_CFG
• PMA_TX_CFG
• POWER_SAVE
• TRANS_TIME_FROM_P2
• TRANS_TIME_NON_P2
• TRANS_TIME_RATE
• TRANS_TIME_TO_P2
Loopback
Ports:
• LOOPBACK[2:0]
Attributes:
• TXDRIVE_LOOPBACK_HIZ
• TXDRIVE_LOOPBACK_PD
Port and Attribute Summary
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DRP
Ports:
• DADDR[7:0]
• DCLK
• DEN
• DI[15:0]
• DRPDO[15:0]
• DRDY
• DWE
FPGA TX Interface
Ports:
• MGTREFCLKFAB[1:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXDATA[31:0]
• TXUSRCLK
• TXUSRCLK2
Attributes:
• GEN_TXUSRCLK
• TX_DATA_WIDTH
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Chapter 1: Transceiver and Tool Overview
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
TX Initialization
Ports:
• GTXTEST[12:0]
• GTXTXRESET
• PLLTXRESET
• TSTIN[19:0]
• TXDLYALIGNRESET
• TXRESET
• TXRESETDONE
Attributes:
• TX_EN_RATE_RESET_BUF
TX Encoder
Ports:
• TXBYPASS8B10B[3:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXCHARISK[3:0]
• TXENC8B10BUSE
• TXKERR[3:0]
• TXRUNDISP[3:0]
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TX Gearbox
Ports:
• TXGEARBOXREADY
• TXHEADER[2:0]
• TXSEQUENCE[6:0]
• TXSTARTSEQ
Attributes:
• GEARBOX_ENDEC
• TXGEARBOX_USE
TX Buffer
Ports:
• TXBUFSTATUS[1:0]
• TXRESET
Attributes:
• TX_BUFFER_USE
• TX_OVERSAMPLE_MODE
TX Buffer Bypass
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Table 1-1: Port and Attribute Summary (Cont’d)
www.BDTIC.com/XILINX
Port/Attribute Section, Page
Ports:
• TXDLYALIGNDISABLE
• TXDLYALIGNMONENB
• TXDLYALIGNMONITOR[7:0]
• TXDLYALIGNOVERRIDE
• TXDLYALIGNRESET
• TXDLYALIGNUPDSW
• TXENPMAPHASEALIGN
• TXOUTCLK
• TXPLLLKDET
• TXPLLLKDETEN
• TXPMASETPHASE
• TXUSRCLK
Attributes:
• TX_BUFFER_USE
• TX_BYTECLK_CFG[5:0]
• TX_DATA_WIDTH
• TX_DLYALIGN_CTRINC
• TX_DLYALIGN_LPFINC
• TX_DLYALIGN_MONSEL
• TX_DLYALIGN_OVRDSETTING
• TX_PMADATA_OPT
• TX_XCLK_SEL
• TXOUTCLK_CTRL
Port and Attribute Summary
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TX Pattern Generator
Ports:
• TXENPRBSTST[2:0]
• TXPRBSFORCEERR
Attributes:
• RXPRBSERR_LOOPBACK
TX Oversampling
Attributes:
• TX_OVERSAMPLE_MODE
TX Polarity Control
Ports:
• TXPOLARITY
TX Fabric Clock Output Control
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UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
Ports:
• GTXTEST[1]
• MGTREFCLKFAB[0]
• O
• ODIV2
• PHYSTATUS
• TXOUTCLK
• TXOUTCLKPCS
• TXRATE
• TXRATEDONE
Attributes:
• TRANS_TIME_RATE
• TX_EN_RATE_RESET_BUF
• TXOUTCLK_CTRL
• TXPLL_DIVSEL_OUT
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TX Configurable Driver
Ports:
• TXBUFDIFFCTRL[2:0]
• TXDEEMPH
• TXDIFFCTRL[3:0]
• TXELECIDLE
• TXINHIBIT
• TXMARGIN[2:0]
• TXPDOWNASYNCH
• TXPOSTEMPHASIS[4:0]
• TXPREEMPHASIS[3:0]
• TXP TXN
• TXSWING
Attributes:
• TX_DEEMPH_0[4:0]
• TX_DEEMPH_1[4:0]
• TX_DRIVE_MODE
• TX_MARGIN_FULL_0[6:0]
• TX_MARGIN_FULL_1[6:0]
• TX_MARGIN_FULL_2[6:0]
• TX_MARGIN_FULL_3[6:0]
• TX_MARGIN_FULL_4[6:0]
• TX_MARGIN_LOW_0[6:0]
• TX_MARGIN_LOW_1[6:0]
• TX_MARGIN_LOW_2[6:0]
• TX_MARGIN_LOW_3[6:0]
• TX_MARGIN_LOW_4[6:0]
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Table 1-1: Port and Attribute Summary (Cont’d)
www.BDTIC.com/XILINX
Port/Attribute Section, Page
TX Receiver Detect Support for PCI Express Designs
Ports:
• PHYSTATUS
• RXPOWERDOWN[1:0]
• TXPOWERDOWN[1:0]
• RXSTATUS[2:0]
• TXDETECTRX
TX OOB
Ports:
• COMFINISH
• TXCOMINIT
• TXCOMSAS
• TXCOMWAKE
• TXELECIDLE
• TXPOWERDOWN[1:0]
Port and Attribute Summary
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Attributes:
• COM_BURST_VAL
• TXPLL_SATA
RX AFE
Ports:
• RXN
• RXP
Attributes:
• AC_CAP_DIS
• CM_TRIM[1:0]
• RCV_TERM_GND
• RCV_TERM_VTTRX
• TERMINATION_CTRL[4:0]
• TERMINATION_OVRD
RX OOB
Ports:
• COMINITDET
• COMSASDET
• COMWAKEDET
• GATERXELECIDLE
• IGNORESIGDET
• RXELECIDLE
• RXSTATUS[2:0]
• RXVALID
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UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
Attributes:
• SAS_MAX_COMSAS
• SAS_MIN_COMSAS
• SATA_BURST_VAL
• SATA_IDLE_VAL
• SATA_MAX_BURST
• SATA_MAX_INIT
• SATA_MAX_WAKE
• SATA_MIN_BURST
• SATA_MIN_INIT
• SATA_MIN_WAKE
RX Equalizer
Ports:
• DFECLKDLYADJ[5:0]
• DFECLKDLYADJMON[5:0]
• DFEDLYOVRD
• DFEEYEDACMON[4:0]
• DFESENSCAL[2:0]
• DFETAP1[4:0]
• DFETAP1MONITOR[4:0]
• DFETAP2[4:0]
• DFETAP2MONITOR[4:0]
• DFETAP3[3:0]
• DFETAP3MONITOR[3:0]
• DFETAP4[3:0]
• DFETAP4MONITOR[3:0]
• DFETAPOVRD
• RXEQMIX[9:0]
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Attributes:
• DFE_CAL_TIME[4:0]
• DFE_CFG[7:0]
• RX_EN_IDLE_HOLD_DFE
RX CDR
Ports:
• RXCDRRESET
• RXRATE[1:0]
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UG366 (v2.5) January 17, 2011
Table 1-1: Port and Attribute Summary (Cont’d)
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Port/Attribute Section, Page
Attributes:
• CDR_PH_ADJ_TIME
• PMA_CDR_SCAN
• PMA_RX_CFG
• RX_EN_IDLE_HOLD_CDR
• RX_EN_IDLE_RESET_FR
• RX_EN_IDLE_RESET_PH
• RX_EYE_SCANMODE
• RXPLL_DIVSEL_OUT
RX Clock Divider Control
Ports:
• MGTREFCLKFAB[1]
• O
• ODIV2
• PHYSTATUS
• RXRATE[1:0]
• RXRATEDONE
• RXRECCLK
• RXRECCLKPCS
Port and Attribute Summary
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Attributes:
• RX_EN_RATE_RESET_BUF
• RXPLL_DIVSEL_OUT
• RXRECCLK_CTRL
• TRANS_TIME_RATE
RX Margin Analysis
Ports:
• RXDATA[31:0]
Attributes:
• RX_EYE_OFFSET
• RX_EYE_SCANMODE
RX Polarity Control
Ports:
• RXPOLARITY
RX Oversampling
Ports:
• RXENSAMPLEALIGN
• RXOVERSAMPLEERR
Attributes:
• PMA_RX_CFG
• RX_OVERSAMPLE_MODE
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Chapter 1: Transceiver and Tool Overview
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
RX Pattern Checker
Ports:
• PRBSCNTRESET
• RXENPRBSTST[2:0]
• RXPRBSERR
Attributes:
• RXPRBSERR_LOOPBACK
Status Registers (Read Only):
• RX_PRBS_ERR_CNT
RX Byte and Word Alignment
Ports:
• RXBYTEISALIGNED
• RXBYTEREALIGN
• RXCOMMADET
• RXCOMMADETUSE
• RXENMCOMMAALIGN
• RXENPCOMMAALIGN
• RXSLIDE
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Attributes:
• ALIGN_COMMA_WORD
• COMMA_10B_ENABLE
• COMMA_DOUBLE
• MCOMMA_10B_VALUE
• MCOMMA_DETECT
• PCOMMA_10B_VALUE
• PCOMMA_DETECT
• SHOW_REALIGN_COMMA
• RX_SLIDE_MODE
• RX_SLIDE_AUTO_WAIT
RX Loss-of-Sync State Machine
Ports:
• RXLOSSOFSYNC
Attributes:
• RX_LOS_INVALID_INCR
• RX_LOS_THRESHOLD
• RX_LOSS_OF_SYNC_FSM
RX 8B/10B Decoder
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Table 1-1: Port and Attribute Summary (Cont’d)
www.BDTIC.com/XILINX
Port/Attribute Section, Page
Ports:
• RXCHARISCOMMA[3:0]
• RXCHARISK[3:0]
• RXDEC8B10BUSE
• RXDISPERR[3:0]
• RXNOTINTABLE[3:0]
• RXRUNDISP[3:0]
Attributes:
• DEC_MCOMMA_DETECT
• DEC_PCOMMA_DETECT
• DEC_VALID_COMMA_ONLY
• RX_DATA_WIDTH
• RX_DECODE_SEQ_MATCH
RX Buffer Bypass
Ports:
• RXDLYALIGNDISABLE
• RXDLYALIGNMONENB
• RXDLYALIGNMONITOR[7:0]
• RXDLYALIGNOVERRIDE
• RXDLYALIGNRESET
• RXDLYALIGNSWPPRECURB
• RXDLYALIGNUPDSW
• RXENPMAPHASEALIGN
• RXPLLLKDET
• RXPLLLKDETEN
• RXPMASETPHASE
• RXRECCLK
• RXUSRCLK
Port and Attribute Summary
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Attributes:
• RX_BUFFER_USE
• RX_DATA_WIDTH
• RX_DLYALIGN_CTRINC
• RX_DLYALIGN_EDGESET
• RX_DLYALIGN_LPFINC
• RX_DLYALIGN_MONSEL
• RX_DLYALIGN_OVRDSETTING
• RX_XCLK_SEL
• RXRECCLK_CTRL
• RXUSRCLK_DLY
• PMA_RXSYNC_CFG
RX Elastic Buffer
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
Ports:
• RXBUFRESET
• RXBUFSTATUS[2:0]
Attributes:
• RX_BUFFER_USE
• RX_EN_IDLE_RESET_BUF
• RX_FIFO_ADDR_MODE
• RX_IDLE_HI_CNT
• RX_IDLE_LO_CNT
• RX_XCLK_SEL
RX Clock Correction
Ports:
• RXBUFRESET
• RXBUFSTATUS[2:0]
• RXCLKCORCNT[2:0]
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Attributes:
• CLK_COR_ADJ_LEN
• CLK_COR_DET_LEN
• CLK_COR_INSERT_IDLE_FLAG
• CLK_COR_KEEP_IDLE
• CLK_COR_MAX_LAT
• CLK_COR_MIN_LAT
• CLK_COR_PRECEDENCE
• CLK_COR_REPEAT_WAIT
• CLK_COR_SEQ_1_1
• CLK_COR_SEQ_1_2
• CLK_COR_SEQ_1_3
• CLK_COR_SEQ_1_4
• CLK_COR_SEQ_1_ENABLE
• CLK_COR_SEQ_2_1
• CLK_COR_SEQ_2_2
• CLK_COR_SEQ_2_3
• CLK_COR_SEQ_2_4
• CLK_COR_SEQ_2_ENABLE
• CLK_COR_SEQ_2_USE
• CLK_CORRECT_USE
• RX_DATA_WIDTH
• RX_DECODE_SEQ_MATCH
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RX Channel Bonding
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Table 1-1: Port and Attribute Summary (Cont’d)
www.BDTIC.com/XILINX
Port/Attribute Section, Page
Ports:
• RXCHANBONDSEQ
• RXCHANISALIGNED
• RXCHANREALIGN
• RXCHBONDI[3:0]
• RXCHBONDO[3:0]
• RXCHBONDLEVEL[2:0]
• RXCHBONDMASTER
• RXCHBONDSLAVE
• RXENCHANSYNC
Attributes:
• CHAN_BOND_1_MAX_SKEW
• CHAN_BOND_2_MAX_SKEW
• CHAN_BOND_KEEP_ALIGN
• CHAN_BOND_SEQ_1_1
• CHAN_BOND_SEQ_1_2
• CHAN_BOND_SEQ_1_3
• CHAN_BOND_SEQ_1_4
• CHAN_BOND_SEQ_1_ENABLE
• CHAN_BOND_SEQ_2_1
• CHAN_BOND_SEQ_2_2
• CHAN_BOND_SEQ_2_3
• CHAN_BOND_SEQ_2_4
• CHAN_BOND_SEQ_2_ENABLE
• CHAN_BOND_SEQ_2_CFG
• CHAN_BOND_SEQ_2_USE
• CHAN_BOND_SEQ_LEN
• PCI_EXPRESS_MODE
• RX_DATA_WIDTH
Port and Attribute Summary
page 247
page 247
page 248
page 248
page 248
page 248
page 248
page 248
page 248
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 249
page 250
page 250
page 250
RX Gearbox
Ports:
• RXDATAVALID
• RXGEARBOXSLIP
• RXHEADER[2:0]
• RXHEADERVALID
• RXSTARTOFSEQ
Attributes:
• GEARBOX_ENDEC
• RXGEARBOX_USE
RX Initialization
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UG366 (v2.5) January 17, 2011
page 256
page 256
page 256
page 256
page 256
page 256
page 256
Chapter 1: Transceiver and Tool Overview
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
Ports:
• GTXRXRESET
• PLLRXRESET
• PRBSCNTRESET
• RXBUFRESET
• RXCDRRESET
• RXDLYALIGNRESET
• RXRESET
• RXRESETDONE
• TSTIN[19:0]
Attributes:
• CDR_PH_ADJ_TIME[4:0]
• RX_EN_IDLE_HOLD_CDR
• RX_EN_IDLE_HOLD_DFE
• RX_EN_IDLE_RESET_BUF
• RX_EN_IDLE_RESET_PH
• RX_EN_IDLE_RESET_FR
• RX_EN_MODE_RESET_BUF
• RX_EN_RATE_RESET_BUF
• RX_EN_REALIGN_RESET_BUF
• RX_IDLE_HI_CNT[3:0]
• RX_IDLE_LO_CNT[3:0]
page 261
page 261
page 261
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 262
page 263
page 263
FPGA RX Interface
Ports:
• MGTREFCLKFAB[1:0]
• RXCHARISK[3:0]
• RXDATA[31:0]
• RXDISPERR[3:0]
• RXUSRCLK
• RXUSRCLK2
Attributes:
• GEN_RXUSRCLK
• RX_DATA_WIDTH
Virtex-6 FPGA GTX Transceiver Wizard
The Virtex-6 FPGA GTX Transceiver Wizard is the preferred tool to generate a wrapper to
instantiate a GTX transceiver primitive called GTXE1. The Wizard can be found in the
CORE Generator tool. Be sure to download the most up-to-date IP Update before using the
Wizard. Details on how to use this Wizard can be found in Virtex-6 FPGA GTX Transceiver
Getting Started Guide.
1. Start the CORE Generator tool.
2. Locate the GTX Transceiver Wizard in the taxonomy tree under:
page 271
page 271
page 271
page 271
page 272
page 272
page 272
page 272
36 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
/FPGA Features & Design/IO Interfaces
UG366_c1_04_010710
www.BDTIC.com/XILINX
See Figure 1-4.
X-Ref Target - Figure 1-4
Simulation
Simulation
Functional Description
Figure 1-4: Virtex-6 FPGA GTX Transceiver Wizard
3. Double-click V6 GTX Wizard to launch the Wizard.
Simulations using GTX transceivers have specific prerequisites that the simulation
environment and the test bench must fulfill.
The Synthesis and Simulation Design Guide explains how to set up the simulation
environment for supported simulators depending on the used Hardware Description
Language (HDL). This design guide can be downloaded from the Xilinx website.
The prerequisites for simulating a design with GTX transceivers are:
• Simulator with support for SecureIP models, which are encrypted versions of the
Verilog HDL used for implementation of the modeled block.
SecureIP is a new IP encryption methodology. To support SecureIP models, a Verilog
LRM - IEEE Std 1364-2005 encryption compliant simulator is required.
• Mixed-language simulator for VHDL simulation.
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 37
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
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SecureIP models use a Verilog standard. To use them in a VHDL design, a mixedlanguage simulator is required. The simulator must be capable of simulating VHDL
and Verilog simultaneously.
•Installed GTX SecureIP model.
• Correct setup of the simulator for SecureIP use (initialization file, environment
variable(s)).
• Running COMPXLIB (which compiles the simulation libraries (e.g. UNISIM,
SIMPRIMS, etc.) in the correct order.
• Correct simulator resolution (Verilog)
• The user guide of the simulator and the Synthesis and Simulation Design Guide provide
a detailed list of settings for SecureIP support.
Ports and Attributes
There are no simulation-only ports.
The GTXE1 primitive has attributes intended only for simulation. Ta b le 1 - 2 lists the
simulation-only attributes of the GTXE1 primitive. The names of these attributes start with
SIM_.
Table 1-2:
SIM_GTXRESET_SPEEDUP Integer This attribute shortens the time it takes to finish the GTXRXRESET
SIM_RECEIVER_DETECT_PASS Boolean This attribute simulates the TXDETECTRX feature in the
GTXE1 Simulation-Only Attributes
Attribute Type Description
and GTXTXRESET sequence and lock the TX PMA PLL and RX
PMA PLL during simulation.
0: The GTXRXRESET and GTXTXRESET sequence is simulated
with its original duration (standard initialization is
approximately 160 µs).
1: Shorten the GTXRXRESET and GTXTXRESET cycle time (fast
initialization is approximately 300 ns).
GTX
transceiver.
TRUE: Simulates an RX connection to the TX serial ports.
TXDETECTRX initiates receiver detection, and
RXSTATUS[2:0] = 011 reports that an RX port is connected.
FALSE (default): Simulates a disconnected TX port.
TXDETECTRX initiates receiver detection, and
RXSTATUS[2:0] = 000 reports that an RX port is not connected.
38 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
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Simulation
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Table 1-2:
SIM_RXREFCLK_SOURCE 3-Bit Binary This attribute selects the reference clock source used to drive the RX
SIM_TX_ELEC_IDLE_LEVEL 1-Bit Binary This attribute sets the value of TXN and TXP during simulation of
GTXE1 Simulation-Only Attributes
Attribute Type Description
(Cont’d)
PMA PLL in simulation for designs where the RX PMA PLL is
always driven by the same reference clock source. The
RXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
RXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKRX[0] port as the source
001: Selects the MGTREFCLKRX[1] port as the source
010: Selects the NORTHREFCLKRX[0] port as the source
011: Selects the NORTHREFCLKRX[1] port as the source
100: Selects the SOUTHREFCLKRX[0] port as the source
101: Selects the SOUTHREFCLKRX[1] port as the source
110: Reserved
111: Selects a clock from the FPGA logic which can be either port
GREFCLKRX or PERFCLKRX as the source
electrical idle. This attribute can be set to 0, 1, x, or z. The default for
this attribute is x.
SIM_TXREFCLK_SOURCE 3-Bit Binary This attribute selects the reference clock source used to drive the TX
PMA PLL in simulation for designs where the TX PMA PLL is
always driven by the same reference clock source. The
TXPLLREFSELDY port must be set to 000 for this attribute to select
the reference clock source. For multi-rate designs that require the
reference clock source to be changed on the fly, the
TXPLLREFSELDY port is used to dynamically select the source
instead.
000: Selects the MGTREFCLKTX[0] port as the source
001: Selects the MGTREFCLKTX[1] port as the source
010: Selects the NORTHREFCLKTX[0] port as the source
011: Selects the NORTHREFCLKTX[1] port as the source
100: Selects the SOUTHREFCLKTX[0] port as the source
101: Selects the SOUTHREFCLKTX[1] port as the source
110: Selects the RX recovered clock from the RX channel as the
source
111: Selects a clock from the FPGA logic that can be either the
GREFCLKTX or the PERFCLKTX port as the source
SIM_VERSION Real This attribute selects the simulation version to match different
steppings of silicon. The default for this attribute is 1.0.
SIM_GTXRESET_SPEEDUP
The SIM_GTXRESET_SPEEDUP attribute can be used to shorten the simulated lock time of
the TX PMA PLL and the RX PMA PLL.
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 39
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
t
USRCLKstabletGTXRESETsequencetlocktimeMMCM
+
www.BDTIC.com/XILINX
If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks
occasionally flatline while the GTX transceiver is locking. If an MMCM is used to divide
TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTX
transceiver and the MMCM have locked. Equation 1-1 provides an estimate of the time
required before a stable source from TXOUTCLK or RXRECCLK is available in simulation,
including the time required for any MMCMs used.
If the MMCM is not used, the term can be removed from the lock time equation.
SIM_RECEIVER_DETECT_PASS
The GTX transceiver includes a TXDETECTRX feature that allows the transmitter to detect
whether its serial ports are currently connected to a receiver by measuring rise time on the
TXP/TXN differential pin pair (see TX Receiver Detect Support for PCI Express Designs,
page 179).
The GTXE1 SecureIP model includes an attribute for simulating TXDETECTRX called
SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for
the GTX transceiver without modeling the measurement of rise time on the TXP/TXN
differential pin pair.
By default, SIM_RECEIVER_DETECT_PASS is set to FALSE. When FALSE, the attribute
models a disconnected receiver and TXDETECTRX operations indicate a receiver is
disconnected. To model a connected receiver, SIM_RECEIVER_DETECT_PASS for the
transceiver is set to TRUE.
Equation 1-1
SIM_RXREFCLK_SOURCE
The GTXE1 SecureIP model includes an attribute to select the reference clock source used
to drive the RX PMA PLL in simulation called SIM_RXREFCLK_SOURCE. This attribute is
to be used in designs where the RX PMA PLL’s clock input is always driven by the same
reference clock source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic. Tab le 1 -2 shows the possible settings for this attribute.
For multi-rate designs requiring the reference clock source driving the RX PMA PLL to be
changed on the fly, the RXPLLREFSELDY port is used to dynamically select the reference
clock source instead.
SIM_TXREFCLK_SOURCE
The GTXE1 SecureIP model includes an attribute to select the reference clock source used to
drive the TX PMA PLL in simulation called SIM_TXREFCLK_SOURCE. This attribute is to be
used in designs where the TX PMA PLL’s clock input is always driven by the same reference clock
source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic. Tab le 1 -2 shows the possible settings for this attribute.
For multi-rate designs requiring the reference clock source driving the TX PMA PLL to be
changed on the fly, the TXPLLREFSELDY port is used to dynamically select the reference
clock source instead.
40 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
SIM_VERSION
www.BDTIC.com/XILINX
The SIM_VERSION attribute selects the simulation version to match different steppings of
silicon. The default for this attribute is 1.0.
SIM_TX_ELEC_IDLE_LEVEL
The SIM_TX_ELEC_IDLE_LEVEL attribute sets the value of the transceiver’s differential
transmitter output pair TXN and TXP during simulation of electrical idle. This attribute
can be set to 0, 1, x, or z. The default for this attribute is x.
Implementation
Functional Description
This section provides the information needed to map Virtex-6 FPGA GTX transceivers
instantiated in a design to device resources, including:
• The location of the GTX transceiver on the available device and package
• The pad numbers of external signals associated with each GTX transceiver.
• How GTX transceiver and clocking resources instantiated in a design are mapped to
Implementation
combinations.
available locations with a user constraints file (UCF).
It is a common practice to define the location of GTX transceivers early in the design
process to ensure correct usage of clock resources and to facilitate signal integrity analysis
during board design. The implementation flow facilitates this practice through the use of
location constraints in the UCF.
While this section describes how to instantiate GTX clocking components, the details of the
different GTX transceiver clocking options are discussed in Reference Clock Selection,
page 102.
The position of the GTX transceiver is specified by an XY coordinate system that describes
the column number and its relative position within that column. In current members of the
Virtex-6 family, all GTX transceivers are located in a single column along one side of the
die.
The transceiver with the coordinates “X0Y0” is for a given device/package combination
always located at the lowest position of the lowest available bank. For the combination of
a package with a large pin count (for example, 1759) and a smaller device (for example,
XC6VLX240T), transceivers at higher or lower banks are not available.
There are two ways to create a UCF for designs that utilize the GTX transceiver. The
preferred method is to use the Virtex-6 FPGA GTX Transceiver Wizard (see Virtex-6 FPGA
GTX Transceiver Wizard, page 36). The Wizard automatically generates UCF templates
that configure the transceivers and contain placeholders for GTX placement information.
The UCFs generated by the Wizard can then be edited to customize operating parameters
and placement information for the application.
The second approach is to create the UCF by hand. When using this approach, the designer
must enter both configuration attributes that control transceiver operation as well as tile
location parameters. Care must be taken to ensure that all of the parameters needed to
configure the GTX transceiver are correctly entered.
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 41
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
LX75T: GTXE1_X0Y7
LX130T: GTXE1_X0Y15
LX75T: GTXE1_X0Y6
LX130T: GTXE1_X0Y14
QUAD_115
LX75T: GTXE1_X0Y5
LX130T: GTXE1_X0Y13
LX75T: GTXE1_X0Y4
LX130T: GTXE1_X0Y12
B1
B2
D1
D2
C3
C4
F1
F2
J4
J3
L4
L3
E3
E4
H1
H2
G3
G4
K1
K2
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_05_051509
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Figure 1-5, page 42 through Figure 1-23, page 60 provide the GTX transceiver position
information for all available device and package combinations along with the pad
numbers for the external signals associated with each GTX transceiver.
FF484 Package Placement Diagrams
Figure 1-5 through Figure 1-6 show the placement diagrams for the FF484 package.
X-Ref Target - Figure 1-5
Figure 1-5: Placement Diagram for the FF484 Package (1 of 2)
42 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-6
LX75T: GTXE1_X0Y3
LX130T: GTXE1_X0Y11
LX75T: GTXE1_X0Y2
LX130T: GTXE1_X0Y10
QUAD_114
LX75T: GTXE1_X0Y1
LX130T: GTXE1_X0Y9
LX75T: GTXE1_X0Y0
LX130T: GTXE1_X0Y8
W3
W4
M1
M2
Y1
Y2
P1
P2
R4
R3
U4
U3
AA3
AA4
T1
T2
AB1
AB2
V1
V2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 43
UG366 (v2.5) January 17, 2011
Figure 1-6: Placement Diagram for the FF484 Package (2 of 2)
Chapter 1: Transceiver and Tool Overview
LX75T: GTXE1_X0Y11
LX130T: GTXE1_X0Y19
LX195T: GTXE1_X0Y19
LX240T: GTXE1_X0Y19
LX75T: GTXE1_X0Y10
LX130T: GTXE1_X0Y18
LX195T: GTXE1_X0Y18
LX240T: GTXE1_X0Y18
QUAD_116
LX75T: GTXE1_X0Y9
LX130T: GTXE1_X0Y17
LX195T: GTXE1_X0Y17
LX240T: GTXE1_X0Y17
LX75T: GTXE1_X0Y8
LX130T: GTXE1_X0Y16
LX195T: GTXE1_X0Y16
LX240T: GTXE1_X0Y16
K1
K2
E3
E4
H1
H2
C3
C4
J4
J3
G4
G3
F1
F2
B1
B2
D1
D2
A3
A4
MGTRXP3_116
MGTRXN3_116
MGTTXP3_116
MGTTXN3_116
MGTRXP2_116
MGTRXN2_116
MGTTXP2_116
MGTTXN2_116
MGTREFCLK1P_116
MGTREFCLK1N_116
MGTREFCLK0P_116
MGTREFCLK0N_116
MGTRXP1_116
MGTRXN1_116
MGTTXP1_116
MGTTXN1_116
MGTRXP0_116
MGTRXN0_116
MGTTXP0_116
MGTTXN0_116
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FF784 Package Placement Diagrams
Figure 1-7 through Figure 1-9 show the placement diagrams for the FF784 package.
X-Ref Target - Figure 1-7
Figure 1-7: Placement Diagram for the FF784 Package (1 of 3)
44 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-8
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Implementation
LX75T: GTXE1_X0Y7
LX130T: GTXE1_X0Y15
LX195T: GTXE1_X0Y15
LX240T: GTXE1_X0Y15
LX75T: GTXE1_X0Y6
LX130T: GTXE1_X0Y14
LX195T: GTXE1_X0Y14
LX240T: GTXE1_X0Y14
QUAD_115
L3
L4
M1
M2
N3
N4
P1
P2
P6
P5
T6
T5
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
LX75T: GTXE1_X0Y5
LX130T: GTXE1_X0Y13
LX195T: GTXE1_X0Y13
LX240T: GTXE1_X0Y13
LX75T: GTXE1_X0Y4
LX130T: GTXE1_X0Y12
LX195T: GTXE1_X0Y12
LX240T: GTXE1_X0Y12
R3
R4
T1
T2
U3
U4
V1
V2
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
Figure 1-8: Placement Diagram for the FF784 Package (2 of 3)
UG366_c1_08_051509
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 45
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
LX75T: GTXE1_X0Y3
LX130T: GTXE1_X0Y11
LX195T: GTXE1_X0Y11
LX240T: GTXE1_X0Y11
LX75T: GTXE1_X0Y2
LX130T: GTXE1_X0Y10
LX195T: GTXE1_X0Y10
LX240T: GTXE1_X0Y10
QUAD_114
LX75T: GTXE1_X0Y1
LX130T: GTXE1_X0Y9
LX195T: GTXE1_X0Y9
LX240T: GTXE1_X0Y9
LX75T: GTXE1_X0Y0
LX130T: GTXE1_X0Y8
LX195T: GTXE1_X0Y8
LX240T: GTXE1_X0Y8
AC3
AC4
Y1
Y2
AE3
AE4
AB1
AB2
W4
W3
AA4
AA3
AG3
AG4
AD1
AD2
AH1
AH2
AF1
AF2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
UG366_c1_09_122109
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X-Ref Target - Figure 1-9
Figure 1-9: Placement Diagram for the FF784 Package (3 of 3)
46 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
FF1156 Package Placement Diagrams
LX130T: GTXE1_X0Y19
LX195T: GTXE1_X0Y19
LX240T: GTXE1_X0Y19
LX365T: GTXE1_X0Y19
SX315T: GTXE1_X0Y19
SX475T: GTXE1_X0Y27
LX130T: GTXE1_X0Y18
LX195T: GTXE1_X0Y18
LX240T: GTXE1_X0Y18
LX365T: GTXE1_X0Y18
SX315T: GTXE1_X0Y18
SX475T: GTXE1_X0Y26
QUAD_116
LX130T: GTXE1_X0Y17
LX195T: GTXE1_X0Y17
LX240T: GTXE1_X0Y17
LX365T: GTXE1_X0Y17
SX315T: GTXE1_X0Y17
SX475T: GTXE1_X0Y25
LX130T: GTXE1_X0Y16
LX195T: GTXE1_X0Y16
LX240T: GTXE1_X0Y16
LX365T: GTXE1_X0Y16
SX315T: GTXE1_X0Y16
SX475T: GTXE1_X0Y24
B5
B6
A3
A4
D5
D6
B1
B2
F6
F5
H6
H5
E3
E4
C3
C4
G3
G4
D1
D2
MGTRXP3_116
MGTRXN3_116
MGTTXP3_116
MGTTXN3_116
MGTRXP2_116
MGTRXN2_116
MGTTXP2_116
MGTTXN2_116
MGTREFCLK1P_116
MGTREFCLK1N_116
MGTREFCLK0P_116
MGTREFCLK0N_116
MGTRXP1_116
MGTRXN1_116
MGTTXP1_116
MGTTXN1_116
MGTRXP0_116
MGTRXN0_116
MGTTXP0_116
MGTTXN0_116
UG366_c1_10_051509
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Figure 1-10 through Figure 1-14 show the placement diagrams for the FF1156 package.
X-Ref Target - Figure 1-10
Implementation
Figure 1-10: Placement Diagram for the FF1156 Package (1 of 5)
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 47
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
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X-Ref Target - Figure 1-11
LX130T: GTXE1_X0Y15
LX195T: GTXE1_X0Y15
LX240T: GTXE1_X0Y15
LX365T: GTXE1_X0Y15
SX315T: GTXE1_X0Y15
SX475T: GTXE1_X0Y23
LX130T: GTXE1_X0Y14
LX195T: GTXE1_X0Y14
LX240T: GTXE1_X0Y14
LX365T: GTXE1_X0Y14
SX315T: GTXE1_X0Y14
SX475T: GTXE1_X0Y22
QUAD_115
J3
J4
F1
F2
K5
K6
H1
H2
M6
M5
P6
P5
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
LX130T: GTXE1_X0Y13
LX195T: GTXE1_X0Y13
LX240T: GTXE1_X0Y13
LX365T: GTXE1_X0Y13
SX315T: GTXE1_X0Y13
SX475T: GTXE1_X0Y21
LX130T: GTXE1_X0Y12
LX195T: GTXE1_X0Y12
LX240T: GTXE1_X0Y12
LX365T: GTXE1_X0Y12
SX315T: GTXE1_X0Y12
SX475T: GTXE1_X0Y20
L3
L4
K1
K2
N3
N4
M1
M2
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_11_051509
Figure 1-11: Placement Diagram for the FF1156 Package (2 of 5)
48 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-12
LX130T: GTXE1_X0Y11
LX195T: GTXE1_X0Y11
LX240T: GTXE1_X0Y11
LX365T: GTXE1_X0Y11
SX315T: GTXE1_X0Y11
SX475T: GTXE1_X0Y19
LX130T: GTXE1_X0Y10
LX195T: GTXE1_X0Y10
LX240T: GTXE1_X0Y10
LX365T: GTXE1_X0Y10
SX315T: GTXE1_X0Y10
SX475T: GTXE1_X0Y18
QUAD_114
LX130T: GTXE1_X0Y9
LX195T: GTXE1_X0Y9
LX240T: GTXE1_X0Y9
LX365T: GTXE1_X0Y9
SX315T: GTXE1_X0Y9
SX475T: GTXE1_X0Y17
LX130T: GTXE1_X0Y8
LX195T: GTXE1_X0Y8
LX240T: GTXE1_X0Y8
LX365T: GTXE1_X0Y8
SX315T: GTXE1_X0Y8
SX475T: GTXE1_X0Y16
R3
R4
P1
P2
U3
U4
T1
T2
T6
T5
V6
V5
W3
W4
V1
V2
AA3
AA4
Y1
Y2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
UG366_c1_12_051509
www.BDTIC.com/XILINX
Implementation
Figure 1-12: Placement Diagram for the FF1156 Package (3 of 5)
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 49
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-13
LX130T: GTXE1_X0Y7
LX195T: GTXE1_X0Y7
LX240T: GTXE1_X0Y7
LX365T: GTXE1_X0Y7
SX315T: GTXE1_X0Y7
SX475T: GTXE1_X0Y15
LX130T: GTXE1_X0Y6
LX195T: GTXE1_X0Y6
LX240T: GTXE1_X0Y6
LX365T: GTXE1_X0Y6
SX315T: GTXE1_X0Y6
SX475T: GTXE1_X0Y14
QUAD_113
AC3
AC4
AB1
AB2
AE3
AE4
AD1
AD2
AB6
AB5
AD6
AD5
MGTRXP3_113
MGTRXN3_113
MGTTXP3_113
MGTTXN3_113
MGTRXP2_113
MGTRXN2_113
MGTTXP2_113
MGTTXN2_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTREFCLK0P_113
MGTREFCLK0N_113
LX130T: GTXE1_X0Y5
LX195T: GTXE1_X0Y5
LX240T: GTXE1_X0Y5
LX365T: GTXE1_X0Y5
SX315T: GTXE1_X0Y5
SX475T: GTXE1_X0Y13
LX130T: GTXE1_X0Y4
LX195T: GTXE1_X0Y4
LX240T: GTXE1_X0Y4
LX365T: GTXE1_X0Y4
SX315T: GTXE1_X0Y4
SX475T: GTXE1_X0Y12
AF5
AF6
AF1
AF2
AG3
AG4
AH1
AH2
MGTRXP1_113
MGTRXN1_113
MGTTXP1_113
MGTTXN1_113
MGTRXP0_113
MGTRXN0_113
MGTTXP0_113
MGTTXN0_113
UG366_c1_13_051509
Figure 1-13: Placement Diagram for the FF1156 Package (4 of 5)
50 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-14
www.BDTIC.com/XILINX
Implementation
LX130T: GTXE1_X0Y3
LX195T: GTXE1_X0Y3
LX240T: GTXE1_X0Y3
LX365T: GTXE1_X0Y3
SX315T: GTXE1_X0Y3
SX475T: GTXE1_X0Y11
LX130T: GTXE1_X0Y2
LX195T: GTXE1_X0Y2
LX240T: GTXE1_X0Y2
LX365T: GTXE1_X0Y2
SX315T: GTXE1_X0Y2
SX475T: GTXE1_X0Y10
QUAD_112
AJ3
AJ4
AK1
AK2
AL3
AL4
AM1
AM2
AH6
AH5
AK6
AK5
MGTRXP3_112
MGTRXN3_112
MGTTXP3_112
MGTTXN3_112
MGTRXP2_112
MGTRXN2_112
MGTTXP2_112
MGTTXN2_112
MGTREFCLK1P_112
MGTREFCLK1N_112
MGTREFCLK0P_112
MGTREFCLK0N_112
LX130T: GTXE1_X0Y1
LX195T: GTXE1_X0Y1
LX240T: GTXE1_X0Y1
LX365T: GTXE1_X0Y1
SX315T: GTXE1_X0Y1
SX475T: GTXE1_X0Y9
LX130T: GTXE1_X0Y0
LX195T: GTXE1_X0Y0
LX240T: GTXE1_X0Y0
LX365T: GTXE1_X0Y0
SX315T: GTXE1_X0Y0
SX475T: GTXE1_X0Y8
AM5
AM6
AN3
AN4
AP5
AP6
AP1
AP2
MGTRXP1_112
MGTRXN1_112
MGTTXP1_112
MGTTXN1_112
MGTRXP0_112
MGTRXN0_112
MGTTXP0_112
MGTTXN0_112
UG366_c1_14_051509
Figure 1-14: Placement Diagram for the FF1156 Package (5 of 5)
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 51
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
FF1759 Package Placement Diagrams
Figure 1-15 through Figure 1-23 show the placement diagrams for the FF1759 package.
X-Ref Target - Figure 1-15
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y35
SX315T: Not available
SX475T: GTXE1_X0Y35
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y34
SX315T: Not available
SX475T: GTXE1_X0Y34
QUAD_118
A5
A6
B3
B4
B7
B8
C1
C2
A10
A9
C10
C9
MGTRXP3_118
MGTRXN3_118
MGTTXP3_118
MGTTXN3_118
MGTRXP2_118
MGTRXN2_118
MGTTXP2_118
MGTTXN2_118
MGTREFCLK1P_118
MGTREFCLK1N_118
MGTREFCLK0P_118
MGTREFCLK0N_118
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y33
SX315T: Not available
SX475T: GTXE1_X0Y33
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y32
SX315T: Not available
SX475T: GTXE1_X0Y32
Figure 1-15: Placement Diagram for the FF1759 Package (1 of 9)
C5
C6
D3
D4
D7
D8
E1
E2
MGTRXP1_118
MGTRXN1_118
MGTTXP1_118
MGTTXN1_118
MGTRXP0_118
MGTRXN0_118
MGTTXP0_118
MGTTXN0_118
UG366_c1_15_051509
52 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-16
www.BDTIC.com/XILINX
Implementation
LX240T: GTXE1_X0Y23
LX365T: GTXE1_X0Y23
LX550T: GTXE1_X0Y31
SX315T: GTXE1_X0Y23
SX475T: GTXE1_X0Y31
LX240T: GTXE1_X0Y22
LX365T: GTXE1_X0Y22
LX550T: GTXE1_X0Y30
SX315T: GTXE1_X0Y22
SX475T: GTXE1_X0Y30
QUAD_117
E5
E6
F3
F4
F7
F8
G1
G2
E10
E9
G10
G9
MGTRXP3_117
MGTRXN3_117
MGTTXP3_117
MGTTXN3_117
MGTRXP2_117
MGTRXN2_117
MGTTXP2_117
MGTTXN2_117
MGTREFCLK1P_117
MGTREFCLK1N_117
MGTREFCLK0P_117
MGTREFCLK0N_117
G5
LX240T: GTXE1_X0Y21
LX365T: GTXE1_X0Y21
LX550T: GTXE1_X0Y29
SX315T: GTXE1_X0Y21
SX475T: GTXE1_X0Y29
LX240T: GTXE1_X0Y20
LX365T: GTXE1_X0Y20
LX550T: GTXE1_X0Y28
SX315T: GTXE1_X0Y20
SX475T: GTXE1_X0Y28
Figure 1-16: Placement Diagram for the FF1759 Package (2 of 9)
G6
H3
H4
H7
H8
J1
J2
MGTRXP1_117
MGTRXN1_117
MGTTXP1_117
MGTTXN1_117
MGTRXP0_117
MGTRXN0_117
MGTTXP0_117
MGTTXN0_117
UG366_c1_16_051509
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 53
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-17
LX240T: GTXE1_X0Y19
LX365T: GTXE1_X0Y19
LX550T: GTXE1_X0Y27
SX315T: GTXE1_X0Y19
SX475T: GTXE1_X0Y27
LX240T: GTXE1_X0Y18
LX365T: GTXE1_X0Y18
LX550T: GTXE1_X0Y26
SX315T: GTXE1_X0Y18
SX475T: GTXE1_X0Y26
QUAD_116
J5
J6
K3
K4
L5
L6
L1
L2
K8
K7
M8
M7
MGTRXP3_116
MGTRXN3_116
MGTTXP3_116
MGTTXN3_116
MGTRXP2_116
MGTRXN2_116
MGTTXP2_116
MGTTXN2_116
MGTREFCLK1P_116
MGTREFCLK1N_116
MGTREFCLK0P_116
MGTREFCLK0N_116
N5
LX240T: GTXE1_X0Y17
LX365T: GTXE1_X0Y17
LX550T: GTXE1_X0Y25
SX315T: GTXE1_X0Y17
SX475T: GTXE1_X0Y25
LX240T: GTXE1_X0Y16
LX365T: GTXE1_X0Y16
LX550T: GTXE1_X0Y24
SX315T: GTXE1_X0Y16
SX475T: GTXE1_X0Y24
Figure 1-17: Placement Diagram for the FF1759 Package (3 of 9)
N6
M3
M4
P7
P8
N1
N2
MGTRXP1_116
MGTRXN1_116
MGTTXP1_116
MGTTXN1_116
MGTRXP0_116
MGTRXN0_116
MGTTXP0_116
MGTTXN0_116
UG366_c1_17_051509
54 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-18
www.BDTIC.com/XILINX
Implementation
LX240T: GTXE1_X0Y15
LX365T: GTXE1_X0Y15
LX550T: GTXE1_X0Y23
SX315T: GTXE1_X0Y15
SX475T: GTXE1_X0Y23
LX240T: GTXE1_X0Y14
LX365T: GTXE1_X0Y14
LX550T: GTXE1_X0Y22
SX315T: GTXE1_X0Y14
SX475T: GTXE1_X0Y22
QUAD_115
R5
R6
P3
P4
U5
U6
R1
R2
T8
T7
V8
V7
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
V3
LX240T: GTXE1_X0Y13
LX365T: GTXE1_X0Y13
LX550T: GTXE1_X0Y21
SX315T: GTXE1_X0Y13
SX475T: GTXE1_X0Y21
LX240T: GTXE1_X0Y12
LX365T: GTXE1_X0Y12
LX550T: GTXE1_X0Y20
SX315T: GTXE1_X0Y12
SX475T: GTXE1_X0Y20
Figure 1-18: Placement Diagram for the FF1759 Package (4 of 9)
V4
T3
T4
W5
W6
U1
U2
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_18_051509
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 55
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
LX240T: GTXE1_X0Y11
LX365T: GTXE1_X0Y11
LX550T: GTXE1_X0Y19
SX315T: GTXE1_X0Y11
SX475T: GTXE1_X0Y19
LX240T: GTXE1_X0Y10
LX365T: GTXE1_X0Y10
LX550T: GTXE1_X0Y18
SX315T: GTXE1_X0Y10
SX475T: GTXE1_X0Y18
QUAD_114
LX240T: GTXE1_X0Y9
LX365T: GTXE1_X0Y9
LX550T: GTXE1_X0Y17
SX315T: GTXE1_X0Y9
SX475T: GTXE1_X0Y17
LX240T: GTXE1_X0Y8
LX365T: GTXE1_X0Y8
LX550T: GTXE1_X0Y16
SX315T: GTXE1_X0Y8
SX475T: GTXE1_X0Y16
Y3
Y4
W1
W2
AA5
AA6
AA1
AA2
Y8
Y7
AB8
AB7
AB3
AB4
AC1
AC2
AC5
AC6
AE1
AE2
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
UG366_c1_19_051509
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-19
56 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-19: Placement Diagram for the FF1759 Package (5 of 9)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-20
www.BDTIC.com/XILINX
Implementation
LX240T: GTXE1_X0Y7
LX365T: GTXE1_X0Y7
LX550T: GTXE1_X0Y15
SX315T: GTXE1_X0Y7
SX475T: GTXE1_X0Y15
LX240T: GTXE1_X0Y6
LX365T: GTXE1_X0Y6
LX550T: GTXE1_X0Y14
SX315T: GTXE1_X0Y6
SX475T: GTXE1_X0Y14
QUAD_113
AD3
AD4
AG1
AG2
AE5
AE6
AH3
AH4
AD8
AD7
AF8
AF7
MGTRXP3_113
MGTRXN3_113
MGTTXP3_113
MGTTXN3_113
MGTRXP2_113
MGTRXN2_113
MGTTXP2_113
MGTTXN2_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTREFCLK0P_113
MGTREFCLK0N_113
AF3
LX240T: GTXE1_X0Y5
LX365T: GTXE1_X0Y5
LX550T: GTXE1_X0Y13
SX315T: GTXE1_X0Y5
SX475T: GTXE1_X0Y13
LX240T: GTXE1_X0Y4
LX365T: GTXE1_X0Y4
LX550T: GTXE1_X0Y12
SX315T: GTXE1_X0Y4
SX475T: GTXE1_X0Y12
Figure 1-20: Placement Diagram for the FF1759 Package (6 of 9)
AF4
AJ1
AJ2
AG5
AG6
AK3
AK4
MGTRXP1_113
MGTRXN1_113
MGTTXP1_113
MGTTXN1_113
MGTRXP0_113
MGTRXN0_113
MGTTXP0_113
MGTTXN0_113
UG366_c1_20_051509
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 57
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
LX240T: GTXE1_X0Y3
LX365T: GTXE1_X0Y3
LX550T: GTXE1_X0Y11
SX315T: GTXE1_X0Y3
SX475T: GTXE1_X0Y11
LX240T: GTXE1_X0Y2
LX365T: GTXE1_X0Y2
LX550T: GTXE1_X0Y10
SX315T: GTXE1_X0Y2
SX475T: GTXE1_X0Y10
QUAD_112
LX240T: GTXE1_X0Y1
LX365T: GTXE1_X0Y1
LX550T: GTXE1_X0Y9
SX315T: GTXE1_X0Y1
SX475T: GTXE1_X0Y9
LX240T: GTXE1_X0Y0
LX365T: GTXE1_X0Y0
LX550T: GTXE1_X0Y8
SX315T: GTXE1_X0Y0
SX475T: GTXE1_X0Y8
AJ5
AJ6
AL1
AL2
AL5
AL6
AM3
AM4
AH8
AH7
AK8
AK7
AM7
AM8
AN1
AN2
AN5
AN6
AP3
AP4
MGTTXP0_112
MGTTXN0_112
MGTRXP0_112
MGTRXN0_112
MGTTXP1_112
MGTTXN1_112
MGTRXP1_112
MGTRXN1_112
MGTREFCLK0P_112
MGTREFCLK0N_112
MGTREFCLK1P_112
MGTREFCLK1N_112
MGTTXP2_112
MGTTXN2_112
MGTRXP2_112
MGTRXN2_112
MGTTXP3_112
MGTTXN3_112
MGTRXP3_112
MGTRXN3_112
UG366_c1_21_051509
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-21
58 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-21: Placement Diagram for the FF1759 Package (7 of 9)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-22
www.BDTIC.com/XILINX
Implementation
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y7
SX315T: Not available
SX475T: GTXE1_X0Y7
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y6
SX315T: Not available
SX475T: GTXE1_X0Y6
QUAD_111
AP7
AP8
AR1
AR2
AR5
AR6
AT 3
AT 4
AT 8
AT 7
AU10
AU9
MGTRXP3_111
MGTRXN3_111
MGTTXP3_111
MGTTXN3_111
MGTRXP2_111
MGTRXN2_111
MGTTXP2_111
MGTTXN2_111
MGTREFCLK1P_111
MGTREFCLK1N_111
MGTREFCLK0P_111
MGTREFCLK0N_111
AU5
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y5
SX315T: Not available
SX475T: GTXE1_X0Y5
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y4
SX315T: Not available
SX475T: GTXE1_X0Y4
Figure 1-22: Placement Diagram for the FF1759 Package (8 of 9)
AU6
AU1
AU2
AV7
AV8
AV3
AV4
MGTRXP1_111
MGTRXN1_111
MGTTXP1_111
MGTTXN1_111
MGTRXP0_111
MGTRXN0_111
MGTTXP0_111
MGTTXN0_111
UG366_c1_22_051509
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 59
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y3
SX315T: Not available
SX475T: GTXE1_X0Y3
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y2
SX315T: Not available
SX475T: GTXE1_X0Y2
QUAD_110
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y1
SX315T: Not available
SX475T: GTXE1_X0Y1
LX240T: Not available
LX365T: Not available
LX550T: GTXE1_X0Y0
SX315T: Not available
SX475T: GTXE1_X0Y0
AW5
AW6
AW1
AW2
AY7
AY8
AY3
AY4
AW10
AW9
BA10
BA9
BA5
BA6
BA1
BA2
BB7
BB8
BB3
BB4
MGTTXP0_110
MGTTXN0_110
MGTRXP0_110
MGTRXN0_110
MGTTXP1_110
MGTTXN1_110
MGTRXP1_110
MGTRXN1_110
MGTREFCLK0P_110
MGTREFCLK0N_110
MGTREFCLK1P_110
MGTREFCLK1N_110
MGTTXP2_110
MGTTXN2_110
MGTRXP2_110
MGTRXN2_110
MGTTXP3_110
MGTTXN3_110
MGTRXP3_110
MGTRXN3_110
UG366_c1_23_051509
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-23
60 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-23: Placement Diagram for the FF1759 Package (9 of 9)
UG366 (v2.5) January 17, 2011
FF1154 Package Placement Diagrams
HX250T:GTXE1_X1Y23
HX380T:GTXE1_X1Y23
HX250T:GTXE1_X1Y22
HX380T:GTXE1_X1Y22
HX250T:GTXE1_X1Y21
HX380T:GTXE1_X1Y21
HX250T:GTXE1_X1Y20
HX380T:GTXE1_X1Y20
QUAD_115
D5
D6
A3
A4
F5
F6
B1
B2
G8
G7
J8
J7
H5
H6
C3
C4
J3
J4
D1
D2
MGTTXP0_115
MGTTXN0_115
MGTRXP0_115
MGTRXN0_115
MGTTXP1_115
MGTTXN1_115
MGTRXP1_115
MGTRXN1_115
MGTREFCLK0P_115
MGTREFCLK0N_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTTXP2_115
MGTTXN2_115
MGTRXP2_115
MGTRXN2_115
MGTTXP3_115
MGTTXN3_115
MGTRXP3_115
MGTRXN3_115
Right Edge of the Die
UG366_c1_24_111110
www.BDTIC.com/XILINX
Figure 1-24 through Figure 1-35 show the placement diagrams for the FF1154 package.
X-Ref Target - Figure 1-24
Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 61
UG366 (v2.5) January 17, 2011
Figure 1-24: Placement Diagram for the FF1154 Package (1 of 12)
Chapter 1: Transceiver and Tool Overview
HX250T:GTXE1_X1Y19
HX380T:GTXE1_X1Y19
HX250T:GTXE1_X1Y18
HX380T:GTXE1_X1Y18
HX250T:GTXE1_X1Y17
HX380T:GTXE1_X1Y17
HX250T:GTXE1_X1Y16
HX380T:GTXE1_X1Y16
QUAD_114
K5
K6
E3
E4
L3
L4
F1
F2
L8
L7
N8
N7
M5
M6
G3
G4
N3
N4
H1
H2
MGTTXP0_114
MGTTXN0_114
MGTRXP0_114
MGTRXN0_114
MGTTXP1_114
MGTTXN1_114
MGTRXP1_114
MGTRXN1_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTTXP2_114
MGTTXN2_114
MGTRXP2_114
MGTRXN2_114
MGTTXP3_114
MGTTXN3_114
MGTRXP3_114
MGTRXN3_114
UG366_c1_25_111110
Right Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-25
62 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-25: Placement Diagram for the FF1154 Package (2 of 12)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-26
HX250T:GTXE1_X1Y15
HX380T:GTXE1_X1Y15
HX250T:GTXE1_X1Y14
HX380T:GTXE1_X1Y14
HX250T:GTXE1_X1Y13
HX380T:GTXE1_X1Y13
HX250T:GTXE1_X1Y12
HX380T:GTXE1_X1Y12
QUAD_113
P5
P6
K1
K2
T5
T6
M1
M2
R8
R7
U8
U7
R3
R4
P1
P2
U3
U4
T1
T2
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
UG366_c1_26_111110
Right Edge of the Die
www.BDTIC.com/XILINX
Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 63
UG366 (v2.5) January 17, 2011
Figure 1-26: Placement Diagram for the FF1154 Package (3 of 12)
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-27
Right Edge of the Die
HX250T:GTXE1_X1Y11
HX380T:GTXE1_X1Y11
HX250T:GTXE1_X1Y10
HX380T:GTXE1_X1Y10
QUAD_112
V5
V6
V1
V2
W3
W4
Y1
Y2
W8
W7
AA8
AA7
MGTRXP3_112
MGTRXN3_112
MGTTXP3_112
MGTTXN3_112
MGTRXP2_112
MGTRXN2_112
MGTTXP2_112
MGTTXN2_112
MGTREFCLK1P_112
MGTREFCLK1N_112
MGTREFCLK0P_112
MGTREFCLK0N_112
Y5
HX250T:GTXE1_X1Y9
HX380T:GTXE1_X1Y9
HX250T:GTXE1_X1Y8
HX380T:GTXE1_X1Y8
Figure 1-27: Placement Diagram for the FF1154 Package (4 of 12)
Y6
AB1
AB2
AA3
AA4
AD1
AD2
MGTRXP1_112
MGTRXN1_112
MGTTXP1_112
MGTTXN1_112
MGTRXP0_112
MGTRXN0_112
MGTTXP0_112
MGTTXN0_112
UG366_c1_27_111110
64 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-28
www.BDTIC.com/XILINX
Implementation
Right Edge of the Die
HX250T:GTXE1_X1Y7
HX380T:GTXE1_X1Y7
HX250T:GTXE1_X1Y6
HX380T:GTXE1_X1Y6
QUAD_111
AB5
AB6
AF1
AF2
AC3
AC4
AH1
AH2
AC8
AC7
AE8
AE7
MGTRXP3_111
MGTRXN3_111
MGTTXP3_111
MGTTXN3_111
MGTRXP2_111
MGTRXN2_111
MGTTXP2_111
MGTTXN2_111
MGTREFCLK1P_111
MGTREFCLK1N_111
MGTREFCLK0P_111
MGTREFCLK0N_111
AD5
HX250T:GTXE1_X1Y5
HX380T:GTXE1_X1Y5
HX250T:GTXE1_X1Y4
HX380T:GTXE1_X1Y4
Figure 1-28: Placement Diagram for the FF1154 Package (5 of 12)
AD6
AJ3
AJ4
AE3
AE4
AK1
AK2
MGTRXP1_111
MGTRXN1_111
MGTTXP1_111
MGTTXN1_111
MGTRXP0_111
MGTRXN0_111
MGTTXP0_111
MGTTXN0_111
UG366_c1_28_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 65
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
HX250T:GTXE1_X1Y3
HX380T:GTXE1_X1Y3
HX250T:GTXE1_X1Y2
HX380T:GTXE1_X1Y2
HX250T:GTXE1_X1Y1
HX380T:GTXE1_X1Y1
HX250T:GTXE1_X1Y0
HX380T:GTXE1_X1Y0
QUAD_110
AF5
AF6
AL3
AL4
AG3
AG4
AM1
AM2
AG8
AG7
AJ8
AJ7
AH5
AH6
AN3
AN4
AK5
AK6
AP1
AP2
MGTTXP0_110
MGTTXN0_110
MGTRXP0_110
MGTRXN0_110
MGTTXP1_110
MGTTXN1_110
MGTRXP1_110
MGTRXN1_110
MGTREFCLK0P_110
MGTREFCLK0N_110
MGTREFCLK1P_110
MGTREFCLK1N_110
MGTTXP2_110
MGTTXN2_110
MGTRXP2_110
MGTRXN2_110
MGTTXP3_110
MGTTXN3_110
MGTRXP3_110
MGTRXN3_110
UG366_c1_29_111110
Right Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-29
66 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-29: Placement Diagram for the FF1154 Package (6 of 12)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-30
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_105
MGTRXN3_105
MGTTXP3_105
MGTTXN3_105
MGTRXP2_105
MGTRXN2_105
MGTTXP2_105
MGTTXN2_105
MGTREFCLK1P_105
MGTREFCLK1N_105
MGTREFCLK0P_105
MGTREFCLK0N_105
D30
D29
A32
A31
F30
F29
B34
B33
G27
G28
J27
J28
HX250T:GTXE1_X0Y23
HX380T:GTXE1_X0Y23
HX250T:GTXE1_X0Y22
HX380T:GTXE1_X0Y22
QUAD_105
MGTRXP1_105
MGTRXN1_105
MGTTXP1_105
MGTTXN1_105
MGTRXP0_105
MGTRXN0_105
MGTTXP0_105
MGTTXN0_105
Figure 1-30: Placement Diagram for the FF1154 Package (7 of 12)
H30
H29
C32
C31
J32
J31
D34
D33
HX250T:GTXE1_X0Y21
HX380T:GTXE1_X0Y21
HX250T:GTXE1_X0Y20
HX380T:GTXE1_X0Y20
UG366_c1_30_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 67
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-31
Left Edge of the Die
MGTRXP3_104
MGTRXN3_104
MGTTXP3_104
MGTTXN3_104
MGTRXP2_104
MGTRXN2_104
MGTTXP2_104
MGTTXN2_104
MGTREFCLK1P_104
MGTREFCLK1N_104
MGTREFCLK0P_104
MGTREFCLK0N_104
K30
K29
E32
E31
L32
L31
F34
F33
L27
L28
N27
N28
HX250T:GTXE1_X0Y19
HX380T:GTXE1_X0Y19
HX250T:GTXE1_X0Y18
HX380T:GTXE1_X0Y18
QUAD_104
MGTRXP1_104
MGTRXN1_104
MGTTXP1_104
MGTTXN1_104
MGTRXP0_104
MGTRXN0_104
MGTTXP0_104
MGTTXN0_104
Figure 1-31: Placement Diagram for the FF1154 Package (8 of 12)
M30
M29
G32
G31
N32
N31
H34
H33
HX250T:GTXE1_X0Y17
HX380T:GTXE1_X0Y17
HX250T:GTXE1_X0Y16
HX380T:GTXE1_X0Y16
UG366_c1_31_111110
68 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-32
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_103
MGTRXN3_103
MGTTXP3_103
MGTTXN3_103
MGTRXP2_103
MGTRXN2_103
MGTTXP2_103
MGTTXN2_103
MGTREFCLK1P_103
MGTREFCLK1N_103
MGTREFCLK0P_103
MGTREFCLK0N_103
P30
P29
K34
K33
T30
T29
M34
M33
R27
R28
U27
U28
HX250T:GTXE1_X0Y15
HX380T:GTXE1_X0Y15
HX250T:GTXE1_X0Y14
HX380T:GTXE1_X0Y14
QUAD_103
MGTRXP1_103
MGTRXN1_103
MGTTXP1_103
MGTTXN1_103
MGTRXP0_103
MGTRXN0_103
MGTTXP0_103
MGTTXN0_103
Figure 1-32: Placement Diagram for the FF1154 Package (9 of 12)
R32
R31
P34
P33
U32
U31
T34
T33
HX250T:GTXE1_X0Y13
HX380T:GTXE1_X0Y13
HX250T:GTXE1_X0Y12
HX380T:GTXE1_X0Y12
UG366_c1_32_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 69
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-33
Left Edge of the Die
MGTRXP3_102
MGTRXN3_102
MGTTXP3_102
MGTTXN3_102
MGTRXP2_102
MGTRXN2_102
MGTTXP2_102
MGTTXN2_102
MGTREFCLK1P_102
MGTREFCLK1N_102
MGTREFCLK0P_102
MGTREFCLK0N_102
V30
V29
V34
V33
W32
W31
Y34
Y33
W27
W28
AA27
AA28
HX250T:GTXE1_X0Y11
HX380T:GTXE1_X0Y11
HX250T:GTXE1_X0Y10
HX380T:GTXE1_X0Y10
QUAD_102
MGTRXP1_102
MGTRXN1_102
MGTTXP1_102
MGTTXN1_102
MGTRXP0_102
MGTRXN0_102
MGTTXP0_102
MGTTXN0_102
Figure 1-33: Placement Diagram for the FF1154 Package (10 of 12)
Y30
Y29
AB34
AB33
AA32
AA31
AD34
AD33
HX250T:GTXE1_X0Y9
HX380T:GTXE1_X0Y9
HX250T:GTXE1_X0Y8
HX380T:GTXE1_X0Y8
UG366_c1_33_111110
70 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-34
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_101
MGTRXN3_101
MGTTXP3_101
MGTTXN3_101
MGTRXP2_101
MGTRXN2_101
MGTTXP2_101
MGTTXN2_101
MGTREFCLK1P_101
MGTREFCLK1N_101
MGTREFCLK0P_101
MGTREFCLK0N_101
AB30
AB29
AF34
AF33
AC32
AC31
AH34
AH33
AC27
AC28
AE27
AE28
HX250T:GTXE1_X0Y7
HX380T:GTXE1_X0Y7
HX250T:GTXE1_X0Y6
HX380T:GTXE1_X0Y6
QUAD_101
MGTRXP1_101
MGTRXN1_101
MGTTXP1_101
MGTTXN1_101
MGTRXP0_101
MGTRXN0_101
MGTTXP0_101
MGTTXN0_101
Figure 1-34: Placement Diagram for the FF1154 Package (11 of 12)
AD30
AD29
AJ32
AJ31
AE32
AE31
AK34
AK33
HX250T:GTXE1_X0Y5
HX380T:GTXE1_X0Y5
HX250T:GTXE1_X0Y4
HX380T:GTXE1_X0Y4
UG366_c1_34_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 71
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-35
Left Edge of the Die
MGTRXP3_100
MGTRXN3_100
MGTTXP3_100
MGTTXN3_100
MGTRXP2_100
MGTRXN2_100
MGTTXP2_100
MGTTXN2_100
MGTREFCLK1P_100
MGTREFCLK1N_100
MGTREFCLK0P_100
MGTREFCLK0N_100
AF30
AF29
AL32
AL31
AG32
AG31
AM34
AM33
AG27
AG28
AJ27
AJ28
HX250T:GTXE1_X0Y3
HX380T:GTXE1_X0Y3
HX250T:GTXE1_X0Y2
HX380T:GTXE1_X0Y2
QUAD_100
MGTRXP1_100
MGTRXN1_100
MGTTXP1_100
MGTTXN1_100
MGTRXP0_100
MGTRXN0_100
MGTTXP0_100
MGTTXN0_100
Figure 1-35: Placement Diagram for the FF1154 Package (12 of 12)
AH30
AH29
AN32
AN31
AK30
AK29
AP34
AP33
HX250T:GTXE1_X0Y1
HX380T:GTXE1_X0Y1
HX250T:GTXE1_X0Y0
HX380T:GTXE1_X0Y0
UG366_c1_35_111110
72 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
FF1155 Package Placement Diagrams
www.BDTIC.com/XILINX
Figure 1-36 through Figure 1-41 show the placement diagrams for the FF1155 package.
X-Ref Target - Figure 1-36
Right Edge of the Die
Implementation
HX255T:GTXE1_X1Y11
HX380T:GTXE1_X1Y11
HX255T:GTXE1_X1Y10
HX380T:GTXE1_X1Y10
QUAD_115
AA3
AA4
V1
V2
AB5
AB6
Y1
Y2
AA8
AA7
AC8
AC7
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
Y5
HX255T:GTXE1_X1Y9
HX380T:GTXE1_X1Y9
HX255T:GTXE1_X1Y8
HX380T:GTXE1_X1Y8
Figure 1-36: Placement Diagram for the FF1155 Package (1 of 6)
Y6
W3
W4
AC3
AC4
AB1
AB2
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_36_111110
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UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-37
Right Edge of the Die
HX255T:GTXE1_X1Y7
HX380T:GTXE1_X1Y7
HX255T:GTXE1_X1Y6
HX380T:GTXE1_X1Y6
QUAD_114
AD5
AD6
AD1
AD2
AE3
AE4
AF1
AF2
AE8
AE7
AG8
AG7
MGTRXP3_114
MGTRXN3_114
MGTTXP3_114
MGTTXN3_114
MGTRXP2_114
MGTRXN2_114
MGTTXP2_114
MGTTXN2_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTREFCLK0P_114
MGTREFCLK0N_114
AF5
HX2555T:GTXE1_X1Y5
HX380T:GTXE1_X1Y5
HX255T:GTXE1_X1Y4
HX380T:GTXE1_X1Y4
Figure 1-37: Placement Diagram for the FF1155 Package (2 of 6)
AF6
AH1
AH2
AG3
AG4
AK1
AK2
MGTRXP1_114
MGTRXN1_114
MGTTXP1_114
MGTTXN1_114
MGTRXP0_114
MGTRXN0_114
MGTTXP0_114
MGTTXN0_114
UG366_c1_37_111110
74 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-38
HX255T:GTXE1_X1Y3
HX380T:GTXE1_X1Y3
HX255T:GTXE1_X1Y2
HX380T:GTXE1_X1Y2
HX255T:GTXE1_X1Y1
HX380T:GTXE1_X1Y1
HX255T:GTXE1_X1Y0
HX380T:GTXE1_X1Y0
QUAD_113
AH5
AH6
AL3
AL4
AJ3
AJ4
AM1
AM2
AJ8
AJ7
AL8
AL7
AK5
AK6
AN3
AN4
AM5
AM6
AP1
AP2
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
UG366_c1_38_111110
Right Edge of the Die
www.BDTIC.com/XILINX
Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 75
UG366 (v2.5) January 17, 2011
Figure 1-38: Placement Diagram for the FF1155 Package (3 of 6)
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-39
Left Edge of the Die
MGTRXP3_105
MGTRXN3_105
MGTTXP3_105
MGTTXN3_105
MGTRXP2_105
MGTRXN2_105
MGTTXP2_105
MGTTXN2_105
MGTREFCLK1P_105
MGTREFCLK1N_105
MGTREFCLK0P_105
MGTREFCLK0N_105
AA32
AA31
V34
V33
AB30
AB29
Y34
Y33
AA27
AA28
AC27
AC28
HX255T:GTXE1_X0Y11
HX380T:GTXE1_X0Y11
HX255T:GTXE1_X0Y10
HX380T:GTXE1_X0Y10
QUAD_105
MGTRXP1_105
MGTRXN1_105
MGTTXP1_105
MGTTXN1_105
MGTRXP0_105
MGTRXN0_105
MGTTXP0_105
MGTTXN0_105
Figure 1-39: Placement Diagram for the FF1155 Package (4 of 6)
Y30
Y29
W32
W31
AC32
AC31
AB34
AB33
HX255T:GTXE1_X0Y9
HX380T:GTXE1_X0Y9
HX255T:GTXE1_X0Y8
HX380T:GTXE1_X0Y8
UG366_c1_39_111110
76 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-40
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_104
MGTRXN3_104
MGTTXP3_104
MGTTXN3_104
MGTRXP2_104
MGTRXN2_104
MGTTXP2_104
MGTTXN2_104
MGTREFCLK1P_104
MGTREFCLK1N_104
MGTREFCLK0P_104
MGTREFCLK0N_104
AD30
AD29
AD34
AD33
AE32
AE31
AF34
AF33
AE27
AE28
AG27
AG28
HX255T:GTXE1_X0Y7
HX380T:GTXE1_X0Y7
HX255T:GTXE1_X0Y6
HX380T:GTXE1_X0Y6
QUAD_104
MGTRXP1_104
MGTRXN1_104
MGTTXP1_104
MGTTXN1_104
MGTRXP0_104
MGTRXN0_104
MGTTXP0_104
MGTTXN0_104
Figure 1-40: Placement Diagram for the FF1155 Package (5 of 6)
AF30
AF29
AH34
AH33
AG32
AG31
AK34
AK33
HX255T:GTXE1_X0Y5
HX380T:GTXE1_X0Y5
HX255T:GTXE1_X0Y4
HX380T:GTXE1_X0Y4
UG366_c1_40_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 77
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-41
Left Edge of the Die
MGTRXP3_103
MGTRXN3_103
MGTTXP3_103
MGTTXN3_103
MGTRXP2_103
MGTRXN2_103
MGTTXP2_103
MGTTXN2_103
MGTREFCLK1P_103
MGTREFCLK1N_103
MGTREFCLK0P_103
MGTREFCLK0N_103
AH30
AH29
AL32
AL31
AJ32
AJ31
AM34
AM33
AJ27
AJ28
AL27
AL28
HX255T:GTXE1_X0Y3
HX380T:GTXE1_X0Y3
HX255T:GTXE1_X0Y2
HX380T:GTXE1_X0Y2
QUAD_103
MGTRXP1_103
MGTRXN1_103
MGTTXP1_103
MGTTXN1_103
MGTRXP0_103
MGTRXN0_103
MGTTXP0_103
MGTTXN0_103
Figure 1-41: Placement Diagram for the FF1155 Package (6 of 6)
AK30
AK29
AN32
AN31
AM30
AM29
AP34
AP33
HX255T:GTXE1_X0Y1
HX380T:GTXE1_X0Y1
HX255T:GTXE1_X0Y0
HX380T:GTXE1_X0Y0
UG366_c1_41_111110
78 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
FF1923 Package Placement Diagrams
www.BDTIC.com/XILINX
Figure 1-42 through Figure 1-51 show the placement diagrams for the FF1923 package.
X-Ref Target - Figure 1-42
Right Edge of the Die
Implementation
HX255T:GTXE1_X1Y11
HX380T:GTXE1_X1Y15
HX565T:GTXE1_X1Y15
HX255T:GTXE1_X1Y10
HX380T:GTXE1_X1Y14
HX565T:GTXE1_X1Y14
QUAD_115
U7
U8
V1
V2
V5
V6
W3
W4
T10
T9
V10
V9
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
W7
HX255T:GTXE1_X1Y9
HX380T:GTXE1_X1Y13
HX565T:GTXE1_X1Y13
HX255T:GTXE1_X1Y8
HX380T:GTXE1_X1Y12
HX565T:GTXE1_X1Y12
Figure 1-42: Placement Diagram for the FF1923 Package (1 of 10)
W8
Y1
Y2
Y5
Y6
AA3
AA4
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_42_111510
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 79
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
HX255T:GTXE1_X1Y7
HX380T:GTXE1_X1Y11
HX565T:GTXE1_X1Y11
HX255T:GTXE1_X1Y6
HX380T:GTXE1_X1Y10
HX565T:GTXE1_X1Y10
HX255T:GTXE1_X1Y5
HX380T:GTXE1_X1Y9
HX565T:GTXE1_X1Y9
HX255T:GTXE1_X1Y4
HX380T:GTXE1_X1Y8
HX565T:GTXE1_X1Y8
QUAD_114
AA7
AA8
AB1
AB2
AB5
AB6
AC3
AC4
Y10
Y9
AB10
AB9
AC7
AC8
AD1
AD2
AD5
AD6
AE3
AE4
UG366_c1_43_111110
MGTTXP0_114
MGTTXN0_114
MGTRXP0_114
MGTRXN0_114
MGTTXP1_114
MGTTXN1_114
MGTRXP1_114
MGTRXN1_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTTXP2_114
MGTTXN2_114
MGTRXP2_114
MGTRXN2_114
MGTTXP3_114
MGTTXN3_114
MGTRXP3_114
MGTRXN3_114
Right Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-43
80 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-43: Placement Diagram for the FF1923 Package (2 of 10)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-44
HX255T:GTXE1_X1Y3
HX380T:GTXE1_X1Y7
HX565T:GTXE1_X1Y7
HX255T:GTXE1_X1Y2
HX380T:GTXE1_X1Y6
HX565T:GTXE1_X1Y6
HX255T:GTXE1_X1Y1
HX380T:GTXE1_X1Y5
HX565T:GTXE1_X1Y5
HX255T:GTXE1_X1Y0
HX380T:GTXE1_X1Y4
HX565T:GTXE1_X1Y4
QUAD_113
AE7
AE8
AF1
AF2
AF5
AF6
AG3
AG4
AD10
AD9
AF10
AF9
AG7
AG8
AH1
AH2
AH5
AH6
AJ3
AJ4
UG366_c1_44_111110
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
Right Edge of the Die
www.BDTIC.com/XILINX
Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 81
UG366 (v2.5) January 17, 2011
Figure 1-44: Placement Diagram for the FF1923 Package (3 of 10)
Chapter 1: Transceiver and Tool Overview
HX255T:Not Available
HX380T:GTXE1_X1Y3
HX565T:GTXE1_X1Y3
HX255T:Not Available
HX380T:GTXE1_X1Y2
HX565T:GTXE1_X1Y2
HX255T:Not Available
HX380T:GTXE1_X1Y1
HX565T:GTXE1_X1Y1
HX255T:Not Available
HX380T:GTXE1_X1Y0
HX565T:GTXE1_X1Y0
QUAD_112
AK5
AK6
AK1
AK2
AJ7
AJ8
AL3
AL4
AH10
AH9
AN8
AN7
AM5
AM6
AM1
AM2
AL7
AL8
AN3
AN4
UG366_c1_45_111110
MGTTXP0_112
MGTTXN0_112
MGTRXP0_112
MGTRXN0_112
MGTTXP1_112
MGTTXN1_112
MGTRXP1_112
MGTRXN1_112
MGTREFCLK0P_112
MGTREFCLK0N_112
MGTREFCLK1P_112
MGTREFCLK1N_112
MGTTXP2_112
MGTTXN2_112
MGTRXP2_112
MGTRXN2_112
MGTTXP3_112
MGTTXN3_112
MGTRXP3_112
MGTRXN3_112
Right Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-45
82 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-45: Placement Diagram for the FF1923 Package (4 of 10)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-46
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_105
MGTRXN3_105
MGTTXP3_105
MGTTXN3_105
MGTRXP2_105
MGTRXN2_105
MGTTXP2_105
MGTTXN2_105
MGTREFCLK1P_105
MGTREFCLK1N_105
MGTREFCLK0P_105
MGTREFCLK0N_105
U38
U37
V44
V43
V40
V39
W42
W41
T35
T36
V35
V36
HX255T:GTXE1_X0Y11
HX380T:GTXE1_X0Y15
HX565T:GTXE1_X0Y15
HX255T:GTXE1_X0Y10
HX380T:GTXE1_X0Y14
HX565T:GTXE1_X0Y14
QUAD_105
MGTRXP1_105
MGTRXN1_105
MGTTXP1_105
MGTTXN1_105
MGTRXP0_105
MGTRXN0_105
MGTTXP0_105
MGTTXN0_105
Figure 1-46: Placement Diagram for the FF1923 Package (5 of 10)
W38
W37
Y44
Y43
Y40
Y39
AA42
AA41
HX255T:GTXE1_X0Y9
HX380T:GTXE1_X0Y13
HX565T:GTXE1_X0Y13
HX255T:GTXE1_X0Y8
HX380T:GTXE1_X0Y12
HX565T:GTXE1_X0Y12
UG366_c1_46_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 83
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
AA38
AA37
AB44
AB43
AB40
AB39
AC42
AC41
Y35
Y36
AB35
AB36
AC38
AC37
AD44
AD43
AD40
AD39
AE42
AE41
UG366_c1_47_111110
HX255T:GTXE1_X0Y7
HX380T:GTXE1_X0Y11
HX565T:GTXE1_X0Y11
HX255T:GTXE1_X0Y6
HX380T:GTXE1_X0Y10
HX565T:GTXE1_X0Y10
HX255T:GTXE1_X0Y5
HX380T:GTXE1_X0Y9
HX565T:GTXE1_X0Y9
HX255T:GTXE1_X0Y4
HX380T:GTXE1_X0Y8
HX565T:GTXE1_X0Y8
QUAD_104
MGTTXP0_104
MGTTXN0_104
MGTRXP0_104
MGTRXN0_104
MGTTXP1_104
MGTTXN1_104
MGTRXP1_104
MGTRXN1_104
MGTREFCLK0P_104
MGTREFCLK0N_104
MGTREFCLK1P_104
MGTREFCLK1N_104
MGTTXP2_104
MGTTXN2_104
MGTRXP2_104
MGTRXN2_104
MGTTXP3_104
MGTTXN3_104
MGTRXP3_104
MGTRXN3_104
Left Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-47
84 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-47: Placement Diagram for the FF1923 Package (6 of 10)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-48
www.BDTIC.com/XILINX
Implementation
Left Edge of the Die
MGTRXP3_103
MGTRXN3_103
MGTTXP3_103
MGTTXN3_103
MGTRXP2_103
MGTRXN2_103
MGTTXP2_103
MGTTXN2_103
MGTREFCLK1P_103
MGTREFCLK1N_103
MGTREFCLK0P_103
MGTREFCLK0N_103
AE38
AE37
AF44
AF43
AF40
AF39
AG42
AG41
AD35
AD36
AF35
AF36
HX255T:GTXE1_X0Y3
HX380T:GTXE1_X0Y7
HX565T:GTXE1_X0Y7
HX255T:GTXE1_X0Y2
HX380T:GTXE1_X0Y6
HX565T:GTXE1_X0Y6
QUAD_103
MGTRXP1_103
MGTRXN1_103
MGTTXP1_103
MGTTXN1_103
MGTRXP0_103
MGTRXN0_103
MGTTXP0_103
MGTTXN0_103
Figure 1-48: Placement Diagram for the FF1923 Package (7 of 10)
AG38
AG37
AH44
AH43
AH40
AH39
AJ42
AJ41
HX255T:GTXE1_X0Y1
HX380T:GTXE1_X0Y5
HX565T:GTXE1_X0Y5
HX255T:GTXE1_X0Y0
HX380T:GTXE1_X0Y4
HX565T:GTXE1_X0Y4
UG366_c1_48_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 85
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-49
Left Edge of the Die
MGTRXP3_102
MGTRXN3_102
MGTTXP3_102
MGTTXN3_102
MGTRXP2_102
MGTRXN2_102
MGTTXP2_102
MGTTXN2_102
MGTREFCLK1P_102
MGTREFCLK1N_102
MGTREFCLK0P_102
MGTREFCLK0N_102
AK40
AK39
AK44
AK43
AJ38
AJ37
AL42
AL41
AH35
AH36
AN37
AN38
HX255T:Not Available
HX380T:GTXE1_X0Y3
HX565T:GTXE1_X0Y3
HX255T:Not Available
HX380T:GTXE1_X0Y2
HX565T:GTXE1_X0Y2
QUAD_102
MGTRXP1_102
MGTRXN1_102
MGTTXP1_102
MGTTXN1_102
MGTRXP0_102
MGTRXN0_102
MGTTXP0_102
MGTTXN0_102
Figure 1-49: Placement Diagram for the FF1923 Package (8 of 10)
AM40
AM39
AM44
AM43
AL38
AL37
AN42
AN41
HX255T:Not Available
HX380T:GTXE1_X0Y1
HX565T:GTXE1_X0Y1
HX255T:Not Available
HX380T:GTXE1_X0Y0
HX565T:GTXE1_X0Y0
UG366_c1_49_111110
86 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-50
AP40
AP39
AP44
AP43
AT 40
AT 39
AR42
AR41
AR37
AR38
AU37
AU38
AV40
AV39
AT 44
AT 43
AY4 0
AY3 9
AU42
AU41
UG366_c1_50_111110
HX255T:Not Available
HX380T:GTXE1_X0Y-1
HX565T:GTXE1_X0Y-1
HX255T:Not Available
HX380T:GTXE1_X0Y-2
HX565T:GTXE1_X0Y-2
HX255T:Not Available
HX380T:GTXE1_X0Y-3
HX565T:GTXE1_X0Y-3
HX255T:Not Available
HX380T:GTXE1_X0Y-4
HX565T:GTXE1_X0Y-4
QUAD_101
MGTTXP0_101
MGTTXN0_101
MGTRXP0_101
MGTRXN0_101
MGTTXP1_101
MGTTXN1_101
MGTRXP1_101
MGTRXN1_101
MGTREFCLK0P_101
MGTREFCLK0N_101
MGTREFCLK1P_101
MGTREFCLK1N_101
MGTTXP2_101
MGTTXN2_101
MGTRXP2_101
MGTRXN2_101
MGTTXP3_101
MGTTXN3_101
MGTRXP3_101
MGTRXN3_101
Left Edge of the Die
www.BDTIC.com/XILINX
Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 87
UG366 (v2.5) January 17, 2011
Figure 1-50: Placement Diagram for the FF1923 Package (9 of 10)
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-51
Left Edge of the Die
MGTRXP3_100
MGTRXN3_100
MGTTXP3_100
MGTTXN3_100
MGTRXP2_100
MGTRXN2_100
MGTTXP2_100
MGTTXN2_100
MGTREFCLK1P_100
MGTREFCLK1N_100
MGTREFCLK0P_100
MGTREFCLK0N_100
BA42
BA41
AV44
AV43
BB40
BB39
AW42
AW41
AW37
AW38
BA37
BA38
HX255T:Not Available
HX380T:GTXE1_X0Y-5
HX565T:GTXE1_X0Y-5
HX255T:Not Available
HX380T:GTXE1_X0Y-6
HX565T:GTXE1_X0Y-6
QUAD_100
MGTRXP1_100
MGTRXN1_100
MGTTXP1_100
MGTTXN1_100
MGTRXP0_100
MGTRXN0_100
MGTTXP0_100
MGTTXN0_100
Figure 1-51: Placement Diagram for the FF1923 Package (10 of 10)
BC42
BC41
AY44
AY43
BD40
BD39
BB44
BB43
HX255T:Not Available
HX380T:GTXE1_X0Y-7
HX565T:GTXE1_X0Y-7
HX255T:Not Available
HX380T:GTXE1_X0Y-8
HX565T:GTXE1_X0Y-8
UG366_c1_51_111110
88 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
FF1924 Package Placement Diagrams
www.BDTIC.com/XILINX
Figure 1-42 through Figure 1-51 show the placement diagrams for the FF1924 package.
X-Ref Target - Figure 1-52
Right Edge of the Die
Implementation
HX380T:GTXE1_X1Y23
HX565T:GTXE1_X1Y23
HX380T:GTXE1_X1Y22
HX565T:GTXE1_X1Y22
QUAD_115
U7
U8
V1
V2
V5
V6
W3
W4
T10
T9
V10
V9
MGTRXP3_115
MGTRXN3_115
MGTTXP3_115
MGTTXN3_115
MGTRXP2_115
MGTRXN2_115
MGTTXP2_115
MGTTXN2_115
MGTREFCLK1P_115
MGTREFCLK1N_115
MGTREFCLK0P_115
MGTREFCLK0N_115
W7
HX380T:GTXE1_X1Y21
HX565T:GTXE1_X1Y21
HX380T:GTXE1_X1Y20
HX565T:GTXE1_X1Y20
Figure 1-52: Placement Diagram for the FF1924 Package (1 of 12)
W8
Y1
Y2
Y5
Y6
AA3
AA4
MGTRXP1_115
MGTRXN1_115
MGTTXP1_115
MGTTXN1_115
MGTRXP0_115
MGTRXN0_115
MGTTXP0_115
MGTTXN0_115
UG366_c1_52_111110
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 89
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
HX380T:GTXE1_X1Y19
HX565T:GTXE1_X1Y19
HX380T:GTXE1_X1Y18
HX565T:GTXE1_X1Y18
HX380T:GTXE1_X1Y17
HX565T:GTXE1_X1Y17
HX380T:GTXE1_X1Y16
HX565T:GTXE1_X1Y16
QUAD_114
AA7
AA8
AB1
AB2
AB5
AB6
AC3
AC4
Y10
Y9
AB10
AB9
AC7
AC8
AD1
AD2
AD5
AD6
AE3
AE4
UG366_c1_53_111110
MGTTXP0_114
MGTTXN0_114
MGTRXP0_114
MGTRXN0_114
MGTTXP1_114
MGTTXN1_114
MGTRXP1_114
MGTRXN1_114
MGTREFCLK0P_114
MGTREFCLK0N_114
MGTREFCLK1P_114
MGTREFCLK1N_114
MGTTXP2_114
MGTTXN2_114
MGTRXP2_114
MGTRXN2_114
MGTTXP3_114
MGTTXN3_114
MGTRXP3_114
MGTRXN3_114
Right Edge of the Die
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-53
90 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-53: Placement Diagram for the FF1924 Package (2 of 12)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-54
HX380T:GTXE1_X1Y15
HX565T:GTXE1_X1Y15
HX380T:GTXE1_X1Y14
HX565T:GTXE1_X1Y14
HX380T:GTXE1_X1Y13
HX565T:GTXE1_X1Y13
HX380T:GTXE1_X1Y12
HX565T:GTXE1_X1Y12
QUAD_113
AE7
AE8
AF1
AF2
AF5
AF6
AG3
AG4
AD10
AD9
AF10
AF9
AG7
AG8
AH1
AH2
AH5
AH6
AJ3
AJ4
UG366_c1_54_111110
Right Edge of the Die
MGTTXP0_113
MGTTXN0_113
MGTRXP0_113
MGTRXN0_113
MGTTXP1_113
MGTTXN1_113
MGTRXP1_113
MGTRXN1_113
MGTREFCLK0P_113
MGTREFCLK0N_113
MGTREFCLK1P_113
MGTREFCLK1N_113
MGTTXP2_113
MGTTXN2_113
MGTRXP2_113
MGTRXN2_113
MGTTXP3_113
MGTTXN3_113
MGTRXP3_113
MGTRXN3_113
Right Edge of the Die
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 91
UG366 (v2.5) January 17, 2011
Figure 1-54: Placement Diagram for the FF1924 Package (3 of 12)
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-55
Right Edge of the Die
HX380T:GTXE1_X1Y11
HX565T:GTXE1_X1Y11
HX380T:GTXE1_X1Y10
HX565T:GTXE1_X1Y10
QUAD_112
AK5
AK6
AK1
AK2
AJ7
AJ8
AL3
AL4
AH10
AH9
AN8
AN7
MGTRXP3_112
MGTRXN3_112
MGTTXP3_112
MGTTXN3_112
MGTRXP2_112
MGTRXN2_112
MGTTXP2_112
MGTTXN2_112
MGTREFCLK1P_112
MGTREFCLK1N_112
MGTREFCLK0P_112
MGTREFCLK0N_112
AM5
HX380T:GTXE1_X1Y9
HX565T:GTXE1_X1Y9
HX380T:GTXE1_X1Y8
HX565T:GTXE1_X1Y8
Figure 1-55: Placement Diagram for the FF1924 Package (4 of 12)
AM6
AM1
AM2
AL7
AL8
AN3
AN4
MGTRXP1_112
MGTRXN1_112
MGTTXP1_112
MGTTXN1_112
MGTRXP0_112
MGTRXN0_112
MGTTXP0_112
MGTTXN0_112
UG366_c1_55_111110
92 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-56
HX380T:GTXE1_X1Y7
HX565T:GTXE1_X1Y7
HX380T:GTXE1_X1Y6
HX565T:GTXE1_X1Y6
HX380T:GTXE1_X1Y5
HX565T:GTXE1_X1Y5
HX380T:GTXE1_X1Y4
HX565T:GTXE1_X1Y4
QUAD_111
AP5
AP6
AP1
AP2
AT 5
AT 6
AR3
AR4
AR8
AR7
AU8
AU7
AV5
AV6
AT 1
AT 2
AY5
AY6
AU3
AU4
UG366_c1_56_111110
MGTTXP0_111
MGTTXN0_111
MGTRXP0_111
MGTRXN0_111
MGTTXP1_111
MGTTXN1_111
MGTRXP1_111
MGTRXN1_111
MGTREFCLK0P_111
MGTREFCLK0N_111
MGTREFCLK1P_111
MGTREFCLK1N_111
MGTTXP2_111
MGTTXN2_111
MGTRXP2_111
MGTRXN2_111
MGTTXP3_111
MGTTXN3_111
MGTRXP3_111
MGTRXN3_111
Right Edge of the Die
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 93
UG366 (v2.5) January 17, 2011
Figure 1-56: Placement Diagram for the FF1924 Package (5 of 12)
Chapter 1: Transceiver and Tool Overview
www.BDTIC.com/XILINX
X-Ref Target - Figure 1-57
Right Edge of the Die
HX380T:GTXE1_X1Y3
HX565T:GTXE1_X1Y3
HX380T:GTXE1_X1Y2
HX565T:GTXE1_X1Y2
QUAD_110
BA3
BA4
AV1
AV2
BB5
BB6
AW3
AW4
AW8
AW7
BA8
BA7
MGTRXP3_110
MGTRXN3_110
MGTTXP3_110
MGTTXN3_110
MGTRXP2_110
MGTRXN2_110
MGTTXP2_110
MGTTXN2_110
MGTREFCLK1P_110
MGTREFCLK1N_110
MGTREFCLK0P_110
MGTREFCLK0N_110
BC3
HX380T:GTXE1_X1Y1
HX565T:GTXE1_X1Y1
HX380T:GTXE1_X1Y0
HX565T:GTXE1_X1Y0
Figure 1-57: Placement Diagram for the FF1924 Package (6 of 12)
BC4
AY1
AY2
BD5
BD6
BB1
BB2
MGTRXP1_110
MGTRXN1_110
MGTTXP1_110
MGTTXN1_110
MGTRXP0_110
MGTRXN0_110
MGTTXP0_110
MGTTXN0_110
UG366_c1_57_111110
94 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-58
QUAD_105
U38
U37
V44
V43
V40
V39
W42
W41
T35
T36
V35
V36
W38
W37
Y44
Y43
Y40
Y39
AA42
AA42
MGTTXP0_105
MGTTXN0_105
MGTRXP0_105
MGTRXN0_105
MGTTXP1_105
MGTTXN1_105
MGTRXP1_105
MGTRXN1_105
MGTREFCLK0P_105
MGTREFCLK0N_105
MGTREFCLK1P_105
MGTREFCLK1N_105
MGTTXP2_105
MGTTXN2_105
MGTRXP2_105
MGTRXN2_105
MGTTXP3_105
MGTTXN3_105
MGTRXP3_105
MGTRXN3_105
UG366_c1_58_111110
HX380T:GTXE1_X0Y23
HX565T:GTXE1_X0Y23
HX380T:GTXE1_X0Y22
HX565T:GTXE1_X0Y22
HX380T:GTXE1_X0Y21
HX565T:GTXE1_X0Y21
HX380T:GTXE1_X0Y20
HX565T:GTXE1_X0Y20
Left Edge of the Die
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 95
UG366 (v2.5) January 17, 2011
Figure 1-58: Placement Diagram for the FF1924 Package (7 of 12)
Chapter 1: Transceiver and Tool Overview
QUAD_104
AA38
AA37
AB44
AB43
AB40
AB39
AC42
AC41
Y35
Y36
AB35
AB36
AC38
AC37
AD44
AD43
AD40
AD39
AE42
AE42
UG366_c1_59_111110
HX380T:GTXE1_X0Y19
HX565T:GTXE1_X0Y19
HX380T:GTXE1_X0Y18
HX565T:GTXE1_X0Y18
HX380T:GTXE1_X0Y17
HX565T:GTXE1_X0Y17
HX380T:GTXE1_X0Y16
HX565T:GTXE1_X0Y16
MGTTXP0_104
MGTTXN0_104
MGTRXP0_104
MGTRXN0_104
MGTTXP1_104
MGTTXN1_104
MGTRXP1_104
MGTRXN1_104
MGTREFCLK0P_104
MGTREFCLK0N_104
MGTREFCLK1P_104
MGTREFCLK1N_104
MGTTXP2_104
MGTTXN2_104
MGTRXP2_104
MGTRXN2_104
MGTTXP3_104
MGTTXN3_104
MGTRXP3_104
MGTRXN3_104
Left Edge of the Die
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X-Ref Target - Figure 1-59
96 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-59: Placement Diagram for the FF1924 Package (8 of 12)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-60
QUAD_103
AE38
AE37
AF44
AF43
AF40
AF39
AG42
AG41
AD35
AD36
AF35
AF36
AG38
AG37
AH44
AH43
AH40
AH39
AJ42
AJ42
UG366_c1_60_111110
HX380T:GTXE1_X0Y15
HX565T:GTXE1_X0Y15
HX380T:GTXE1_X0Y14
HX565T:GTXE1_X0Y14
HX380T:GTXE1_X0Y13
HX565T:GTXE1_X0Y13
HX380T:GTXE1_X0Y12
HX565T:GTXE1_X0Y12
MGTTXP0_103
MGTTXN0_103
MGTRXP0_103
MGTRXN0_103
MGTTXP1_103
MGTTXN1_103
MGTRXP1_103
MGTRXN1_103
MGTREFCLK0P_103
MGTREFCLK0N_103
MGTREFCLK1P_103
MGTREFCLK1N_103
MGTTXP2_103
MGTTXN2_103
MGTRXP2_103
MGTRXN2_103
MGTTXP3_103
MGTTXN3_103
MGTRXP3_103
MGTRXN3_103
Left Edge of the Die
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 97
UG366 (v2.5) January 17, 2011
Figure 1-60: Placement Diagram for the FF1924 Package (9 of 12)
Chapter 1: Transceiver and Tool Overview
QUAD_102
AK40
AK39
AK44
AK43
AJ38
AJ37
AL42
AL41
AH35
AH36
AN37
AN38
AM40
AM39
AM44
AM43
AL38
AL37
AN42
AN42
UG366_c1_61_111110
HX380T:GTXE1_X0Y11
HX565T:GTXE1_X0Y11
HX380T:GTXE1_X0Y10
HX565T:GTXE1_X0Y10
HX380T:GTXE1_X0Y9
HX565T:GTXE1_X0Y9
HX380T:GTXE1_X0Y8
HX565T:GTXE1_X0Y8
MGTTXP0_102
MGTTXN0_102
MGTRXP0_102
MGTRXN0_102
MGTTXP1_102
MGTTXN1_102
MGTRXP1_102
MGTRXN1_102
MGTREFCLK0P_102
MGTREFCLK0N_102
MGTREFCLK1P_102
MGTREFCLK1N_102
MGTTXP2_102
MGTTXN2_102
MGTRXP2_102
MGTRXN2_102
MGTTXP3_102
MGTTXN3_102
MGTRXP3_102
MGTRXN3_102
Left Edge of the Die
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X-Ref Target - Figure 1-61
98 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-61: Placement Diagram for the FF1924 Package (10 of 12)
UG366 (v2.5) January 17, 2011
X-Ref Target - Figure 1-62
QUAD_101
AP40
AP39
AP44
AP43
AT 40
AT 39
AR42
AR41
AR37
AR38
AU37
AU38
AV40
AV39
AT 44
AT 43
AY40
AY39
AU42
AU41
UG366_c1_62_111110
HX380T:GTXE1_X0Y7
HX565T:GTXE1_X0Y7
HX380T:GTXE1_X0Y6
HX565T:GTXE1_X0Y6
HX380T:GTXE1_X0Y5
HX565T:GTXE1_X0Y5
HX380T:GTXE1_X0Y4
HX565T:GTXE1_X0Y4
MGTTXP0_101
MGTTXN0_101
MGTRXP0_101
MGTRXN0_101
MGTTXP1_101
MGTTXN1_101
MGTRXP1_101
MGTRXN1_101
MGTREFCLK0P_101
MGTREFCLK0N_101
MGTREFCLK1P_101
MGTREFCLK1N_101
MGTTXP2_101
MGTTXN2_101
MGTRXP2_101
MGTRXN2_101
MGTTXP3_101
MGTTXN3_101
MGTRXP3_101
MGTRXN3_101
Left Edge of the Die
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Implementation
Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 99
UG366 (v2.5) January 17, 2011
Figure 1-62: Placement Diagram for the FF1924 Package (11 of 12)
Chapter 1: Transceiver and Tool Overview
QUAD_100
BA42
BA41
AV44
AV43
BB40
BB39
AW42
AW41
AW37
AW36
BA37
BA38
BC42
BC41
AY44
AY43
BD40
BD39
BB44
BB43
UG366_c1_63_111110
HX380T:GTXE1_X0Y3
HX565T:GTXE1_X0Y3
HX380T:GTXE1_X0Y2
HX565T:GTXE1_X0Y2
HX380T:GTXE1_X0Y1
HX565T:GTXE1_X0Y1
HX380T:GTXE1_X0Y0
HX565T:GTXE1_X0Y0
MGTTXP0_100
MGTTXN0_100
MGTRXP0_100
MGTRXN0_100
MGTTXP1_100
MGTTXN1_100
MGTRXP1_100
MGTRXN1_100
MGTREFCLK0P_100
MGTREFCLK0N_100
MGTREFCLK1P_100
MGTREFCLK1N_100
MGTTXP2_100
MGTTXN2_100
MGTRXP2_100
MGTRXN2_100
MGTTXP3_100
MGTTXN3_100
MGTRXP3_100
MGTRXN3_100
Left Edge of the Die
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X-Ref Target - Figure 1-63
100 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-63: Placement Diagram for the FF1924 Package (12 of 12)
UG366 (v2.5) January 17, 2011
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