Xilinx ML361 User Manual

ML361 Virtex-II Pro DDR400/PC3200 Memory Board User Guide

UG060 (v1.2) November 8, 2007

Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

ML361 Virtex-II Pro DDR400/PC3200 Memory Board User Guide UG060 (v1.2) November 8, 2007

The following table shows the revision history for this document.

Version Revision

01/23/04 1.0 Initial Xilinx release.

03/26/04 1.1 Revised Figure 4-6, Figure 4-7, Figure 4-8, Figure 4-9, Figure 4-26, and Figure 4-27.

11/08/07 1.2

• Ta bl e 5 -1 : Typographical corrections.

• Ta bl e B -1 : Deleted Slice Coordinates column from table.

• Updated copyright notice and legal disclaimer.

ML361 Virtex-II Pro Memory Board www.xilinx.com UG060 (v1.2) November 8, 2007

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 1: Introduction

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Chapter 2: Architecture

ML361 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDR SDRAM DIMM (Banks 6 and 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDR SDRAM Components (Banks 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDR SDRAM Component (Bank 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

200 MHz LVDS Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

166 MHz LVDS Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mictor Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Seven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Push Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Grounded I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Linear Regulators for the MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 3: Electrical Requirements

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4: Signal Integrity Recommendations and Simulations

Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Terminations and Transmission Lines for DDR Components . . . . . . . . . . . . . . . . . . . 26

Data and Clock Signals (DQ, DQS, DM, CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE) . . . . . . . . . . . . . . 26

Terminations and Transmission Lines for the DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Data and Clock Signals (DQ, DQS, DM, CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE) . . . . . . . . . . . . . . 27

Duty Cycle Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

IBIS Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Notes on the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Data Signals from the FPGA to Memory (SSTL2_C2 at FPGA). . . . . . . . . . . . . . . . . . . . 32

Data Signals from the Last Memory to the FPGA: Measured at FPGA. . . . . . . . . . . . . . 36

Clock Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Address and Control Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Simulations with 10% Tolerance on the Transmission Line Impedance . . . . . . . . . . . 56

Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Address/Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Chapter 5: Board Layout Guidelines

Decoupling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Providing Additional Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Board Stackup Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Appendix A: Related Documentation

Appendix B: FPGA Pinout

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Schedule of Figures

Chapter 1: Introduction

Figure 1-1: Simplified Block Diagram of Memory Board Interfaces . . . . . . . . . . . . . . . . . 11

Chapter 2: Architecture

Figure 2-1: ML361 Board Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 3: Electrical Requirements

Chapter 4: Signal Integrity Recommendations and Simulations

Figure 4-1: Data Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 4-2: Data Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . . . 32

Figure 4-3: Data Signal from FPGA to Memory (Slow Weak Case). . . . . . . . . . . . . . . . . . 33

Figure 4-4: Data Signal from FPGA to Memory (Fast Strong Case) . . . . . . . . . . . . . . . . . . 34

Figure 4-5: Eye Diagram for Data from the FPGA to Last Memory Component. . . . . . . 35

Figure 4-6: Data Signal from Last Memory at FPGA (Typical Case) . . . . . . . . . . . . . . . . . 36

Figure 4-7: Data Signal from Last Memory at FPGA (Slow Weak Corner Case). . . . . . . 37

Figure 4-8: Data Signal from Memory at FPGA (Fast Strong Corner Case) . . . . . . . . . . . 38

Figure 4-9: Eye Diagram for Data at the FPGA to the Last Memory Component . . . . . . 39

Figure 4-10: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 4-11: Clock Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . 41

Figure 4-12: Clock Signal from FPGA to Memory (Slow Weak Case). . . . . . . . . . . . . . . . 42

Figure 4-13: Clock Signal from FPGA to Memory (Fast Strong Case) . . . . . . . . . . . . . . . . 43

Figure 4-14: Eye Diagram for Clock at Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 4-15: Address and Control Signal Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 4-16: Address/Control Signals for All Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 4-17: Address/Control Signals at First DDR Memory (Typical Case). . . . . . . . . . 47

Figure 4-18: Address/Control Signals at First DDR Memory (Slow Weak Case) . . . . . . 48

Figure 4-19: Address/Control Signals at First DDR Memory (Fast Strong Case) . . . . . . 49

Figure 4-20: Address/Control Signals at Last DDR Memory (Typical Case) . . . . . . . . . . 50

Figure 4-21: Address/Control Signals at Last DDR Memory (Slow Weak Case). . . . . . . 51

Figure 4-22: Address/Control Signals at Last DDR Memory (Fast Strong Corner Case) 52

Figure 4-23: Address/Control Signals at Middle DDR Memory (Typical Case) . . . . . . . 53

Figure 4-24: Address/Control Signals at Middle DDR Memory (Slow Weak Corner

Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 4-25: Address/Control Signals at Middle DDR Memory (Fast Strong Corner

Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 4-26: Data Signals from Last DDR Memory to FPGA (45Ω Impedance) . . . . . . . 56

Figure 4-27: Data Signals from Last DDR Memory to FPGA (55Ω Impedance) . . . . . . . 57

Figure 4-28: Data Signals from FPGA to Last DDR Memory (45Ω Impedance) . . . . . . . 58

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Figure 4-29: Data Signals from Memory to FPGA (55Ω Impedance) . . . . . . . . . . . . . . . . . 59

Figure 4-30: Clock Signals with 45Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 4-31: Clock Signals with 55Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 4-32: Address/Control Signals with 45Ω Impedance Measured at First DDR

Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 4-33: Address/Control Signals with 55Ω Impedance Measured at First DDR

Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Chapter 5: Board Layout Guidelines

Appendix A: Related Documentation

Appendix B: FPGA Pinout

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Schedule of Tables

Chapter 1: Introduction

Chapter 2: Architecture

Table 2-1: GPIO Header 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2-2: GPIO Header 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-3: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-4: Display 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 2-5: Display 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 2-6: LED Connections to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Chapter 3: Electrical Requirements

Table 3-1: ML361 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 3-2: XC2VP20FF1152 Estimated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3-3: XC2VP20FF1152 Temperature Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3-4: Device Quiescent Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3-5: CLB Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 3-6: Digital Clock Manager Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 3-7: Input/Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 4: Signal Integrity Recommendations and Simulations

Table 4-1: DDR SDRAM Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4-2: DIMM Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4-3: Duty Cycle Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 5: Board Layout Guidelines

Table 5-1: FPGA Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 5-2: DDR SDRAM Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 5-3: DIMM Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 5-4: 16-Layer Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Appendix A: Related Documentation

Appendix B: FPGA Pinout

Table B-1: FPGA Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

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About This Guide

This document describes the design of the ML361 Virtex-II Pro™ DDR400/PC3200 Memory Board, which connects a Virtex-II Pro FPGA to DDR memories.

Guide Contents

This manual contains the following chapters:

• Chapter 1, “Introduction,” describes the purpose of the ML361 board and provides its

key features.

• Chapter 2, “Architecture,” provides a block diagram of the memory board and

describes the key components.

• Chapter 3, “Electrical Requirements,” lists the electrical specifications for the memory

board.

• Chapter 4, “Signal Integrity Recommendations and Simulations,” provides

information on termination, transmission lines, and duty cycles. It also gives the results of several IBIS simulations.

• Chapter 5, “Board Layout Guidelines,” provides information on decoupling

capacitors, ground signals, and PCB layout.

• Appendix A, “Related Documentation,” lists data sheet and external website

references specific to the ML361 components.

• Appendix B, “FPGA Pinout,” provides the pinout of the Virtex-II Pro FPGA.

Preface

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design flows, from design entry to verification

and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser Database of Xilinx solution records

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes Descriptions of device-specific design techniques and approaches

http://support.xilinx.com/apps/appsweb.htm

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Preface: About This Guide

Data Sheets Device-specific information on Xilinx device characteristics, including

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

Tech Tips Latest news, design tips, and patch information for the Xilinx design

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Resource Description/URL

readback, boundary scan, configuration, length count, and debugging

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

http://support.xilinx.com/support/troubleshoot/psolvers.htm

environment

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

Convention Meaning or Use Example

Italic font

Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Blue text

Blue, underlined text

References to other manuals

Emphasis in text

Cross-reference link to a location in the current document

Hyperlink to a website (URL)

See the Development System Reference Guide for more information.

If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

See the section “Additional

Resources” for details.

Refer to “Title Formats” in

Chapter 1 for details.

Go to http://www.xilinx.com for the latest speed files.

10 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Introduction

Overview

The ML361 Virtex-II Pro DDR400/PC3200 Memory Board provides a communications platform between a Virtex-II Pro FPGA and high-speed double-data-rate (DDR) memories with operating speeds up to 200 MHz. The ML361 has three major functions:

• Tests and verifies the interoperability of Virtex-II Pro devices with high-speed DDR memories

• Serves as a development platform for Xilinx and its customers to use for building memory controllers

• Provides a means by which Xilinx can demonstrate high-speed DDR memory interoperability

Chapter 1

X-Ref Target - Figure 1-1

DDR

SDRAM DIMM

128MB

(MT4VDDT1664-AG-40BC3)

This document describes the functional blocks within the ML361. It also provides various recommendations and requirements for usage of the board, including electrical requirements, logic analyzer requirements, and signal integrity issues. Simulation results using IBIS also are included.

Figure 1-1 shows a simplified block diagram of the ML361 memory interfaces.

DDR SDRAM

(MT46V32M8TG-5B)

Data (8 bits)

Data (72 bits)

Address/Control

Virtex-II Pro FPGA

XC2VP20FF1152-6

Address/Control

Data (72 bits)

Address/Control

DDR

SDRAMs

256Mb

(4 MT46V16M16TG-5B

and

1 MT46V32M8TG-5B)

ug060_c1_01_012104

Figure 1-1: Simplified Block Diagram of Memory Board Interfaces

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UG060 (v1.2) November 8, 2007

Chapter 1: Introduction

Features

The ML361 demonstrates a 64-/72-bit interface to a 128 MByte, 200 MHz DDR SDRAM DIMM, a 72-bit interface to five 256 Mbit, 200 MHz DDR SDRAM components, and an additional 8-bit interface to a 256 Mbit, 200 MHz DDR SDRAM component on one of the top banks.

The key features of the ML361 are summarized below:

• One Virtex-II Pro FPGA (XC2VP20FF1152-6)

• One DDR SDRAM DIMM (MT4VDDT1664-AG-40BC3)

♦ 128 MBytes

♦ 64-/72-bit data interface

• Five DDR SDRAMs (four MT46V16M16TG-5B devices and one MT46V32M8TG-5B

device)

♦ 1.28 Gbits

♦ 72-bit data interface

• One DDR SDRAM (MT46V32M8TG-5B)

♦ 256 Mbits

♦ 8-bit data interface

• Two separate controllers for each 72-bit memory interface

• 200 MHz interface

• The memory interfaces are located on the FPGA left/right interface and top I/O

banks (banks 1, 2, 3, 6, and 7)

12 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Architecture

This chapter provides functional descriptions of the major blocks within the ML361 board design. For more detailed information on the design, refer to the schematics, which are located at http://www.xilinx.com/bvdocs/userguides/ug060.zip

ML361 Board Block Diagram

Figure 2-1 shows a block diagram of the ML361 board. Refer to the following section for

additional information on the major blocks.

X-Ref Target - Figure 2-1

5V Input Jack

JTAG Port

PROM

7-Segment Displays

DIP Switch

Chapter 2

Serial Port

3.3V Regulator

Switch

1.3V Regulator

2.6V Regulator

(5.5A)

2.6V Regulator (10A)

(5.5A)

(10A)

GPIO Header GPIO Header

CLOCK

(200 MHz)

DDR SDRAM

(x16)

DDR SDRAM

(x16)

DDR SDRAM

(x16)

DDR SDRAM

(x16)

DDR SDRAM

(x8)

MICTOR (38-pin) MICTOR (38-pin)

XC2VP20FF1152C-6

DDR SDRAM

CLOCK

(166 MHz)

(x8)

Push1 Push2 Prgm Reset

Figure 2-1: ML361 Board Block Diagram

DDR

SDRAM

DIMM

(x64)

ug060_c2_01_121703

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UG060 (v1.2) November 8, 2007

Chapter 2: Architecture

Block Descriptions

This section describes the major blocks of the ML361 board.

FPGA

The ML361 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged in a 1152-pin BGA package with a -6 speed grade. Refer to Appendix B, “FPGA Pinout,”for a complete pinout of the Virtex-II Pro device.

Memories

The ML361 board supports two types of memories: DDR SDRAM DIMM and DDR SDRAM.

DDR SDRAM DIMM (Banks 6 and 7)

The DDR SDRAM DIMM used on the ML361 board is a 184-pin, 200 MHz, unbuffered, non-ECC Micron MT4VDDT1664-AG-40BC3 device. This DIMM module has a 64-bit wide data interface. The board also has provisions to interface to a 72-bit wide DIMM.

DDR SDRAM Components (Banks 2 and 3)

DDR SDRAM Component (Bank 1)

RS232

Clocks

200 MHz LVDS Clock

The ML361 board contains five 200 MHz DDR SDRAM components that provide a 72-bit interface. These devices include four 16-bit Micron MT46V16M16TG-5B devices and one MT46V32M8TG-5B DDR SDRAM devices. They are packaged in 66-pin TSOP packages. They share a common address and control bus and have separate clocks and DQS/DQ signals.

The ML361 board contains one 8-bit Micron MT46V32M8TG-5B device on the top bank of the FPGA.

The ML361 board provides an RS232 serial interface using a Texas Instruments MAX3221CDBR device. The maximum speed of this device is 250 Kb/s. The RS232 interface is accessible through a female DB9 RA connector.

The ML361 board contains 166 MHz and 200 MHz LVDS clock oscillators and connectors for external LVDS clock inputs.

The LVDS clock is a Pletronics LV1145BW-200.0M oscillator with a differential output. The oscillator runs at 200 MHz ± 50 PPM with an operating voltage of 2.5 V ± 5%. It is terminated at the FPGA with a 100 CLK_200_LVDSP and CLK_200_LVDSN inputs, respectively.

14 www.xilinx.com ML361 Virtex-II Pro Memory Board

Ω resistor. FPGA pins J17 and H17 in Bank 1 serve as the

UG060 (v1.2) November 8, 2007

166 MHz LVDS Test Clock

SMA Clock

User I/Os

Mictor Connectors

Block Descriptions

The LVDS test clock is a Pletronics SM7745DW-100.0M clock oscillator with a single-ended output. This oscillator runs at 166 MHz ± 50 PPM with an operating voltage of 2.5 V ± 5%. FPGA pins E17 and D17 in Bank 1 serve as the CLK_166_LVDSP and CLK_166_LVDSN inputs, respectively.

Two SMA connectors are provided for the input of an off-board differential clock. The traces from the SMAs are run as a pair to the FPGA where they are terminated with a 100 ohm resistor. AK18 serves as the CLK_SMAP input, and AL18 serves as the CLK_SMAN input for the SMA connector pair.

This subsection describes the devices that connect to the User I/Os of the ML361 board.

The FPGA interfaces to two 38-pin Mictor connectors. They can be used to hook up to a logic analyzer. All signals from the FPGA to the connectors are matched closely. Refer to the Xilinx data sheets in Appendix A, “Related Documentation,” for more information.

GPIO

The ML361 board contains 16 general-purpose I/Os (GPIOs), which are accessible through two 2 x 8 0.100" pin headers (see Ta bl e 2 -1 and Tab le 2 - 2). The even-numbered pins on each header are connected to ground. The GPIO header pins can be accessed through I/Os in Bank 0.

Table 2-1: GPIO Header 1

GPIO Pin # FPGA I/O Pin

G00 F22

G01 E22

G02 E25

G03 D25

G04 H21

G05 D22

G06 D23

G07 D24

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UG060 (v1.2) November 8, 2007

Chapter 2: Architecture

DIP Switch

Table 2-2: GPIO Header 2

GPIO Pin # FPGA I/O Pin

G08 D30

G09 D29

G10 K23

G11 J23

G12 H22

G13 G22

G14 D26

G15 C26

One eight-position DIP switch is connected to the FPGA I/Os as shown in Ta bl e 2 -3 . These switches can be used to externally pull up or pull down any signal on the FPGA.

Table 2-3: DIP Switch Connections

DIP Switch Input FPGA I/O Pin #

DIP1 G26

DIP2 H25

DIP3 G25

DIP4 J25

DIP5 K24

DIP6 J24

DIP7 F26

DIP8 E26

Seven-Segment Displays

Two seven-segment displays connect to the FPGA I/Os (see Tab le 2- 4 and Ta bl e 2 - 5). The red displays are active Low. The decimal points are not connected.

Table 2-4: Display 1

DIsplay Input FPGA I/O Pin #

Display1A C21

Display1B E21

Display1C F21

Display1D J20

Display1E K20

16 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Block Descriptions

Table 2-4: Display 1

DIsplay Input FPGA I/O Pin #

Display1F C24

Display1G D24

Table 2-5: Display 2

DIsplay Input FPGA I/O Pin #

Display2A D20

Display2B D21

Display2C F20

Display2D G20

Display2E K19

Display2F L19

Display2G C22

LEDs

Four green LEDs connect to the FPGA I/Os as indicated in Ta bl e 2 -6 . The LEDs are active Low.

Table 2-6: LED Connections to FPGA

LED # FPGA I/O Pin #

LED1 L18

LED2 K18

LED3 G18

LED4 F18

Push Buttons

The ML361 board contains four momentary push buttons. Their functions are as follows:

• Program the FPGA

• Reset the board

• User function 1

• User function 2

Grounded I/Os

Unused I/Os are connected to GND in all FPGA banks. However, all memory banks have eight unused I/Os connected to GND through 0

Ω resistors. These can be depopulated

when needed for test purposes. Care must be taken to not drive any unused I/Os connected to GND.

ML361 Virtex-II Pro Memory Board www.xilinx.com 17

UG060 (v1.2) November 8, 2007

Chapter 2: Architecture

Power

Power Distribution

Input Voltage

3.3 V Generation

2.6 V Generation

The ML361 board uses a 5V input voltage source to generate all the on-board voltages (1.3V, 1.5V, 2.6V, and 3.3V, and the 2.5V for the MGTs)

The input voltage is specified at 5 V @ 6.5 A. The recommended power supply is a CUI Inc. DTS050650UTC-PSP-SZ. The jack used is a 4-pin barrel jack, CUI stack PJ-002A-SMT. The slide switch is a CW Industries G1123-0009. This power input has alternate input solder pads.

The Texas Instruments PTH05000WAH voltage regulator generates the 3.3 V @ 5.5 A power. This power input has alternate input solder pads.

The Texas Instruments PTH05010WAS voltage regulator generates the 2.6 V @ 10 A power. This regulator provides 2.5 Vout with ± 10% trim. This power input has alternate input solder pads.

1.5 V Generation

The Texas Instruments PTH05000WAH voltage regulator generates the 1.5 V @ 5.5 A power. This power input has alternate input solder pads.

1.3 V Generation

The Texas Instruments PTH05000WAH voltage regulator generates the 1.3 V @ 1.5 A power.

Linear Regulators for the MGTs

The Texas Instruments TPS78625 voltage regulator generates 2.5 V @ 1.5 A power for the Multi Gigabit Transceivers (MGTs).

FPGA Configuration

The Virtex-II Pro FPGA can be programmed through either the JTAG interface or three onboard PROMs.

JTAG

Two headers are used for JTAG: a standard header and a parallel-IV header.

Standard Header

The standard JTAG header is a 1 x 7 0.100" RA header.

Parallel-IV Header

The parallel-IV headers is a 2 x 7 2 mm RA shrouded header.

18 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Block Descriptions

PROMs

The ML361 board contains XCF04S PROMs that can be used to program the Virtex-II Pro FPGA. The PROM operates with a 3.3 V core voltage and a 2.5 V I/O voltage.

ML361 Virtex-II Pro Memory Board www.xilinx.com 19

UG060 (v1.2) November 8, 2007

Chapter 2: Architecture

20 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Electrical Requirements

Power Consumption

Tab le 3- 1 lists the operating voltages, maximum currents, and power consumption used by

the ML361 board devices. Refer to Appendix A, “Related Documentation,” for more information on the source material.

Table 3-1: ML361 Power Consumption

Chapter 3

Device Quantity

Total Available Power

Power Supply 1 5 6500 32.5

FPGA Power (Based on Design)

FPGA (XC2VP20-6 FF1152) 1 6.873 Power Estimator Tool

Board Power

Static Power-on Termination Resistors (50Ω)

DDR SDRAM (72-bit interface) 5 2.6 260 3.38 Micron DDR SDRAM Data Sheet

DDR SDRAM (8-bit interface) 1 2.6 260 0.676

DDR SDRAM DIMM 1 2.6 1040 2.704 Micron DDR SDRAM DIMM Data

200 MHz LVDS Clock Oscillator 1 3.3 40 0.132 Pletronics LV1145B-200 Data Sheet

166 MHz LVDS Clock Oscillator 1 3.3 40 0.132 Pletronics LV1145B-166 Data Sheet

PROMs (XCF04SV020C) 3 2.6 25 0.2 Estimated

375 1.3 16.2 4.92 Virtex-II Pro User Guide (SSTL2

3 3.3 25 0.25 Estimated

Volt ag e

(V)

Current

(mA)

Power

(W)

Source

current specification)

Sheet

8-pin GPIO Header 2 2.6 160 0.416 Average 10 mA * 16 pins

Seven Segment Display 2 2.6 86 0.224 Fourteen 130Ω loads

LEDs 9 2.6 25 0.585 Nine 130Ω loads

DIP Switch 1 2.6 6 0.016 Eight 3.3 kΩ pull-ups

RS232 Serial Port 1 3.3 40 0.132 TI MAX3221 Data Sheet

Worst Case Power Consumption: 20.64

ML361 Virtex-II Pro Memory Board www.xilinx.com 21

UG060 (v1.2) November 8, 2007

Chapter 3: Electrical Requirements

FPGA Internal Power Budget

The following tables show the power consumption values inside the FPGA based on the complete DDR design. These results are derived using the Xilinx Power Estimator tool. Block Select RAM, Block Multiplier, Processor, and MGT Power tables are not included in this section as they are not used in this application.

• Tab le 3- 2, “XC2VP20FF1152 Estimated Power Consumption,” page 22

• Tab le 3- 3, “XC2VP20FF1152 Temperature Specifications,” page 22

• Tab le 3- 4, “Device Quiescent Power,” page 22

• Tab le 3- 5, “CLB Logic Power,” page 23

• Tab le 3- 6, “Digital Clock Manager Power,” page 23

• Tab le 3- 7, “Input/Output Power,” page 24

Table 3-2: XC2VP20FF1152 Estimated Power Consumption

Parameter Value Units

Total Estimated Design Power 6873 mW

Estimated Design VCC

1.5 V Power 3811 mW

INT

2.5 V Power 417 mW

AUX

Estimated Design VCCO 3.3 V Power 0 mW

Estimated Design VCCO 2.5 V Power 2645 mW

Estimated Design VCCO 1.8V Power 0 mW

Estimated Design VCCO 1.5 V Power 0 mW

Estimated Design VCCO 1.2 V Power 0 mW

Estimated Design VCC

Estimated Design VT

RX 2.5 V Power 0 mW

AUX

TX 2.5 V Power 0 mW

AUX

2.5 V Power 0 mW

Table 3-3: XC2VP20FF1152 Temperature Specifications

Parameter Value Units

Ambient Temperature 25 •C

Air Flow 0 LFM

Junction Temperature 107 •C

Table 3-4: Device Quiescent Power

VCC

Subtotal (mW) VCC

INT

Subtotal (mW)

AUX

450 417

22 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Table 3-5: CLB Logic Power

FPGA Internal Power Budget

Tot al

Name

User Module 1 200 2597 2603 0 1088 40% High 2439

User Module 2 0 0 0 0 0 0% Low 0

User Module 3 0 0 0 0 0 0% Low 0

User Module 4 0 0 0 0 0 0% Low 0

User Module 5 0 0 0 0 0 0% Low 0

User Module 6 0 0 0 0 0 0% Low 0

User Module 7 0 0 0 0 0 0% Low 0

User Module 8 0 0 0 0 0 0% Low 0

User Module 9 0 0 0 0 0 0% Low 0

User Module 10 0 0 0 0 0 0% Low 0

User Module 11 0 0 0 0 0 0% Low 0

User Module 12 0 0 0 0 0 0% Low 0

Frequency

(MHz)

Number

of CLB

Slices

Tot al

Number of

Flip/Flop or

Latches

Tota l N u m be r

of Shift

Tot al Numbe r

of Select

RAM LUTs

Average

Toggle

Rate

Amount of

Routing

Used

Total 2439

VCC

Subtotal

(mW)

INT

Table 3-6: Digital Clock Manager Power

Name

Clock Input

Frequency (MHz)

DCM Frequency Mode

VCC

INT

User DCM 1 200 Low 6

User DCM 2 200 Low 6

User DCM 3 0 Low 0

User DCM 4 0 Low 0

User DCM 5 0 Low 0

User DCM 6 0 Low 0

User DCM 7 0 Low 0

User DCM 8 0 Low 0

User DCM 9 0 Low 0

User DCM 10 0 Low 0

User DCM 11 0 Low 0

User DCM 12 0 Low 0

To t al 1 2

Subtotal

(mW)

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UG060 (v1.2) November 8, 2007

Chapter 3: Electrical Requirements

Table 3-7: Input/Output Power

Average

Output Enable

Rate

Average

Output

Load

(pF)

IOB

Registers

VCC

INT

Subtotal

(mW)

VCCO

Subtotal

Name

Frequency

(MHz)

I/O Standard

Typ e

Tot al

Number

of Inputs

Tot al

Number

Outputs

Average

IOB

Tog gle

Rate

Jpheader 200 LVCMOS25_12 0 16 25% 100% 0 SDR 2 30

ddr_dq 200 SSTL2_II 138 138 80% 50% 5 DDR 462 877

ddr_dqs 2000 SSTL2_II 18 18 80% 50% 5 DDR 335 363

ddr_address 200 SSTL2_II 0 15 25% 100% 3 SDR 1 106

ddr_control 200 SSTL2_II 0 5 25% 100% 3 SDR 0 35

dimm_address 200 SSTL2_I_DCI 0 15 25% 100% 12 SDR 13 157

dimm_control 200 SSTL2_I_DCI 0 4 50% 100% 12 SDR 12 96

ddr_clks 200 SSTL2_II 0 2 100% 100% 3 DDR 0 42

Display 200 LVCMOS25_12 0 14 6% 100% 0 SDR 1 6

dimm_control_1 200 SSTL2_II 0 3 50% 100% 12 SDR 0 28

ddr_dm 200 SSTL2_II 0 17 10% 100% 5 SDR 2 100

(mW)

dimm_clks 200 SSTL2_II 0 6 100% 100% 12 SDR 1 82

top_dq 200 SSTL2_II_DCI 8 8 80% 50% 5 DDR 39 366

top_dqs 200 SSTL2_II_DCI 1 1 80% 50% 5 DDR 15 103

top_address 200 SSTL2_I_DCI 0 15 25% 100% 5 SDR 13 153

top_control 200 SSTL2_I_DCI 0 5 25% 100% 5 SDR 12 95

Total 910 2645

24 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

Chapter 4

Signal Integrity Recommendations and Simulations

This chapter provides the following information:

• Summary of the termination schemes for various signals (“Termination and

Transmission Line Summaries,” page 25)

• Summary of the observed duty cycles for all signals in the IBIS simulations (“Duty

Cycle Summary,” page 27)

• IBIS simulations and duty cycle measurements (“IBIS Simulations,” page 29)

Termination and Transmission Line Summaries

Tab le 4- 1 summarizes the terminations for the five DDR SDRAM components at the FPGA

and at memory.

Table 4-1: DDR SDRAM Terminations

No. Signal

1 Data (DQ) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V

2 Data Strobe (DQS) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V

3 Data Mask (DM) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V

4 Clock (CK, CKn) SSTL2_C2 50Ω pull up to 1.3 V 50Ω pull-up to 1.3 V

5 Address (A, BA) SSTL2_C2 No termination 50Ω pull-up to 1.3 V after the

6 Control (RASn, CASn, WEn,

CSn, CKE)

Tab le 4- 2 summarizes the terminations for the DIMM at the FPGA and at memory.

Table 4-2: DIMM Terminations

No. Signal

Drivers at the

FPGA

SSTL2_C2 No termination 50Ω pull-up to 1.3 V after the

Drivers at the

FPGA

Termination at FPGA Termination at Memory

last component

Termination at FPGA Termination at Memory

1 Data (DQ) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V

2 Data Strobe (DQS) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V

3 Data Mask (DM) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V

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UG060 (v1.2) November 8, 2007

Chapter 4: Signal Integrity Recommendations and Simulations

Table 4-2: DIMM Terminations

No. Signal

4 3 pairs of Clocks (CK, CKn) SSTL2_C2 50Ω pull-up to 1.3 V 50Ω pull-up to 1.3 V

5 Address (A, BA) SSTL2_C2_DCI No termination No termination

6 Control (RASn, CASn, WEn,

CSn, CKE and others)

Drivers at the

FPGA

SSTL2_C2_DCI No termination No termination

Termination at FPGA Termination at Memory

Terminations and Transmission Lines for DDR Components

Data and Clock Signals (DQ, DQS, DM, CLK)

For these DDR signals, the terminations at the FPGA and memory consist of a 50Ω parallel termination pulled up to 1.3 V.

Use 50

Ω transmission lines with less than ± 1% tolerance on the transmission line

impedance. The recommendations for the transmission line lengths are as follows:

• All these data and clock signals are point-to-point from the FPGA to each DDR component. All signals going to one individual DDR SDRAM component need to be matched with respect to each other with a ± 2% tolerance.

• All signals going to the first component are matched to a trace length of 2.8 inches with a ± 2% tolerance. The 2.5 inch requirement includes the FPGA internal package skew (available on the pinout table) and the skew between the ball of the FPGA to the resistor pack as well as the length of the actual trace.

• The trace length variation on these signals across the five DDR components is kept as small as possible to enable data capture while also ensuring they fall within the address window. The trace lengths on all five DDR components are: 2.8 inches, 2.8 inches, 3.5 inches, 3.8 inches, and 3.8 inches. All signals corresponding to the same DDR component are matched as close as ± 1% of the above mentioned trace lengths.

Microstrip is used to model the transmission lines in the IBIS simulations.

Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE)

For the address and control signals, no termination is required at the FPGA. At memory, a 50

Ω resistor pulled up to 1.3 V at the end of the daisy chain is required (after the last DDR

component).

Use 50

Ω transmission lines with ± 5% tolerance from the FPGA to all the memory

components. The recommendations for the transmission line lengths are as follows:

• All the signals are routed in a daisy chain fashion.

• There is a maximum of 2.5 inch trace with ± 2% tolerance from the FPGA to the first

DDR component. The 2.5 inch requirement includes the FPGA internal package skew (that is available on the pinout table) and the skew between the ball of the FPGA to the resistor pack as well as the length of the actual trace.

• 0.6 inches of distance with ± 2% tolerance is used in the trace length calculations below between the individual components. Ideally, straight line routing is desired. During placement, the components are placed as close as 0.5 inches or lesser by straight line routing, if possible. The main requirement is that all signals going to each DDR component must be matched by ± 2% tolerance.

26 www.xilinx.com ML361 Virtex-II Pro Memory Board

UG060 (v1.2) November 8, 2007

• There is a total of 4.9 inches of trace from the FPGA to the last component assuming the DDR memory components are 0.6 inch apart.

Microstrip is used to model the transmission lines for the first DDR component. All other DDR components use Buried Microstrip to model the transmission lines.

Terminations and Transmission Lines for the DIMM

Data and Clock Signals (DQ, DQS, DM, CLK)

For these DIMM signals, the terminations at the FPGA and memory consist of a 50Ω parallel termination pulled up to 1.3 V.

Ω transmission lines are used with less than ± 1% tolerance on the transmission line

impedance. The transmission line lengths are as follows:

• There is a 65 mm trace length from FPGA to memory with ± 0.5 mm tolerance.

• A maximum of 1 inch tolerance is allowed to include the FPGA internal package skew

and the skew between the ball of the FPGA to the resistor pack. Package deskew is necessary if the 1 inch tolerance is not met.

Duty Cycle Summary

Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE)

For the address and control signals, no termination is required at the FPGA or DIMM.

Use 50

Ω transmission lines with less than ± 5% tolerance on the transmission line

impedance. The recommendations for the transmission line lengths are as follows:

• There must be a 65 mm trace length from FPGA to memory with ± 5 mm tolerance.

• Use a maximum of 1 inch tolerance to include the FPGA internal package skew and

the skew between the ball of the FPGA to the resistor pack. Package deskew is necessary if the 1 inch tolerance is not met.

Duty Cycle Summary

Tab le 4- 3 summarizes the duty cycle measurements taken from prelayout simulations on

Ω transmission lines. Refer to “IBIS Simulations,” page 29 for more simulation results.

Table 4-3: Duty Cycle Summary

No. Signal DDR Component Case

1 Address/control Last component

(farthest from FPGA)

Typical 49.22/50.92 NA

Slow weak 49.22/50.63 NA

Duty Cycle

Measured at

Memory(%)

Duty Cycle

Measured at

FPGA (%)

Fast strong 49.22/51.2 NA

2 Address/control First component

(closest to FPGA)

ML361 Virtex-II Pro Memory Board www.xilinx.com 27

UG060 (v1.2) November 8, 2007

Typical 48.94/51.2 NA

Slow weak 49.22/51.48 NA

Fast strong 48.66/51.2 NA

+ 63 hidden pages

Xilinx ML361 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table of Contents

Schedule of Figures

Schedule of Tables

About This Guide

Guide Contents

Additional Resources

Conventions

Typographical

Online Document

Overview

Features

ML361 Board Block Diagram

Block Descriptions

FPGA

Memories

RS232

Clocks

User I/Os

Power

FPGA Configuration

Power Consumption

FPGA Internal Power Budget

Termination and Transmission Line Summaries

Terminations and Transmission Lines for DDR Components

Terminations and Transmission Lines for the DIMM

Duty Cycle Summary