Xilinx LogiCORE IP I/O Module v1.02a Product Manual
LogiCORE IP I/O
Module v1.02a
Product Guide
PG052 October 16, 2012
Table of Contents
SECTION I: SUMMARY
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LMB Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SECTION II: VIVADO DESIGN SUITE
Chapter 4: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 5: Constraining the Core
Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Device, Package, and Speed Grade Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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PG052 October 16, 2012
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Transceiver Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O Standard and Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SECTION III: ISE DESIGN SUITE
Chapter 6: Customizing and Generating the Core
GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 7: Constraining the Core
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SECTION IV: APPENDICES
Appendix A: Migrating
Appendix B: Debugging
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix C: Application Software Development
Device Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix D: Additional Resources
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
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PG052 October 16, 2012
SECTION I: SUMMARY
IP Facts
Overview
Product Specification
Designing with the Core
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PG052 October 16, 2012
IP Facts
Introduction
The LogiCORE™ I/O Module is a highly
integrated and light-weight implementation of
a standard set of peripherals.
The I/O Module is a standalone version of the
tightly coupled I/O Module included in the
LogiCORE MicroBlaze™ Micro Controller
System (MCS). Using the I/O Module, a system
equivalent to MicroBlaze MCS can be design
using the ISE® Design Suite Embedded Edition
or the Vivado™ Design Suite.
The I/O Module connects to MicroBlaze
through the lmb_v10 bus.
Features
• LMB v1.0 bus interfaces to communicate
with MicroBlaze
•I/O Bus
• Interrupt Controller with fast interrupt
mode support
•UART
•Fixed Interval Timers
• Programmable Interval Timers
• General Purpose Inputs
• General Purpose Outputs
LogiCORE IP Facts Table
Core Specifics
Supported
Device
(1)
Family
Supported
User Interfaces
Resources See Ta b le 2 -2 .
Zynq™-7000
(2)
, Virtex-7, Kintex™-7, Artix™-7,
Virtex-6, Spartan-6, Virtex-5, Virtex®-4,
Local Memory Bus (LMB), Dynamic
Reconfiguration Port (DRP)
Spartan®-3
Provided with Core
Design Files
Example
Design
Tes t B e nc h Not Provid e d
Constraints
File
Simulation
Model
Supported
S/W Driver
(3)
ISE: VHDL
Vivado: RTL
Not Provided
Not Provided
VHDL Behavioral
Standalone
Tested Design Flows
Design Entr y Xilinx Platform Studio (XPS)
Simulation Mentor Graphics ModelSim
Synthesis
Xilinx Synthesis Technology (XST)
Vivado Synthesis
(5)
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported derivative devices, see the
mbedded Edition Derivative Device Support.
E
2. Supported in ISE Design Suite implementations only.
3. Standalone driver details can be found in the EDK or SDK
directory (<install_directory>/doc/usenglish/
xilinx_drivers.htm). Linux OS and driver support information is
available from //wiki.xilinx.com
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
5. Supports only 7 series devices.
.
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PG052 October 16, 2012 Product Specification
Overview
I/O Module
LMB
UART_Tx_IO
UART_Interrupt
FITx_Interrupt
PITx_Interrupt
GPOx_IO
INTC_Interrupt
INTC_IRQ
IO_Addr_Strobe
IO_Read_Strobe
IO_Write_Strobe
IO_Address
IO_Byte_Enable
IO_Write_Data
IO_Read_Data
IO_Ready
PITx_Toggle
INTC_Interrupt_Address
INTC_Interrupt_Ack
Interrupt
GPIx_IO
UART_Rx_IO
PITx_Enable
FITx_Toggle
IO_Bus
GPIx_Interrupt
The I/O Module is a light-weight implementation of a set of standard I/O functions
commonly used in a MicroBlaze™ processor sub-system. The input/output signals of the I/O
Module are shown in Figure 1-1. The detailed list of signals are listed and described in
Tab le 2- 3. See the description of LMB Signals in the MicroBlaze Bus Interfaces chapter in the
MicroBlaze Processor Reference Guide [Ref 1].
.
X-Ref Target - Figure 1-1
Chapter 1
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PG052 October 16, 2012
In a MicroBlaze system the I/O Module would typically be connected according to
Figure 1-2.
Figure 1-1: I/O Module Block Diagram
ILMB
MicroBlaze
LMB_v10
LMB BRAM
Interface Controller
BRAM Block
(Dual Port)
DLMB
LMB_v10
LMB BRAM
Interface Controller
I/O Module
X-Ref Target - Figure 1-2
Feature Summary
Figure 1-2: Typical MicroBlaze System
Feature Summary
I/O Bus
The I/O Bus provides a simple bus for accessing to external modules. The I/O Bus is mapped
in the MicroBlaze memory space, with the I/O Bus address directly reflecting the byte
address used by MicroBlaze Load/Store instructions. I/O Bus data is 32-bit wide, with byte
enables to write byte and half-word data.
The I/O Bus is fully compatible with the Xilinx Dynamic Reconfiguration Port (DRP).
UART
The Universal Asynchronous Receiver Transmitter (UART) interface provides the controller
interface for asynchronous serial data transfers. Features supported include:
• One transmit and one receive channel (full duplex)
• Configurable number of data bits in a character (5-8)
• Configurable parity bit (odd or even)
• Configurable and programmable baud rate
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PG052 October 16, 2012
Licensing and Ordering Information
Fixed Interval Timer, FIT
The Fixed Interval Timer generates a strobe signal at fixed intervals. The Fixed Interval
Timer asserts the output signal and generates an interrupt according to the selected
parameter values.
Programmable Interval Timer, PIT
The Programmable Interval Timer, PIT, has a configurable width from 1 to 32. The PIT
operation and period are controlled by software. An interrupt can be generated when the
timer lapses.
General Purpose Output, GPO
The General Purpose Output, GPO, drives I/O Module GPO output signals defined by the
value of the corresponding GPO register, programmable from software. The width and
initial value are defined by parameters.
General Purpose Input, GPI
The General Purpose Input, GPI, makes it possible for software to sample the value of the
I/O Module GPI input signals by reading the GPI register. The width and whether to
generate an interrupt are defined by parameters.
Interrupt Controller INTC
The Interrupt Controller handles both I/O module internal interrupt events and external
ones. The internal interrupt events originate from the UART, the Fixed Interval Timers, the
Programmable Interval Timers, or the General Purpose Inputs.
Licensing and Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado
Design Suite and ISE Design Suite Embedded Edition tools under the terms of the Xilinx End
User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative
.
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PG052 October 16, 2012
Product Specification
Standards
The I/O Bus interface provided by the I/O Module is fully compatible with the Xilinx
Dynamic Reconfiguration Port (DRP). For a detailed description of the DRP, see the 7 Series
FPGAs Configuration User Guide [Ref 2].
Performance
The frequency and latency of the I/O Module are optimized for use together with
MicroBlaze™. This means that the frequency targets are aligned to MicroBlaze targets as
well as the access latency optimized for MicroBlaze data access.
Chapter 2
Maximum Frequencies
The following are clock frequencies for the target families. The maximum achievable clock
frequency can vary. The maximum achievable clock frequency and all resource counts can
be affected by the used tool flow, other tool options, additional logic in the FPGA, using
different versions of Xilinx tools, and other factors.
Table 2-1: Maximum Frequencies
Architecture Speed grade Max Frequency
Virtex-7 -3 320
Kintex™-7 -3 320
Artix™-7 -3 225
Virtex®-6 -3 300
Spartan®-6 -4 195
Latency
Data read from I/O Module registers is available two clock cycles after the address strobe is
asserted.
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PG052 October 16, 2012 Product Specification
Resource Utilization
Data write to I/O Module registers is performed the clock cycle after the address strobe is
asserted.
Data accesses to peripherals connected on the I/O Bus take three clock cycles plus the
number of wait states introduced by the accessed peripheral.
Throughput
The maximum throughput when using the I/O Bus is one read or write access every three
clock cycles.
Resource Utilization
Because the MicroBlaze MCS is a module that is used together with other parts of the
design in the FPGA, the utilization and timing numbers reported in this section are just
estimates, and the actual utilization of FPGA resources and timing of the MicroBlaze MCS
design will vary from the results reported here. All parameters not given in the table below
have their default values.
Table 2-2: Performance and Resource Utilization Benchmarks on Virtex-6 (xc6vlx240t-1-ff1156)
Parameter Values (other parameters at default value) Device Resources
LUTs Flip-Flops
C_USE_UART_TX
C_USE_UART_RX
C_INTC_USE_EXT_INTR
11000 0 000000 00 40 75
11150 0 000000 00 69 110
11150 0 000000 01 118 173
1 1 1 5 1 65000 0 0 0 0 0 0 0 0 75 122
1 1 1 5 1 65000 1 32 0 0 0 0 0 0 121 216
1115165000132132132 00 121 280
1115165000132132132 10 119 361
C_INTC_INTR_SIZE
C_USE_FIT1
C_FIT1_No_CLOCKS
C_USE_PIT1
C_USE_GPI1
C_PIT1_SIZE
C_GPI1_SIZE
C_USE_GPO1
C_GPO1_SIZE
C_USE_IO_BUS
C_INTC_HAS_FAST
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PG052 October 16, 2012 Product Specification
Port Descriptions
Port Descriptions
The I/O ports and signals for the I/O Module are listed and described in Ta bl e 2 -3.
Table 2-3: I/O Module I/O Signals
Port Name MSB:LSB I/O Description
LMB Signals
LMB_ABus 0:C_LMB_AWIDTH-1
LMB_WriteDBus 0:C_LMB_DWIDTH-1
LMB_ReadStrobe
LMB_AddrStrobe
LMB_WriteStrobe
LMB_BE 0:C_LMB_DWIDTH/8-1
Sl_DBus 0:C_LMB_DWIDTH-1
Sl_Ready
Sl_Wait
Sl_CE
Sl_UE
I/O Bus Signals
IO_Addr_Strobe
IO_Read_Strobe
IO_Write_Strobe
IO_Address 31:0
IO_Byte_Enable 3:0
IO_Write_Data 31:0
IO_Read_Data 31:0
IO_Ready
I
LMB Address Bus
I
LMB Write Data Bus
I
LMB Read Strobe
I
LMB Address Strobe
I
LMB Write Strobe
I
LMB Byte Enable Bus
O
LMB Read Data Bus
O
LMB Data Ready
O
LMB Wait
O
LMB Correctable Error
O
LMB Uncorrectable Error
O
Address strobe signals valid I/O Bus output
signals
O
I/O Bus access is a read
O
I/O Bus access is a write
O
Address for access
O
Byte enables for access
O
Data to write for I/O Bus write access
I
Read data for I/O Bus read access
I
Ready handshake to end I/O Bus access
UART Signals
UART_Rx_IO
UART_Tx_IO
UART_Interrupt
I
Receive Data
O
Trans m i t Data
O
UART Interrupt
FIT Signals
FITx_Interrupt
FITx_Toggle
(1)
(1)
O
FITx timer lapsed
O
Inverted FITx_Toggle when FITx timer lapses
PIT Signals
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PG052 October 16, 2012 Product Specification
Table 2-3: I/O Module I/O Signals (Cont ’d)
Port Name MSB:LSB I/O Description
(1)
(1)
(1)
(1)
(1)
[C_GPOx_SIZE - 1]:0
[C_GPIx_SIZE - 1]:0
[C_GPIx_SIZE - 1]:0
PITx_Enable
PITx_Interrupt
PITx_Toggle
GPOx
(1)
GPIx
GPIx_Interrupt
I
O
O
GPO Signals
O
GPI Signals
I
O
INTC Signals
Port Descriptions
PITx count enable when C_PITx_PRESCALER
= External
PITx timer lapsed
Inverted PITx_Toggle when PITx lapses
GPOx Output
GPIx Input
GPIx input changed
INTC_Interrupt 0:[C_INTC_INTR_SIZE - 1]
INTC_IRQ
INTC_Interrupt_Address [C_INTC_ADDR_WIDTH-1]:0
INTC_Interrupt_Ack 1:0
1. x = 1, 2, 3 or 4
I
External interrupt inputs
O
Interrupt Output
O
Interrupt Address Output
I
Interrupt Acknowledge Input
Parameter - Port Dependencies
The width of many of the I/O Module signals depends on design parameters. The
dependencies between the design parameters and I/O signals are shown in Tab le 2-4 .
Table 2-4: Parameter-Port Dependencies
Parameter Name Ports (Port width depends on parameter)
C_INTC_INTR_SIZE INTC_Interrupt
C_INTC_ADDR_WIDTH INTC_Interrupt_Address
C_GPO1_SIZE GPO1
C_GPO2_SIZE GPO2
C_GPO3_SIZE GPO3
C_GPO4_SIZE GPO4
C_GPI1_SIZE GPI1
C_GPI2_SIZE GPI2
C_GPI3_SIZE GPI3
C_GPI4_SIZE GPI4
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PG052 October 16, 2012 Product Specification
Register Space
Table 2-5: I/O Module Register Address Map
Register Space
Base Address + Offset (hex) Register
C_BASEADDR + 0x0 UART_RX R
C_BASEADDR + 0x4 UART_TX W
C_BASEADDR + 0x8 UART_STATUS R
C_BASEADDR + 0xC IRQ_MODE W
C_BASEADDR + 0x10 GPO1 W
C_BASEADDR + 0x14 GPO2 W
C_BASEADDR + 0x18 GPO3 W
C_BASEADDR + 0x1C GPO4 W
C_BASEADDR + 0x20 GPI1 R
C_BASEADDR + 0x24 GPI2 R
C_BASEADDR + 0x28 GPI3 R
C_BASEADDR + 0x2C GPI4 R
C_BASEADDR + 0x30 IRQ_STATUS R
C_BASEADDR + 0x34 IRQ_PENDING R
C_BASEADDR + 0x38 IRQ_ENABLE W
C_BASEADDR + 0x3C IRQ_ACK W
C_BASEADDR + 0x40 PIT1_PRELOAD W
C_BASEADDR + 0x44 PIT1_COUNTER R
C_BASEADDR + 0x48 PIT1_CONTROL W
C_BASEADDR + 0x4C UART_BAUD W
C_BASEADDR + 0x50 PIT2_PRELOAD W
C_BASEADDR + 0x54 PIT2_COUNTER R
C_BASEADDR + 0x58 PIT2_CONTROL W
C_BASEADDR + 0x5C Reserved
C_BASEADDR + 0x60 PIT3_PRELOAD W
C_BASEADDR + 0x64 PIT3_COUNTER R
C_BASEADDR + 0x68 PIT3_CONTROL W
C_BASEADDR + 0x6C Reserved
C_BASEADDR + 0x70 PIT4_PRELOAD W
C_BASEADDR + 0x74 PIT4_COUNTER R
C_BASEADDR + 0x78 PIT4_CONTROL W
C_BASEADDR + 0x7C Reserved
Access
Type
Description
UART Receive Data Register
UART Transmit Data Register
UART Status Register
Interrupt Mode Register
Gen e ra l P u r p os e O u t p ut 1 Re g is te r
Gen e ra l P u r p os e O u t p ut 2 Re g is te r
Gen e ra l P u r p os e O u t p ut 3 Re g is te r
Gen e ra l P u r p os e O u t p ut 4 Re g is te r
General Purpose Input 1 Register
General Purpose Input 2 Register
General Purpose Input 3 Register
General Purpose Input 4 Register
Interrupt Status Register
Pending Interrupt Register
Interrupt Enable Register
Interrupt Acknowledge Register
PIT1 Preload Register
PIT1 Counter Register
PIT1 Control Register
UART Programmable Baud Rate
PIT2 Preload Register
PIT2 Counter Register
PIT2 Control Register
PIT3 Preload Register
PIT3 Counter Register
PIT3 Control Register
PIT4 Preload Register
PIT4 Counter Register
PIT4 Control Register
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PG052 October 16, 2012 Product Specification
Table 2-5: I/O Module Register Address Map (Cont’d)
Register Space
Base Address + Offset (hex) Register
C_BASEADDR + 0x80 -
C_BASEADDR + 0xFC
(C_BASEADDR + 0x100) - C_HIGHADDR Reserved
C_IO_BASEADDR - C_IO_HIGHADDR I/O Bus RW
IRQ_VECTOR_0 -
IRQ_VECTOR_31
Access
Type
W
Description
Interrupt Address Vector Registers
Mapped to I/O Bus address output
IO_Address
UART Receive Data Register (UART_RX)
This register contains data received by the UART. Reading this location results in reading the
current word from the register. When a read request is issued without having received a new
character, the previously read data is read again. This register is a read-only register. Issuing
a write request to the register does nothing but generate the write acknowledgement. The
register is implemented if C_USE_UART_RX is set to 1.
Table 2-6: UART Receive Data Register (UART_RX) (C_DATA_BITS=8)
Reserved UART_RX
31 87 0
Table 2-7: UART Receive Data Register Bit Definitions
Bit(s) Name
31:C_UART_DATA_BITS
[C_UART_DATA_BITS-1]:0
Core
Access
-R0
UART_RX R 0
Reset
Value
Description
Reserved
UART Receive Data
UART Transmit Data Register (UART_TX)
A register contains data to be output by the UART. Data to be transmitted is written into this
register. This is write only location. Issuing a read request to this register generates the read
acknowledgement with zero data. Writing this register when the character has not been
transmitted will overwrite previously written data, resulting in loss of data. The register is
implemented if C_USE_UART_TX is set to 1.
Table 2-8: UART Transmit Data Register (UART_TX) (C_DATA_BITS=8)
Reserved UART_TX
31 87 0
Table 2-9: UART Transmit Data Register Bit Definitions
Bit(s) Name
Core
Access
Reset
Value
Description
31:C_UART_DATA_BITS - R 0
[C_UART_DATA_BITS-1]:0 UART_TX R 0
Reserved
UART Transmit Data
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PG052 October 16, 2012 Product Specification
Register Space
UART Status Register (UART_Status)
The UART Status Register contains the status of the receive and transmit registers, and if
there are any errors. This is read only register. If a write request is issued to status register
it will do nothing but generate write acknowledgement. The register is implemented if
C_USE_UART_RX or C_USE_UART_TX is set to 1.
Table 2-10: UART Status Register (UART_Status)
Reserved UART_Status
31 87 0
Table 2-11: UART Status Register Bit Definitions
Bit(s) Name
7 Parity Error R 0
6 Frame Error R 0
5 Overrun Error R 0
Core
Access
Reset
Value
Description
Indicates that a parity error has occurred after the last time
the status register was read. If the UART is configured without
any parity handling, this bit is always ‘0’. The received
character is written into the receive register. This bit is cleared
when the status register is read.
0 = No parity error has occurred
1 = A parity error has occurred
Indicates that a frame error has occurred after the last time
the status register was read. Frame Error is defined as
detection of a stop bit with the value 0. The receive character
is ignored and not written to the receive register.
This bit is cleared when the status register is read.
0 = No Frame error has occurred
1 = A frame error has occurred
Indicates that a overrun error has occurred since the last time
the status register was read. Overrun occurs when a new
character has been received but the receive register has not
been read. The received character is ignored and not written
into the receive register. This bit is cleared when the status
register is read.
0 = No interrupt has occurred
1 = Interrupt has occurred
4- R0Reserved
Indicates if the transmit register is in use
3Tx Used R 0
2- R0Reserved
1- R0Reserved
0 Rx Valid Data R 0
0 = Transmit register is not in use
1= Transmit register is in use
Indicates if the receive register has valid data
0 = Receive register is empty
1 = Receive register has valid data
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PG052 October 16, 2012 Product Specification
Register Space
UART_BAUD
C_FREQ
C_UART_BAUDRATE 16•
------------------------------------ ------------------
1–=
UART Programmable Baud Rate Register (UART_BAUD)
This register sets the baud rate when using programmable baud rate. The initial value of the
register is determined from the selected fixed baud rate C_UART_BAUDRATE and the clock
frequency C_FREQ, using the formula:
Table 2-12: UART Programmable Baud Rate Register (UART_BAUD)
Reserved UART_BAUD
31 20 19 0
Table 2-13: UART Programmable Baud Rate Register Bit Definitions
Bit(s) Name
31:20 - - -
19:0 UART_BAUD W See above
Core
Access
Reset
Value
Description
Reserved
Programmed UART Baud Rate
General Purpose Output x Register (GPOx) (x = 1, 2, 3 or 4)
This register holds the value that will be driven to the corresponding bits in the I/O Module
GPOx port output signals. All bits in the register are updated when the register is written.
This register is not implemented if the value of C_USE_GPOx is 0.
Table 2-14: General Purpose Output x Register (GPOx)
Reserved GPOx
31 C_GPOx_SIZE C_GPOx_SIZE-1 0
Table 2-15: General Purpose Output x Register Bit Definitions
Bit(s) Name
31:C_GPOx_SIZE
[C_GPOx_SIZE-1]:0
Core
Access
---
GPOx W 0
Reset
Valu e
Description
Reserved
Register holds data driven to corresponding bits in the GPO
port
General Purpose Input x Register (GPIx) (x=1, 2, 3 or 4)
This register reads the value that is input on the corresponding I/O Module GPIx port input
signal bits. This register is not implemented if the value of C_USE_GPIx is 0.
Table 2-16: General Purpose Input x Register (GPIx)
Reserved GPIx
31 C_GPIx_SIZE C_GPIx_SIZE-1 0
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PG052 October 16, 2012 Product Specification
Table 2-17: General Purpose Input x Register Bit Definitions
Register Space
Bit(s) Name
31:C_GPIx_SIZE
[C_GPIx_SIZE-1]:0
Core
Access
-R0
GPIx R 0
Reset
Value
Description
Reserved
Register reads value input on the I/O Module GPIx port input
signals
Interrupt Status Register (IRQ_STATUS)
The Interrupt Status Register holds information on interrupt events that have occurred. The
register is read-only and the IRQ_ACK register should be used to clear individual interrupts.
Table 2-18: Interrupt Status Register (IRQ_STATUS)
Reserved INTC_Interrupt Reserved Internal Interrupts
31 C_INTC_EXT_INTR+16 C_INTC_EXT_INTR+15 16 15 11 10 0
Table 2-19: Interrupt Status Register Bit Definitions
Bit(s) Name
31:[C_INTC_EXT_INTR + 16] - R 0
[C_INTC_EXT_INTR+15]:16 INTC_Interrupt R 0
Core
Access
Reset
Value
Description
Reserved
I/O Module external interrupt input signal
INTC_Interrupt [C_INTC_EXT_INTR-1:0]
mapped to corresponding bit positions in
IRQ_STATUS
15 - R 0
14 GPI4 R 0
13 GPI3 R 0
12 GPI2 R 0
11 GPI1 R 0
10 FIT4 R 0
9FIT3R0
8FIT2R0
7FIT1R0
6PIT4R0
5PIT3R0
4PIT2R0
3PIT1R0
2UART_RXR0
1UART_TXR0
0UART_ERRR0
Reserved
GPI4 changed
GPI3 changed
GPI2 changed
GPI1 changed
FIT4 strobe
FIT3 strobe
FIT2 strobe
FIT1 strobe
PIT4 lapsed
PIT3 lapsed
PIT2 lapsed
PIT1 lapsed
UART Received Data
UART Transmitted Data
UART Error
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PG052 October 16, 2012 Product Specification
Register Space
Interrupt Pending Register (IRQ_PENDING)
The Interrupt Pending Register holds information on enabled interrupt events that have
occurred. IRQ_PENDING is the contents of IRQ_STATUS bit-wised masked with the
IRQ_ENABLE register. The register is read-only and the IRQ_ACK register should be used to
clear individual interrupts.
Table 2-20: Interrupt Pending Register (IRQ_PENDING)
Reserved INTC_Interrupt Reserved Internal Interrupts
31 C_INTC_EXT_INTR+16 C_INTC_EXT_INTR+15 16 15 11 10 0
Table 2-21: Interrupt Pending Register Bit Definitions
Bit(s) Name
31:[C_INTC_EXT_INTR+16] - R 0
[C_INTC_EXT_INTR+15]:16 INTC_Interrupt R 0
15 - R 0
14 GPI4 R 0
13 GPI3 R 0
12 GPI2 R 0
11 GPI1 R 0
10 FIT4 R 0
9FIT3R0
8FIT2R0
7FIT1R0
6PIT4R0
5PIT3R0
Core
Access
Reset
Valu e
Description
Reserved
I/O Module external interrupt input signal
INTC_Interrupt [C_INTC_EXT_INTR-1:0]
mapped to corresponding bit positions in
IRQ_STATUS
Reserved
GPI4 changed
GPI3 changed
GPI2 changed
GPI1 changed
FIT4 strobe
FIT3 strobe
FIT2 strobe
FIT1 strobe
PIT4 lapsed
PIT3 lapsed
4PIT2R0
3PIT1R0
2UART_RXR0
1 UART_TX R 0
0UART_ERRR0
PIT2 lapsed
PIT1 lapsed
UART Received Data
UART Transmitted Data
UART Error
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PG052 October 16, 2012 Product Specification