Xilinx LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 User Manual

LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

User Guide

UG155 March 24, 2008

Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification.

THE SPECIFICATION IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRDPARTY RIGHTS.

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The Specification is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Specification in such High-Risk Applications is fully at your risk.

© 2004-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Revision History

The following table shows the revision history for this document.

Date

09/30/04 1.0 Initial Xilinx release.

04/28/05 2.0 Updated to Xilinx tools 7.1i SP2, support for Virtex-4 Rocket IO.

01/18/06 3.0 Updated to Xilinx tools 8.1i SP1 for 7.0 release, added new chapter for dynamic switching.

07/13/06 4.0 Updated to core version 7.1; Xilinx tools 8.2i.

10/23/06 5.0 Updated to core version 8.0, support for Virtex-5 LXT and Spartan-3A families.

02/15/07 6.0 Updated to core version 8.1, Xilinx tools 9.1i.

08/08/07 7.0 Updated to core version 9.0, Xilinx tools 9.2i.

03/24/08 8.0 Updated to core version 9.1, Xilinx tools 10.1.

Doc

Version

Revision

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Table of Contents

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Preface: About This Guide

Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 1: Introduction

About the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Designs Using RocketIO Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Recommended Design Experience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Related Xilinx Ethernet Products and Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Ethernet 1000BASE-X PCS/PMA or SGMII Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 2: Core Architecture

System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver . . . . . . . 23

Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface . . . . . . . . . . . . . . . 25

Core Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Client Side Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Physical Side Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Chapter 3: Generating and Customizing the Core

GUI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Component Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Select Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Core Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SGMII/Dynamic Standard Switching Elastic Buffer Options. . . . . . . . . . . . . . . . . . . . 41

RocketIO Tile Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Parameter Values in the XCO File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Output Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 4: Designing with the Core

Design Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Generate the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Examine the Example Design Provided with the Core . . . . . . . . . . . . . . . . . . . . . . . . . 50

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com

UG155 March 24, 2008

Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core

in Your Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 5: Using the Client-side GMII Data Path

Designing with the Client-side GMII for the 1000BASE-X Standard. . . . . . . . . . . . 53

GMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

GMII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

status_vector[4:0] signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Using the Virtex-II Pro RocketIO Transceiver CRC Functionality . . . . . . . . . . . . . . . . 57

Designing with Client-side GMII for the SGMII Standard. . . . . . . . . . . . . . . . . . . . . . 59

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

GMII Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

GMII Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Using the GMII as an Internal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Implementing External GMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

GMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 6: The Ten-Bit Interface

Ten-Bit-Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Receiver Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Clock Sharing across Multiple Cores with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 7: 1000BASE-X with RocketIO Transceivers

RocketIO Transceiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Clock Sharing Across Multiple Cores with RocketIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO

Transceivers

Receiver Elastic Buffer Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Selecting the Buffer Implementation from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

The Requirement for the FPGA Fabric Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . 96

The RocketIO Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

RocketIO Logic using the RocketIO Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

RocketIO Logic with the Fabric Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Virtex-4 Devices for SGMII or Dynamic Standards Switching . . . . . . . . . . . . . . . . . . 101

Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching . . . . . . . 103

Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching . . . . . . . . . . . . . . 105

Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer . . . . . . . . . 107

Virtex-II Pro Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Virtex-4 FX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Virtex-5 LXT and SXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Virtex-5 FXT Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Chapter 9: Configuration and Status

MDIO Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

MDIO Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

MDIO Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

MDIO Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Connecting the MDIO to an Internally Integrated STA . . . . . . . . . . . . . . . . . . . . . . . . 118

Connecting the MDIO to an External STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

1000BASE-X Standard Using the Optional Auto-Negotiation . . . . . . . . . . . . . . . . . . 119

1000BASE-X Standard Without the Optional Auto-Negotiation . . . . . . . . . . . . . . . . 129

SGMII Standard Using the Optional Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . 135

SGMII Standard without the Optional Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . 145

Both 1000BASE-X and SGMII Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Optional Configuration Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Chapter 10: Auto-Negotiation

Overview of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

1000BASE-X Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Setting the Configurable Link Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

1000BASE-X Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Simulating Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Using the Auto-Negotiation Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards

Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Operation of the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Selecting the Power-On / Reset Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Switching the Standard Using MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Auto-Negotiation State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Setting the Auto-Negotiation Link Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Chapter 12: Constraining the Core

Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Device, Package, and Speedgrade Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

I/O Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Placement Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . 161

Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Virtex-4 RocketIO MGTs for 1000BASE-X Constraints . . . . . . . . . . . . . . . . . . . . . . . . 164

Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints 166

Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . 166

Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints . . . . . . . . . . . . . . 167

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com

UG155 March 24, 2008

Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards

Switching Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Ten-Bit Interface Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Constraints When Implementing an External GMII. . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Understanding Timing Reports for Setup/Hold Timing . . . . . . . . . . . . . . . . . . . . . . 176

Chapter 13: Interfacing to Other Cores

Integrating with the 1-Gigabit Ethernet MAC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI . . . . . . . . 179

Integration of the 1-Gigabit Ethernet MAC Using a RocketIO Transceiver . . . . . . . 181

Integration of the 1-Gigabit Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Integrating with the Tri-Mode Ethernet MAC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Integration of the Tri-Mode Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality with TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

Integration of the Tri-Mode Ethernet MAC to Provide SGMII

(or Dynamic Switching) Functionality using RocketIO Transceivers . . . . . . . . . . 188

Chapter 14: Special Design Considerations

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Startup Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Core with the TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Core with RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Chapter 15: Implementing the Design

Pre-implementation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Using the Simulation Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XST - VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XST - Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Generating the Xilinx Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Mapping the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Placing and Routing the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Generating a Bitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Post-Implementation Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Generating a Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Using the Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Other Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Appendix A: Core Verification, Compliance, and Interoperability

Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Hardware Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

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Appendix B: Core Latency

Core Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Latency for 1000BASE-X PCS with TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver . . . . . . . . . . 208

Latency for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Appendix C: Calculating the DCM Fixed Phase Shift Value

Requirement for DCM Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Finding the Ideal Phase Shift Value for Your System . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Appendix D: 1000BASE-X State Machines

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Start of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

The Even Transmission Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Reception of the Even Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

The Odd Transmission Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Reception of the Odd Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

Preamble Shrinkage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

End of Frame Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

The Even Transmission case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Reception of the Even Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

The Odd Transmission Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Reception of the Odd Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Appendix E: Rx Elastic Buffer Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Rx Elastic Buffers: Depths and Maximum Frame Sizes . . . . . . . . . . . . . . . . . . . . . . . . . 219

RocketIO Rx Elastic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

SGMII Fabric Rx Elastic Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

TBI Rx Elastic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Maximum Frame Sizes for Sustained Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . 226

Jumbo Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Appendix F: Debugging Guide

General Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Problems with the MDIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Problems with Data Reception or Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Problems with Auto-Negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Problems in Obtaining a Link (Auto-Negotiation Disabled) . . . . . . . . . . . . . . . . . . . 228

Problems with a High Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Symptoms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

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Schedule of Figures

Chapter 2: Core Architecture

Figure 2-1: Functional Block Diagram Using RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2-2: Functional Block Diagram with a Ten-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 2-3: Component Pinout Using RocketIO Transceiver

with PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 2-4: Component Pinout Using RocketIO Transceiver

without PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 2-5: Component Pinout Using the Ten-Bit Interface

with PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 2-6: Component Pinout Using Ten-Bit Interface

without PCS Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 2-7: Component Pinout with the Dynamic Switching Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 3: Generating and Customizing the Core

Figure 3-1: Core Customization Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 3-2: 1000BASE-X Standard Options Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 3-3: SGMII/Dynamic Standard Switching Options Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 3-4: RocketIO Tile Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 4: Designing with the Core

Figure 4-1: 1000BASE-X Standard Using a RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 4-2: Example Design 1000BASE-X Standard Using TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 4-3: Example Design Performing the SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 4-4: Example Design Performing the SGMII Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Chapter 5: Using the Client-side GMII Data Path

Figure 5-1: GMII Normal Frame Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 5-2: GMII Error Propagation Within a Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 5-3: GMII Normal Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 5-4: GMII Normal Frame Reception with Carrier Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 5-5: GMII Frame Reception with Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 5-6: False Carrier Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 5-7: status_vector[4:2] timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 5-8: GMII Frame Transmission with RocketIO Transceiver CRC Logic Enabled . . . . . . . . 58

Figure 5-9: GMII Frame Reception with the RocketIO Transceiver CRC Logic Enabled . . . . . . . . 58

Figure 5-10: GMII Frame Transmission at 1 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 5-11: GMII Data Transmission at 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 5-12: GMII Frame Reception at 1 Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 5-13: GMII Data Reception at 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 5-14: GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 5-15: External GMII Transmitter Logic for Spartan-3, Spartan-3E and

Spartan-3A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 5-16: External GMII Transmitter Logic for Virtex-4 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 5-17: External GMII Transmitter Logic for Virtex-5 Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 5-18: External GMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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Chapter 6: The Ten-Bit Interface

Figure 6-1: Ten-Bit Interface Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 6-2: Ten-Bit-Interface Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices. . . . . . . . . . . . . 72

Figure 6-4: Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design) . . . . . . . . . . . . . . 73

Figure 6-5: Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices . . . . . . . . . . . . . . . . . . . 74

Figure 6-6: Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design) . . . . . . . . . . . . . . 75

Figure 6-7: Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . . 76

Figure 6-8: Clock Management, Multiple Core Instances with Ten-Bit Interface. . . . . . . . . . . . . . . 77

Chapter 7: 1000BASE-X with RocketIO Transceivers

Figure 7-1: 1000BASE-X Connection to a Virtex-II Pro MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 7-3: 1000BASE-X Connection to Virtex-5 GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 7-4: 1000BASE-X Connection to Virtex-5 GTX Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 7-5: Clock Management: Two Core Instances, Virtex-II Pro

MGTs for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X . . . . . . . . . . . . . 89

Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX

Transceivers for 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO

Transceivers

Figure 8-1: SGMII Implementation using Separate Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 8-2: SGMII Implementation using Shared Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver. . . . . . . . . . . . . . . . . . . . . . 100

Figure 8-4: SGMII Connection to a Virtex-4 MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 8-5: SGMII Connection to a Virtex-5 RocketIO GTP Transceiver . . . . . . . . . . . . . . . . . . . . . 104

Figure 8-6: SGMII Connection to a Virtex-5 RocketIO GTX Transceiver . . . . . . . . . . . . . . . . . . . . . 106

Figure 8-7: Clock Management with Multiple Core Instances with Virtex-II Pro

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 8-8: Clock Management with Multiple Core Instances with Virtex-4 MGTs for SGMII . 110 Figure 8-9: Clock Management with Multiple Core Instances with Virtex-5 GTP

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 8-10: Clock Management with Multiple Core Instances with Virtex-5 GTX

RocketIO Transceivers for SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Chapter 9: Configuration and Status

Figure 9-1: A Typical MDIO-managed System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 9-2: MDIO Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 9-3: MDIO Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 9-4: Creating an External MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Figure 9-5: Dynamic Switching (Register 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Chapter 10: Auto-Negotiation

Figure 10-1: 1000BASE-X Auto-Negotiation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 10-2: SGMII Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

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Chapter 11: Dynamic Switching of 1000BASE-X and SGMII Standards

Figure 11-1: Typical Application for Dynamic Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Chapter 12: Constraining the Core

Figure 12-1: Local Clock Place and Route for Top MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 12-2: Input TBI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Figure 12-3: Input GMII timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 12-4: Timing Report Setup/Hold Illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

Chapter 13: Interfacing to Other Cores

Figure 13-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI . . . . . . . . 180

Figure 13-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-II Pro MGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Figure 13-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-4 MGT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 13-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-5 GTP Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 13-5: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA

Using a Virtex-5 GTX Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

Figure 13-6: Tri-Speed Ethernet MAC Extended to use an SGMII with TBI . . . . . . . . . . . . . . . . . . 187

Figure 13-7: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-II Pro . . . . . . . . . . . . 189

Figure 13-8: Tri-Speed Ethernet MAC Extended to Use an SGMII in Virtex-4 . . . . . . . . . . . . . . . . 191

Figure 13-9: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 LXT/SXT. . . . . . . . 193

Figure 13-10: Tri-Speed Ethernet MAC Extended to use an SGMII in Virtex-5 FXT . . . . . . . . . . . 195

Chapter 14: Special Design Considerations

Figure 14-1: Loopback Implementation Using the TBI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Figure 14-2: Loopback Implementation When Using the Core with RocketIO Transceivers . . . . 199

Appendix D: 1000BASE-X State Machines

Figure D-1: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 212

Figure D-2: 1000BASE-X Reception State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . 213

Figure D-3: 1000BASE-X Transmit State Machine Operation (Odd Case) . . . . . . . . . . . . . . . . . . . . 214

Figure D-4: 1000BASE-X Reception State Machine Operation (Odd Case). . . . . . . . . . . . . . . . . . . . 214

Figure D-5: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 215

Figure D-6: 1000BASE-X Reception State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . 216

Figure D-7: 1000BASE-X Transmit State Machine Operation (Even Case) . . . . . . . . . . . . . . . . . . . . 217

Figure D-8: 1000BASE-X Reception State Machine Operation (Odd Case). . . . . . . . . . . . . . . . . . . . 217

Appendix E: Rx Elastic Buffer Specifications

Figure E-1: Elastic Buffer Sizes for all RocketIO Transceiver Families . . . . . . . . . . . . . . . . . . . . . . . 220

Figure E-2: Elastic Buffer Size for all RocketIO families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure E-3: TBI Elastic Buffer Size for All Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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Schedule of Tables

Chapter 2: Core Architecture

Table 2-1: GMII Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 2-2: Other Common Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 2-3: Optional MDIO Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 2-4: Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 2-5: Optional Auto-Negotiation Interface Signal Pinout. . . . . . . . . . . . . . . . . . . . . . 35

Table 2-6: Optional Dynamic Standard Switching Signals . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 2-7: Optional RocketIO Transceiver Interface Pinout . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 2-8: Optional TBI Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Chapter 3: Generating and Customizing the Core

Table 3-1: XCO File Values and Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 4: Designing with the Core

Table 4-1: Degree of Difficulty for Various Implementations . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 9: Configuration and Status

Table 9-1: Abbreviations and Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 9-2: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . . 119

Table 9-3: Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 9-4: Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 9-5: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 9-6: Auto-Negotiation Advertisement Register (Register 4) . . . . . . . . . . . . . . . . . . 124

Table 9-7: Auto-Negotiation Link Partner Ability Base Register (Register 5) . . . . . . . . 125

Table 9-8: Auto-Negotiation Expansion Register (Register 6) . . . . . . . . . . . . . . . . . . . . . . 126

Table 9-9: Auto-Negotiation Next Page Transmit (Register 7). . . . . . . . . . . . . . . . . . . . . . 127

Table 9-10: Auto-Negotiation Next Page Receive (Register 8) . . . . . . . . . . . . . . . . . . . . . . 128

Table 9-11: Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Table 9-12: Vendor Specific Register: Auto-Negotiation Interrupt

Control Register (Register 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 9-13: MDIO Registers for 1000BASE-X without Auto-Negotiation. . . . . . . . . . . . 130

Table 9-14: Control Register (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 9-15: Status Register (Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Table 9-16: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 9-17: Extended Status (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 9-18: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . 135

Table 9-19: SGMII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 9-20: SGMII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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Table 9-21: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 9-22: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 139

Table 9-23: SGMII Auto-Negotiation Link Partner Ability Base (Register 5) . . . . . . . . 140

Table 9-24: SGMII Auto-Negotiation Expansion (Register 6) . . . . . . . . . . . . . . . . . . . . . . 141

Table 9-25: SGMII Auto-Negotiation Next Page Transmit (Register 7) . . . . . . . . . . . . . . 141

Table 9-26: SGMII Auto-Negotiation Next Page Receive (Register 8) . . . . . . . . . . . . . . . 142

Table 9-27: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 9-28: SGMII Auto-Negotiation Interrupt Control (Register 16). . . . . . . . . . . . . . . 144

Table 9-29: MDIO Registers for 1000BASE-X with Auto-Negotiation. . . . . . . . . . . . . . . 145

Table 9-30: SGMII Control (Register 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Table 9-31: SGMII Status (Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 9-32: PHY Identifier (Registers 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Table 9-33: SGMII Auto-Negotiation Advertisement (Register 4) . . . . . . . . . . . . . . . . . . 149

Table 9-34: SGMII Extended Status Register (Register 15) . . . . . . . . . . . . . . . . . . . . . . . . 150

Table 9-35: Vendor-specific Register: Standard Selection Register (Register 17) . . . . . 151

Table 9-36: Optional Configuration and Status Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 12: Constraining the Core

Table 12-1: Input TBI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

Table 12-2: Input GMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Appendix D: 1000BASE-X State Machines

Table D-1: Defined Ordered Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

Appendix E: Rx Elastic Buffer Specifications

Table E-1: Maximum Frame Sizes: RocketIO Transceiver Rx Elastic Buffers

(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Table E-2: Maximum Frame Sizes: Fabric Rx Elastic Buffers

(100ppm Clock Tolerance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

Table E-3: Maximum Frame Size: (Sustained Frame Reception)

Capabilities of the Rx Elastic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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About This Guide

The LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII User Guide provides information about generating a Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools.

Guide Contents

This guide contains the following information.

• Preface, “About This Guide” introduces the organization and purpose of this guide

and defines the conventions used in this document.

• Chapter 1, “Introduction” describes the core and related information, including

recommended design experience, additional documentation resources, technical support, and submitting feedback to Xilinx.

• Chapter 2, “Core Architecture” provides an overview of the core including all

interfaces and major functional blocks.

• Chapter 3, “Generating and Customizing the Core” describes the Graphical User

Interface (GUI) options used to generate and customize the core.

• Chapter 4, “Designing with the Core” provides general guidelines for creating

designs with the core.

• Chapter 5, “Using the Client-side GMII Data Path” provides general guidelines for

creating designs using client side GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core.

• Chapter 6, “The Ten-Bit Interface” provides general design guidelines when using the

Ten-Bit Interface (TBI) as the Physical Side of the core.

• Chapter 7, “1000BASE-X with RocketIO Transceivers” provides general design

guidelines when using the 1000BASE-X standard with the RocketIO™ transceiver as the physical side of the core.

• Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers” provides general design guidelines when using either the SGMII standard, or the Dynamic Switching option (between 1000BASE-X and SGMII standards). These options always use a RocketIO as the physical interface.

• Chapter 9, “Configuration and Status” provides general guidelines for configuring

and monitoring the core, including a detailed description of the management registers present in the core.

• Chapter 10, “Auto-Negotiation” provides guidelines for Auto-Negotiation function of

the core.

Preface

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Preface: About This Guide

• Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards” provides

general guidelines for using the core to perform dynamic standards switching between 1000BASE-X and SGMII.

• Chapter 12, “Constraining the Core” defines the constraint requirements of the core.

• Chapter 13, “Interfacing to Other Cores” describes additional design considerations

associated with implementing the core with the 1-Gigabit Ethernet MAC and TriMode Ethernet MAC cores.

• Chapter 14, “Special Design Considerations” describes additional design

considerations associated with implementing the core.

• Chapter 15, “Implementing the Design”describes how to simulate and implement

your design containing the core.

• Appendix A, “Core Verification, Compliance, and Interoperability” describes how the

core was verified.

• Appendix B, “Core Latency” defines the latency of the core.

• Appendix C, “Calculating the DCM Fixed Phase Shift Value” instructs the user about

how to calculate the system timing requirements when using DCMs with the core.

• Appendix D, “1000BASE-X State Machines” serves as a reference for the basic

operation of the 1000BASE-X IEEE 802.3 clause 36 transmitter and receiver state machines.

• Appendix E, “Rx Elastic Buffer Specifications” describes the depth of the Rx Elastic

Buffers which are available with the core. The size of the buffer is related to the maximum frame size which the core can accommodate.

• Appendix F, “Debugging Guide” provides information for debugging the core within

a system.

Conventions

Typographical

This document uses the following conventions. An example illustrates each convention.

The following typographical conventions are used in this document.

Convention Meaning or Use Example

Messages, prompts, and

Courier font

program files that the system

speed grade: - 100

displays

Courier bold

Literal commands you enter in a syntactical statement

ngdbuild

design_name

References to other manuals See the User Guide for details.

Italic font

Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Dark Shading

Items that are not supported or reserved

This feature is not supported

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Conventions

Convention Meaning or Use Example

An optional entry or

Square brackets [ ]

parameter. However, in bus specifications, such as

ngdbuild [

design_name

bus[7:0], they are required.

option_name

]

Braces { }

Vertical bar |

Vertical ellipsis

Horizontal ellipsis . . .

Notations

Online Document

The following conventions are used in this document.

A list of items from which you must choose one or more

Separates items in a list of choices

lowpwr ={on|off}

IOB #1: Name = QOUT’

. .

Repetitive material that has been omitted

The prefix ‘0x’ or the suffix ‘h’ indicate hexadecimal notation

A ‘_n’ means the signal is active low

IOB #2: Name = CLKIN’ . . .

allow block

block_name

loc1 loc2 ... locn;

A read of address

0x00112975 returned 45524943h.

usr_teof_n is active low.

Convention Meaning or Use Example

See the section “Additional

Resources” for details.

See “Title Formats” in

Blue text

Cross-reference link to a location in the current document

Chapter 1 for details.

Blue, underlined text

Hyperlink to a website (URL)

Go to w latest speed files.

ww.xilinx.com for the

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Preface: About This Guide

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Introduction

The Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully verified solution that supports Verilog HDL and VHDL. In addition, the example design provided with the core supports both Verilog and VHDL.

This chapter introduces the Ethernet 1000BASE-X PCS/PMA or SGMII core and provides related information, including recommended design experience, additional resources, technical support, and methods for submitting feedback to Xilinx.

About the Core

The Ethernet 1000BASE-X PCS/PMA or SGMII core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the Ethernet 100BASE-X PCS/PMA product page requirements and licensing options, see Chapter 2, “Licensing the Core,” in the Getting

Started Guide.

Chapter 1

. For information about system

Designs Using RocketIO Transceivers

RocketIO transceivers are defined by device family in the following way:

• For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)

• For Virtex-5 LXT and SXT devices, RocketIO GTP transceivers; Virtex-5 FXT devices,

RocketIO GTX transceivers

Recommended Design Experience

Although the Ethernet 1000BASE-X PCS/PMA or SGMII core is a fully-verified solution, the challenge associated with implementing a complete design varies depending on the configuration and functionality of the application. For best results, previous experience building high-performance, pipelined FPGA designs using Xilinx implementation software and User Constraint Files (UCF) is recommended.

Contact your local Xilinx representative for a closer review and estimation for your specific requirements.

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Additional Core Resources

For detailed information and updates about the Ethernet 1000BASE-X PCS/PMA or SGMII core, see the following documents, located on the Xilinx Ethernet 100BASE-X PCS/PMA product page

• Ethernet 1000BASE-X PCS/PMA or SGMII Data Sheet

• Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide

After generating the core, the following documents are available in the document directory:

• Ethernet 1000BASE-X PCS/PMA or SGMII Release Notes

• Ethernet 1000BASE-X PCS/PMA or SGMII User Guide

Related Xilinx Ethernet Products and Services

For information about all Xilinx Ethernet solutions, see

www.xilinx.com/products/design_resources/conn_central/protocols/gigabit_ethernet. htm.

Chapter 1: Introduction

Specifications

• IEEE 802.3

• Serial-GMII Specification (CISCO SYSTEMS, ENG-46158)

Technical Support

To obtain technical support specific to the Ethernet 1000BASE-X PCS/PMA or SGMII core, visit www.s using the Ethernet 1000BASE-X PCS/PMA or SGMII core.

Xilinx provides technical support for use of this product as described in the Ethernet

1000BASE-X PCS/PMA or SGMII User Guide and the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of

this product for designs that do not follow these guidelines.

Feedback

Xilinx welcomes comments and suggestions about the Ethernet 1000BASE-X PCS/PMA or SGMII core and the documentation supplied with the core.

Ethernet 1000BASE-X PCS/PMA or SGMII Core

For comments or suggestions about the core, please submit a WebCase from

www.s

upport.xilinx.com/. Questions are routed to a team of engineers with expertise

upport.xilinx.com/. Be sure to include the following information:

• Product name

• Core version number

• Explanation of your comments

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Feedback

Document

For comments or suggestions about this document, please submit a WebCase from

www.support.xilinx.com/

. Be sure to include the following information:

• Document title

• Document number

• Page number(s) to which your comments refer

• Explanation of your comments

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Chapter 1: Introduction

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Core Architecture

This chapter describes the architecture of the Ethernet 1000BASE-X PCS/PMA or SGMII core, including all interfaces and major functional blocks.

System Overview

Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver

The Ethernet 1000BASE-X PCS/PMA or SGMII core provides the functionality to implement the 1000BASE-X PCS and PMA sub-layers or used to provide a GMII to SGMII bridge when used with a RocketIO transceiver. RocketIO transceivers are defined in the following way:

Chapter 2

• For Virtex-II Pro and Virtex-4 devices, RocketIO Multi-Gigabit Transceivers (MGT)

• For Virtex-5 LXT and SXT FPGAs, RocketIO GTP transceivers; Virtex-5 FXT FPGA,

RocketIO GTX transceiver

The core interfaces to a RocketIO transceiver, providing some of the PCS layer functionality such as 8B/10B encoding/decoding, the PMA SERDES, and clock recovery.

Figure 2-1 illustrates the remaining PCS sublayer functionality, and also shows the major

functional blocks of the core.

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LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core

PCS Transmit Engine

Chapter 2: Core Architecture

GMII to MAC

MDIO Interface

GMII Block

Optional PCS Management

Optional

Auto-Negotiation

PCS Receive Engine

and Synchronization

RocketIO I/F Block

RocketIO Transeiver

Figure 2-1: Functional Block Diagram Using RocketIO Transceiver

GMII Block

A client-side GMII is provided with the core, which can be used as an internal interface for connection to an embedded Media Access Controller (MAC) or other custom logic. Alternatively, the GMII may be routed to device IOBs to provide an external (off chip) GMII.

PCS Transmit Engine

The PCS transmit engine converts the GMII data octets into a sequence of ordered sets by implementing the state diagrams of IEEE 802.3 (figures 36-5 and 36-6). See Appendix D,

“1000BASE-X State Machines.”

To PMD Sublaye

PCS Receive Engine and Synchronization

The synchronization process implements the state diagram of IEEE 802.3 (figure 36-9). The PCS receive engine converts the sequence of ordered sets to GMII data octets by implementing the state diagrams of IEEE 802.3 (figures 36-7a and 36-7b). See Appendix D,

“1000BASE-X State Machines.”

Optional Auto-Negotiation Block

IEEE 802.3 clause 37 describes the 1000BASE-X Auto-Negotiation function that allows a device to advertise the modes of operation that it supports to a device at the remote end of a link segment (link partner), and to detect corresponding operational modes that the link partner may be advertising.

Auto-Negotiation is controlled and monitored through the PCS Management Registers. See Chapter 10, “Auto-Negotiation.”

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System Overview

Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface

Optional PCS Management Registers

Configuration and status of the core, including access to and from the optional AutoNegotiation function, uses the 1000BASE-X PCS Management Registers defined in IEEE

802.3 clause 37. These registers are accessed through the serial Management Data

Input/Output Interface (MDIO), defined in IEEE 802.3 clause 22, as if it were an externally connected PHY.

The PCS Management Registers may be omitted from the core when the core is performing the 1000BASE-X standard. In this situation, configuration and status of the core is made possible with the use of an alternative configuration vector and a status signal.

When the core is performing the SGMII standard, the PCS Management Registers become mandatory and information in the registers takes on a different interpretation. For more information, see “Management Registers” in Chapter 9.

RocketIO Interface Block

The RocketIO Interface Block enables the core to connect to a Virtex-II Pro, Virtex-4, or Virtex-5 FPGA RocketIO transceiver.

The Ethernet 1000BASE-X PCS/PMA or SGMII core, when used with the Ten-Bit Interface (TBI), allows you to implement only the 1000BASE-X PCS sublayer.

LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII Core

8B/10B

Encoder

8B/10B

Decoder

Elastic

Buffer

TBI

IOBs

TBI Block

to PMA Sublayer

GMII to MAC

MDIO Interface

GMII Block

Optional PCS Management

PCS Transmit Engine

Optional

Atuo-negotiation

PCS Receive Engine and Synchronization

Figure 2-2: Functional Block Diagram with a Ten-Bit Interface

The optional TBI can be used in place of the RocketIO transceiver to provide a parallel interface for connection to an external PMA SERDES device. In this implementation, additional logic blocks are required to replace some of the RocketIO transceiver functionality. These are shown in the surrounded by the dotted line box in Figure 2-2 and are described in the following sections. The other blocks are described previously in this document.

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8B/10B Encoder

8B10B encoding, as defined in IEEE 802.3 (Tables 36-1a to 36-1e and Table 36-2), is implemented in a block SelectRAM™, configured as ROM, and used as a large look-up table.

8B/10B Decoder

8B10B decoding, as defined in IEEE 802.3 (Table 36-1a to 36-1e and Table 36-2), is implemented in a block SelectRAM, configured as ROM, and used as a large look-up table.

Receiver Elastic Buffer

The Receiver Elastic Buffer enables the 10-bit parallel TBI data, received from the PMA sublayer synchronously to the TBI receiver clocks, to be transferred onto the cores internal 125 MHz clock domain. It is an asynchronous FIFO implemented in internal RAM. The Receiver Elastic Buffer attempts to maintain a constant occupancy by inserting or removing Idle sequences as necessary. This causes no corruption to the frames of data.

TBI Block

The core provides a TBI interface that should be routed to device IOBs to provide an offchip TBI.

Chapter 2: Core Architecture

Core Interfaces

All ports of the core are internal connections in FPGA fabric. An HDL example design (delivered with the core) connects the core, where appropriate, to a RocketIO transceiver, and/or add IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII and TBI. IOBs are added to the remaining unconnected ports to take the example design through the Xilinx implementation software.

All clock management logic is placed in this example design, allowing you more flexibility in implementation (such as designs using multiple cores). This example design is provided in both VHDL and Verilog. For more information, see the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide.

Figure 2-3 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using

a RocketIO transceiver with the optional PCS Management Registers. The signals shown in the Auto-Negotiation box included only when the core includes the Auto-Negotiation

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Core Interfaces

functionality. For more information, see Chapter 3, “Generating and Customizing the

Core.”

GMII

MDIO

Auto_Negotiation

gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset

gtx_clk

an_interrupt

link_timer_value[8:0]

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2

dcm_locked rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0] rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata

enablealign

signal_detect

status_vector[4:0]

Figure 2-3: Component Pinout Using RocketIO Transceiver

with PCS Management Registers

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Chapter 2: Core Architecture

Figure 2-4 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using

a RocketIO transceiver without the optional PCS Management Registers

GMII

MDIO Replacement

configuration_vector[3:0]

gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

reset

gtx_clk

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2

dcm_locked rxbufstatus[1:0]

rxchariscomma rxcharisk

rxclkcorcnt[2:0] rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata

enablealign

signal_detect

status_vector[4:0]

Figure 2-4: Component Pinout Using RocketIO Transceiver

without PCS Management Registers

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Core Interfaces

Figure 2-5 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when

using the TBI with optional PCS Management Registers. The signals shown in the AutoNegotiation box are included only when the core includes the Auto-Negotiation functionality (see Chapter 3, “Generating and Customizing the Core”).

GMII

MDIO

Auto_Negotiation

gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset

gtx_clk

an_interrupt

link_timer_value[8:0]

Ten-Bit Interface (TBI)

tx_code_group[9:0]

loc_ref ewrap

en_cdet

rx_code_group0[9:0]

rx_code_group1[9:0] pma_rx_clk0 pma_rx_clk1

signal_detect

status_vector[4:0]

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Figure 2-5: Component Pinout Using the Ten-Bit Interface

with PCS Management Registers

Chapter 2: Core Architecture

Figure 2-6 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core when

using a TBI without the optional PCS Management Registers.

GMII

MDIO Replacement

configuration_vector[3:0]

gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

reset

gtx_clk

Ten-Bit Interface (TBI)

tx_code_group[9:0]

loc_ref ewrap

en_cdet

rx_code_group0[9:0] rx_code_group1[9:0]

pma_rx_clk0 pma_rx_clk1

signal_detect

status_vector[4:0]

Figure 2-6: Component Pinout Using Ten-Bit Interface

without PCS Management Registers

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Core Interfaces

Figure 2-7 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using

the optional dynamic switching logic (between 1000BASE-X and SGMII standards). This mode is shown used with a RocketIO transceiver interface. For more information, see

Chapter 11, “Dynamic Switching of 1000BASE-X and SGMII Standards.”

GMII

MDIO

Auto_Negotiation

gmii_txd[7:0] gmii_tx_en gmii_tx_er

gmii_rxd[7:0] gmii_rx_dv gmii_rx_er

gmii_isolate

mdc mdio_in mdio_out mdio_tri

phyad[4:0]

reset gtx_clk

an_interrupt

link_timer_basex[8:0]

link_timer_sgmii[8:0]

basex_or_sgmii

RocketIO Interface

mgt_rx_reset mgt_tx_reset

userclk userclk2

dcm_locked

rxbufstatus[1:0] rxchariscomma

rxcharisk rxclkcorcnt[2:0]

rxdata[7:0] rxdisperr rxnotintable

rxrundisp txbuferr

powerdown txchardispmode txchardispval txcharisk txdata

enablealign

signal_detect

status_vector[4:0]

Figure 2-7: Component Pinout with the Dynamic Switching Logic

Client Side Interface

GMII Pinout

Tab le 2- 1 describes the GMII-side interface signals of the core common to all

parameterizations of the core. These are typically attached to an Ethernet MAC, either offchip or internally integrated. The HDL example design delivered with the core connects these signals to IOBs to provide a place-and-route example.

For more information, see “Designing with the Client-side GMII for the 1000BASE-X

Standard” in Chapter 5.

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Chapter 2: Core Architecture

Table 2-1: GMII Interface Signal Pinout

Signal Direction Description

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

gmii_isolate

Input GMII Transmit data from MAC.

Input GMII Transmit control signal from MAC.

Output GMII Received data to MAC.

Output GMII Received control signal to MAC.

Output IOB Tri-state control for GMII Isolation. Only of use

when implementing an External GMII as illustrated by the example design HDL.

1. When the Transmitter Elastic Buffer is present these signals are synchronous to gmii_tx_clk. When the Transmitter Elastic Buffer is omitted, see Note 2.

2. These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; gtx_clk when the core is used with TBI.

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Core Interfaces

Common Signal Pinout

Tab le 2- 2 describes the remaining signals common to all parameterizations of the core.

Table 2-2: Other Common Signals

Signal Direction Description

reset Input Asynchronous reset for the entire core. Active High. Clock

domain is not applicable.

signal_detect Input Signal direct from PMD sublayer indicating the presence

of light detected at the optical receiver. If set to ’1,’ indicates that the optical receiver has detected light. If set to ’0,’ this indicates the absence of light.

If unused this signal should be set to ’1’to enable correct operation the core. Clock domain is not applicable.

status_vector[4:0]

Output Bit[0]: Link Status

Indicates the status of the link.

• When high, the link is valid: synchronization of the link has been obtained and Auto-Negotiation (if present and enabled) has successfully completed.

• When low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and enabled) has failed to complete.

• When auto-negotiation is enabled this signal is identical to Status Register Bit 1.2: Link Status.

• When auto-negotiation is disabled this signal is identical to status_vector Bit[1].

Bit[1]: Link Synchronization

Indicates the state of the synchronization state machine (IEEE802.3 figure 36-9) which is based on the reception of valid 8B10B code groups. This signal is similar to Bit[0] (Link Status), but is NOT qualified with Auto-Negotiation.

• When high, link synchronization has been obtained and in the synchronization state machine, sync_status = OK.

• When low, synchronization has failed.

Bit[2]: RUDI(/C/)

The core is receiving /C/ ordered sets (Auto-Negotiation Configuration sequences).

Bit[3]: RUDI(/I/)

The core is receiving /I/ ordered sets (Idles).

Bit[4]: RUDI(INVALID)

The core has received invalid data whilst receiving/C/ or /I/ ordered set. See “status_vector[4:0] signals” in

Chapter 5 for more information.

1. These signals are synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

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MDIO Management Interface Pinout (Optional)

Tab le 2- 3 describes the optional MDIO interface signals of the core used to access the PCS

Management Registers. These signals are typically connected to the MDIO port of a MAC device, either off-chip or to an internally integrated MAC core. For more information, see

“Management Registers” in Chapter 9.

Table 2-3: Optional MDIO Interface Signal Pinout

Chapter 2: Core Architecture

Signal Direction

Clock

Domain

Description

mdc Input N/A Management clock (<= 2.5 MHz).

mdio__in

Input mdc Input data signal for communication with

MDIO controller (for example, an Ethernet MAC). Tie high if unused.

mdio_out

Output mdc Output data signal for communication with

MDIO controller (for example, an Ethernet MAC).

mdio_tri

Output mdc Tri-state control for MDIO signals; ‘0’ signals

that the value on mdio_out should be asserted onto the MDIO interface.

phyad[4:0] Input N/A Physical Address of the PCS Management

1. These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for connection to an external MDIO controller (for example, an Ethernet MAC).

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Core Interfaces

Configuration Vector (Optional)

Tab le 2- 4 shows the alternative to the optional MDIO Management Interface, the

configuration vector. See “Optional Configuration Vector” in Chapter 9.

Table 2-4: Optional Configuration and Status Vectors

Signal Direction Description

configuration_vector[3:0]

Input Bit[0]: Reserved (currently unused)

Bit[1]: Loopback Control

• When the core with RocketIO transceiver is used, the core is placed in internal loopback mode.

• With the TBI version, Bit 1 is connected to ewrap. When set to ‘1,’ this indicates to the external PMA module to enter loopback mode.

Bit[2]: Power Down

• When the RocketIO transceiver is used (when set to ‘1’), the MGT is placed in a low power state. A reset must be applied to clear.

• With the TBI version this bit is unused.

Bit[3]: Isolate

When set to ‘1,’ the GMII should be electrically isolated. When set to ‘0,’ normal operation is enabled.

1. This signal is synchronous to the core’s internal 125 MHz reference clock. This is userclk2 when the core is used with the RocketIO transceiver; this is gtx_clk when the core is used with TBI.

Auto-Negotiation Signal Pinout

Tab le 2- 5 describes the signals present when the optional Auto-Negotiation functionality is

present. For more information, see Chapter 10, “Auto-Negotiation.”

Table 2-5: Optional Auto-Negotiation Interface Signal Pinout

Signal Direction Description

link_timer_value[8:0]

an_interrupt

Input Used to configure the duration of the Auto-

Negotiation Link Timer period. The duration of this timer is set to the binary number input into this port multiplied by 4096 clock periods of the 125 MHz reference clock (8 ns). It is expected that this signal will be tied off to a logical value.

This port is replaced when using the dynamic switching mode.

Output Active high interrupt to signal the completion of an

Auto-Negotiation cycle. This interrupt can be enabled/disabled and cleared by writing to the appropriate PCS Management Register.

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Dynamic Switching Signal Pinout

Tab le 2- 6 describes the signals present when the optional Dynamic Switching mode

(between 1000BASE-X and SGMII standards) is selected. In this case, the MDIO (Tabl e 2 -3) and RocketIO transceiver (Tabl e 2 -7) interfaces are always present.

Table 2-6: Optional Dynamic Standard Switching Signals

Signal Direction Description

link_timer_basex[8:0]

link_timer_sgmii[8:0]

basex_or_sgmii

Chapter 2: Core Architecture

Input Used to configure the duration of the Auto-

Negotiation Link Timer period when performing the 1000BASE-X standard. The duration of this timer is set to the binary number input into this port multiplied by 4096 clock periods of the 125 MHz reference clock (8 ns). It is expected that this signal will be tied off to a logical value.

Input Used to configure the duration of the Auto-

Negotiation Link Timer period when performing the SGMII standard. The duration of this timer is set to the binary number input into this port multiplied by 4096 clock periods of the 125 MHz reference clock (8 ns). It is expected that this signal will be tied off to a logical value.

Input Used as the reset default to select the standard. It is

expected that this signal will be tied off to a logical value.

‘0’ signals that the core will come out of reset operating as 1000BASE-X.

‘1’ signals that the core will come out of reset operating as SGMII.

Note: The standard can be set following reset through the MDIO Management.

1. Clock domain is userclk2.

Physical Side Interface

1000BASE-X PCS with PMA Using RocketIO Transceiver Signal Pinout (Optional)

Tab le 2- 7 describes the optional interface to the RocketIO transceiver. The core is connected

to a RocketIO transceiver in the appropriate HDL example design delivered with the core. For more information, see:

• Chapter 7, “1000BASE-X with RocketIO Transceivers”

• Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers”

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Core Interfaces

Table 2-7: Optional RocketIO Transceiver Interface Pinout

Signal Direction Description

mgt_rx_reset

Output Reset signal issued by the core to the RocketIO

transceiver receiver path. Connect to RXRESET signal of RocketIO transceiver.

mgt_tx_reset

Output Reset signal issued by the core to the RocketIO

transceiver transmitter path. Connect to TXRESET signal of RocketIO transceiver.

userclk Input Also connected to TXUSRCLK and RXUSRCLK of the

RocketIO transceiver. Clock domain is not applicable.

userclk2 Input Also connected to TXUSRCLK2 and RXUSRCLK2 of

the RocketIO transceiver. Clock domain is not applicable.

dcm_locked Input A DCM may be used to derive userclk and userclk2.

This is implemented in the HDL design example delivered with the core. The core will use this input to hold the RocketIO transceiver in reset until the DCM obtains lock. Clock domain is not applicable.

rxbufstatus[1:0]

rxchariscomma

rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0]

rxdisperr

rxnotintable

rxrundisp

txbuferr

powerdown

txchardispmode

txchardispval

txcharisk

txdata[7:0]

enablealign

Input Connect to RocketIO signal of the same name.

Input Connects to RocketIO signal of the same name.

Input Connect to RocketIO signal of the same name.

Input Connects to RocketIO signal of the same name.

Output Connects to RocketIO signal of the same name.

Output Connect to RocketIO signal of the same name.

Output Allows the transceivers to serially realign to a comma

character. Connects to ENMCOMMAALIGN and ENPCOMMAALIGN of the RocketIO.

1. When the core is used with a RocketIO transceiver, userclk2 is used as the 125 MHz reference clock for the entire core.

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1000BASE-X PCS with TBI Pinout

Tab le 2- 8 describes the optional TBI signals, used as an alternative to the RocketIO receiver

interface. The appropriate HDL example design delivered with the core connects these signals to IOBs to provide an external TBI suitable for connection to an off-chip PMA SERDES device. When the core is used with the TBI, gtx_clk is used as the 125 MHz reference clock for the entire core. For more information, see Chapter 6, “The Ten-Bit

Interface.”

Table 2-8: Optional TBI Interface Signal Pinout

Signal Direction Clock Domain Description

gtx_clk Input N/A Clock signal at 125 MHz. Tolerance

tx_code_group[9:0] Output gtx_clk 10-bit parallel transmit data to PMA

loc_ref Output N/A Causes the PMA sublayer clock

Chapter 2: Core Architecture

must be within IEEE 802.3 specification.

Sublayer (SERDES).

recovery unit to lock to pma_tx_clk. This signal is currently tied to Ground.

ewrap Output gtx_clk When ’1,’ this indicates to the external

PMA SERDES device to enter loopback mode. When ’0,’ this indicates normal operation

rx_code_group0[9:0] Input pma_rx_clk0 10-bit parallel received data from PMA

Sublayer (SERDES). This is synchronous to pma_rx_clk0.

rx_code_group1[9:0] Input pma_rx_clk1 10-bit parallel received data from PMA

Sublayer (SERDES). This is synchronous to pma_rx_clk1.

pma_rx_clk0 Input N/A Received clock signal from PMA

Sublayer (SERDES) at 62.5 MHz.

pma_rx_clk1 Input N/A Received clock signal from PMA

Sublayer (SERDES) at 62.5 MHz. This is 180 degrees out of phase with pma_rx_clk0.

en_cdet Output gtx_clk Enables the PMA Sublayer to perform

comma realignment. This is driven from the PCS Receive Engine during the Loss-Of-Sync state.

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Chapter 3

Generating and Customizing the Core

The Ethernet 1000BASE-X PCS/PMA or SGMII core is generated using the CORE Generator. This chapter describes the GUI options used to generate and customize the core.

GUI Interface

Figure 3-1 displays the Ethernet 1000BASE-X PCS/PMA or SGMII customization screen,

used to set core parameters and options. For help starting and using CORE Generator on your system, see the documentation included with ISE™, including the CORE Generator Guide, at www.xilinx.com/support/software_manuals.htm

Component Name

The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and “_.”

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Figure 3-1: Core Customization Screen

Select Standard

Select from the following standards for the core:

• 1000BASE-X. 1000BASE-X Physical Coding Sublayer (PCS) functionality is designed

to the IEEE 802.3 specification. Depending on the choice of physical interface, the functionality may be extended to include the 1000BASE-X Physical Medium Attachment (PMA) sublayer. Default setting.

• SGMII. Provides the functionality to provide a Gigabit Media Independent Interface

(GMII) to Serial-GMII (SGMII) bridge, as defined in the Serial-GMII Specification (Cisco Systems, ENG-46158). SGMII may be used to replace GMII at a much lower pin count and for this reason often favored by PCB designers.

• Both (a combination of 1000BASE-X and SGMII). Combining the 1000BASE-X and

SGMII standards lets you dynamically configure the core to switch between 1000BASE-X and SGMII standards. The core can be switched by writing through the MDIO Management Interface. For more information, see Chapter 9, “Configuration

and Status.”

Core Functionality

Figure 3-2 displays the Ethernet 1000BASE-X PCS/PMA or SGMII functionality screen.

Chapter 3: Generating and Customizing the Core

40 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

Figure 3-2: 1000BASE-X Standard Options Screen

UG155 March 24, 2008

GUI Interface

Physical Interface

Depending on the target architecture, two physical interface options are available for the core.

• RocketIO. Uses a RocketIO transceiver specific to the selected device family to extend

the 1000BASE-X functionality to include both PCS and PMA sub-layers. For this reason, it is available only for Virtex-II Pro, Virtex-4 FX, Virtex-5 LXT, Virtex-5 SXT, and Virtex-5 FXT devices. For additional information, see “RocketIO Transceiver

Logic” in Chapter 7.

• Ten Bit Interface (TBI). Available in all supported families and provides 1000BASE-X

or SGMII functionality with a parallel TBI used to interface to an external SERDES. For more information, see “Ten-Bit-Interface Logic” in Chapter 6. Default setting.

MDIO Management Interface

Select this option to include the MDIO Management Interface to access the PCS Configuration Registers. See “MDIO Management Interface” in Chapter 9.

If this option is not selected, the core is generated with a replacement configuration vector. See “Optional Configuration Vector” in Chapter 9. The Management Interface is selected by default.

Auto-Negotiation

Select this option to include Auto-Negotiation functionality with the core, available only if the core includes the optional Management Interface. For more information, see Chapter

10, “Auto-Negotiation.” The default is to include Auto-Negotiation.

RocketIO Transceiver CRC Logic

This option is visible in the GUI only when a Virtex-II Pro device family is selected, and then only when the RocketIO Interface is selected with the 1000BASE-X standard.

Select this option to use the built-in CRC functionality of the Virtex-II Pro RocketIO transceiver. See Chapter 5, “Using the Virtex-II Pro RocketIO Transceiver CRC

Functionality.” This option is disabled (not displayed) by default.

SGMII/Dynamic Standard Switching Elastic Buffer Options

The SGMII/Dynamic Standard Switching Options screen, used to customize the Ethernet 1000BASE-X PCS/PMA or SGMII core, is only displayed if either SGMII or Both is selected in the Select Standard section of the initial customization screen, and only if RocketIO is selected as the Physical Standard.

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Chapter 3: Generating and Customizing the Core

Figure 3-3: SGMII/Dynamic Standard Switching Options Screen

This screen lets you select the Receiver Elastic Buffer type to be used with the core. Before selecting this option, see “Receiver Elastic Buffer Implementations” in Chapter 8.

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Parameter Values in the XCO File

RocketIO Tile Configuration

The RocketIO Tile Configuration screen is only displayed if the RocketIO interface is used with the Virtex-4 or Virtex-5 device families.

Figure 3-4: RocketIO Tile Configuration Screen

RocketIO transceivers for Virtex-4 FX and Virtex-5 device families are available in tiles, each tile consisting of a pair of transceivers. The RocketIO Tile Selection has no effect on the functionality of the core netlist, but determines the functionality of the example design delivered with the core.

Depending on the option selected, the example design instantiates a single core netlist and does one of the following:

• MGT A (0). Connects to RocketIO transceiver A

• MGT B (1). Connects to RocketIO transceiver B

• Both MGTs. Two instantiations of the core are created in the example design and

connected to both RocketIO transceiver A and B.

Parameter Values in the XCO File

XCO file parameters are used to run the CORE Generator from the command line. XCO file parameter names and their values are similar to the names and values shown in the GUI, except that underscore characters (_) may be used instead of spaces. The text in an XCO file is not case sensitive.

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Chapter 3: Generating and Customizing the Core

Tab le 3- 1 describes the XCO file parameters, values and summarizes the GUI defaults. The

following is an example of the CSET parameters in an XCO file:

CSET component_name=gig_eth_pcs_pma_v9_1 CSET standard=1000BASEX CSET physical_interface=TBI CSET management_interface=true CSET auto_negotiation=true CSET mgt_crc_enabled=false CSET sgmii_mode=10_100_1000 CSET rocketio_tile=A

Table 3-1: XCO File Values and Default Values

Parameter XCO File Values

component_name ASCII text starting with a letter and based upon

the following character set: a..z, 0..9 and _

standard One of the following keywords: 1000BASEX,

Default GUI

Setting

gig_eth_pcs

_pma_v9_1

1000BASEX

SGMII, Both

physical_interface One of the following keywords: TBI, RocketIO TBI

management_interface One of the following keywords: true, false true

auto_negotiation One of the following keywords: true, false true

mgt_crc_enabled One of the following keywords: true, false false

sgmii_mode One of the following keywords: 10_100_1000,

10_100_1000

100_1000

• 10_100_1000 corresponds to “10/100/1000 Mbps (clock tolerance compliant with Ethernet specification)“

• 100_1000 corresponds to “10/100/1000 Mbps (restricted tolerance for clocks) OR 100/1000 Mbps“

rocketio_tile One of the following keywords: A, B, Both A

Output Generation

The files output by the CORE Generator are placed in the CORE Generator project directory and include the following:

• The netlist file for the core

• Supporting CORE Generator files

• Release notes and documentation

• Subdirectories containing an HDL example design

• Scripts to run the core through the back-end tools and simulate the core using either

Mentor Graphics® ModelSim®, Cadence® IUS, and Synopsys® simulators

See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for a complete description of the CORE Generator output files, simulation requirements, and detailed information about the HDL example design.

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Designing with the Core

This chapter provides information about creating your own designs using the Ethernet 1000BASE-X PCS/PMA or SGMII core. Design guidelines, as well as the variety of implementations presented, are based on the example design delivered with the core. See the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for information about the example design delivered with the core.

Note that not all implementations require all of the design steps defined in this chapter. Carefully follow the provided logic design guidelines to ensure success.

Design Overview

Chapter 4

An HDL example design built around the core is provided through the CORE Generator and allows for a demonstration of core functionality using either a simulation package or in hardware if placed on a suitable board. Four implementations of the core, based on the provided example design, are illustrated in the following sections.

• “1000BASE-X Standard Using RocketIO Transceiver Example Design”

• “1000BASE-X Standard with TBI Example Design”

• “SGMII Standard Using a RocketIO Transceiver Example Design”

• “SGMII Standard with TBI Transceiver Example Design”

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Chapter 4: Designing with the Core

1000BASE-X Standard Using RocketIO Transceiver Example Design

Figure 4-1 illustrates the example design in 1000BASE-X mode using the Virtex-II Pro or

Virtex-4 MGT, Virtex-5 GTP or Virtex-5 GTX transceiver. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into your design and performs the following functions:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to a RocketIO transceiver

The top level of the example design creates a specific example that can be simulated, synthesized, implemented, and if required, placed on a suitable board and demonstrated in hardware. The top level of the example design performs the following functions:

• Instantiates the block level from HDL

• Derives the clock management logic for RocketIO and the core

• Implements an external GMII

component_name_example_design

component_name_block

GMII

Transceiver

Connect to Client MA

Clock

Logic

Elastic

Buffer

Ethernet

1000BASE-X

PCS/PMA

Core

RocketIO

Transceiver

(Connect to

Optical

ansceiver)

IOBs

Out

Management

Figure 4-1: 1000BASE-X Standard Using a RocketIO Transceiver

PMA

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Design Overview

1000BASE-X Standard with TBI Example Design

Figure 4-2 illustrates the example design in 1000BASE-X mode using a TBI. As illustrated,

the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to device IOBs, creating an external

TBI. See Chapter 6, “The Ten-Bit Interface.”

• Instantiates the block level from HDL

• Derives the clock management logic for the core

• Implements an external GMII

component_name_example_design

component_name_block

GMII

TBI

Connect to

Client MAC

Clock

Logic

Elastic

Buffer

Ethernet

1000BASE-X

PCS/PMA

Core

IOBs

Out

(Connect to

SERDES)

IOBs

(DDR)

IOBs

Out

Management

Figure 4-2: Example Design 1000BASE-X Standard Using TBI

TBI

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Chapter 4: Designing with the Core

SGMII Standard Using a RocketIO Transceiver Example Design

Figure 4-3 illustrates the example design in SGMII mode using the Virtex-II Pro or Virtex-

4 MGT, Virtex-5 GTP or Virtex-5 GTX transceiver. This is also the example design created when the Dynamic Switching capability between SGMII and 1000BASE-X standards is present. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to a RocketIO transceiver

• Connects the client side GMII of the core to an SGMII Adaptation Module, which

provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps

The top level of the example design creates a specific example which can be simulated, synthesized and implemented. The top level of the example design performs the following functions:

• Instantiates the block level from HDL

• Derives the clock management logic for RocketIO and the core

• Implements an external GMII-style interface

GMII-style

8-bit I/F

component_name_example_design

component_name_block

GMII

IOBs

SGMII

Adaptation

Module

IOBs

Out

Clock

Management

Logic

1000BASE-X

Ethernet

PCS/PMA

Core

Transceiver

Fabric

Elastic

Buffer

RocketIO

Serial GMII

(SGMII)

48 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

Figure 4-3: Example Design Performing the SGMII Standard

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Design Overview

SGMII Standard with TBI Transceiver Example Design

Figure 4-3 illustrates the example design with the SGMII standard using a TBI. This is also

the example design created when the Dynamic Switching capability between SGMII and 1000BASE-X standards is present. As illustrated, the example is split between two hierarchical layers. The block level is designed so that it can be instantiated directly into customer designs and performs the following functions:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to device IOBs, creating an external

TBI. See Chapter 6, “The Ten-Bit Interface.”

• Connects the client side GMII of the core to an SGMII Adaptation Module, which provides the functionality to operate at speeds of 1 Gbps, 100 Mbps and 10 Mbps

The top level of the example design creates a specific example which can be simulated, synthesized and implemented. The top level of the example design performs the following functions:

• Instantiates the block level from HDL

• Derives the clock management logic for the core

• Implements an external GMII-style interface

GMII-style

8-bit I/F

component_name_example_design

component_name_block

GMII

IOBs

SGMII

Adaptation

Module

IOBs

Out

Clock

Management

Logic

1000BASE-X

Ethernet

PCS/PMA

Core

TBI

IOBs

Out

TBI

(Connect to

SERDES)

IOBs

(DDR)

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Figure 4-4: Example Design Performing the SGMII Standard

Design Guidelines

Generate the Core

Generate the core using the CORE Generator, as described in Chapter 3, “Generating and

Customizing the Core.”

Examine the Example Design Provided with the Core

Before implementing the core in your application, examine the example design provided with the core to identify the steps that can be performed:

• Edit the HDL top level of the example design file to change the clocking scheme, add or remove IOBs as required, and replace the GMII IOB logic with user-specific application logic (for example, an Ethernet MAC).

• Synthesize the entire design. The Xilinx Synthesis Tool (XST) script and Project file in the /implement/vhdl (or

/implement/verilog) directory may be adapted to include any added user’s HDL files.

Chapter 4: Designing with the Core

• Run the implement script in the /implement directory to create a top-level netlist for the design.

The script may also run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. SimPrim-based simulation models for the entire design are also produced by the implement scripts.

• Simulate the entire design using the demonstration test bench provided in /test/vhdl (or /test/verilog) as a template.

• Download the bitstream to a target device.

Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application

Before implementing your application, examine the example design delivered with the core for information about the following:

• Instantiating the core from HDL

• Connecting the physical-side interface of the core (RocketIO transceiver or TBI)

• Deriving the clock management logic

It is expected that the block level module from the example design will be instantiated directly into customer designs rather than the core netlist itself. The block level contains the core and a completed physical interface.

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Design Guidelines

Write an HDL Application

After reviewing the example design delivered with the core, write an HDL application that uses single or multiple instances of the block level module for the Ethernet 1000BASE-X PCS/PMA or SGMII core. Client-side interfaces and operation of the core are described in

Chapter 5, “Using the Client-side GMII Data Path.” See the following information for

additional details:

• Using the Ethernet 1000BASE-X PCS/PMA or SGMII core in conjunction with the 1-Gigabit Ethernet MAC core in “Integrating with the 1-Gigabit Ethernet MAC Core,”

page 179.

• Using the Ethernet 1000BASE-X PCS/PMA or SGMII core in conjunction with the TriMode Ethernet MAC core in “Integrating with the Tri-Mode Ethernet MAC Core,”

page 185.

Synthesize your Design

Synthesize your entire design using the desired synthesis tool. The Ethernet 1000BASE-X PCS/PMA or SGMII core is pre-synthesized and delivered as an NGC netlist—for this reason, it appears as a black box to synthesis tools.

Create a Bitstream

Run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. The UCF produced by the CORE Generator should be used as the basis for the user UCF and care must be taken to constrain the design correctly. See Chapter 12,

“Constraining the Core” for more information.

Simulate and Download your Design

After creating a bitstream that can be downloaded to a Xilinx device, simulate the entire design and download it to the desired device.

Know the Degree of Difficulty

An Ethernet 1000BASE-X PCS/PMA or SGMII core is challenging to implement in any technology and as such, all Ethernet 1000BASE-X PCS/PMA or SGMII core applications require careful attention to system performance requirements. Pipelining, logic mapping, placement constraints, and logic duplication are all methods that help boost system performance.

Review Tab le 4- 1 to determine the relative level of difficulty associated with different designs. This relates to meeting the core’s required system clock frequency of 125 MHz.

Table 4-1: Degree of Difficulty for Various Implementations

Device Family Difficulty

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Virtex-II Easy

Virtex-II Pro Easy

Virtex-4 Easy

Virtex-5 Easy

Spartan™-3 Difficult

Table 4-1: Degree of Difficulty for Various Implementations

Device Family Difficulty

Spartan-3E Difficult

Spartan-3A Difficult

Keep it Registered

To simplify timing and to increase system performance in an FPGA design, keep all inputs and outputs registered between the user application and the core. All inputs and outputs from the user application should come from, or connect to, a flip-flop. While registering signals may not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place and route the design.

Recognize Timing Critical Signals

The UCF provided with the example design for the core identifies the critical signals and the timing constraints that should be applied. See Chapter 12, “Constraining the Core”for more information.

Chapter 4: Designing with the Core

Use Supported Design Flows

The core is pre-synthesized and is delivered as an NGC netlist. The example implementation scripts provided currently uses ISE 10.1 as the synthesis tool for the HDL example design delivered with the core. Other synthesis tools may be used for the user application logic. The core will always be unknown to the synthesis tool and should appear as a black box. Post synthesis, only ISE 10.1i tools are supported.

Make Only Allowed Modifications

The Ethernet 1000BASE-X PCS/PMA or SGMII core should not be modified. Modifications may have adverse effects on system timing and protocol compliance. Supported user configurations of the Ethernet 1000BASE-X PCS/PMA or SGMII core can only be made by the selecting the options from within CORE Generator when the core is generated. See

Chapter 3, “Generating and Customizing the Core.”

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Chapter 5

Using the Client-side GMII Data Path

This chapter provides general guidelines for creating designs using client-side GMII of the Ethernet 1000BASE-X PCS/PMA or SGMII core.

Designing with the Client-side GMII for the 1000BASE-X Standard

It is not within the scope of this document to define the Gigabit Media Independent Interface (GMII)— see clause 35 of the IEEE 802.3 specification for information about the GMII. Timing diagrams and descriptions are provided only as an informational guide.

GMII Transmission

This section includes figures that illustrate GMII transmission. In these figures the clock is not labeled. The source of this clock signal varies, depending on the options selected when the core is generated. For more information on clocking, see Chapters 6, 7 and 8.

Normal Frame Transmission

Normal outbound frame transfer timing is illustrated in Figure 5-1. This figure shows that an Ethernet frame is proceeded by an 8-byte preamble field (inclusive of the Start of Frame Delimiter (SFD)), and completed with a 4-byte Frame Check Sequence (FCS) field. This frame is created by the MAC connected to the other end of the GMII. The PCS logic itself does not recognize the different fields within a frame and will treat any value placed on gmii_txd[7:0] within the gmii_tx_en assertion window as data.

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

preamble FCS

Figure 5-1: GMII Normal Frame Transmission

SFD

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Error Propagation

A corrupted frame transfer is illustrated in Figure 5-2. An error may be injected into the frame by asserting gmii_tx_er at any point during the gmii_tx_en assertion window. The core ensures that all errors are propagated through both transmit and receive paths so that the error is eventually detected by the link partner.

Chapter 5: Using the Client-side GMII Data Path

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

GMII Reception

This section includes figures that illustrate GMII reception. In these figures the clock is not labelled. The source of this clock signal will vary, depending on the options used when the core is generated. For more information on clocking, see Chapters 6, 7 and 8.

Normal Frame Reception

The timing of normal inbound frame transfer is illustrated in Figure 5-3. This shows that Ethernet frame reception is proceeded by a preamble field. The IEEE 802.3 specification (see clause 35) allows for up to all of the seven preamble bytes that proceed the Start of Frame Delimiter (SFD) to be lost in the network. The SFD will always be present in wellformed frames.

preamble FCS

SFD

Figure 5-2: GMII Error Propagation Within a Frame

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

54 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

preamble FCS

SFD

Figure 5-3: GMII Normal Frame Reception

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Designing with the Client-side GMII for the 1000BASE-X Standard

Normal Frame Reception with Extension Field

In accordance with the IEEE 802.3, clause 36, state machines for the 1000BASE-X PCS,

gmii_rx_er may be driven high following reception of the end frame in conjunction with gmii_rxd[7:0] containing the hexadecimal value of 0x0F to signal carrier extension.

This is illustrated in Figure 5-4. See Appendix D, “1000BASE-X State Machines” for more information.

This is not an error condition and may occur even for full-duplex frames.

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

preamble FCS

SFD

Figure 5-4: GMII Normal Frame Reception with Carrier Extension

Frame Reception with Errors

The signal gmii_rx_er when asserted within the assertion window signals that a frame was received with a detected error (Figure 5-5). In addition, a late error may also be detected during the Carrier Extension interval. This is indicated by gmii_rxd[7:0] containing the hexadecimal value 0x1F, also illustrated in Figure 5-5.

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

preamble FCS

SFD

0x0F

0x1F

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error during frame error during extension

Figure 5-5: GMII Frame Reception with Errors

False Carrier

Chapter 5: Using the Client-side GMII Data Path

Figure 5-6 illustrates the GMII signaling for a False Carrier condition. False Carrier is

asserted by the core in response to certain error conditions, such as a frame with a corrupted start code, or for random noise.

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

status_vector[4:0] signals

Bit[0]: Link Status

This signal indicates the status of the link. This information is duplicated in the optional PCS Management Registers, if present (“Status Register (Register 1),”bit 1.2). However, this would always serve a useful function as a Link Status LED.

When high, the link is valid: synchronization of the link has been obtained and AutoNegotiation (if present and enabled) has completed.

When low, a valid link has not been established. Either link synchronization has failed or Auto-Negotiation (if present and enabled) has failed to complete.

Note:

versions of the core.

this bit is identical to the SYNC_ACQUIRED_STATUS port which was present in previous

0x0E

False Carrier Indication

Figure 5-6: False Carrier Indication

Bit[1]: Link Synchronization

This signal indicates the state of the synchronization state machine (IEEE802.3 figure 36-9). This signal is similar to Bit[0] (Link Status), but is NOT qualified with Auto-Negotiation.

When high, link synchronization has been obtained.

When low, synchronization has failed.

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Designing with the Client-side GMII for the 1000BASE-X Standard

Bits[4:2]: Code Group Reception Indicators

These signals indicate the reception of particular types of group, as defined below.

Figure 5-7 illustrates the timing of these signals, showing that they are aligned with the

code groups themselves, as they appear on the output gmii_rxd[7:0] port.

gmii_rxd[7:0]

status_vector[2] “RUDI(/C/)”

status_vector[3] “RUDI(/I/)”

status_vector[4] “RUDI(INVALID)”

/C2/

/C1/D0 D1

D0 D1

/C2/

/C1/D0 D1

D0 /I2/D1

/I2/ /I2/

/I2/

Figure 5-7: status_vector[4:2] timing

Bit[2]: RUDI(/C/)

The core is receiving /C/ ordered sets (Auto-Negotiation Configuration sequences) as defined in IEEE802.3 clause 36.2.4.10.

Bit[3]: RUDI(/I/)

The core is receiving /I/ ordered sets (Idles) as defined in IEEE802.3 clause 36.2.4.12.

Bit[4]: RUDI(INVALID)

The core has received invalid data whilst receiving/C/ or /I/ ordered set as defined in IEEE802.3 clause 36.2.5.1.6. This may be caused, for example, by bit errors occurring in any clock cycle of the /C/ or /I/ ordered set: Figure 5-7 illustrates an error occurring in the second clock cycle of an /I/ idle sequence.

Using the Virtex-II Pro RocketIO Transceiver CRC Functionality

When the core is generated with the Virtex-II Pro RocketIO transceiver, the CRC functionality of the RocketIO transceiver may be enabled. When the core is generated in this mode (see “RocketIO Transceiver CRC Logic” in Chapter 3), the core ensures that the /K28.5/ characters are left-justified in the RocketIO transceiver internal two-byte data path. This is done by ensuring that the /K28.5/ is strobed into the RocketIO transceiver on the rising edge of TXUSRCLK2 only when TXUSRCLK is high. For more information, see the

Virtex-II Pro RocketIO Transceiver User Guide.

Caution!

standard.

GMII Transmission

The timing of normal outbound frame transfer with the RocketIO transceiver CRC functionality is illustrated in Figure 5-8. This figure shows that an Ethernet frame can be completed by allowing the RocketIO transceiver to create the Frame Check Sequence field (FCS) using the in-built CRC logic. For this to be successful, four place-holder bytes must

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Do not use the Virtex-II Pro RocketIO CRC functionality when using the SGMII

Chapter 5: Using the Client-side GMII Data Path

be included in the frame supplied to the core. The RocketIO transceiver will replace these four bytes with the calculated CRC value.

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

preamble

SFD

4 place holder bytes

Figure 5-8: GMII Frame Transmission with RocketIO Transceiver CRC Logic

Enabled

GMII Reception

The timing of normal inbound frame transfer with RocketIO transceiver CRC functionality is illustrated in Figure 5-9. The RocketIO transceiver calculates the CRC value of the received frame and checks it against that contained in the frames FCS field. The RocketIO transceiver will assert RXCHECKINGCRC and RXCRCERR signals, as defined in the Virtex-II

Pro RocketIO Transceiver User Guide. Figure 5-9 illustrates a frame received with a correct

FCS field since RXCRCERR is not asserted.

Please note that RXCHECKINGCRC and RXCRCERR are obtained directly from the output of the RocketIO transceiver. The core receiver behavior is unchanged.

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

RXCHECKINGCRC

RXCRCERR

Figure 5-9: GMII Frame Reception with the RocketIO Transceiver CRC Logic

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preamble FCS

SFD

Enabled

3 clock periods

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Designing with Client-side GMII for the SGMII Standard

Overview

When the core is generated for the SGMII standard, changes are made to the core that affect the PCS Management Registers and the Auto-Negotiation function (see “Select Standard”

in Chapter 3). However, the data path through both transmitter and receiver sections of the

core remains unchanged.

GMII Transmission

1 Gigabit per Second Frame Transmission

The timing of normal outbound frame transfer is illustrated in Figure 5-10. At 1 Gbps speed, the operation of the transmitter GMII signals remains identical to that described in

“Designing with the Client-side GMII for the 1000BASE-X Standard.”

userclk2

gmii_txd[7:0]

gmii_tx_en

gmii_tx_er

preamble FCS

SFD

Figure 5-10: GMII Frame Transmission at 1 Gbps

100 Megabit per Second Frame Transmission

The operation of the core remains unchanged. It is the responsibility of the client logic (for example, an Ethernet MAC) to enter data at the correct rate. When operating at a speed of 100 Mbps, every byte of the MAC frame (from preamble field to the Frame Check Sequence field, inclusive) should each be repeated for 10 clock periods to achieve the desired bit rate, as illustrated in Figure 5-11. It is also the responsibility of the client logic to ensure that the interframe gap period is legal for the current speed of operation.

userclk2

gmii_txd[7:0]

gmii_tx_en

preamble

SFD

gmii_tx_er

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10 clock periods

Figure 5-11: GMII Data Transmission at 100 Mbps

10 Megabit per Second Frame Transmission

The operation of the core remains unchanged. It is the responsibility of the client logic (for example, an Ethernet MAC), to enter data at the correct rate. When operating at a speed of 10 Mbps, every byte of the MAC frame (from destination address to the frame check sequence field, inclusive) should each be repeated for 100 clock periods to achieve the desired bit rate. It is also the responsibility of the client logic to ensure that the interframe gap period is legal for the current speed of operation.

GMII Reception

1 Gigabit per Second Frame Reception

The timing of normal inbound frame transfer is illustrated in Figure 5-12. At 1 Gbps speed, the operation of the receiver GMII signals remains identical to that described in

“Designing with the Client-side GMII for the 1000BASE-X Standard” in Chapter 5.

userclk2

Chapter 5: Using the Client-side GMII Data Path

gmii_rxd[7:0]

gmii_rx_dv

gmii_rx_er

preamble FCS

SFD

Figure 5-12: GMII Frame Reception at 1 Gbps

100 Megabit per Second Frame Reception

The operation of the core remains unchanged. When operating at a speed of 100 Mbps, every byte of the MAC frame (from destination address to the frame check sequence field, inclusive) is repeated for 10 clock periods to achieve the desired bit rate. See Figure 5-13. It is the responsibility of the client logic, for example an Ethernet MAC, to sample this data correctly.

userclk2

gmii_rxd[7:0]

gmii_rx_dv

preamble

SFD

gmii_rx_er

60 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

10 clock periods

Figure 5-13: GMII Data Reception at 100 Mbps

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Using the GMII as an Internal Connection

10 Megabit per Second Frame Reception

The operation of the core remains unchanged. When operating at a speed of 10 Mbps, every byte of the MAC frame (from destination address to the frame check sequence field, inclusive) is repeated for 100 clock periods to achieve the desired bit rate. It is the responsibility of the client logic (for example, an Ethernet MAC) to sample this data correctly.

Using the GMII as an Internal Connection

The client-side GMII of the core may be used to connect to an internally integrated Media Access Controller. For details, see “Integrating with the 1-Gigabit Ethernet MAC Core,”

page 179 and “Integrating with the Tri-Mode Ethernet MAC Core,” page 185.

Implementing External GMII

GMII Transmitter Logic

When implementing an external GMII, the GMII transmitter signals will be synchronous to their own clock domain. The core must be used with a Transmitter Elastic Buffer to transfer these GMII transmitter signals onto the cores internal 125 MHz reference clock (gtx_clk when using the TBI; userclk2 when using the RocketIO transceiver). A Transmitter Elastic Buffer is provided for the 1000BASE-X standard by the example design provided with the core. See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for more information.

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Virtex-II Pro and Virtex-II Devices

Figure 5-14 illustrates how to create an external GMII transmitter in a Virtex-II family

device. The signal names and logic shown on the figure exactly match those delivered with the example design.

Figure 5-14 shows that the input transmitter signals are registered in device IOBs before

presenting them to the FPGA fabric. This logic achieves the required setup and hold times.

Chapter 5: Using the Client-side GMII Data Path

gmii_tx_clk

IPAD

gmii_txd[0]

IPAD

gmii_tx_en

IPAD

IBUFG

IBUF

IOB LOGIC

gmii_tx_clk_ibufg

gmii_txd_ibuf[0]

gmii_tx_en_ibuf

Ethernet 1000BASE-X

PCS/PMA

or SGMII LogiCORE

BUFG

gmii_tx_clk_bufg

userclk2 (if RocketIO is used) gtx_clk (if TBI is used)

Transmitter

Elastic

Buffer

gmii_txd_int[0]

gmii_tx_en_int

gmii_txd[0]

gmii_tx_en

gmii_tx_er

IPAD

IBUF

gmii_tx_er_ibuf

62 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

gmii_tx_er_int

Figure 5-14: GMII Transmitter Logic

gmii_tx_er

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Implementing External GMII

Spartan-3, Spartan-3E and Spartan-3A Devices

The logic described previously for Virtex-II and Virtex-II Pro devices does not meet the input setup and hold requirements for GMII with Spartan-3, Spartan-3E, and Spartan-3A devices. A DCM must be used on the gmii_tx_clk clock path, as illustrated in

Figure 5-15. This is performed by the top-level example design delivered with the core (all

signal names and logic match Figure 5-15). This DCM circuitry may optionally be used in other families.

Phase-shifting may then be applied to the DCM to fine-tune the setup and hold times at the GMII IOB input flip-flops. The fixed phase shift is applied to the DCM with the example UCF for the example design. See “Constraints When Implementing an External GMII” in

Chapter 12.

IOB LOGIC

gmii_tx_clk

IPAD

IBUFG

gmii_tx_clk_ibufg

CLKIN

DCM

CLK0

BUFG

Ethernet 1000BASE-X

PCS/PMA

or SGMII LogiCORE

gmii_txd[0]

IPAD

gmii_tx_en

IPAD

gmii_tx_er

IPAD

IBUF

gmii_txd_ibuf[0]

gmii_tx_en_ibuf

gmii_tx_er_ibuf

gmii_tx_clk_bufg

gmii_txd_int[0]

gmii_tx_en_int

gmii_tx_er_int

userclk2 (if RocketIO is used) gtx_clk (if TBI is used)

Transmitter

Elastic Buffer

gmii_txd[0]

gmii_tx_en

gmii_tx_er

Figure 5-15: External GMII Transmitter Logic for Spartan-3, Spartan-3E and Spartan-3A Devices

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Virtex-4 Devices

Chapter 5: Using the Client-side GMII Data Path

The logic described previously for Virtex-II and Virtex-II Pro devices does not meet the input setup and hold requirements for GMII with Virtex-4 devices. Two possible solutions are:

1. A DCM may be used on the gmii_tx_clk clock path for the Spartan-3 family, as illustrated in Figure 5-15.

2. Input Delay Elements may be used on the GMII data path, as illustrated in Figure 5-16.

The IODELAY elements can be adjusted to fine-tune the setup and hold times at the GMII IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the UCF; these can be edited if desired. See “Constraints When

Implementing an External GMII” in Chapter 12 for more information.

gmii_tx_clk

IPAD

gmii_txd[0]

IPAD

gmii_tx_en

IPAD

IBUFG

IBUF

IOB LOGIC

IDELAY

Ethernet 1000BASE-X

PCS/PMA

or SGMII LogiCORE

BUFG

gmii_tx_clk_bufg

userclk2 (if RocketIO is used) gtx_clk (if TBI is used)

Transmitter

Elastic

Buffer

gmii_txd_int[0]

gmii_tx_en_int

gmii_txd[0]

gmii_tx_en

gmii_tx_er

IPAD

IBUF

IDELAY

Figure 5-16: External GMII Transmitter Logic for Virtex-4 Devices

64 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

gmii_tx_er_int

gmii_tx_er

UG155 March 24, 2008

Implementing External GMII

Virtex-5 Devices

Figure 5-17 illustrates how to create an external GMII transmitter in a Virtex-5 family

device. The signal names and logic shown on the figure exactly match those delivered with the example design.

GMII” in Chapter 12 for more information.

gmii_tx_clk

IPAD

gmii_txd[0]

IPAD

gmii_tx_en

IPAD

IBUFG

IBUF

IOB LOGIC

IODELAY

Ethernet 1000BASE-X

PCS/PMA

or SGMII LogiCORE

BUFG

gmii_tx_clk_bufg

userclk2 (if RocketIO is used) gtx_clk (if TBI is used)

Transmitter

Elastic

Buffer

gmii_txd_int[0]

gmii_tx_en_int

gmii_txd[0]

gmii_tx_en

gmii_tx_er

IPAD

IBUF

IODELAY

Figure 5-17: External GMII Transmitter Logic for Virtex-5 Devices

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UG155 March 24, 2008

gmii_tx_er_int

gmii_tx_er

GMII Receiver Logic

Figure 5-18 illustrates an external GMII receiver created in a Virtex-II family device. The

signal names and logic shown in the figure exactly match those delivered with the example design when the GMII is selected. If other families are selected, equivalent primitives and logic specific to that family is automatically used in the example design.

Figure 5-18 also shows that the output receiver signals are registered in device IOBs before

driving them to the device pads. The logic required to forward the receiver GMII clock is also shown. This uses an IOB output Double-Data-Rate (DDR) register so that the clock signal produced incurs exactly the same delay as the data and control signals. This clock signal, gmii_rx_clk, is inverted so that the rising edge of gmii_rx_clk occurs in the center of the data valid window, which maximizes setup and hold times across the interface. All receiver logic is synchronous to a single clock domain.

The clock name varies depending on the CORE Generator options. When used with the RocketIO transceiver, the clock name is userclk2; when used with the TBI, the clock name is gtx_clk. For more information on clocking, see Chapters 6, 7 and 8.

Chapter 5: Using the Client-side GMII Data Path

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Implementing External GMII

)

IOB LOGIC

FDDRRSE

gmii_rx_clk

OPAD

gmii_rxd[0]

OPAD

gmii_rx_dv

OPAD

OBUFT

gmii_rx_clk_obuf

gmii_rxd_obuf[0]

gmii_rx_dv_obuf

'0'

userclk2 (if RocketIO is used gtx_clk (if TBI is used)

'1'

Ethernet 1000BASE-X

PCS/PMA

or SGMII LogiCORE

gmii_isolate

gmii_rxd[0]

gmii_rx_dv

gmii_rx_er

OPAD

OBUFT

gmii_rx_er_obuf

Figure 5-18: External GMII Receiver Logic

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 67

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gmii_rx_er

Chapter 5: Using the Client-side GMII Data Path

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The Ten-Bit Interface

This chapter provides general guidelines for creating 1000BASE-X, SGMII or Dynamic Standards Switching designs using the Ten-Bit Interface (TBI). An explanation of the TBI logic in all supported device families is provided, as well as examples in which multiple instantiations of the core are required. Whenever possible, clock sharing should occur to save device resources.

Ten-Bit-Interface Logic

The example design delivered with the core is split between two hierarchical layers, as illustrated in Figure 4-2. The block level is designed so that it can be instantiated directly into customer designs and provides the following functionality:

Chapter 6

• Instantiates the core from HDL

• Connects the physical-side interface of the core to device IOBs, creating an external

TBI

The TBI logic implemented in the block level is illustrated in all the figures in this chapter.

Transmitter Logic

Figure 6-1 illustrates the use of the physical transmitter interface of the core to create an

external TBI in a Virtex-II family device. The signal names and logic shown exactly match those delivered with the example design when TBI is chosen. If other families are chosen, equivalent primitives and logic specific to that family will automatically be used in the example design.

Figure 6-1 shows that the output transmitter data path signals are registered in device IOBs

before driving them to the device pads. The logic required to forward the transmitter clock is also shown. The logic uses an IOB output Double-Data-Rate (DDR) register so that the clock signal produced incurs exactly the same delay as the data and control signals. This clock signal, pma_tx_clk, is inverted with respect to gtx_clk so that the rising edge of pma_tx_clk occurs in the center of the data valid window to maximize setup and hold times across the interface.

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UG155 March 24, 2008

gtx_clk

IPAD

IOB LOGIC

IBUFG

gtx_clk_ibufg (125 MHz)

Chapter 6: The Ten-Bit Interface

BUFG

gtx_clk_bufg

component_name

_block (Block Level from example design)

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

gtx_clk

tx_code_group[0]

tx_code_group_int[0]

IOB LOGIC

FDDRRSE

'0'

'1'

pma_tx_clk_obuf

tx_code_group_reg[0]

OBUF

tx_code_group[0]

pma_tx_clk

OPAD

Receiver Logic

Virtex-II and Virtex-II Pro Devices

Figure 6-2 illustrates an external receiver TBI in Virtex-II devices. The signal names and

logic displayed precisely match those delivered with the example design when the TBI is chosen.

Figure 6-2 shows that the input receiver signals are registered in device IOB Double-Data

Rate (DDR) input registers, alternatively on the rising edges of both pma_rx_clk0_bufg and pma_rx_clk1_bufg (pma_rx_clk0 and pma_rx_clk1 are 180 degrees out of phase with each other). This splits the input TBI data bus, rx_code_group[9:0], up into two buses: rx_code_group0_reg[9:0] and rx_code_group1_reg[9:0],

tx_code_group[9]

tx_code_group_int[9]

tx_code_group_reg[9]

Figure 6-1: Ten-Bit Interface Transmitter Logic

OBUF

tx_code_group[9]

OPAD

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Ten-Bit-Interface Logic

synchronous to pma_rx_clk0_bufg and pma_rx_clk1_bufg, respectively. These busses are then immediately registered inside the core on their respective clock.

component_name

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

_block (Block Level from example design)

pma_rx_clk0_bufg

pma_rx_clk0

pma_rx_clk1_bufg

pma_rx_clk1

rx_code_group0[0]

rx_code_group1[0]

rx_code_group1_reg[0]

BUFG

(62.5 MHz)

BUFG

(62.5 MHz)

rx_code_group0_reg[0]

pma_rx_clk0_ibufg

pma_rx_clk1_ibufg

IOB LOGIC

rx_code_group_ibuf[0]

IOB LOGIC

IBUFG

IOB LOGIC

IBUFG

IBUF

pma_rx_clk0

IPAD

pma_rx_clk1

IPAD

rx_code_group[0]

IPAD

Figure 6-2: Ten-Bit-Interface Receiver Logic

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Spartan-3, Spartan-3E and Spartan-3A Devices

The logic described previously for Virtex-II and Virtex-II Pro devices does not meet the input setup and hold requirements for TBI with Spartan-3, Spartan-3E and Spartan-3A devices. A DCM must be used on both the pma_rx_clk0 and pma_rx_clk1 clock paths (see Figure 6-3). This is performed by the example design delivered with the core (all signal names and logic match Figure 6-3).

Phase shifting may then be applied to the DCM to fine-tune the setup and hold times at the TBI IOB input flip-flops. Fixed phase shift is applied to the DCM using constraints in the example UCF for the example design. See “Constraints When Implementing an External

GMII” in Chapter 12 for more information.

Chapter 6: The Ten-Bit Interface

component_name

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

_block (Block Level from example design)

pma_rx_clk0

pma_rx_clk1

rx_code_group0[0]

rx_code_group1[0]

rx_code_group0_reg[0]

rx_code_group1_reg[0]

BUFG

pma_rx_clk0_bufg

(62.5 MHz)

BUFG

pma_rx_clk1_bufg

(62.5 MHz)

CLK0

DCM

CLKIN

IOB LOGIC

IBUFG

IOB LOGIC

IBUFG

IBUF

rx_code_group_ibuf[0]

pma_rx_clk0

IPAD

pma_rx_clk1

IPAD

rx_code_group[0]

IPAD

Figure 6-3: TBI Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices

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Ten-Bit-Interface Logic

Virtex-4 Devices

Method 1

The Virtex-4 FPGA logic used by the example design delivered with the core is illustrated in Figure 6-4. This shows a Virtex-4 device IDDR primitive used with the DDR_CLK_EDGE attribute set to SAME_EDGE (see the Virtex-4 FPGA User Guide). This uses local inversion of pma_rx_clk0 within the IOB logic to receive the rx_code_group[9:0] data bus on both the rising and falling edges of pma_rx_clk0. The SAME_EDGE attribute causes the IDDR to output both Q1 and Q2 data on the rising edge of pma_rx_clk0.

For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1 clock inputs of the core as illustrated.

Caution!

degrees out of phase with each other since the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the case.

The IDELAY elements can be adjusted to fine-tune the setup and hold times at the TBI IOB input flip-flops. The delay is applied to the IDELAY elements using constraints in the UCF; these can be edited if desired. See “Ten-Bit Interface Constraints” in Chapter 12 for more information.

component_name

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180

_block (Block Level from example design)

pma_rx_clk0

pma_rx_clk1

rx_code_group0[0]

rx_code_group1[0]

rx_code_group0_reg[0]

rx_code_group1_reg[0]

BUFG

IOB LOGIC

IDDR

IDELAY

IOB LOGIC

IBUFG

IBUF

rx_code_group[0]

pma_rx_clk0

IPAD

Figure 6-4: Ten-Bit Interface Receiver Logic - Virtex-4 Device (Example Design)

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Method 2

This logic from method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase with each other since the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the case. If not, then the logic of Figure 6-5 illustrates an alternative implementation where both pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of rx_code_group[9:0] must be routed to two separate device pads.

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

rx_code_group0[0]

pma_rx_clk0

BUFG

pma_rx_clk0_bufg

(62.5 MHz)

rx_code_group0_reg[0]

IOB LOGIC

IDELAY

Chapter 6: The Ten-Bit Interface

IOB LOGIC

IBUFG

pma_rx_clk0

IPAD

IBUF

rx_code_group[0]

IPAD

IOB LOGIC

pma_rx_clk1

rx_code_group1[0]

BUFG

pma_rx_clk1_bufg

(62.5 MHz)

rx_code_group1_reg[0]

IOB LOGIC

IDELAY

IBUFG

IBUF

pma_rx_clk1

IPAD

rx_code_group[0]

IPAD

Figure 6-5: Alternate Ten-Bit Interface Receiver Logic for Virtex-4 Devices

rx_code_group[0]

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Ten-Bit-Interface Logic

Virtex-5 Devices

Method 1

The Virtex-5 FPGA logic used by the example design delivered with the core is illustrated in Figure 6-6. This shows a Virtex-5 device IDDR primitive used with the DDR_CLK_EDGE attribute set to SAME_EDGE (see the Virtex-5 FPGA User Guide). This uses local inversion of pma_rx_clk0 within the IOB logic to receive the rx_code_group[9:0] data bus on both the rising and falling edges of pma_rx_clk0. The SAME_EDGE attribute causes the IDDR to output both Q1 and Q2 data on the rising edge of pma_rx_clk0.

For this reason, pma_rx_clk0 can be routed to both pma_rx_clk0 and pma_rx_clk1 clock inputs of the core as illustrated.

The IODELAY elements can be adjusted to fine-tune the setup and hold times at the TBI IOB input flip-flops. The delay is applied to the IODELAY element using constraints in the UCF; these can be edited if desired. See “Ten-Bit Interface Constraints” in Chapter 12 for more information.

component_name

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

Caution!

This logic relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the case.

_block (Block Level from example design)

pma_rx_clk0

pma_rx_clk1

rx_code_group0[0]

rx_code_group1[0]

rx_code_group0_reg[0]

rx_code_group1_reg[0]

BUFG

IODELAY

IOB LOGIC

IDDR

IODELAY

IOB LOGIC

IBUFG

IBUF

rx_code_group[0]

pma_rx_clk0

IPAD

Figure 6-6: Ten-Bit Interface Receiver Logic - Virtex-5 Device (Example Design)

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UG155 March 24, 2008

Method 2

This logic from method 1 relies on pma_rx_clk0 and pma_rx_clk1 being exactly 180 degrees out of phase with each other because the falling edge of pma_rx_clk0 is used in place of pma_rx_clk1. See the data sheet for the attached SERDES to verify that this is the case. If not, the logic of Figure 6-7 illustrates an alternate implementation where both

pma_rx_clk0 and pma_rx_clk1 are used as intended. Each bit of rx_code_group[9:0] must be routed to two separate device pads. The IODELAY

elements shown on Figure 6-7 can be used to compensate for any bus skew that has resulted.

Ethernet 1000BASE-X PCS/PMA

or SGMII LogiCORE

pma_rx_clk0

rx_code_group0[0]

pma_rx_clk0_bufg

(62.5 MHz)

rx_code_group0_reg[0]

BUFG

IOB LOGIC

IODELAY

Chapter 6: The Ten-Bit Interface

IOB LOGIC

IBUFG

IBUF

pma_rx_clk0

IPAD

rx_code_group[0]

IPAD

IOB LOGIC

pma_rx_clk1

rx_code_group1[0]

pma_rx_clk1_bufg

(62.5 MHz)

rx_code_group1_reg[0]

BUFG

IOB LOGIC

IODELAY

IBUFG

IBUF

pma_rx_clk1

IPAD

rx_code_group[0]

IPAD

Figure 6-7: Alternate Ten-Bit Interface Receiver Logic - Virtex-5 Devices

rx_code_group[0]

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Clock Sharing across Multiple Cores with TBI

Figure 6-8 illustrates sharing clock resources across multiple instantiations of the core

when using the TBI. gtx_clk may be shared between multiple cores, resulting in a common clock domain across the device.

The receiver clocks pma_rx_clk0 and pma_rx_clk1 cannot be shared. Each core will be provided with its own versions of these clocks from its externally connected SERDES.

Figure 6-8 illustrates the receiver clock logic used for the Virtex-II family. See “Receiver Logic,” page 70, for a description of the clock logic for other device families.

Figure 6-8 illustrates only two cores. However, more can be added using the same

principle. This is done by instantiating the cores using the block level (from the example design) and sharing gtx_clk across all instantiations.

Customer Design

Block Level

Ethernet 1000BASE-X

PCS/PMA

or SGMII Core

IBUFG

gtx_clk

(125MHz)

BUFG

gtx_clk

pma_rx_clk0

pma_rx_clk1

IBUFGBUFG

pma_rx_clk0#1

IBUFGBUFG

pma_rx_clk1#1

Block Level

Ethernet 1000BASE-X

PCS/PMA

or SGMII Core

IBUFGBUFG

gtx_clk

pma_rx_clk0

IBUFGBUFG

pma_rx_clk1

pma_rx_clk0#2

pma_rx_clk1#2

Figure 6-8: Clock Management, Multiple Core Instances with Ten-Bit Interface

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Chapter 6: The Ten-Bit Interface

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1000BASE-X with RocketIO Transceivers

This chapter provides general guidelines for creating 1000BASE-X designs that use RocketIO transceivers for Virtex-II Pro, Virtex-4, and Virtex-5 devices. Information about RocketIO transceiver and core logic in all supported device families is provided, as well as information about designs requiring multiple instantiations of the core. Note that clock sharing should occur whenever possible to save device resources.

RocketIO Transceiver Logic

Chapter 7

The example is split between two discrete hierarchical layers, as illustrated in Figure 4-1. The block level is designed so that it can be instantiated directly into customer designs and provides the following functionality:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to a Virtex-II Pro, Virtex-4, or Virtex-5

RocketIO transceiver

The logic implemented in the block level is illustrated in all the figures in this chapter.

Virtex-II Pro Devices

The core is designed for seamless integration with the Virtex-II Pro RocketIO Multi-Gigabit Transceiver (MGT). Figure 7-1 illustrates the connections and logic required between the core and the MGT—the signal names and logic in the figure precisely match those delivered with the example design when an MGT is used.

Some modifications can be made to the MGT. For example, REFCLK may be used instead of BREFCLK. See the RocketIO Transceiver User Guide (UG024) for details.

The placement of the flip-flop that connects to ENMCOMMAALIGN and ENPCOMMAALIGGN is important (see Figure 7-1). For detailed information, see “Virtex-II Pro RocketIO MGTs for

1000BASE-X Constraints,” and the RocketIO Transceiver User Guide.

Note:

The brefclk differential pair applied to the MGT is of frequency 62.5 MHz.

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UG155 March 24, 2008

Chapter 7: 1000BASE-X with RocketIO Transceivers

IOB LOGIC

brefclkp

IPAD

brefclkn

IBUFGDS

brefclk (62.5MHz)

DCM

CLKIN CLK0

CLK2X180

LOCKED

BUFG

userclk (62.5MHz)

userclk2 (125MHz)

component_name_block (Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

userclk

dcm_locked

userclk2

mgt_rx_reset

mgt_tx_reset

rxbufstatus[1:0]

rxchariscomma

rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0]

rxdisperr

powerdown

txchardispmode

txchardispval

txcharisk

txdata[7:0]

enablealign

GND

(GT_ETHERNET_1)

REFCLKSEL

REFCLK

REFCLK2

BREFCLK

BREFCLK2

TXUSRCLK

TXUSRCLK2

RXUSRCLK

RXUSRCLK2

RXRESET

TXRESET

RXBUFSTATUS[1:0]

RXCHARISCOMMA

RXCHARISK

RXCLKCORCNT[2:0]

RXDATA[7:0]

RXDISPERR

LOOPBACK[1:0]

POWERDOWN

TXCHARDISPMODE

TXCHARDISPVAL

TXCHARISK

TXDATA[7:0]

ENPCOMMAALIGN

ENMCOMMAALIGN

Virtex-II Pro

RocketIO

80 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

RXRECCLK

RXPOLARITY

TXPOLARITY

TXFORCECRCERR

TXINHIBIT

GND

Figure 7-1: 1000BASE-X Connection to a Virtex-II Pro MGT

UG155 March 24, 2008

RocketIO Transceiver Logic

Virtex-4 FX Devices

The core is designed to integrate with the Virtex-4 RocketIO MGT. Figure 7-2 illustrates the connections and logic required between the core and MGT—the signal names and logic in the figure precisely match those delivered with the example design when an MGT is used.

Note:

port differences between the Virtex-II Pro and Virtex-4 RocketIO transceivers.

A small logic shim (included in the block-level wrapper) is required to convert between the

The MGT clock distribution in Virtex-4 devices is column-based and consists of multiple MGT tiles (each tile contains two MGTs). For this reason, the MGT wrapper delivered with the core always contains two MGT instantiations, even if only a single MGT is in use.

Figure 7-2 illustrates a single MGT tile for clarity.

A GT11CLK_MGT primitive is also instantiated to derive the reference clocks required by the MGT column-based tiles. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076) for information about layout and clock distribution.

The 250 MHz reference clock from the GT11CLK_MGT primitive is routed to the MGT, configured to internally synthesize a 125 MHz clock. This is output on the TXOUTCLK1 port of the MGT and after placed onto global clock routing, can be used by all core logic. This clock is input back into the MGT on the user interface clock ports rxusrclk2 and

txusrclk2. With the attribute settings applied to the MGT from the example design, the txusrclk and rxusrclk ports are derived internally within the MGT using the internal

clock dividers and do not need to be provided from the FPGA fabric.

The Virtex-4 FX MGTs require the inclusion of a calibration block in the fabric logic; the example design provided with the core instantiates calibration blocks as required. Calibration blocks require a clock source of between 25 to 50 MHz that is shared with the Dynamic Reconfiguration Port (DRP) of the MGT, which is named dclk in the example design. See Xilinx A

nswer Record 22477 for more information.

Figure 7-2 also illustrates the TX_SIGNAL_DETECT and RX_SIGNAL_DETECT ports of the

calibration block, which should be driven to indicate whether or not dynamic data is being transmitted and received through the MGT (see Virtex-4 Errata

). However,

RX_SIGNAL_DETECT is connected to the signal_detect port of the example design. signal_detect is intended to be connected to the optical transceiver to indicate the

presence of light. When light is detected, the optical transceiver provides dynamic data to the Rx ports of the MGT. When no light is detected, the calibration block switches the MGT into loopback to force dynamic data through the MGT receiver path.

Caution!

used, the RX_SIGNAL_DETECT port of the calibration block must be driven by an alternative method. Please refer to XAPP732 for more information.

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UG155 March 24, 2008

signal_detect is an optional port in the IEEE 802.3 specification. If this is not

Chapter 7: 1000BASE-X with RocketIO Transceivers

userclk2 (125MHz)

component_name_block (Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

userclk

userclk2

rxchariscomma

rxbufstatus[1:0]

rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0]

rxrundisp

rxdisperr

powerdown

txchardispmode

txchardispval

txcharisk

txdata[7:0]

BUFG

brefclkp (250 MHz)

brefclkn (250 MHz)

LOGIC

SHIM

IPAD

Virtex-4

GT11CLK_MGT

MGTCLKP

MGTCLKN

SYNCLK1OUT

Virtex-4

GT11

RocketIO

(used)

REFCLK1

TXOUTCLK1

'0'

TXUSRCLK

TXUSRCLK2

RXUSRCLK

RXUSRCLK2

RXCHARISCOMMA

RXBUFERR

RXCHARISK

RXSTATUS[5:0]

RXDATA[7:0]

RXRUNDISP

RXDISPERR

POWERDOWN

TXCHARDISPMODE

TXCHARDISPVAL

TXCHARISK

TXDATA[7:0]

synclk1

dclk

signal_detect

82 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

enablealign

BUFG

'1'

ENPCOMMAALIGN

ENMCOMMAALIGN

DCLK

Cal Block v1.4.1

DCLK

RX_SIGNAL_DETECT

TX_SIGNAL_DETECT

Figure 7-2: 1000BASE-X Connection to Virtex-4 MGT

UG155 March 24, 2008

RocketIO Transceiver Logic

Virtex-5 LXT and SXT Devices

The core is designed to integrate with the Virtex-5 RocketIO GTP transceiver. Figure 7-3 illustrates the connections and logic required between the core and the GTP transceiver— the signal names and logic in the figure precisely match those delivered with the example design when a GTP transceiver is used.

Note:

port differences between the Virtex-II Pro and Virtex-5 GTP transceiver.

A small logic shim (included in the block-level wrapper) is required to convert between the

A GTP tile consists of a pair of transceivers. For this reason, the GTP transceiver wrapper delivered with the core always contains two GTP instantiations, even if only a single GTP transceiver tile is in use. Figure 7-3 illustrates a single GTP transceiver tile.

The 125 MHz differential reference clock is routed directly to the GTP transceiver. The GTP transceiver is configured to output a version of this clock on the REFCLKOUT port and after placement onto global clock routing, can be used by all core logic. This clock is input back into the GTP transceiver on the user interface clock ports rxusrclk, rxusrclk2, txusrclk, and txusrclk2.

See also “Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints,” page 166.

Virtex-5 RocketIO GTP Wizard

The two wrapper files immediately around the GTP transceiver pair, rocketio_wrapper_gtp_tile and rocketio_wrapper_gtp (see Figure 7-3), are generated from the RocketIO GTP Wizard. These files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated by customers and therefore be easily targeted at ES or Production silicon. Note that this core targets production silicon.

The CORE Generator log file (XCO file) which was created when the RocketIO GTP Wizard project was generated is available in the following location:

<project_directory>/<component_name>/example_design/transceiver/ rocketio_wrapper_gtp.xco

This file can be used as an input to the CORE Generator to regenerate the RocketIO wrapper files. The XCO file itself contains a list of all of the GTP Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTP Wizard Getting Started Guide (UG188) and the CORE Generator Guide, at

www.xilinx.com/support/software_manuals.htm

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Chapter 7: 1000BASE-X with RocketIO Transceivers

userclk2 (125MHz)

component_name_block (Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

userclk

userclk2

rxchariscomma

rxbufstatus[1:0]

rxcharisk

rxdisperr

rxdata[7:0]

rxrundisp

rxclkcorcnt[2:0]

powerdown

txchardispmode

txchardispval

txcharisk

txdata[7:0]

BUFG

LOGIC

SHIM

brefclkp

IBUFGDS

IPAD

brefclkn

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

Virtex-5

GTP

RocketIO

(0)

REFCLKOUT

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

RXCHARISCOMMA0

RXBUFERR0

RXCHARISK0

RXDISPERR0

RXDATA[07:0]

RXRUNDISP0

RXCLKCORCNT[2:0]

POWERDOWN0

TXCHARDISPMODE0

TXCHARDISPVAL0

TXCHARISK0

TXDATA[07:0]

clkin (125MHz)

CLKIN

Figure 7-3: 1000BASE-X Connection to Virtex-5 GTP Transceivers

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enablealign

RXENMCOMMAALIGN0

RXENPCOMMAALIGN0

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RocketIO Transceiver Logic

Virtex-5 FXT Devices

The core is designed to integrate with the Virtex-5 RocketIO GTX transceiver. Figure 7-4 illustrates the connections and logic required between the core and the GTX transceiver— the signal names and logic in the figure precisely match those delivered with the example design when a GTX transceiver is used.

Note:

port differences between the Virtex-II Pro and Virtex-5 GTX transceiver.

A small logic shim (included in the block-level wrapper) is required to convert between the

A GTX tile consists of a pair of transceivers. For this reason, the GTX transceiver wrapper delivered with the core always contains two GTX instantiations, even if only a single GTX transceiver tile is in use. Figure 7-4 illustrates a single GTX transceiver tile.

The 125 MHz differential reference clock is routed directly to the GTX transceiver. The GTX transceiver is configured to output a version of this clock on the REFCLKOUT port: this is then routed to a DCM.

From the DCM, the CLK0 port (125MHz) is placed onto global clock routing and can be used as the 125MHz clock source for all core logic: this clock is also input back into the GTX transceiver on the user interface clock ports rxusrclk2 and txusrclk2.

From the DCM, the CLKDV port (62.5MHz) is placed onto global clock routing and is input back into the GTX transceiver on the user interface clock ports rxusrclk and txusrclk.

See also “Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints,” page 167.

Virtex-5 RocketIO GTX Wizard

The two wrapper files immediately around the GTX transceiver pair, rocketio_wrapper_gtx_tile and rocketio_wrapper_gtx (see Figure 7-4), are generated from the RocketIO GTX Wizard. These files apply all the gigabit Ethernet attributes. Consequently, these files can be regenerated by customers and therefore be easily targeted at ES or Production silicon. Note that this core targets production silicon.

The CORE Generator log file (XCO file) which was created when the RocketIO GTX Wizard project was generated is available in the following location:

<project_directory>/<component_name>/example_design/transceiver/ rocketio_wrapper_gtx.xco

This file can be used as an input to the CORE Generator to regenerate the RocketIO wrapper files. The XCO file itself contains a list of all of the GTX Wizard attributes which were used. For further information, please refer to the Virtex-5 RocketIO GTX Wizard Getting Started Guide and the CORE Generator Guide, at

www.xilinx.com/support/software_manuals.htm

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Chapter 7: 1000BASE-X with RocketIO Transceivers

DCM

CLKIN

CLK0

CLKDV

component_name_block (Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

rxchariscomma

rxbufstatus[1:0]

rxdata[7:0]

rxclkcorcnt[2:0]

powerdown

txchardispmode

txchardispval

BUFG

userclk

userclk2

rxcharisk

rxdisperr

rxrundisp

txcharisk

txdata[7:0]

userclk2 (125MHz)

userclk (62.5MHz)

LOGIC

SHIM

brefclkp

IBUFGDS

IPAD

brefclkn

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

Virtex-5

GTP

RocketIO

(0)

CLKIN

REFCLKOUT

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

RXCHARISCOMMA0

RXBUFERR0

RXCHARISK0

RXDISPERR0

RXDATA[07:0]

RXRUNDISP0

RXCLKCORCNT[2:0]

POWERDOWN0

TXCHARDISPMODE0

TXCHARDISPVAL0

TXCHARISK0

TXDATA[07:0]

clkin (125MHz)

Figure 7-4: 1000BASE-X Connection to Virtex-5 GTX Transceivers

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enablealign

RXENMCOMMAALIGN0

RXENPCOMMAALIGN0

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Clock Sharing Across Multiple Cores with RocketIO

Virtex-II Pro Devices

Figure 7-5 illustrates sharing clock resources across two instantiations of the core on the

same half of the device when using the core with the Virtex-II Pro MGT. Note that more can be added by instantiating the cores using the block level (from the example design) and continuing to share userclk, userclk2, and brefclk across all instantiations. For each core, userclk and userclk2 must always be derived from the brefclk or refclk used by that core.

When using the fixed routing resources of brefclk, MGTs along the top edge of the device must use a separate brefclk routing resource to those along the bottom edge of the device. For more information, see the Virtex-II Pro RocketIO Transceiver User Guide (UG024). Each brefclk domain must use its own DCM to derive its version of userclk and userclk2.

Customer Design

brefclkp IPAD IPAD

brefclkn

IBUFGDS

DCM

CLKIN CLK0 FB

CLK2X180

brefclk (62.5MHz)

BUFG

userclk (62.5 MHz)

userclk2 (125 MHz)

component_name

(Block Level)

Ethernet 1000BASE-X

component_name

(Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

PCS/PMA or

SGMII core

userclk

userclk2

_block

GT_ETHERNET_1

BREFCLK

TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2

_block

GT_ETHERNET_1

BREFCLK

TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2

Figure 7-5: Clock Management: Two Core Instances, Virtex-II Pro

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UG155 March 24, 2008

MGTs for 1000BASE-X

Virtex-4 FX Devices

Figure 7-6 illustrates sharing clock resources across multiple instantiations of the core

when using MGTs. Note that the example design, when using the Virtex-4 family, can be generated to connect either a single instance of the core, or connect a pair of core instances to the transceiver pair present in an MGT tile. Figure 7-6 shows two instantiations of the block level, where each block contains a pair of cores, subsequently illustrating clock sharing between four cores in total.

More cores can be added by continuing to instantiate extra block-level modules. Share clocks only between the MGTs in a single column. For each column, use a single brefclk_p and brefclk_n differential clock pair and connect this to a GT11CLK_MGT primitive. The clock output from this primitive should be shared across all used RocketIO tiles in the column. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076) for more information.

To provide the 125 MHz clock for all core instances, select a TXOUTCLK1 port from any MGT. This can be routed onto global clock routing using a BUFG as illustrated, and shared between all cores and MGTs in the column. Although not illustrated in Figure 7-6, dclk (the clock used for the calibration blocks and for the Dynamic Reconfiguration Port (DRP) of the MGTs) can also be shared.

Chapter 7: 1000BASE-X with RocketIO Transceivers

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Clock Sharing Across Multiple Cores with RocketIO

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

userclk2 (125 MHz)

BUFG

brefclkp (250MHz)

IPAD

brefclkn (250MHz)

Virtex-4

GT11CLK_MGT

MGTCLKP

MGTCLKN

synclk1

SYNCLK1OUT

MGT tile

Virtex-4

GT11

RocketIO

(A)

TXOUTCLK1

REFCLK1

TXUSRCLK

‘0’

TXUSRCLK2

‘0’

RXUSRCLK

RXUSRCLK2

Virtex-4

GT11

RocketIO

(B)

TXOUTCLK1

REFCLK1

TXUSRCLK

‘0’

TXUSRCLK2

RXUSRCLK

‘0’

RXUSRCLK2

MGT tile

Virtex-4

GT11

RocketIO

(A)

TXOUTCLK1

REFCLK1

TXUSRCLK

‘0’

TXUSRCLK2

‘0’

RXUSRCLK

RXUSRCLK2

Virtex-4

GT11

RocketIO

(B)

TXOUTCLK1

REFCLK1

TXUSRCLK

‘0’

TXUSRCLK2

RXUSRCLK

‘0’

RXUSRCLK2

(250MHz)

Figure 7-6: Clock Management - Multiple Core Instances, MGTs for 1000BASE-X

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UG155 March 24, 2008

Virtex-5 LXT and SXT Devices

Figure 7-7 illustrates sharing clock resources across multiple instantiations of the core

when using Virtex-5 RocketIO GTP transceivers.

The example design can be generated to connect either a single instance of the core or connect a pair of core instances to the transceiver pair present in a GTP tile. Figure 7-7 illustrates two instantiations of the block level, and each block level contains a pair of cores, consequently illustrating clock sharing between a total of four cores.

Additional cores can be added by continuing to instantiate extra block level modules. Share the brefclk_p and brefclk_n differential clock pair. See the Virtex-5 RocketIO GTP Transceiver User Guide (UG196) for more information.

To provide the 125 MHz clock for all core instances, select a REFCLKOUT port from any GTP transceiver. This can be routed onto global clock routing using a BUFG as illustrated and shared between all cores and GTP transceivers.

Chapter 7: 1000BASE-X with RocketIO Transceivers

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Clock Sharing Across Multiple Cores with RocketIO

BUFG

brefclkp

IPAD

IPAD brefclkn

IBUFGDS

clkin (125MHz)

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

userclk2 (125 MHz)

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

REFCLKOUT

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

REFCLKOUT

Virtex-5

GTP

RocketIO

(0)

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

Virtex-5

GTP

RocketIO

(1)

TXUSRCLK1

TXUSRCLK21

RXUSRCLK1

RXUSRCLK21

Virtex-5

GTP

RocketIO

(0)

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

Virtex-5

GTP

RocketIO

(1)

CLKIN

Figure 7-7: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTP

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UG155 March 24, 2008

TXUSRCLK1

TXUSRCLK21

RXUSRCLK1

RXUSRCLK21

Transceivers for 1000BASE-X

Virtex-5 FXT Devices

Figure 7-8 illustrates sharing clock resources across multiple instantiations of the core

when using Virtex-5 RocketIO GTX transceivers.

The example design can be generated to connect either a single instance of the core or connect a pair of core instances to the transceiver pair present in a GTX tile. Figure 7-8 illustrates two instantiations of the block level, and each block level contains a pair of cores, consequently illustrating clock sharing between a total of four cores.

Additional cores can be added by continuing to instantiate extra block level modules. Share the brefclk_p and brefclk_n differential clock pair. See the Virtex-5 RocketIO GTX Transceiver User Guide for more information.

To provide the FPGA fabric clocks for all core instances, select a REFCLKOUT port from any GTX transceiver and route this to a single DCM. The CLK0 (125MHz) and CLKDV (62.5MHz) outputs from this DCM, placed onto global clock routing using a BUFGs, can be shared across all core instances and GTX transceivers as illustrated.

Chapter 7: 1000BASE-X with RocketIO Transceivers

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UG155 March 24, 2008

Clock Sharing Across Multiple Cores with RocketIO

DCM

CLKIN

CLK0

CLKDV

BUFG

userclk (62.5MHz)

userclk2 (125MHz)

brefclkp

IPAD

IPAD brefclkn

IBUFGDS

clkin (125MHz)

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

component_name_block (Block Level)

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

Ethernet 1000BASE-X

PCS/PMA or

SGMII core

userclk

userclk2

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

REFCLKOUT

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

TXUSRCLK1

TXUSRCLK21

RXUSRCLK1

RXUSRCLK21

rocketio_wrapper_gtp

rocketio_wrapper_gtp_tile

REFCLKOUT

TXUSRCLK0

TXUSRCLK20

RXUSRCLK0

RXUSRCLK20

Virtex-5

GTP

RocketIO

(0)

Virtex-5

GTP

RocketIO

(1)

Virtex-5

GTP

RocketIO

(0)

Virtex-5

GTP

RocketIO

(1)

CLKIN

Figure 7-8: Clock Management - Multiple Core Instances, Virtex-5 RocketIO GTX

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UG155 March 24, 2008

TXUSRCLK1

TXUSRCLK21

RXUSRCLK1

RXUSRCLK21

Transceivers for 1000BASE-X

Chapter 7: 1000BASE-X with RocketIO Transceivers

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UG155 March 24, 2008

Chapter 8

SGMII / Dynamic Standards Switching with RocketIO Transceivers

This chapter provides general guidelines for creating SGMII designs, and designs capable of switching between 1000BASE-X and SGMII standards (Dynamic Standards Switching), using a RocketIO transceiver. Throughout this chapter, any reference to SGMII also applies to the Dynamic Standards Switching implementation.

The chapter begins with an explanation of the two Receiver Elastic Buffer implementations: one implementation uses the buffer present in the RocketIO transceivers, and the other uses a larger buffer, implemented in the FPGA fabric.

After selecting the Rx Elastic Buffer implementation type, an explanation of the RocketIO transceiver and core logic in all supported device families is provided in the following sections:

• “RocketIO Logic using the RocketIO Rx Elastic Buffer,” page 98

• “RocketIO Logic with the Fabric Rx Elastic Buffer,” page 98

Instances where multiple instantiations of the core are required when using the fabric Receiver Elastic Buffer are then presented. Clock sharing should occur whenever possible to save device resources.

Receiver Elastic Buffer Implementations

Selecting the Buffer Implementation from the GUI

The GUI provides two SGMII Capability options:

• 10/100/1000 Mbps (clock tolerance compliant with Ethernet specification)

• 10/100/1000 Mbps (restricted tolerance for clocks) OR 100/1000 Mbps

The first option, 10/100/1000 Mbps (clock tolerance compliant with Ethernet specification) is the default and provides the implementation using the Receiver Elastic Buffer in FPGA fabric. This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the RocketIO transceiver, for this reason consuming extra logic resources. However, this default mode is reliable for all implementations using standard Ethernet frame sizes. Further consideration must be made for jumbo frames.

The second option, 10/100/1000 Mbps (restricted tolerance for clocks) or 100/1000 Mbps, uses the receiver elastic buffer present in the RocketIOs. This is half the size and can potentially underflow or overflow during SGMII frame reception at 10 Mbps operation

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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

(see the next section). However, there are logical implementations where this can be reliable and has the benefit of lower logic utilization.

The Requirement for the FPGA Fabric Rx Elastic Buffer

Figure 8-1 illustrates a simplified diagram of a common situation where the core, in SGMII

mode, is interfaced to an external PHY device. Separate oscillator sources are used for the FPGA and the external PHY. The Ethernet specification uses clock sources with a tolerance of 100ppm. In Figure 8-1, the clock source for the PHY is slightly faster than the clock source to the FPGA. For this reason, during frame reception, the receiver elastic buffer (shown here as implemented in the RocketIO) starts to fill.

Following frame reception, in the interframe gap period, idles are removed from the received data stream to return the Rx Elastic Buffer to half-full occupancy. This is performed by the clock correction circuitry (see the RocketIO User Guide for the targeted device).

FPGA

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

RocketIO

Elastic

Buffer

TXP/TXN

RXP/RXN

SGMII Link

10 BASE-T

100BASE-T

1000BASE-T

PHY

Twisted Copper

Pair

125MHz +100ppm125MHz -100ppm

Figure 8-1: SGMII Implementation using Separate Clock Sources

Analysis

Assuming separate clock sources, each of tolerance 100 ppm, the maximum frequency difference between the two devices can be 200 ppm. It can be shown that this translates into a full clock period difference every 5000 clock periods.

Relating this to an Ethernet frame, there will be a single byte of difference every 5000 bytes of received frame data, and this will cause the Rx Elastic Buffer to either fill or empty by an occupancy of one.

The maximum Ethernet frame size (non-jumbo) is 1522 bytes for a VLAN frame.

• At 1 Gbps operation, this translates into 1522 clock cycles.

• At 100 Mbps operation, this translates into 15220 clock cycles (as each byte is repeated

10 times).

• At 10 Mbps operation, this translates into 152200 clock cycles (as each byte is repeated 100 times).

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Receiver Elastic Buffer Implementations

Considering the 10 Mbps case, we would need 152200/5000 = 31 FIFO entries in the Elastic Buffer above and below the half way point to guarantee that the buffer will not under or overflow during frame reception. This assumes that frame reception begins when the buffer is exactly half full.

The size of the Rx Elastic Buffer in the RocketIOs is 64 entries. However, we cannot assume that the buffer is exactly half full at the start of frame reception. Additionally, the underflow and overflow thresholds are not exact (see Appendix E, “Rx Elastic Buffer

Specifications” for more information).

To guarantee reliable SGMII operation at 10 Mbps (non-jumbo frames), the RocketIO Elastic Buffer must be bypassed and a larger buffer implemented in the FPGA fabric. The fabric buffer, provided by the example design, is twice the size of the RocketIO alternative. This has been proven to cope with standard (none jumbo) Ethernet frames at all three SGMII speeds.

Appendix E, “Rx Elastic Buffer Specifications” provides further information about all Rx

Elastic Buffers used by the core. Information about the reception of jumbo frames is also provided.

The RocketIO Rx Elastic Buffer

The Elastic Buffer in the RocketIO can be used reliably when the following conditions are met:

• 10 Mbps operation is not required (for example, when connecting the core to the Xilinx 1-Gigabit Ethernet MAC to provide only 1 Gbps operation). Both 1 Gbps and 100 Mbps operation can be guaranteed.

• When the clocks are closely related (see the following section).

If there is any doubt, select the FPGA fabric Rx Elastic Buffer Implementation.

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Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

Closely Related Clock Sources

Case 1

Figure 8-2 illustrates a simplified diagram of a common situation where the core, in SGMII

mode, is interfaced to an external PHY device. A common oscillator source is used for both the FPGA and the external PHY.

FPGA

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

RocketIO

Elastic

Buffer

TXP/TXN

RXP/RXN

SGMII Link

10 BASE-T

100BASE-T

1000BASE-T

PHY

Twisted Copper

Pair

125MHz -100ppm

Figure 8-2: SGMII Implementation using Shared Clock Sources

If the PHY device sources the receiver SGMII stream synchronously from the shared oscillator (check PHY data sheet), the RocketIO will receive data at exactly the same rate as that used by the core. The receiver elastic buffer will neither empty nor fill, having the same frequency clock on either side.

In this situation, the receiver elastic buffer will not under or overflow, and the elastic buffer implementation in the RocketIO should be used to save logic resources.

Case 2

Consider again the case illustrated in Figure 8-1 with the following exception: assume that the clock sources used are both 50 ppm. Now the maximum frequency difference between the two devices is 100 ppm. It can be shown that this translates into a full clock period difference every 10000 clock periods, resulting in a requirement for 16 FIFO entries above and below the half-full point. This provides reliable operation with the RocketIO Rx Elastic Buffers. Again, however, check the PHY data sheet to ensure that the PHY device sources the receiver SGMII stream synchronously to its reference oscillator.

RocketIO Logic using the RocketIO Rx Elastic Buffer

When the RocketIO Rx Elastic Buffer implementation is selected, the connections between the core and the RocketIO as well as all clock circuitry in the system are identical to the 1000BASE-X implementation. For a detailed explanation, see Chapter 7, “1000BASE-X

with RocketIO Transceivers.”

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RocketIO Logic with the Fabric Rx Elastic Buffer

The example design delivered with the core is split between two hierarchical layers, as illustrated in Figure 4-3. The block level is designed so to be instantiated directly into customer designs and provides the following functionality:

• Instantiates the core from HDL

• Connects the physical-side interface of the core to a Virtex-II Pro, Virtex-4 or Virtex-5

RocketIO transceiver via the fabric Rx Elastic Buffer

The logic implemented in the block level is illustrated in all figures throughout the remainder of this chapter.

Virtex-II Pro Devices

The core is designed for connection to a Virtex-II Pro MGT. The connections and logic required between the core and RocketIO transceiver are illustrated in Figure 8-3–the signal names and logic in the figure precisely match those delivered with the example design when an MGT transceiver is used.

Some modifications may be made to the MGT. For example, REFCLK may be used instead of BREFCLK. See the Virtex-II Pro RocketIO Transceiver User Guide (UG024) for details.

Figure 8-3 shows that the Rx Elastic Buffer is implemented in the FPGA fabric between the

MGT transceiver and the core. This replaces the Rx Elastic Buffer in the MGT (which is bypassed).

This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as large as the one present in the MGT. It is able to cope with larger frame sizes before clock tolerances accumulate and result in emptying or filling of the buffer. This is necessary to guarantee SGMII operation at 10 Mbps, where each frame size is effectively 100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see

“Designing with Client-side GMII for the SGMII Standard,” page 59).

In bypassing the MGT Rx Elastic Buffer, data is clocked out of the MGT synchronously to rxrecclk. This must be placed on constrained local clock routing for reliable operation. See “Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching

Constraints,” page 163 for constraint details. This methodology is also described in

XAPP763.

Note:

The brefclk differential pair applied to the MGT is of frequency 62.5 MHz.

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 99

UG155 March 24, 2008

Chapter 8: SGMII / Dynamic Standards Switching with RocketIO Transceivers

IOB LOGIC

brefclkp

IPAD

brefclkn

IBUFGDS

brefclk (62.5MHz)

DCM

CLKIN CLK0

CLK2X180

LOCKED

BUFG

userclk (62.5MHz)

userclk2 (125MHz)

component_name_block (Block Level from example design)

Ethernet 1000BASE-X

PCS/PMA or SGMII

LogiCORE

userclk

userclk2

dcm_locked

powerdown

txchardispmode

txchardispval

txcharisk

txdata[7:0]

mgt_rx_reset

mgt_tx_reset

GND

REFCLKSEL

REFCLK

REFCLK2

BREFCLK

BREFCLK2

TXUSRCLK

TXUSRCLK2

LOOPBACK[1:0]

POWERDOWN

TXCHARDISPMODE

TXCHARDISPVAL

TXCHARISK

TXDATA[7:0]

RXRESET

TXRESET

Virtex-II Pro

RocketIO

(GT_CUSTOM)

rxbufstatus[1:0]

rxchariscomma

rxcharisk

rxclkcorcnt[2:0]

rxdata[7:0]

rxdisperr

enablealign

FPGA

fabric

Elastic

Buffer

local

clock

routing

GND

RXCHARISCOMMA[1:0]

RXCHARISK[1:0]

RXDATA[15:0] RXDISPERR[1:0]

RXUSRCLK

RXUSRCLK2

ENPCOMMAALIGN

ENMCOMMAALIGN

RXRECCLK

RXPOLARITY

TXPOLARITY

TXFORCECRCERR

TXINHIBIT

Figure 8-3: SGMII Connection to a Virtex-II Pro RocketIO Transceiver

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Xilinx LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual