Xilinx EDK 8.2i User Manual

MicroBlaze Processor Reference Guide

Embedded Development Kit EDK 8.2i

UG081 (v6.0) June 1, 2006

NOTICEOFDISCLAIMER:Xilinxis providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or ﬁtness for a particular purpose.

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The following table shows the revision history for this document.

Date Version Revision

10/01/02 1.0 Xilinx EDK 3.1 release 03/11/03 2.0 Xilinx EDK 3.2 release 09/24/03 3.0 Xilinx EDK 6.1 release 02/20/04 3.1 Xilinx EDK 6.2 release 08/24/04 4.0 Xilinx EDK 6.3 release 09/21/04 4.1 Minor corrections for EDK 6.3 SP1 release 11/18/04 4.2 Minor corrections for EDK 6.3 SP2 release 01/20/05 5.0 Xilinx EDK 7.1 release 04/02/05 5.1 Minor corrections for EDK 7.1 SP1 release 05/09/05 5.2 Minor corrections for EDK 7.1 SP2 release 10/05/05 5.3 Minor corrections for EDK 8.1 release 02/21/06 5.4 Corrections for EDK 8.1 SP2 release 06/01/06 6.0 Xilinx EDK 8.2 release

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Preface: About This Guide

Manual Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 1: MicroBlaze Architecture

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Types and Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Special Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pipeline Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset, Interrupts, Exceptions, and Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Hardware Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Breaks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

User Vector (Exception) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

General Instruction Cache Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Instruction Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Instruction Cache Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Data Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General Data Cache Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data Cache Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Rounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Fast Simplex Link (FSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Acceleration using FSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Debug and Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Debug Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Trace Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Chapter 2: MicroBlaze Signal Interface Description

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

On-Chip Peripheral Bus (OPB) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . 48

Local Memory Bus (LMB) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LMB Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

LMB Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Read and Write Data Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Fast Simplex Link (FSL) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Master FSL Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Slave FSL Signal Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

FSL Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Xilinx CacheLink (XCL) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

CacheLink Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

CacheLink Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Debug Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Trace Interface Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

MicroBlaze Core Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Chapter 3: MicroBlaze Application Binary Interface

Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Register Usage Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Stack Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Small data area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Data area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Common un-initialized area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Literals or constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Interrupt and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Chapter 4: MicroBlaze Instruction Set Architecture

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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About This Guide

Welcome to the MicroBlaze Processor Reference Guide. This document provides information about the 32-bit soft processor MicroBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as a guide to the MicroBlaze hardware architecture.

Manual Contents

This manual discusses the following topics speciﬁc to MicroBlaze soft processor:

• Core Architecture

• Bus Interfaces and Endianness

• Application Binary Interface

• Instruction Set Architecture

Preface

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this web-site. You can also directly access these resources using the provided URLs.

Resource Description/URL

Tutorials Tutorials covering Xilinx design ﬂows, from design entry to

Answer Browser Database of Xilinx solution records

Application Notes Descriptions of device-speciﬁc design techniques and approaches

Data Book Pages from The Programmable Logic Data Book, which contains

veriﬁcation and debugging

http://support.xilinx.com/support/techsup/tutorials/index.htm

http://support.xilinx.com/xlnx/xil_ans_browser.jsp

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?c ategory=Application+Notes

device-speciﬁc information on Xilinx device characteristics, including readback, boundary scan, conﬁguration, length count, and debugging

http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

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Conventions

Typographical

Preface: About This Guide

Resource Description/URL

Problem Solvers Interactive tools that allow you to troubleshoot your design issues

http://support.xilinx.com/support/troubleshoot/psolvers.htm

Tech Tips Latest news, design tips, and patch information for the Xilinx

design environment

http://www.support.xilinx.com/xlnx/xil_tt_home.jsp

GNU Manuals The entire set of GNU manuals

http://www.gnu.org/manual

This document uses the following conventions. An example illustrates each convention.

The following typographical conventions are used in this document:

Convention Meaning or Use Example

Messages, prompts, and

Courier font

Courier bold

Helvetica bold

Italic font

Square brackets [ ]

program ﬁles that the system displays

Literal commands that you enter in a syntactical statement

Commands that you select from a menu

Keyboard shortcuts Ctrl+C Variables in a syntax

statement for which you must supply values

References to other manuals

Emphasis in text

An optional entry or parameter. However, in bus speciﬁcations, such as bus[7:0], they are required.

speed grade: - 100

ngdbuild design_name

File → Open

ngdbuild design_name

See the Development System Reference Guide for more

information. If a wire is drawn so that it

overlaps the pin of a symbol, the two nets are not connected.

ngdbuild [option_name] design_name

Braces { }

Vertical bar |

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A list of items from which you must choose one or more

Separates items in a list of choices

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lowpwr ={on|off}

Conventions

Convention Meaning or Use Example

Vertical ellipsis

Horizontal ellipsis ...

Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Blue text

Red text

Blue, underlined text Hyperlink to a web-site (URL)

IOB #1: Name = QOUT’

. .

Repetitive material that has been omitted

Cross-reference link to a location in the current ﬁle or in another ﬁle in the current document

Cross-reference link to a location in another document

IOB #2: Name = CLKIN’ . . .

allow block block_name loc1 loc2 ... locn;

See the section “Additional

Resources” for details.

Refer to “Title Formats” in

Chapter 1 for details.

See Figure 2-5 in the Virtex-II

Handbook.

Go to http://www.xilinx.com for the latest speed ﬁles.

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Preface: About This Guide

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MicroBlaze Architecture

Overview

The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx ﬁeld programmable gate arrays (FPGAs).

Figure 1-1 shows a functional block diagram of the MicroBlaze core.

Chapter 1

IXCL_M

IXCL_S

Features

bus interface bus interface

I-Cache

IOPB

ILMB

Bus

Optional MicroBlaze feature

Program

Counter

Instruction

Special

Purpose

Registers

Buffer

Instruction

Decode

ALU Shift

Barrel Shift

Multiplier

Divider

FPU

32 X 32b

Figure 1-1: MicroBlaze Core Block Diagram

Data-sideInstruction-side

D-Cache

Bus

DXCL_M

DXCL_S

DOPB

DLMB

MFSL 0..7

SFSL 0..7

The MicroBlaze soft core processor is highly conﬁgurable, allowing users to select a speciﬁc set of features required by their design.

The processor’s ﬁxed feature set includes:

• Thirty-two 32-bit general purpose registers

• 32-bit instruction word with three operands and two addressing modes

• 32-bit address bus

• Single issue pipeline

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Chapter 1: MicroBlaze Architecture

In addition to these ﬁxed features the MicroBlaze processor is parametrized to allow selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze support a subset of the optional features described in this manual. Only the latest (active) version of MicroBlaze (v5.00a) supports all options.

Xilinx recommends that all new designs use the latest active version of the MicroBlaze processor.

Table 1-1: Conﬁgurable Feature Overview by MicroBlaze Version

MicroBlaze Versions

Feature

v2.10a v3.00a v4.00a v5.00a

Version Status deprecated deprecated deprecated active

Processor pipeline depth 3 3 35 On-chip Peripheral Bus (OPB) data side interface option option option option On-chip Peripheral Bus (OPB) instruction side interface option option option option Local Memory Bus (LMB) data side interface option option option option Local Memory Bus (LMB) instruction side interface option option option option Hardware barrel shifter option option option option Hardware divider option option option option Hardware debug logic option option option option Fast Simplex Link (FSL) interfaces 0-7 0-7 0-7 0-7 Machine status set and clear instructions option option option Yes Instruction cache over IOPB interface option option option No Data cache over IOPB interface option option option No Instruction cache over CacheLink (IXCL) interface - option option option Data cache over CacheLink (DXCL) interface - option option option 4 or 8-word cache line on XCL - 4 4 option Hardware exception support - option option option Pattern compare instructions - - option Yes Floating point unit (FPU) - - option option Disable hardware multiplier

- - option option Hardware debug readable ESR and EAR - - Yes Yes Processor Version Register (PVR) - - - option

1. Used in Virtex-II and subsequent families, for saving MUL18 and DSP48 primitives

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Data Types and Endianness

MicroBlaze uses Big-Endian, bit-reversed format to represent data. The hardware supported data types for MicroBlaze are word, half word, and byte. The bit and byte organization for each type is shown in the following tables.

Table 1-2: Word Data Type

Byte address n n+1 n+2 n+3 Byte label 0 1 2 3 Byte

signiﬁcance Bit label 0 31 Bit signiﬁcance MSBit LSBit

Table 1-3: Half Word Data Type

Byte address n n+1 Byte label 0 1 Byte

signiﬁcance Bit label 0 15 Bit signiﬁcance MSBit LSBit

Table 1-4: Byte Data Type

Byte address n Bit label 0 7

MSByte LSByte

Bit signiﬁcance MSBit LSBit

Instructions

All MicroBlaze instructions are 32 bits and are deﬁned as either Type A or TypeB. Type A instructions have up to two source register operands and one destination register operand. TypeB instructions have one sourceregister and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an IMM instruction). Type B instructions have a single destination register operand. Instructions are provided in the following functional categories: arithmetic, logical, branch, load/store, and special.

Table 1-6 lists the MicroBlaze instruction set. Refer to Chapter 4, “MicroBlaze Instruction Set Architecture”, for more information on these instructions. Table 1-5 describes the

instruction set nomenclature used in the semantics of each instruction.

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Chapter 1: MicroBlaze Architecture

Table 1-5: Instruction Set Nomenclature

Symbol Description

Ra R0 - R31, General Purpose Register, source operand a Rb R0 - R31, General Purpose Register, source operand b Rd R0 - R31, General Purpose Register, destination operand SPR[x] Special Purpose Register number x MSR Machine Status Register = SPR[1] ESR Exception Status Register = SPR[5] EAR Exception Address Register = SPR[3] FSR Floating Point Unit Status Register = SPR[7] PVRx Processor Version Register, where x is the register number = SPR[8192 + x] BTR Branch Target Register = SPR[11] PC Execute stage Program Counter = SPR[0]

x[y] Bit y of register x x[y:z] Bit range y to z of register x x Bit inverted value of register x

Imm 16 bit immediate value Immxx bit immediate value FSLx 3 bit Fast Simplex Link (FSL) port designator where x is the port number C Carry ﬂag, MSR[29] Sa Special Purpose Register, source operand Sd Special Purpose Register, destination operand s(x) Sign extend argument x to 32-bit value *Addr Memory contents at location Addr (data-size aligned) := Assignment operator = Equality comparison != Inequality comparison > Greater than comparison >= Greater than or equal comparison < Less than comparison <= Less than or equal comparison + Arithmetic add * Arithmetic multiply / Arithmetic divide >> x Bit shift right x bits

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Instructions

Table 1-5: Instruction Set Nomenclature

Symbol Description

<< x Bit shift left x bits and Logic AND or Logic OR xor Logic exclusive OR op1 if cond else op2 Perform op1 if condition cond is true, else perform op2 & Concatenate. E.g. “0000100 & Imm7” is the concatenation of the ﬁxed ﬁeld “0000100” and

a 7 bit immediate value.

signed Operation performed on signed integer data type. All arithmetic operations are performed

on signed word operands, unless otherwise speciﬁed unsigned Operation performed on unsigned integer data type ﬂoat Operation performed on ﬂoating point data type

Table 1-6: MicroBlaze Instruction Set Summary

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

ADD Rd,Ra,Rb 000000 Rd Ra Rb 00000000000 Rd := Rb + Ra RSUB Rd,Ra,Rb 000001 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1 ADDC Rd,Ra,Rb 000010 Rd Ra Rb 00000000000 Rd := Rb + Ra + C RSUBC Rd,Ra,Rb 000011 Rd Ra Rb 00000000000 Rd := Rb + Ra + C ADDK Rd,Ra,Rb 000100 Rd Ra Rb 00000000000 Rd := Rb + Ra RSUBK Rd,Ra,Rb 000101 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1 ADDKC Rd,Ra,Rb 000110 Rd Ra Rb 00000000000 Rd := Rb + Ra + C RSUBKC Rd,Ra,Rb 000111 Rd Ra Rb 00000000000 Rd := Rb + Ra + C CMP Rd,Ra,Rb 000101 Rd Ra Rb 00000000001 Rd := Rb + Ra + 1

Rd[0] := 0 if (Rb >= Ra) else Rd[0] := 1

CMPU Rd,Ra,Rb 000101 Rd Ra Rb 00000000011 Rd := Rb + Ra + 1 (unsigned)

Rd[0] := 0 if (Rb >= Ra, unsigned) else

Rd[0] := 1 ADDI Rd,Ra,Imm 001000 Rd Ra Imm Rd := s(Imm) + Ra RSUBI Rd,Ra,Imm 001001 Rd Ra Imm Rd := s(Imm) + Ra + 1 ADDIC Rd,Ra,Imm 001010 Rd Ra Imm Rd := s(Imm) + Ra + C RSUBIC Rd,Ra,Imm 001011 Rd Ra Imm Rd := s(Imm) + Ra + C ADDIK Rd,Ra,Imm 001100 Rd Ra Imm Rd := s(Imm) + Ra RSUBIK Rd,Ra,Imm 001101 Rd Ra Imm Rd := s(Imm) + Ra + 1

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Table 1-6: MicroBlaze Instruction Set Summary (Continued)

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) +

Ra + C MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00000000000 Rd : = 0 & (Ra >> Rb) BSRA Rd,Ra,Rb 010001 Rd Ra Rb 01000000000 Rd := s(Ra >> Rb) BSLL Rd,Ra,Rb 010001 Rd Ra Rb 10000000000 Rd := (Ra << Rb) & 0 MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm) BSRLI Rd,Ra,Imm 011001 Rd Ra 00000000000 &

Rd : = 0 & (Ra >> Imm5)

Imm5

BSRAI Rd,Ra,Imm 011001 Rd Ra 00000010000 &

Rd := s(Ra >> Imm5)

Imm5

BSLLI Rd,Ra,Imm 011001 Rd Ra 00000100000 &

Rd := (Ra << Imm5) & 0

Imm5 IDIV Rd,Ra,Rb 010010 Rd Ra Rb 00000000000 Rd := Rb/Ra IDIVU Rd,Ra,Rb 010010 Rd Ra Rb 00000000010 Rd := Rb/Ra, unsigned FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, ﬂoat FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, ﬂoat FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, ﬂoat FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, ﬂoat

FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000 Rd := 1 if (Rb = NaN or Ra = NaN, ﬂoat1)

else Rd := 0

FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000 Rd := 1 if (Rb < Ra, ﬂoat1) else

Rd := 0

FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000 Rd := 1 if (Rb = Ra, ﬂoat1) else

Rd := 0

FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000 Rd := 1 if (Rb <= Ra, ﬂoat1) else

Rd := 0

FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000 Rd := 1 if (Rb > Ra, ﬂoat1) else

Rd := 0

FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000 Rd := 1 if (Rb != Ra, ﬂoat1) else

Rd := 0

FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000 Rd := 1 if (Rb >= Ra, ﬂoat1) else

Rd := 0

GET Rd,FSLx 011011 Rd 00000 0000000000000 &

FSLx

Rd := FSLx (blocking data read) MSR[FSL] := 1 if (FSLx_S_Control = 1)

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Instructions

Table 1-6: MicroBlaze Instruction Set Summary (Continued)

Type A 0-5 6-10 11-15 16-20 21-31 Type B 0-5 6-10 11-15 16-31

Semantics

PUT Ra,FSLx 011011 00000 Ra 1000000000000 &

FSLx := Ra (blocking data write)

FSLx

NGET Rd,FSLx 011011 Rd 00000 0100000000000 &

FSLx

Rd := FSLx (non-blocking data read) MSR[FSL] := 1 if (FSLx_S_Control = 1) MSR[C] := not FSLx_S_Exists

NPUT Ra,FSLx 011011 00000 Ra 1100000000000 &

FSLx

CGET Rd,FSLx 011011 Rd 00000 0010000000000 &

FSLx

CPUT Ra,FSLx 011011 00000 Ra 1010000000000 &

FSLx := Ra (non-blocking data write) MSR[C] := FSLx_M_Full

Rd := FSLx (blocking control read) MSR[FSL] := 1 if (FSLx_S_Control = 0)

FSLx := Ra (blocking control write)

FSLx

NCGET Rd,FSLx 011011 Rd 00000 0110000000000 &

FSLx

Rd := FSLx (non-blocking control read) MSR[FSL] := 1 if (FSLx_S_Control = 0) MSR[C] := not FSLx_S_Exists

NCPUT Ra,FSLx 011011 00000 Ra 1110000000000 &

FSLx

FSLx := Ra (non-blocking control write)

MSR[C] := FSLx_M_Full OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and

PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else

Rd := 2 if (Rb[8:15] = Ra[8:15]) else

Rd := 3 if (Rb[16:23] = Ra[16:23]) else

Rd := 4 if (Rb[24:31] = Ra[24:31]) else

Rd := 0 PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rd = Ra) else

Rd := 0 PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rd != Ra) else

Rd := 0 SRA Rd,Ra 100100 Rd Ra 0000000000000001 Rd := s(Ra >> 1)

C := Ra[31] SRC Rd,Ra 100100 Rd Ra 0000000000100001 Rd := C & (Ra >> 1)

C := Ra[31] SRL Rd,Ra 100100 Rd Ra 0000000001000001 Rd := 0 & (Ra >> 1)

C := Ra[31] SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31]) SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31]) WIC Ra,Rb 100100 00000 Ra Rb 01101000 ICache_Tag := Ra WDC Ra,Rb 100100 00000 Ra Rb 01100100 DCache_Tag := Ra

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Table 1-6: MicroBlaze Instruction Set Summary (Continued)

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

MTS Sd,Ra 100101 00000 Ra 11 & Sd SPR[Sd] := Ra, where:

• SPR[0x0001] is MSR

• SPR[0x0007] is FSR

MFS Rd,Sa 100101 Rd 00000 10 & Sa Rd := SPR[Sa], where:

• SPR[0x0000] is PC

• SPR[0x0001] is MSR

• SPR[0x0003] is EAR

• SPR[0x0005] is ESR

• SPR[0x0007] is FSR

• SPR[0x000B] is BTR

• SPR[0x2000:0x200B] is PVR[0] to

PVR[11]

MSRCLR Rd,Imm 100101 Rd 00001 00 & Imm14 Rd := MSR

MSR := MSR and

Imm14

MSRSET Rd,Imm 100101 Rd 00000 00 & Imm14 Rd := MSR

MSR := MSR or Imm14 BR Rb 100110 00000 00000 Rb 00000000000 PC := PC + Rb BRD Rb 100110 00000 10000 Rb 00000000000 PC := PC + Rb BRLD Rd,Rb 100110 Rd 10100 Rb 00000000000 PC := PC + Rb

Rd := PC BRA Rb 100110 00000 01000 Rb 00000000000 PC := Rb BRAD Rb 100110 00000 11000 Rb 00000000000 PC := Rb BRALD Rd,Rb 100110 Rd 11100 Rb 00000000000 PC := Rb

Rd := PC BRK Rd,Rb 100110 Rd 01100 Rb 00000000000 PC := Rb

Rd := PC

MSR[BIP] := 1 BEQ Ra,Rb 100111 00000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0 BNE Ra,Rb 100111 00001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0 BLT Ra,Rb 100111 00010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0 BLE Ra,Rb 100111 00011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0 BGT Ra,Rb 100111 00100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0 BGE Ra,Rb 100111 00101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0 BEQD Ra,Rb 100111 10000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0 BNED Ra,Rb 100111 10001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0 BLTD Ra,Rb 100111 10010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0 BLED Ra,Rb 100111 10011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0

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Instructions

Table 1-6: MicroBlaze Instruction Set Summary (Continued)

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

BGTD Ra,Rb 100111 10100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0 BGED Ra,Rb 100111 10101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0 ORI Rd,Ra,Imm 101000 Rd Ra Imm Rd := Ra or s(Imm) ANDI Rd,Ra,Imm 101001 Rd Ra Imm Rd := Ra and s(Imm) XORI Rd,Ra,Imm 101010 Rd Ra Imm Rd := Ra xor s(Imm)

ANDNI Rd,Ra,Imm 101011 Rd Ra Imm Rd := Ra and

s(Imm) IMM Imm 101100 00000 00000 Imm Imm[0:15] := Imm RTSD Ra,Imm 101101 10000 Ra Imm PC := Ra + s(Imm) RTID Ra,Imm 101101 10001 Ra Imm PC := Ra + s(Imm)

MSR[IE] := 1

RTBD Ra,Imm 101101 10010 Ra Imm PC := Ra + s(Imm)

MSR[BIP] := 0

RTED Ra,Imm 101101 10100 Ra Imm PC := Ra + s(Imm)

MSR[EE] := 1 MSR[EIP] := 0

ESR := 0 BRI Imm 101110 00000 00000 Imm PC := PC + s(Imm) BRID Imm 101110 00000 10000 Imm PC := PC + s(Imm) BRLID Rd,Imm 101110 Rd 10100 Imm PC := PC + s(Imm)

Rd := PC BRAI Imm 101110 00000 01000 Imm PC := s(Imm) BRAID Imm 101110 00000 11000 Imm PC := s(Imm) BRALID Rd,Imm 101110 Rd 11100 Imm PC := s(Imm)

Rd := PC BRKI Rd,Imm 101110 Rd 01100 Imm PC := s(Imm)

Rd := PC

MSR[BIP] := 1 BEQI Ra,Imm 101111 00000 Ra Imm PC := PC + s(Imm) if Ra = 0 BNEI Ra,Imm 101111 00001 Ra Imm PC := PC + s(Imm) if Ra != 0 BLTI Ra,Imm 101111 00010 Ra Imm PC := PC + s(Imm) if Ra < 0 BLEI Ra,Imm 101111 00011 Ra Imm PC := PC + s(Imm) if Ra <= 0 BGTI Ra,Imm 101111 00100 Ra Imm PC := PC + s(Imm) if Ra > 0 BGEI Ra,Imm 101111 00101 Ra Imm PC := PC + s(Imm) if Ra >= 0 BEQID Ra,Imm 101111 10000 Ra Imm PC := PC + s(Imm) if Ra = 0 BNEID Ra,Imm 101111 10001 Ra Imm PC := PC + s(Imm) if Ra != 0 BLTID Ra,Imm 101111 10010 Ra Imm PC := PC + s(Imm) if Ra < 0

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Table 1-6: MicroBlaze Instruction Set Summary (Continued)

Type A 0-5 6-10 11-15 16-20 21-31

Semantics

Type B 0-5 6-10 11-15 16-31

BLEID Ra,Imm 101111 10011 Ra Imm PC := PC + s(Imm) if Ra <= 0 BGTID Ra,Imm 101111 10100 Ra Imm PC := PC + s(Imm) if Ra > 0 BGEID Ra,Imm 101111 10101 Ra Imm PC := PC + s(Imm) if Ra >= 0 LBU Rd,Ra,Rb 110000 Rd Ra Rb 00000000000 Addr := Ra + Rb

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7] LHU Rd,Ra,Rb 110001 Rd Ra Rb 00000000000 Addr := Ra + Rb

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15] LW Rd,Ra,Rb 110010 Rd Ra Rb 00000000000 Addr := Ra + Rb

Rd := *Addr SB Rd,Ra,Rb 110100 Rd Ra Rb 00000000000 Addr := Ra + Rb

*Addr[0:8] := Rd[24:31] SH Rd,Ra,Rb 110101 Rd Ra Rb 00000000000 Addr := Ra + Rb

*Addr[0:16] := Rd[16:31] SW Rd,Ra,Rb 110110 Rd Ra Rb 00000000000 Addr := Ra + Rb

*Addr := Rd LBUI Rd,Ra,Imm 111000 Rd Ra Imm Addr := Ra + s(Imm)

Rd[0:23] := 0

Rd[24:31] := *Addr[0:7] LHUI Rd,Ra,Imm 111001 Rd Ra Imm Addr := Ra + s(Imm)

Rd[0:15] := 0

Rd[16:31] := *Addr[0:15] LWI Rd,Ra,Imm 111010 Rd Ra Imm Addr := Ra + s(Imm)

Rd := *Addr SBI Rd,Ra,Imm 111100 Rd Ra Imm Addr := Ra + s(Imm)

*Addr[0:7] := Rd[24:31] SHI Rd,Ra,Imm 111101 Rd Ra Imm Addr := Ra + s(Imm)

*Addr[0:15] := Rd[16:31] SWI Rd,Ra,Imm 111110 Rd Ra Imm Addr := Ra + s(Imm)

*Addr := Rd

1. Due to the many differentcorner cases involved in ﬂoating point arithmetic, only the normal behavior is described. A full description of the behavior can be found in: Chapter 4, “MicroBlaze Instruction Set Architecture,”

Registers

MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to seven 32-bit special purpose registers, depending on conﬁgured options.

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Registers

General Purpose Registers

The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register ﬁle is reset on bit stream download (reset value is 0x00000000).

Note: The register ﬁle is not reset by the external reset inputs: reset and debug_rst.

0 31

↑

R0-R31

Figure 1-2: R0-R31

Table 1-7: General Purpose Registers (R0-R31)

Bits Name Description Reset Value

0:31 R0 R0 is deﬁned to always have thevalue

0x00000000 of zero. Anything written to R0 is discarded.

0:31 R1 through R13 R1 through R13 are 32-bit general

purpose registers

0:31 R14 32-bit used to store return addresses

for interrupts

0:31 R15 32-bit general purpose register 0:31 R16 32-bit used to store return addresses

for breaks

0:31 R17

0:31 R18 through R31 R18 through R31 are 32-bit general

If MicroBlaze is conﬁgured to support hardware exceptions, this register is loaded with HW exception return address (see also “Branch Target

purpose register

purpose registers.

Please refer to Table 3-2 for software conventions on general purpose register usage.

Special Purpose Registers

Program Counter (PC)

The Program Counter is the 32-bit address of the execution instruction. It can be read with an MFS instruction, but it can not be written to using an MTS instruction. When used with the MFS instruction the PC register is speciﬁed by setting Sa = 0x0000.

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0 31

Chapter 1: MicroBlaze Architecture

↑

Figure 1-3: PC

Table 1-8: Program Counter (PC)

Bits Name Description Reset Value

0:31 PC

Program Counter

0x00000000

Address of executing instruction, i.e. “mfs r2 0” will store the address of the mfs instruction itself in R2

Machine Status Register (MSR)

The Machine Status Register contains control and status bits for the processor. It can be read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry copy. MSR can be written using either an MTS instruction or the dedicated MSRSET and MSRCLR instructions.

When writing to the MSR, some of the bits will takes effect immediately (e.g Carry) and the remaining bits take effect one clock cycle later. Any value written to bit 0 is discarded. When used with an MTS or MFS instruction the MSR is speciﬁed by setting Sx = 0x0001.

0 21 22 23 24 25 26 27 28 29 30 31

↑ ↑ ↑↑↑↑ ↑↑↑↑↑↑↑

CC RESERVED PVR EIP EE DCE DZ ICE FSL BIP C IE BE

Figure 1-4: MSR

Table 1-9: Machine Status Register (MSR)

Bits Name Description Reset Value

0CC

Arithmetic Carry Copy

Copy of the Arithmetic Carry (bit 29).

CC is always the same as bit C. 1:20 Reserved 21 PVR

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Processor Version Register exists

0 No Processor Version Register

1 Processor Version Register exists

Read only

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Based on option C_PVR

Registers

Table 1-9: Machine Status Register (MSR) (Continued)

Bits Name Description Reset Value

22 EIP

23 EE

24 DCE

25 DZ

26 ICE

Exception In Progress

0 No hardware exception in progress

1 Hardware exception in progress

Read/Write

Exception Enable

0 Hardware exceptions disabled

1 Hardware exceptions enabled

Read/Write

Data Cache Enable

0 Data Cache is Disabled

1 Data Cache is Enabled

Read/Write

Division by Zero

0 No division by zero has occurred

1 Division by zero has occurred

Read/Write

Instruction Cache Enable

0 Instruction Cache is Disabled

1 Instruction Cache is Enabled

Read/Write

27 FSL

28 BIP

FSL Error

0 FSL get/put had no error

1 FSL get/put had mismatch in

control type

Read/Write

Break in Progress

0 No Break in Progress

1 Break in Progress

Source of break can be software break

instruction or hardware break from

Ext_Brk or Ext_NM_Brk pin.

Read/Write

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Table 1-9: Machine Status Register (MSR) (Continued)

Bits Name Description Reset Value

29 C

Arithmetic Carry

0 No Carry (Borrow)

1 Carry (No Borrow)

Read/Write 30 IE

Interrupt Enable

0 Interrupts disabled

1 Interrupts enabled

Read/Write 31 BE

Buslock Enable

0 Buslock disabled on data-side OPB

1 Buslock enabled on data-side OPB

Buslock Enable does not affect

operation of IXCL, DXCL, ILMB,

DLMB, or IOPB.

Read/Write

1. This bit is only used for integer divide-by-zero signaling. There is a ﬂoating point equivalent in the FSR. The DZ-bit will ﬂag divide by zero conditions regardless if the processor is conﬁgured with exception handling or not.

2. For a details on the OPB protocol, please refer to the IBM CoreConnect speciﬁcation: 64-Bit On-Chip Peripheral Bus, Architectural Speciﬁcations, Version 2.0.

Exception Address Register (EAR)

The Exception Address Register stores the full load/store address that caused the exception. For an unaligned access exception that means the unaligned access address,and for an DOPB exception, the failing OPB data access address. The contents of this register is undeﬁned for all other exceptions. When read with the MFS instruction the EAR is speciﬁed by setting Sa = 0x0003.

0 31

↑

EAR

Figure 1-5: EAR

Table 1-10: Exception Address Register (EAR)

Bits Name Description Reset Value

0:31 EAR Exception Address Register 0x00000000

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Registers

Exception Status Register (ESR)

The Exception Status Register contains status bits for the processor. When read with the MFS instruction the ESR is speciﬁed by setting Sa = 0x0005.

19 20 26 27 31

↑↑↑↑

RESERVED

Figure 1-6: ESR

Table 1-11: Exception Status Register (ESR)

Bits Name Description Reset Value

0:18 Reserved

ESS EC

19 DS

20:26 ESS

27:31 EC

Exception in delay slot.

0 not caused by delay slot instruction 1 caused by delay slot instruction

Read-only

Exception Speciﬁc Status

For details refer to Table 1-12. Read-only

Exception Cause

00001 = Unaligned data access exception 00010 = Illegal op-code exception 00011 = Instruction bus error exception 00100 = Data bus error exception 00101 = Divide by zero exception 00110 = Floating point unit exception

Read-only

See Table 1-12

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Table 1-12: Exception Speciﬁc Status (ESS)

Exception

Cause

Bits Name Description Reset Value

Unaligned Data Access

Illegal Instruction

Instruction bus error

Data bus error

Divide by zero

Floating point unit

20 W

Word Access Exception

0 unaligned halfword access 1 unaligned word access

21 S Store Access Exception

0 unaligned load access 1 unaligned store access

22:26 Rx

Source/Destination Register

General purpose register used as source (Store) or destination (Load) in unaligned access

20:26 Reserved 0

Branch Target Register (BTR)

The Branch Target Register only exists if the MicroBlaze processor is conﬁgured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (i.e. ESR[DS]=1) then the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in r17. When read with the MFS instruction the BTR is speciﬁed by setting Sa = 0x000B.

0 31

↑

BTR

Figure 1-7: BTR

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Registers

Table 1-13: Branch Target Register (BTR)

Bits Name Description Reset Value

0:31 BTR Branch target address used by handler

0x00000000 when returning from an exception caused by an instruction in a delay slot

Read-only

Floating Point Status Register (FSR)

The Floating Point Status Register contains status bits for the ﬂoating point unit. It can be read with an MFS, and written with an MTS instruction. When read or written, the register is speciﬁed by setting Sa = 0x0007.

27 28 29 30 31

↑ ↑↑↑↑↑

RESERVED IO DZ OF UF DO

Figure 1-8: FSR

Table 1-14: Floating Point Status Register (FSR)

Bits Name Description Reset Value

0:26 Reserved undeﬁned 27 IO 28 DZ 29 OF 30 UF 31 DO

Invalid operation Divide-by-zero Overﬂow Underﬂow Denormalized operand error

Processor Version Register (PVR)

The Processor Version Register is controlled by the C_PVR conﬁguration option on MicroBlaze. When C_PVR is set to 0 the processor does not implement any PVR and MSR[PVR]=0. If C_PVR is set to 1 then MicroBlaze implements only the ﬁrst register: PVR0, and if set to 2 all 12 PVR registers (PVR0 to PVR11) are implemented.

When read with the MFS instruction the PVR is speciﬁed by setting Sa = 0x200x, with x being the register number between 0x0 and 0xB.

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Table 1-15: Processor Version Register 0 (PVR0)

Bits Name Description Value

0 CFG PVR implementation: 0=basic,

Based on C_PVR

1=full 1 BS Use barrel shifter C_USE_BARREL 2 DIV Use divider C_USE_DIV 3 MUL Use hardware multiplier C_USE_HW_MUL 4 FPU Use FPU C_USE_FPU 5 EXC Use any type of exceptions Based on C_*_EXCEPTION 6 ICU Use instruction cache C_USE_ICACHE 7 DCU Use data cache C_USE_DCACHE 8:15 Reserved 0 16:23 MBV MicroBlaze release version code

Release Speciﬁc

0x1 = v5.00.a 24:31 USR1 User conﬁgured value 1 C_PVR_USER1

Table 1-16: Processor Version Register 1 (PVR1)

Bits Name Description Value

0:31 USR2 User conﬁgured value 2 C_PVR_USER2

Table 1-17: Processor Version Register 2 (PVR2)

Bits Name Description Value

0 DOPB Data side OPB in use C_D_OPB 1 DLMB Data side LMB in use C_D_LMB 2 IOPB Instruction side OPB in use C_I_OPB 3 IOPB Instruction side OPB in use C_I_LMB 4 IRQEDGE Interrupt is edge triggered C_INTERRUPT_IS_EDGE 5 IRQPOS Interrupt edge is positive C_EDGE_IS_POSITIVE 6:16 Reserved 17 BS Use barrel shifter C_USE_BARREL 18 DIV Use divider C_USE_DIV 19 MUL Use hardware multiplier C_USE_HW_MUL 20 FPU Use FPU C_USE_FPU 21:24 Reserved

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Registers

Table 1-17: Processor Version Register 2 (PVR2) (Continued)

Bits Name Description Value

25 OP0EXEC Generate exception for 0x0

illegal opcode

26 UNEXEC Generate exception for

unaligned data access

27 OPEXEC Generate exception for any

illegal opcode

28 IOPBEXEC Generate exception for IOPB

error

29 DOPBEXEC Generate exception for DOPB

error

30 DIVEXEC Generate exception for division

by zero

31 FPUEXEC Generate exceptions from FPU C_FPU_EXCEPTION

Table 1-18: Processor Version Register 3 (PVR3)

Bits Name Description Value

0 DEBUG Use debug logic C_DEBUG_ENABLED 1:2 Reserved

C_OPCODE_0x0_ILLEGAL

C_UNALIGNED_EXCEPTION

C_ILL_OPCODE_EXCEPTION

C_IOPB_BUS_EXCEPTION

C_DOPB_BUS_EXCEPTION

C_DIV_ZERO_EXCEPTION

3:6 PCBRK Number of PC breakpoints C_NUMBER_OF_PC_BRK 7:9 Reserved 10:12 RDADDR Number of read address

breakpoints

C_NUMBER_OF_RD_ADDR_B

RK 13:15 Reserved 16:18 WRADDR Number of write address

breakpoints

C_NUMBER_OF_WR_ADDR_B

RK 19:21 Reserved 22:24 FSL Number of FSLs C_FSL_LINKS 25:31 Reserved

Table 1-19: Processor Version Register 4 (PVR4)

Bits Name Description Value

0 ICU Use instruction cache C_USE_ICACHE 1:5 ICTS Instruction cache tag size C_ADDR_TAG_BITS 6 Reserved 1 7 ICW Allow instruction cache write C_ALLOW_ICACHE_WR

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Chapter 1: MicroBlaze Architecture

Table 1-19: Processor Version Register 4 (PVR4) (Continued)

Bits Name Description Value

8:10 ICLL Instruction cache line length

C_ICACHE_LINE_LEN

2^n 11:15 ICBS Instruction cache byte size 2^n C_CACHE_BYTE_SIZE 16:31 Reserved 0

Table 1-20: Processor Version Register 5 (PVR5)

Bits Name Description Value

0 DCU Use data cache C_USE_DCACHE 1:5 DCTS Data cache tag size C_DCACHE_ADDR_TAG 6 Reserved 1 7 DCW Allow data cache write C_ALLOW_DCACHE_WR 8:10 DCLL Data cache line length 2^n C_DCACHE_LINE_LEN 11:15 DCBS Data cache byte size 2^n C_DCACHE_BYTE_SIZE 16:31 Reserved 0

Table 1-21: Processor Version Register 6 (PVR6)

Bits Name Description Value

0:31 ICBA InstructionCache Base Address C_ICACHE_BASEADDR

Table 1-22: Processor Version Register 7 (PVR7)

Bits Name Description Value

0:31 ICHA Instruction Cache High

C_ICACHE_HIGHADDR

Address

Table 1-23: Processor Version Register 8 (PVR8)

Bits Name Description Value

0:31 DCBA Data Cache Base Address C_DCACHE_BASEADDR

Table 1-24: Processor Version Register 9 (PVR9)

Bits Name Description Value

0:31 DCHA Data Cache High Address C_DCACHE_HIGHADDR

30 www.xilinx.com MicroBlaze Processor Reference Guide

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Online Document

MicroBlaze Architecture

Overview

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