Xilinx DS610 User Manual

1

Spartan-3A DSP FPGA Family Data Sheet

DS610 October 4, 2010 Product Specification

Module 1: Introduction and Ordering Information

DS610 (v3.0) October 4, 2010

• Introduction

• Features

• Architectural Overview

• Configuration Overview

• General I/O Capabilities

• Supported Packages and Package Marking

• Ordering Information

Module 2: Functional Description

DS610 (v3.0) October 4, 2010

The functionality of the Spartan®-3A DSP FPGA family is described in the following documents.

• UG331

• Clocking Resources

• Digital Clock Managers (DCMs)

•Block RAM

• Configurable Logic Blocks (CLBs)

• I/O Resources

• Programmable Interconnect

• ISE® Software Design Tools and IP Cores

• Embedded Processing and Control Solutions

• Pin Types and Package Overview

• Package Drawings

• Powering FPGAs

• Power Management

• UG332

• Configuration Overview

• Configuration Pins and Behavior

• Bitstream Sizes

• Detailed Descriptions by Mode

• ISE iMPACT Programming Examples

• MultiBoot Reconfiguration

• Design Authentication using Device DNA

: Spartan-3 Generation FPGA User Guide

- Distributed RAM

- SRL16 Shift Registers

- Carry and Arithmetic Logic

: Spartan-3 Generation Configuration User Guide

- Master Serial Mode using Platform Flash PROM

- Master SPI Mode using Commodity Serial Flash

- Master BPI Mode using Commodity Parallel Flash

- Slave Parallel (SelectMAP) using a Processor

- Slave Serial using a Processor

- JTAG Mode

• UG431

FPGAs User Guide

• DSP48A Slice Design Considerations

• DSP48A Architecture Highlights

• DSP48A Application Examples

: XtremeDSP™ DSP48A for Spartan-3A DSP

- 18 x 18-Bit Multipliers

- 48-Bit Accumulator

- 18-bit Pre-Adder

Module 3: DC and Switching Characteristics

DS610 (v3.0) October 4, 2010

• DC Electrical Characteristics

• Absolute Maximum Ratings

• Supply Voltage Specifications

• Recommended Operating Conditions

• Switching Characteristics

• I/O Timing

• Configurable Logic Block (CLB) Timing

• Digital Clock Manager (DCM) Timing

• Block RAM Timing

• XtremeDSP Slice Timing

• Configuration and JTAG Timing

Module 4: Pinout Descriptions

DS610 (v3.0) October 4, 2010

• Pin Descriptions

• Package Overview

• Pinout Tables

• Footprint Diagrams

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 October 4, 2010 www.xilinx.com Product Specification 1

6

Spartan-3A DSP FPGA Family:

Introduction and Ordering Information

DS610 (v3.0) October 4, 2010 Product Specification

Introduction

The Spartan®-3A DSP family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high- volume, cost-sensitive, high-performance DSP applications. two-member family offers densities ranging from

The

1.8 to 3.4

million

system gates, as shown in Ta b l e 1 . The Spartan-3A DSP family builds on the success of the

Spartan-3A FPGA family by increasing the amount of memory per logic and adding XtremeDSP™ DSP48A slices. New features improve system performance and reduce the cost of configuration. These Spartan-3A DSP FPGA enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic

and DSP processing

industry.

The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A FPGA family. The XC3SD1800A and the XC3SD3400A devices are tailored for DSP applications and have additional block RAM and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices replace the 18x18 multipliers found in the Spartan-3A devices and are based on the DSP48 blocks found in the Virtex®-4 devices. The block RAMs are also enhanced to run faster by adding an output register. Both the block RAM and DSP48A slices in the Spartan-3A DSP devices run at 250 MHz in the lowest cost, standard -4 speed grade.

Because of their exceptional DSP price/performance ratio, Spartan-3A DSP FPGAs are ideally suited to a wide range of consumer electronics applications, such as broadband access, home networking, display/projection, and digital television.

The Spartan-3A DSP family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Features

• Very low cost, high-performance DSP solution for high-volume, cost-conscious applications

• 250 MHz XtremeDSP DSP48A Slices

• Dedicated 18-bit by 18-bit multiplier

• Available pipeline stages for enhanced performance of at

least 250 MHz in the standard -4 speed grade

• 48-bit accumulator for multiply-accumulate (MAC) operation

• Integrated adder for complex multiply or multiply-add

operation

• Integrated 18-bit pre-adder

• Optional cascaded Multiply or MAC

• Hierarchical SelectRAM™ memory architecture

• Up to 2268 Kbits of fast block RAM with byte write enables for processor applications

• Up to 373 Kbits of efficient distributed RAM

• Registered outputs on the block RAM with operation of at

• Dual-range V

• Suspend, Hibernate modes reduce system power

least 280 MHz in the standard -4 speed grade

supply simplifies 3.3V-only design

CCAUX

• Low-power option reduces quiescent current

• Multi-voltage, multi-standard SelectIO™ interface pins

• Up to 519 I/O pins or 227 differential signal pairs

• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

• Selectable output drive, up to 24 mA per pin

• QUIETIO standard reduces I/O switching noise

• Full 3.3V ± 10% compatibility and hot swap compliance

• 622+ Mb/s data transfer rate per differential I/O

• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

• Enhanced Double Data Rate (DDR) support

• DDR/DDR2 SDRAM support up to 333 Mb/s

• Fully compliant 32-/64-bit, 33/66 MHz PCI support

• Abundant, flexible logic resources

• Densities up to 53712 logic cells, including optional shift register

• Efficient wide multiplexers, wide logic, fast carry logic

• IEEE 1149.1/1532 JTAG programming/debug port

• Eight Digital Clock Managers (DCMs)

• Clock skew elimination (delay locked loop)

• Frequency synthesis, multiplication, division

• High-resolution phase shifting

• Wide frequency range (5 MHz to over 320 MHz)

• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing

• Configuration interface to industry-standard PROMs

• Low-cost, space-saving SPI serial Flash PROM

• x8 or x8/x16 BPI parallel NOR Flash PROM

• Low-cost Xilinx® Platform Flash

• Unique Device DNA identifier for design authentication

• Load multiple bitstreams under FPGA control

• Post-configuration CRC checking

with JTAG

• MicroBlaze™ and PicoBlaze™ embedded processor cores

• BGA and CSP packaging with Pb-free options

• Common footprints support easy density migration

• XA Automotive version available

Table 1: Summary of Spartan-3A DSP FPGA Attributes

Device

XC3SD1800A 1800K 37,440 88 48 4,160 16,640 260K 1512K 84 8 519 227 XC3SD3400A 3400K 53,712 104 58 5,968 23,872 373K 2268K 126 8 469 213

Notes:

1. By convention, one Kb is equivalent to 1,024 bits.

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

System

Gates

Equivalent

Logic Cells

CLB Array (One CLB = Four Slices)

Tot al

CLBs

Tot al

Slices

Distributed

RAM

Bits

Block

RAM

(1)

Bits

(1)

DSP48As DCMs

Maximum

User I/O

Maximum

Differential

I/O PairsRows Columns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 2

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

CLB

Block RAM

DCM

IOBs

DS610-1_01_031207

IOBs

DCM

Block RAM / DSP48A Slice

DCM

CLBs

IOBs

DSP48A Slice

Notes:

1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A columns of the 4 or 5 columns in the selected device, as shown in the diagram above.

2. A detailed diagram of the DSP48A can be found in UG431

: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.

Architectural Overview

The Spartan-3A DSP family architecture consists of five fundamental programmable functional elements:

• XtremeDSP™ DSP48A Slice provides an 18-bit x 18-bit multiplier, 18-bit pre-adder, 48-bit post-adder/accumulator, and cascade capabilities for various DSP applications.

• Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

• Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.

• Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included.

X-Ref Target - Figure 1

• Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. The XC3SD1800A has four columns of DSP48As, and the XC3SD3400A has five columns of DSP48As. Each DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the 4 or 5 columns of block RAM and DSP48As.

The Spartan-3A DSP family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 3

Figure 1: Spartan-3A DSP Family Architecture

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

Configuration

Spartan-3A DSP FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes:

• Master Serial from a Xilinx Platform Flash PROM

• Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash

• Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash

• Slave Serial, typically downloaded from a processor

• Slave Parallel, typically downloaded from a processor

• Boundary Scan (JTAG), typically downloaded from a processor or system tester

Furthermore, Spartan-3A DSP FPGAs support MultiBoot configuration, allowing two or more FPGA configuration bitstreams to be stored in a single SPI serial Flash or a BPI parallel NOR Flash. The FPGA application controls which configuration to load next and when to load it.

Additionally, each Spartan-3A DSP FPGA contains a unique, factory-programmed Device DNA identifier useful for tracking purposes, anti-cloning designs, or IP protection.

I/O Capabilities

The Spartan-3A DSP FPGA SelectIO interface supports many popular single-ended and differential standards.

Ta bl e 2 shows the number of user I/Os as well as the

number of differential I/O pairs available for each device/package combination. Some of the user I/Os are unidirectional input-only pins as indicated in Tab l e 2 .

Spartan-3A DSP FPGAs support the following single-ended standards:

• 3.3V low-voltage TTL (LVTTL)

• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,

1.5V, or 1.2V

• 3.3V PCI at 33 MHz or 66 MHz

• HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications

• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications

• Spartan-3A DSP FPGAs support the following differential standards:

• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or

3.3V

• Bus LVDS I/O at 2.5V

• TMDS I/O at 3.3V

• Differential HSTL and SSTL I/O

• LVPECL inputs at 2.5V or 3.3V

Tab le 2 : Available User I/Os and Differential (Diff) I/O Pairs

CS484

(1)

CSG484

140

(78)

140 (78)

519

(110)

469

(60)

Device

User Diff User Diff

XC3SD1800A

XC3SD3400A

Notes:

1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs.

309

(60)

309

(60)

FG676

FGG676

227

(131)

213

(117)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 4

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

-4 CS 484 LI

Device Type

Speed Grade

Power/Temperature Range

Package Type

Number of Pins

Example:

DS610-1_05_021009

XC3SD1800A

Package Marking

Figure 2 shows the top marking for Spartan-3A DSP FPGAs. The “5C” and “4I” Speed Grade/Temperature Range part

combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range.

X-Ref Target - Figure 2

BGA Ball A1

Device Type

Package

Low-Power

(optional)

Speed Grade

Operating Range

R

SPARTAN

R

XC3SD1800A CSG484XGQ####

X#######X

L4 I

Mask Revision

Fabrication/ Process Code

Date Code Lot Code

DS610-1_02_070607

Figure 2: Spartan-3A DSP FPGA Package Marking Example

Ordering Information

Spartan-3A DSP FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a ‘G’ character in the ordering code.

Device Speed Grade Package Type / Number of Pins

XC3SD1800A -4 Standard Performance CS484/

484-ball Chip-Scale Ball Grid Array (CSBGA) C Commercial (0°C to 85°C)

Power/Temperature Range

CSG484

XC3SD3400A -5 High Performance

FG676/

676-ball Fine-Pitch Ball Grid Array (FBGA) I Industrial (–40°C to 100°C)

(1)

FGG676

LI Low-power Industrial

Notes:

1. The -5 speed grade is exclusively available in the Commercial temperature range.

2. The low-power option (LI) is exclusively available in the CS(G)484 package and industrial temperature range.

3. See DS705

, XA Spartan-3A DSP Automotive FPGA Family Data Sheet for the XA Automotive Spartan-3A DSP FPGAs.

(T

)

J

(–40°C to 100°C)

(2)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 5

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/07 1.0 Initial Xilinx release.

05/25/07 1.0.1 Minor edits.

06/18/07 1.2 Updated for Production release.

07/16/07 2.0 Added Low-power options.

06/02/08 2.1 Added reference to SCD 4103 for 750 Mbps performance. Add dual mark clarification to Package

Marking. Updated links.

03/11/09 2.2 Simplified ordering information. Removed reference to SCD 4103.

10/04/10 3.0 Updated the Notice of Disclaimer section.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

CRITICAL APPLICATIONS DISCLAIMER

XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.

AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

. THIS LIMITED

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 6

8

Spartan-3A DSP FPGA Family:

Functional Description

DS610 (v3.0) October 4, 2010 Product Specification

Spartan-3A DSP FPGA Design Documentation

The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. The topics covered in each guide are listed.

• DS706

• UG331

• Clocking Resources

• Digital Clock Managers (DCMs)

• Block RAM

• Configurable Logic Blocks (CLBs)

• I/O Resources

• Programmable Interconnect

• ISE® Software Design Tools

•IP Cores

• Embedded Processing and Control Solutions

• Pin Types and Package Overview

• Package Drawings

• Powering FPGAs

• Power Management

• UG332

Guide

• Configuration Overview

• Detailed Descriptions by Mode

• ISE iMPACT Programming Examples

• MultiBoot Reconfiguration

• Design Authentication using Device DNA

: Extended Spartan-3A Family Overview

: Spartan-3 Generation FPGA User Guide

- Distributed RAM

- SRL16 Shift Registers

- Carry and Arithmetic Logic

: Spartan-3 Generation Configuration User

- Configuration Pins and Behavior

- Bitstream Sizes

- Master Serial Mode using Xilinx Platform Flash

PROM

- Master SPI Mode using Commodity SPI Serial Flash PROM

- Master BPI Mode using Commodity Parallel NOR Flash PROM

- Slave Parallel (SelectMAP) using a Processor

- Slave Serial using a Processor

- JTAG Mode

• UG431

FPGAs User Guide

• XtremeDSP DSP48A Slices

• XtremeDSP DSP48A Pre-Adder

For specific hardware examples, please see the Spartan-3A DSP FPGA Starter Kit board web pages.

• XtremeDSP Starter Platform—Spartan-3A DSP

1800A Edition

http://www.xilinx.com/products/devkits /HW-SD1800A-DSP-SB-UNI-G.htm

• XtremeDSP Starter Kit—Spartan-3A DSP 1800A

Edition

http://www.xilinx.com/products/devkits /DO-SD1800A-DSP-SK-UNI-G.htm

• XtremeDSP Video Starter Kit—Spartan-3A DSP

Edition

http://www.xilinx.com/products/devkits /DO-S3ADSP-VIDEO-SK-UNI-G.htm

• Embedded Development HW/SW Kit—Spartan-3A

DSP S3D1800A MicroBlaze Processor Edition

http://www.xilinx.com/products/devkits /DO-SD1800A-EDK-DK-UNI-G.htm

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated.

• Sign Up for Alerts on Xilinx.com

https://secure.xilinx.com/webreg/register.do?group=my profile&languageID=1

: XtremeDSP DSP48A for Spartan-3A DSP

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 7

Spartan-3A DSP FPGA Family: Functional Description

Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/07 1.0 Initial Xilinx release.

05/25/07 1.0.1 Minor edits.

06/18/07 1.2 Updated for Production release.

07/16/07 2.0 Added Low-power options; no changes to this module.

06/02/08 2.1 Updated links.

03/11/09 2.2 Added link to DS706 on Extended Spartan-3A family.

10/04/10 3.0 Updated link to sign up for Alerts and updated Notice of Disclaimer.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

CRITICAL APPLICATIONS DISCLAIMER

XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.

AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

. THIS LIMITED

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 8

61

Spartan-3A DSP FPGA Family:

DC and Switching Characteristics

DS610 (v3.0) October 4, 2010 Product Specification

DC Electrical Characteristics

In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:

Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production.

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless

otherwise noted, the published parameter values apply to all Spartan®-3A DSP devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.

Absolute Maximum Ratings

Preliminary: Based on characterization. Further changes

are not expected.

Stresses beyond those listed under Ta bl e 3 : Absolute Maximum Ratings may cause permanent damage to the

Production: These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected.

device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability.

Tab le 3 : Absolute Maximum Ratings

Symbol Description Conditions Min Max Units

V

CCINT

V

CCAUX

V

CCO

V

REF

V

I

V

ESD

T

STG

Notes:

1. Upper clamp applies only when using PCI IOSTANDARDs.

2. For soldering guidelines, see UG112 Guidelines for Pb-Free Packages.

Internal supply voltage –0.5 1.32 V

Auxiliary supply voltage –0.5 3.75 V

Output driver supply voltage –0.5 3.75 V

Input reference voltage –0.5 V

Voltage applied to all User I/O pins and

IN

Dual-Purpose pins

Voltage applied to all Dedicated pins –0.5 4.6 V

Input clamp current per I/O pin –0.5V < VIN<(V

IK

Electrostatic Discharge Voltage Human body model ±2000 V–

Junction temperature –125°C

J

Storage temperature –65 150 °C

: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow

Driver in a high-impedance state

CCO

Charged device model

Machine model

+0.5V)

(1)

–0.95 4.6 V

–±100mA

–±500V

–±200V

+0.5 V

CCO

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 9

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Power Supply Specifications

Tab le 4 : Supply Voltage Thresholds for Power-On Reset

Symbol Description Min Max Units

V

CCINTT

V

CCAUXT

V

CCO2T

Notes:

1. V

, V

CCINT

Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply V information).

CCAUX

CCINT

2. To ensure successful power-on, V no dips at any point.

Tab le 5 : Supply Voltage Ramp Rate

Symbol Description Min Max Units

V

CCINTR

V

CCAUXR

V

CCO2R

Notes:

1. V

2. To ensure successful power-on, V

Tab le 6 :

, V

CCINT

Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply V information).

CCAUX

CCINT

no dips at any point.

Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data

Symbol Description Min Units

V

DRINT

V

DRAUX

Threshold for the V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI

CCO

supply 0.4 1.0 V

CCINT

supply 1.0 2.0 V

CCAUX

Bank 2 supply 1.0 2.0 V

CCO

last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more

, V

CCINT

Ramp rate from GND to valid V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI

CCO

Bank 2, and V

CCO

CCINT

CCAUX

CCO

supplies must rise through their respective threshold-voltage ranges with

CCAUX

supply level 0.2 100 ms

Bank 2 supply level 0.2 100 ms

last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more

, V

CCINT

V

level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V

CCINT

V

level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V

CCAUX

Bank 2, and V

CCO

supplies must rise through their respective threshold-voltage ranges with

CCAUX

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 10

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

General Recommended Operating Conditions

Tab le 7 : General Recommended Operating Conditions

Symbol Description Min Nominal Max Units

T

J

V

CCINT

(1)

V

CCO

V

CCAUX

(3)

V

IN

T

IN

Notes:

1. This V range specific to each of the single-ended I/O standards, and Ta bl e 1 2 lists that specific to the differential standards.

2. Define V

range spans the lowest and highest operating voltages for all supported I/O standards. Tab l e 10 lists the recommended V

CCO

CCAUX

3. See XAPP459

4. For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331

5. Measured between 10% and 90% V

Junction temperature Commercial 0 –85°C

Industrial –40 –100°C

Internal supply voltage 1.14 1.20 1.26 V

Output driver supply voltage 1.10 –3.60V

Auxiliary supply voltage

Input voltage PCI™ IOSTANDARD –0.5 –V

Input signal transition time

(2)

V

CCAUX

V

CCAUX

All other IOSTANDARDs

(5)

= 2.5 2.25 2.50 2.75 V

= 3.3 3.00 3.30 3.60 V

CCO

IP or IO_# –0.5 –4.10V

IO_Lxxy_#

(4)

–0.5 –4.10V

– – 500 ns

selection using CONFIG VCCAUX constraint.

, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.

of –0.2V to –0.5V is supported but can cause increased leakage

, Spartan-3 Generation FPGA User Guide.

. Follow Signal Integrity recommendations.

CCO

IN

+0.5 V

CCO

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 11

General DC Characteristics for I/O Pins

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 8 : General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins

(1)

Symbol Description Test Conditions Min Typ Max Units

(2)

I

RPU

R

I

RPD

R

I

PU

PD

Leakage current at User I/O,

L

Input-only, Dual-Purpose, and Dedicated pins, FPGA powered

Leakage current on pins during

HS

hot socketing, FPGA unpowered

(3)

Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins. Dedicated pins are powered by V

.

CCAUX

(3)

Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on I

(3)

Current through pull-down

per Note 2)

RPU

resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins

(3)

Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on I

per Note 2)

RPD

Driver is in a high-impedance state, V

=0V or V

IN

max, sample-tested

CCO

All pins except INIT_B, PROG_B, DONE, and JTAG pins when PUDC_B = 1.

INIT_B, PROG_B, DONE, and JTAG pins or other pins when PUDC_B = 0.

VIN = GND V

= GND V

V

IN

V

CCAUX

VIN = V

CCO

= 3.0V to 3.6V VIN = 3.0V to 3.6V 5.5 10.4 20.8 kΩ

V

CCO

V

or V

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCAUX

= 3.0V to 3.6V –151 –315 –710 µA

CCAUX

= 2.3V to 2.7V –82 –182 –437 µA

CCAUX

= 1.7V to 1.9V –36 –88 –226 µA

= 1.4V to 1.6V –22 –56 –148 µA

= 1.14V to 1.26V –11 –31 –83 µA

= 3.0V to 3.6V 5.1 11.4 23.9 kΩ

= 2.3V to 2.7V 6.2 14.8 33.1 kΩ

= 1.7V to 1.9V 8.4 21.6 52.6 kΩ

= 1.4V to 1.6V 10.8 28.4 74.0 kΩ

= 1.14V to 1.26V 15.3 41.1 119.4 kΩ

= 3.0V to 3.6V 167 346 659 µA

= 2.25V to 2.75V

VIN = 2.3V to 2.7V 4.1 7.8 15.7 kΩ

VIN = 1.7V to 1.9V 3.0 5.7 11.1 kΩ

V

= 1.4V to 1.6V 2.7 5.1 9.6 kΩ

IN

–10

–+10µA

–10 –+10µA

Add I

HS

+ I

RPU

µA

100 225 457 µA

VIN = 1.14V to 1.26V 2.4 4.5 8.1 kΩ

= 2.25V to 2.75V VIN = 3.0V to 3.6V 7.9 16.0 35.0 kΩ

CCAUX

V

= 2.3V to 2.7V 5.9 12.0 26.3 kΩ

IN

= 1.7V to 1.9V 4.2 8.5 18.6 kΩ

V

IN

V

= 1.4V to 1.6V 3.6 7.2 15.7 kΩ

IN

V

= 1.14V to 1.26V 3.0 6.0 12.5 kΩ

IN

levels –10 –+10µA

CCO

V

= 3.3V ± 10% LVDS_33, MINI_LVDS_33,

CCO

V

= 2.5V ± 10% LVDS_25, MINI_LVDS_25,

CCO

RSDS_33

RSDS_25

90 100 115 Ω

90 110 – Ω

I

REF

C

R

V

current per pin All V

REF

Input capacitance – – –10pF

IN

Resistance of optional

DT

differential termination circuit within a differential I/O pair. Not available on Input-only pairs.

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 .

2. For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331

3. This parameter is based on characterization. The pull-up resistance R

, Spartan-3 Generation FPGA User Guide.

of –0.2V to –0.5V is supported but can cause increased leakage

IN

PU

= V

CCO/IRPU

. The pull-down resistance RPD=VIN/I

RPD

.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 12

Quiescent Current Requirements

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 9 : Quiescent Supply Current Characteristics

Symbol Description Device Power Typical

I

CCINTQ

Quiescent V

supply current XC3SD1800A C,I 41 390 500 mA

CCINT

(1)

LI 36

(2)

Commercial

Maximum

(2)

Industrial

Maximum

– 175 mA

(2)

Units

XC3SD3400A C,I 64 550 725 mA

I

CCOQ

Quiescent V

LI 55

supply current XC3SD1800A C,I 0.4 4 5 mA

CCO

– 300 mA

LI 0.2 –5mA

XC3SD3400A C,I 0.4 4 5 mA

I

CCAUXQ

Quiescent V

LI 0.2

supply current XC3SD1800A C,I 25 90 110 mA

CCAUX

–5mA

LI 24 –72mA

XC3SD3400A C,I 39 130 160 mA

LI 38

– 105 mA

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 .

2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (T = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with V with no functional elements instantiated). For conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table.

3. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A DSP FPGA XPower Estimator typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.

4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.

5. For information on the power-saving Suspend mode, see XAPP480 typically saves 40% total power consumption compared to quiescent current.

CCINT

= 1.26V, V

= 3.6V, and V

CCO

= 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design

CCAUX

: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode

of 25°C at V

J

CCINT

= 1.2V, V

provides quick, approximate,

= 3.3V, and V

CCO

CCAUX

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 13

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Single-Ended I/O Standards

Tab le 1 0 : Recommended Operating Conditions for User I/Os Using Single-Ended Standards

V

for Drivers

IOSTANDARD

Attribute

Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)

CCO

LV TT L 3 .0 3 .3 3 . 6

LV CM OS 33

LV CM OS 25

(4)

(4,5)

3.0 3.3 3.6 0.8 2.0

2.3 2.5 2.7 0.7 1.7

LVCMOS18 1.65 1.8 1.95 0.4 0.8

LVCMOS15 1.4 1.5 1.6 0.4 0.8

LVCMOS12 1.1 1.2 1.3 0.4 0.7

PCI33_3

PCI66_3

(6)

3.0 3.3 3.6 0.3 • V

HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 V

HSTL_III 1.4 1.5 1.6

HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 V

HSTL_II_18 1.7 1.8 1.9 –0.9–V

HSTL_III_18 1.7 1.8 1.9

SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 V

SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 V

SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 V

SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 V

SSTL3_I 3.0 3.3 3.6 1.3 1.5 1.7 V

SSTL3_II 3.0 3.3 3.6 1.3 1.5 1.7 V

Notes:

1. Descriptions of the symbols used in this table are as follows: V

—the supply voltage for output drivers

CCO

V

—the reference voltage for setting the input switching threshold

REF

V

—the input voltage that indicates a Low logic level

IL

V

—the input voltage that indicates a High logic level

IH

2. In general, the V and for PCI I/O standards.

rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V

CCO

3. For device operation, the maximum signal voltage (V

4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.

5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V LVCMOS33 standard depending on V using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V

CCAUX

throughout configuration.

6. For information on PCI IP solutions, see www.xilinx.com/pci IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.

(2)

V

REF

V

IL

0.8 2.0

V

is not used for

REF

these I/O standards

CCAUX

0.5 • V

REF

= 3.3V range

CCO

–0.1 V

REF

–0.9–V

–1.1–V

max) can be as high as VIN max. See Ta bl e 7 .

IH

. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When

lines of Banks 0, 1, and 2 at power-on as well as

CCO

CCAUX

–0.1 V

REF

–0.1 V

REF

–0.1 V

REF

–0.1 V

REF

–0.125 V

REF

–0.125 V

REF

–0.150 V

REF

–0.150 V

REF

–0.2 V

REF

–0.2 V

REF

rail and use the LVCMOS25 or

. The PCI IOSTANDARD is not supported on input-only pins. The PCIX

(3)

V

IH

CCO

+0.1

+0.125

+0.150

+0.2

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 14

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 1 1 : DC Characteristics of User I/Os Using Single-Ended Standards

IOSTANDARD

Attribute

(3)

LV TT L

LV CM OS 33

LV CM OS 25

LV CM OS 18

LV CM OS 15

LV CM OS 12

Tes t

Conditions

I

OL

(mA)

OH

(mA)

2 2 –2 0.4 2.4

44–4

66–6

88–8

12 12 –12

16 16 –16

24 24 –24

(3)

2 2 –2 0.4 V

44–4

66–6

88–8

12 12 –12

16 16 –16

(5)

24

(3)

24 –24

2 2 –2 0.4 V

44–4

66–6

88–8

12 12 –12

(5)

16

24

(3)

16 –16

(5)

24 –24

2 2 –2 0.4 V

44–4

66–6

88–8

(5)

12

16

(3)

12 –12

(5)

16 –16

2 2 –2 0.4 V

44–4

66–6

(5)

8

12

(3)

4

6

8–8

(5)

12 –12

2 2 –2 0.4 V

(5)

4–4

(5)

6–6

Logic Level

Characteristics

V

OL

Max (V)

Min (V)

CCO

V

OH

– 0.4

Tab l e 1 1: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)

Test

IOSTANDARD

Attribute

PCI33_3

PCI66_3

HSTL_I

HSTL_III

(4)

(5)

Conditions

I

OL

(mA)

OH

(mA)

1.5 –0.5 10% V

8–8 0.4 V

24 –8 0.4 V

HSTL_I_18 8 –8 0.4 V

HSTL_II_18

(5)

16 –16 0.4 V

HSTL_III_18 24 –8 0.4 V

SSTL18_I 6.7 –6.7 V

SSTL18_II

(5)

13.4 –13.4 V

SSTL2_I 8.1 –8.1 V

SSTL2_II

(5)

16.2 –16.2 V

SSTL3_I 8 –8 V

SSTL3_II

(5)

16 –16 V

Notes:

1. The numbers in this table are based on the conditions set forth in

Ta bl e 7 and Ta bl e 1 0 .

2. Descriptions of the symbols used in this table are as follows: I

—the output current condition under which VOL is tested

OL

I

—the output current condition under which VOH is tested

OH

V

— the output voltage that indicates a Low logic level

OL

V

—the output voltage that indicates a High logic level

OH

V

—the supply voltage for output drivers

CCO

V

—the voltage applied to a resistor termination

TT

3. For the LVCMOS and LVTTL standards: the same V limits apply for the Fast, Slow, and QUIETIO slew attributes.

4. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/products/

design_resources/conn_central/protocols/pci_pcix.htm. The

PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.

5. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the Using I/O Resources chapter in UG331

.

Logic Level

Characteristics

V

OL

Max (V)

CCO

– 0.475 V

TT

– 0.603 V

TT

– 0.61 V

TT

– 0.81 V

TT

– 0.6 V

TT

– 0.8 V

TT

V

OH

Min (V)

90% V

CCO

+ 0.475

TT

+ 0.603

TT

+0.61

TT

+0.81

TT

and VOH

OL

CCO

– 0.4

+0.6

+0.8

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 15

DS610-3_03_061507

V

INN

V

INN

V

INP

V

INP

GND level

50%

V

ICM

V

ICM

= Input common mode voltage =

V

ID

Internal

Logic

Differential I/O Pair Pins

N

P

2

V

INP

+

V

INN

V

ID

= Differential input voltage =

V

INP

-

V

INN

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Differential I/O Standards

Differential Input Pairs

X-Ref Target - Figure 3

Figure 3: Differential Input Voltages

Tab le 1 2 : Recommended Operating Conditions for User I/Os Using Differential Signal Standards

V

for Drivers

IOSTANDARD Attribute

LV DS _ 25

LV DS _ 33

BLVDS_25

MINI_LVDS_25

MINI_LVDS_33

LVPECL_25

LVPECL_33

RSDS_25

RSDS_33

TMDS_33

PPDS_25

PPDS_33

(3)

(4)

(3)

(5)

(3)

(3,4,7)

(3)

Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V)

CCO

2.25 2.5 2.75 100 350 600 0.3 1.25 2.35

3.0 3.3 3.6 100 350 600 0.3 1.25 2.35

2.25 2.5 2.75 100 300 –0.31.32.35

2.25 2.5 2.75 200 – 600 0.3 1.2 1.95

3.0 3.3 3.6 200 – 600 0.3 1.2 1.95

Inputs Only 100 800 1000 0.3 1.2 1.95

Inputs Only 100 800 1000 0.3 1.2 2.8

2.25 2.5 2.75 100 200 –0.31.21.5

3.0 3.3 3.6 100 200 –0.31.21.5

3.14 3.3 3.47 150 – 1200 2.7 –3.23

2.25 2.5 2.75 100 – 400 0.2 –2.3

3.0 3.3 3.6 100 – 400 0.2 –2.3

DIFF_HSTL_I_18 1.7 1.8 1.9 100

DIFF_HSTL_II_18

(8)

1.7 1.8 1.9 100 – –0.8–1.1

DIFF_HSTL_III_18 1.7 1.8 1.9 100

DIFF_HSTL_I 1.4 1.5 1.6 100

DIFF_HSTL_III 1.4 1.5 1.6 100

DIFF_SSTL18_I 1.7 1.8 1.9 100

DIFF_SSTL18_II

(8)

1.7 1.8 1.9 100 – –0.7–1.1

DIFF_SSTL2_I 2.3 2.5 2.7 100

DIFF_SSTL2_II

DIFF_SSTL3_I 3.0 3.3 3.6 100

DIFF_SSTL3_II 3.0 3.3 3.6 100

Notes:

1. The V

2. V

ICM

3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331

4. See "External Termination Requirements for Differential I/O."

5. LVPECL is supported on inputs only, not outputs. LVPECL_33 requires V

6. LVPECL_33 maximum V

7. Requires V

8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331

9. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 16

(8)

rails supply only differential output drivers, not input circuits.

CCO

must be less than V

CCAUX

ICM

=3.3V±10%. (V

2.3 2.5 2.7 100 – –1.0–1.5

.

= the lower of 2.8V or V

CCAUX

-300 mV)≤ V

CCAUX

ICM

(1)

–(VID/2). ≤ (V

CCAUX

- 37 mV).

=3.3V ± 10%.

V

ID

– –0.8–1.1

– –0.68–0.9

– – –0.9–

– –0.7–1.1

– –1.0–1.5

– –1.1–1.9

(2)

V

ICM

.

(6)

Differential Output Pairs

V

OUTN

V

OUTP

GND level

50%

V

OCM

V

OCM

V

OD

V

OL

V

OH

V

OUTP

Internal

Logic

V

OUTN

N

P

= Output common mode voltage =

2

V

OUTP+VOUTN

V

OD

= Output differential voltage =

V

OH

= Output voltage indicating a High logic level

V

OL

= Output voltage indicating a Low logic level

V

OUTP-VOUTN

Differential I/O Pair Pins

DS312-3_03_090510

X-Ref Target - Figure 4

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Figure 4: Differential Output Voltages

Tab le 1 3 : DC Characteristics of User I/Os Using Differential Signal Standards

V

IOSTANDARD Attribute

Min (mV) Typ (mV) Max (mV) Min (V) Typ (V) Max (V) Min (V) Max (V)

OD

LVDS_25 247 350 454 1.125

LVDS_33 247 350 454 1.125

BLVDS_25 240 350 460

MINI_LVDS_25 300

MINI_LVDS_33 300

RSDS_25 100

RSDS_33 100

TMDS_33 400

PPDS_25 100

PPDS_33 100

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DIFF_HSTL_I

DIFF_HSTL_III

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL3_I

DIFF_SSTL3_II

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 and Tab l e 12 .

2. See "External Termination Requirements for Differential I/O."

3. Output voltage measurements for all differential standards are made with a termination resistor (R

4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 17

V

=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V

CCO

– – – – – –V

– – – – – – V

– – – – – –

– 600 1.0 –1.4 – –

– 400 1.0 –1.4 – –

–800V

– 400 0.5 0.8 1.4 – –

–1.30– – –

– 0.405 –V

CCO

=3.3V

CCO

V

OCM

V

OH

–1.375 – –

– 0.190 – –

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

+ 0.475 VTT – 0.475

TT

+ 0.603 VTT – 0.603

TT

+ 0.61 VTT – 0.61

TT

+ 0.81 VTT – 0.81

TT

+ 0.6 VTT - 0.6

TT

V

+ 0.8 VTT - 0.8

TT

) of 100Ω across the N and P pins of the differential signal pair.

T

V

OL

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Z0 = 50Ω

Z

0 = 50Ω

100Ω

DS529-3_09_020107

a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint

Z0 = 50Ω

Z

0 = 50Ω

b) Differential pairs using DIFF_TERM=Yes constraint

DIFF_TERM=No

DIFF_TERM=Yes

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

LVD S_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33, PPDS_25

CAT16-PT4F4

Part Number

/ th of Bourns

1

4

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

No VCCO Restrictions

R

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

DT

Bank 0

Bank 2

Bank 0

Bank 2

Bank 3

Bank 1

Bank 0 and 2 Any Bank

Z0 = 50Ω

Z

0 = 50Ω

140Ω

165Ω

100Ω

VCCO = 2.5V

No VCCO Requirement

DS529-3_07_020107

BLVDS_25

CAT16-LV4F12

Part Number

/ th of Bourns

1

4

CAT16-PT4F4

Part Number

/ th of Bourns

1

4

Bank 0

Bank 2

Bank 3

Bank 1

Any Bank

Bank 0

Bank 2

Bank 3

Bank 1

Any Bank

External Termination Requirements for Differential I/O

LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

X-Ref Target - Figure 5

Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

BLVDS_25 I/O Standard

X-Ref Target - Figure 6

Figure 6: External Output and Input Termination Resistors for BLVDS_25 I/O Standard

TMDS_33 I/O Standard

X-Ref Target - Figure 7

Bank 0 and 2

Bank 0

3.3V

Bank 2

50Ω

VCCO = 3.3V

TMDS_33 TMDS_33

Device DNA Read Endurance

Tab le 1 4 : Device DNA Identifier Memory Characteristics

Symbol Description Minimum Units

DNA_CYCLES

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 18

Figure 7: External Input Resistors Required for TMDS_33 I/O Standard

Number of READ operations or JTAG ISC_DNA read operations. Unaffected by HOLD or SHIFT operations.

Any Bank

Bank 0

Bank 3

Bank 2

50Ω

VCCAUX = 3.3V

DS529-3_08_020107DVI/HDMI cable

Bank 1

30,000,000

Read

cycles

Switching Characteristics

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

All Spartan-3A DSP FPGAs ship in two speed grades: –4 and the higher performance –5. Switching characteristics in this document are designated as Advance, Preliminary, or Production, as shown in Tab l e 1 5. Each category is defined as follows:

Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.

Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data.

Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated.

• Sign Up for Alerts on Xilinx.com

http://www.xilinx.com/support/answers/18683.htm

Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3A DSP FPGA speed files (v1.32), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Ta bl e 1 5 . For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.

Tab l e 1 5: Spartan-3A DSP v1.32 Speed Grade Designations

Device Advance Preliminary Production

XC3SD1800A -4, -5

XC3SD3400A

-4, -5

Software Version Requirements

Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status. FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system.

Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx® ISE® software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.

Production designs will require updating the Xilinx ISE development software with a future version and/or Service Pack.

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless

otherwise noted, the published parameter values apply to all Spartan-3A DSP devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.

Ta bl e 1 6 provides the recent history of the Spartan-3A DSP

FPGA speed files.

Tab l e 1 6: Spartan-3A DSP Speed File Version History

Version

1.32 ISE 10.1.02

1.31 ISE 10.1 Added Automotive support

1.30 ISE 9.2.03i Added absolute minimum values

1.29 ISE 9.2.01i

1.28 ISE 9.2i Minor updates

1.27 ISE 9.1.03i Advance Speed Files for -4 speed grade

ISE

Release

Description

Updated DSP timing model to reflect higher performance for some implementations

Production Speed Files for -4 and -5 speed grades

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 19

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

I/O Timing

Pin-to-Pin Clock-to-Output Times

Tab le 1 7 : Pin-to-Pin Clock-to-Output Times for the IOB Output Path

Speed Grade

Symbol Description Conditions Device

Max Max

Clock-to-Output Times

T

ICKOFDCM

When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global

LV CM OS 25 output drive, Fast slew rate, with DCM

(2)

, 12 mA

(3)

XC3SD1800A 3.28 3.51 ns

XC3SD3400A 3.36 3.82 ns

Clock pin to data appearing at the Output pin. The DCM is in use.

T

ICKOF

When reading from OFF, the time from the active transition on the Global Clock pin to data appearing

LV CM OS 25 output drive, Fast slew rate, without DCM

(2)

, 12 mA

XC3SD1800A 5.23 5.58 ns

XC3SD3400A 5.51 6.13 ns

at the Output pin. The DCM is not in use.

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Tab le 2 2 . If the latter is true, add the appropriate Output adjustment from Ta bl e 2 5 .

3. DCM output jitter is included in all measurements.

Units-5 -4

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 20

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Pin-to-Pin Setup and Hold Times

Tab le 1 8 : Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)

Symbol Description Conditions Device

Setup Times

(4)

(2)

(3)

,

XC3SD1800A 2.65 3.11 ns

XC3SD3400A 2.25 2.49 ns

,

XC3SD1800A 2.98 3.39 ns

XC3SD3400A 2.78 3.08 ns

,

XC3SD1800A –0.38 –0.38 ns

XC3SD3400A –0.26 –0.26 ns

,

XC3SD1800A –0.71 –0.71 ns

XC3SD3400A –0.65 –0.65 ns

T

PSDCM

T

PSFD

Hold Times

T

PHDCM

T

PHFD

When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is in use. No Input Delay is programmed.

When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not in use. The Input Delay is programmed.

When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is in use. No Input Delay is programmed.

When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not in use. The Input Delay is programmed.

LV CM OS 25 IFD_DELAY_VALUE = 0, with DCM

LV CM OS 25 IFD_DELAY_VALUE = 6, without DCM

LV CM OS 25 IFD_DELAY_VALUE = 0, with DCM

LV CM OS 25 IFD_DELAY_VALUE = 6, without DCM

Speed Grade

Units-5 -4

Max Max

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Ta bl e 2 2 . If this is true of the data Input, add the appropriate Input adjustment from the same table.

3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Ta bl e 2 2 . If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge.

4. DCM output jitter is included in all measurements.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 21

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Setup and Hold Times

Tab le 1 9 : Setup and Hold Times for the IOB Input Path

Symbol Description Conditions

Setup Times

T

IOPICK

T

IOPICKD

Hold Times

T

IOICKP

Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed.

Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed.

Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed.

LV CM OS 25

DELAY_

VALUE

Device

-5 -4

Min Min

Speed

(2)

IFD_DELAY_VALUE=0 XC3SD1800A 1.65 1.81 ns

XC3SD3400A 1.51 1.88 ns

(2)

1 XC3SD1800A 2.09 2.24 ns

2 2.67 2.83 ns

3 3.25 3.64 ns

4 3.75 4.20 ns

5 3.69 4.16 ns

6 4.47 5.09 ns

7 5.27 6.02 ns

8 5.79 6.63 ns

1 XC3SD3400A 2.07 2.44 ns

2 2.57 3.02 ns

3 3.44 3.81 ns

4 4.01 4.39 ns

5 3.89 4.26 ns

6 4.43 5.08 ns

7 5.20 5.95 ns

8 5.70 6.55 ns

(3)

0 XC3SD1800A –0.63 –0.52 ns

XC3SD3400A –0.56 –0.56

Units

ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 22

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 1 9 : Setup and Hold Times for the IOB Input Path (Cont’d)

Symbol Description Conditions

T

IOICKPD

Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed.

Set/Reset Pulse Width

T

RPW_IOB

Minimum pulse width to SR control input on IOB

LV CM OS 25

(3)

– – All 1.33 1.61 ns

DELAY_

VALUE

Device

-5 -4

Min Min

1 XC3SD1800A –1.40 –1.40 ns

2 –2.11 –2.11 ns

3 –2.48 –2.48 ns

4 –2.77 –2.77 ns

5 –2.62 –2.62 ns

6 –3.06 –3.06 ns

7 –3.42 –3.42 ns

8 –3.65 –3.65 ns

1 XC3SD3400A –1.31 –1.31 ns

2 –1.88 –1.88 ns

3 –2.44 –2.44 ns

4 –2.89 –2.89 ns

5 –2.83 –2.83 ns

6 –3.33 –3.33 ns

7 –3.63 –3.63 ns

8 –3.96 –3.96 ns

Speed

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Tab l e 2 2.

3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Tab l e 2 2. When the hold time is negative, it is possible to change the data before the clock’s active edge.

Tab le 2 0 : Sample Window (Source Synchronous)

Symbol Description Max Units

T

SAMP

Setup and hold capture window of an IOB flip-flop.

The input capture sample window value is highly specific to a particular application, device, package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the appropriate Xilinx Answer Record for application-specific values.

• Answer Record 30879

ps

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 23

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Propagation Times

Tab le 2 1 : Propagation Times for the IOB Input Path

Symbol Description Conditions DELAY_VALUE Device

Propagation Times

T

IOPI

T

IOPID

The time it takes for data to travel from the Input pin to the I output with no input delay programmed

The time it takes for data to travel from the Input pin to the I output with the input delay programmed

LV CM OS 25

(2)

IBUF_DELAY_VALUE=0

(2)

1 XC3SD1800A 1.29 1.62 ns

2 1.67 2.08 ns

3 1.92 2.36 ns

4 2.38 2.89 ns

5 2.61 3.17 ns

6 2.98 3.55 ns

7 3.30 3.92 ns

8 3.63 4.37 ns

9 3.31 4.02 ns

10 3.69 4.47 ns

11 3.94 4.77 ns

12 4.41 5.27 ns

13 4.67 5.56 ns

14 5.03 5.94 ns

15 5.36 6.31 ns

16 5.64 6.73 ns

1 XC3SD3400A 1.56 1.99 ns

2 1.92 2.44 ns

3 2.18 2.72 ns

4 2.66 3.19 ns

5 2.91 3.43 ns

6 3.27 3.81 ns

7 3.59 4.17 ns

8 3.87 4.58 ns

9 3.52 4.22 ns

10 3.87 4.65 ns

11 4.14 4.94 ns

12 4.68 5.40 ns

13 4.93 5.66 ns

14 5.29 6.06 ns

15 5.61 6.43 ns

16 5.88 6.80 ns

XC3SD1800A 0.51 0.53 ns

XC3SD3400A 0.73 0.93 ns

Speed Grade

-5 -4

Max Max

Units

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 24

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 1 : Propagation Times for the IOB Input Path (Cont’d)

Symbol Description Conditions DELAY_VALUE Device

T

IOPLI

T

IOPLID

The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed

The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed

LV CM OS 25

(2)

0 XC3SD1800A 1.79 2.04 ns

XC3SD3400A 1.65 2.11 ns

1 XC3SD1800A 2.23 2.47 ns

2 2.81 3.06 ns

3 3.39 3.86 ns

4 3.89 4.43 ns

5 3.83 4.39 ns

6 4.61 5.32 ns

7 5.40 6.24 ns

8 5.93 6.86 ns

1 XC3SD3400A 2.21 2.67 ns

2 2.71 3.25 ns

3 3.58 4.04 ns

4 4.15 4.62 ns

5 4.03 4.49 ns

6 4.57 5.31 ns

7 5.34 6.18 ns

8 5.84 6.78 ns

Speed Grade

-5 -4

Max Max

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Ta bl e 2 2 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 25

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Timing Adjustments

Tab le 2 2 : Input Timing Adjustments by IOSTANDARD

Convert Input Time from

LVCMOS25 to the

Following Signal Standard

(IOSTANDARD)

Single-Ended Standards

LV TT L 0 .6 2 0 .6 2 n s

LVCMOS33 0.54 0.54 ns

LVCMOS25 0.00 0.00 ns

LVCMOS18 0.83 0.83 ns

LVCMOS15 0.60 0.60 ns

LVCMOS12 0.31 0.31 ns

PCI33_3 0.41 0.41 ns

PCI66_3 0.41 0.41 ns

HSTL_I 0.72 0.72 ns

HSTL_III 0.77 0.77 ns

HSTL_I_18 0.69 0.69 ns

HSTL_II_18 0.69 0.69 ns

HSTL_III_18 0.79 0.79 ns

SSTL18_I 0.71 0.71 ns

SSTL18_II 0.71 0.71 ns

SSTL2_I 0.68 0.68 ns

SSTL2_II 0.68 0.68 ns

SSTL3_I 0.78 0.78 ns

SSTL3_II 0.78 0.78 ns

Add the

Adjustment Below

Speed Grade

-5 -4

Units

Tab l e 2 2: Input Timing Adjustments by IOSTANDARD

Convert Input Time from

LVCMOS25 to the

Following Signal Standard

(IOSTANDARD)

Differential Standards

LV DS _ 25 0 .7 6 0 .7 6 n s

LV DS _ 33 0 .7 9 0 .7 9 n s

BLVDS_25 0.79 0.79 ns

MINI_LVDS_25 0.78 0.78 ns

MINI_LVDS_33 0.79 0.79 ns

LVPECL_25 0.78 0.78 ns

LVPECL_33 0.79 0.79 ns

RSDS_25 0.79 0.79 ns

RSDS_33 0.77 0.77 ns

TMDS_33 0.79 0.79 ns

PPDS_25 0.79 0.79 ns

PPDS_33 0.79 0.79 ns

DIFF_HSTL_I_18 0.74 0.74 ns

DIFF_HSTL_II_18 0.72 0.72 ns

DIFF_HSTL_III_18 1.05 1.05 ns

DIFF_HSTL_I 0.72 0.72 ns

DIFF_HSTL_III 1.05 1.05 ns

DIFF_SSTL18_I 0.71 0.71 ns

DIFF_SSTL18_II 0.71 0.71 ns

DIFF_SSTL2_I 0.74 0.74 ns

DIFF_SSTL2_II 0.75 0.75 ns

DIFF_SSTL3_I 1.06 1.06 ns

DIFF_SSTL3_II 1.06 1.06 ns

Add the

Adjustment Below

Speed Grade

-5 -4

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in Ta bl e 7 , Ta b le 1 0, and Ta b le 1 2 .

2. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 26

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Output Propagation Times

Tab le 2 3 : Timing for the IOB Output Path

Symbol Description Conditions Device

Clock-to-Output Times

T

IOCKP

When reading from the Output Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output pin

Propagation Times

T

IOOP

The time it takes for data to travel from the IOB’s O input to the Output pin

Set/Reset Times

T

IOSRP

Time from asserting the OFF’s SR input to setting/resetting data at the Output pin

T

IOGSRQ

Time from asserting the Global Set Reset (GSR) input on the STARTUP_SPARTAN3A primitive to setting/resetting data at the Output pin

LV CM O S2 5 drive, Fast slew rate

(2)

, 12 mA output

(2)

, 12 mA output

(2)

, 12 mA output

Speed Grade

Units-5 -4

Max Max

All 2.87 3.13 ns

All 2.78 2.91 ns

All 3.63 3.89 ns

8.62 9.65 ns

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Ta bl e 2 5 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 27

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Three-State Output Propagation Times

Tab le 2 4 : Timing for the IOB Three-State Path

Symbol Description Conditions Device

Synchronous Output Enable/Disable Times

T

IOCKHZ

IOCKON

(2)

T

Asynchronous Output Enable/Disable Times

T

GTS

Set/Reset Times

T

IOSRHZ

IOSRON

(2)

T

Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state

Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data

Time from asserting the Global Three State (GTS) input on the STARTUP_SPARTAN3A primitive to when the Output pin enters the high-impedance state

Time from asserting TFF’s SR input to when the Output pin enters a high-impedance state

Time from asserting TFF’s SR input at TFF to when the Output pin drives valid data

LVCMOS25, 12 mA output drive, Fast slew rate

Speed Grade

Units-5 -4

Max Max

All 1.13 1.39 ns

All 3.08 3.35 ns

All 9.47 10.36 ns

All 1.61 1.86 ns

All 3.57 3.82 ns

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Ta bl e 2 5 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 28

Output Timing Adjustments

Tab le 2 5 : Output Timing Adjustments for IOB

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

Single-Ended Standards

LVTTL Slow 2 mA 5.58 5.58 ns

4 mA 3.16 3.16 ns

6 mA 3.17 3.17 ns

8 mA 2.09 2.09 ns

12 mA 1.62 1.62 ns

16 mA 1.24 1.24 ns

24 mA 2.74

Fast 2 mA 3.03 3.03 ns

4 mA 1.71 1.71 ns

6 mA 1.71 1.71 ns

8 mA 0.53 0.53 ns

12 mA 0.53 0.53 ns

16 mA 0.59 0.59 ns

24 mA 0.60 0.60 ns

QuietIO 2 mA 27.67 27.67 ns

4 mA 27.67 27.67 ns

6 mA 27.67 27.67 ns

8 mA 16.71 16.71 ns

12 mA 16.67 16.67 ns

16 mA 16.22 16.22 ns

24 mA 12.11 12.11 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.74

Units

(3)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab l e 2 5: Output Timing Adjustments for IOB (Cont’d)

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.55

(3)

Units

ns

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS33 Slow 2 mA 5.58 5.58 ns

4 mA 3.17 3.17 ns

6 mA 3.17 3.17 ns

8 mA 2.09 2.09 ns

12 mA 1.24 1.24 ns

16 mA 1.15 1.15 ns

24 mA 2.55

Fast 2 mA 3.02 3.02 ns

4 mA 1.71 1.71 ns

6 mA 1.72 1.72 ns

8 mA 0.53 0.53 ns

12 mA 0.59 0.59 ns

16 mA 0.59 0.59 ns

24 mA 0.51 0.51 ns

QuietIO 2 mA 27.67 27.67 ns

4 mA 27.67 27.67 ns

6 mA 27.67 27.67 ns

8 mA 16.71 16.71 ns

12 mA 16.29 16.29 ns

16 mA 16.18 16.18 ns

24 mA 12.11 12.11 ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 29

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 5 : Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS25 Slow 2 mA 5.33 5.33 ns

4 mA 2.81 2.81 ns

6 mA 2.82 2.82 ns

8 mA 1.14 1.14 ns

12 mA 1.10 1.10 ns

16 mA 0.83 0.83 ns

24 mA 2.26

Fast 2 mA 4.36 4.36 ns

4 mA 1.76 1.76 ns

6 mA 1.25 1.25 ns

8 mA 0.38 0.38 ns

12 mA 0.00 0.00 ns

16 mA 0.01 0.01 ns

24 mA 0.01 0.01 ns

QuietIO 2 mA 25.92 25.92 ns

4 mA 25.92 25.92 ns

6 mA 25.92 25.92 ns

8 mA 15.57 15.57 ns

12 mA 15.59 15.59 ns

16 mA 14.27 14.27 ns

24 mA 11.37 11.37 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.26

Units

(3)

ns

Tab l e 2 5: Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS18 Slow 2 mA 4.48 4.48 ns

4 mA 3.69 3.69 ns

6 mA 2.91 2.91 ns

8 mA 1.99 1.99 ns

12 mA 1.57 1.57 ns

16 mA 1.19 1.19 ns

Fast 2 mA 3.96 3.96 ns

4 mA 2.57 2.57 ns

6 mA 1.90 1.90 ns

8 mA 1.06 1.06 ns

12 mA 0.83 0.83 ns

16 mA 0.63 0.63 ns

QuietIO 2 mA 24.97 24.97 ns

4 mA 24.97 24.97 ns

6 mA 24.08 24.08 ns

8 mA 16.43 16.43 ns

12 mA 14.52 14.52 ns

16 mA 13.41 13.41 ns

LVCMOS15 Slow 2 mA 5.82 5.82 ns

4 mA 3.97 3.97 ns

6 mA 3.21 3.21 ns

8 mA 2.53 2.53 ns

12 mA 2.06 2.06 ns

Fast 2 mA 5.23 5.23 ns

4 mA 3.05 3.05 ns

6 mA 1.95 1.95 ns

8 mA 1.60 1.60 ns

12 mA 1.30 1.30 ns

QuietIO 2 mA 34.11 34.11 ns

4 mA 25.66 25.66 ns

6 mA 24.64 24.64 ns

8 mA 22.06 22.06 ns

12 mA 20.64 20.64 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

Units

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 30

Xilinx DS610 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Introduction and Ordering Information

Introduction

Features

Architectural Overview

Configuration

I/O Capabilities

Package Marking

Ordering Information

Revision History

Notice of Disclaimer

Functional Description

Spartan-3A DSP FPGA Design Documentation

Revision History

Notice of Disclaimer

DC and Switching Characteristics

DC Electrical Characteristics

Absolute Maximum Ratings

Power Supply Specifications

General Recommended Operating Conditions

General DC Characteristics for I/O Pins

Quiescent Current Requirements

Single-Ended I/O Standards

Differential I/O Standards

Differential Input Pairs

Differential Output Pairs

External Termination Requirements for Differential I/O

Device DNA Read Endurance

Switching Characteristics

Software Version Requirements

I/O Timing

Pin-to-Pin Clock-to-Output Times

Pin-to-Pin Setup and Hold Times

Input Setup and Hold Times

Input Propagation Times

Input Timing Adjustments

Output Propagation Times

Three-State Output Propagation Times

Output Timing Adjustments