Xilinx DS610 User Manual

1

Spartan-3A DSP FPGA Family Data Sheet

DS610 October 4, 2010 Product Specification

Module 1: Introduction and Ordering Information

DS610 (v3.0) October 4, 2010

• Introduction

• Features

• Architectural Overview

• Configuration Overview

• General I/O Capabilities

• Supported Packages and Package Marking

• Ordering Information

Module 2: Functional Description

DS610 (v3.0) October 4, 2010

The functionality of the Spartan®-3A DSP FPGA family is described in the following documents.

• UG331

• Clocking Resources

• Digital Clock Managers (DCMs)

•Block RAM

• Configurable Logic Blocks (CLBs)

• I/O Resources

• Programmable Interconnect

• ISE® Software Design Tools and IP Cores

• Embedded Processing and Control Solutions

• Pin Types and Package Overview

• Package Drawings

• Powering FPGAs

• Power Management

• UG332

• Configuration Overview

• Configuration Pins and Behavior

• Bitstream Sizes

• Detailed Descriptions by Mode

• ISE iMPACT Programming Examples

• MultiBoot Reconfiguration

• Design Authentication using Device DNA

: Spartan-3 Generation FPGA User Guide

- Distributed RAM

- SRL16 Shift Registers

- Carry and Arithmetic Logic

: Spartan-3 Generation Configuration User Guide

- Master Serial Mode using Platform Flash PROM

- Master SPI Mode using Commodity Serial Flash

- Master BPI Mode using Commodity Parallel Flash

- Slave Parallel (SelectMAP) using a Processor

- Slave Serial using a Processor

- JTAG Mode

• UG431

FPGAs User Guide

• DSP48A Slice Design Considerations

• DSP48A Architecture Highlights

• DSP48A Application Examples

: XtremeDSP™ DSP48A for Spartan-3A DSP

- 18 x 18-Bit Multipliers

- 48-Bit Accumulator

- 18-bit Pre-Adder

Module 3: DC and Switching Characteristics

DS610 (v3.0) October 4, 2010

• DC Electrical Characteristics

• Absolute Maximum Ratings

• Supply Voltage Specifications

• Recommended Operating Conditions

• Switching Characteristics

• I/O Timing

• Configurable Logic Block (CLB) Timing

• Digital Clock Manager (DCM) Timing

• Block RAM Timing

• XtremeDSP Slice Timing

• Configuration and JTAG Timing

Module 4: Pinout Descriptions

DS610 (v3.0) October 4, 2010

• Pin Descriptions

• Package Overview

• Pinout Tables

• Footprint Diagrams

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 October 4, 2010 www.xilinx.com Product Specification 1

6

Spartan-3A DSP FPGA Family:

Introduction and Ordering Information

DS610 (v3.0) October 4, 2010 Product Specification

Introduction

The Spartan®-3A DSP family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high- volume, cost-sensitive, high-performance DSP applications. two-member family offers densities ranging from

The

1.8 to 3.4

million

system gates, as shown in Ta b l e 1 . The Spartan-3A DSP family builds on the success of the

Spartan-3A FPGA family by increasing the amount of memory per logic and adding XtremeDSP™ DSP48A slices. New features improve system performance and reduce the cost of configuration. These Spartan-3A DSP FPGA enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic

and DSP processing

industry.

The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A FPGA family. The XC3SD1800A and the XC3SD3400A devices are tailored for DSP applications and have additional block RAM and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices replace the 18x18 multipliers found in the Spartan-3A devices and are based on the DSP48 blocks found in the Virtex®-4 devices. The block RAMs are also enhanced to run faster by adding an output register. Both the block RAM and DSP48A slices in the Spartan-3A DSP devices run at 250 MHz in the lowest cost, standard -4 speed grade.

Because of their exceptional DSP price/performance ratio, Spartan-3A DSP FPGAs are ideally suited to a wide range of consumer electronics applications, such as broadband access, home networking, display/projection, and digital television.

The Spartan-3A DSP family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.

Features

• Very low cost, high-performance DSP solution for high-volume, cost-conscious applications

• 250 MHz XtremeDSP DSP48A Slices

• Dedicated 18-bit by 18-bit multiplier

• Available pipeline stages for enhanced performance of at

least 250 MHz in the standard -4 speed grade

• 48-bit accumulator for multiply-accumulate (MAC) operation

• Integrated adder for complex multiply or multiply-add

operation

• Integrated 18-bit pre-adder

• Optional cascaded Multiply or MAC

• Hierarchical SelectRAM™ memory architecture

• Up to 2268 Kbits of fast block RAM with byte write enables for processor applications

• Up to 373 Kbits of efficient distributed RAM

• Registered outputs on the block RAM with operation of at

• Dual-range V

• Suspend, Hibernate modes reduce system power

least 280 MHz in the standard -4 speed grade

supply simplifies 3.3V-only design

CCAUX

• Low-power option reduces quiescent current

• Multi-voltage, multi-standard SelectIO™ interface pins

• Up to 519 I/O pins or 227 differential signal pairs

• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

• Selectable output drive, up to 24 mA per pin

• QUIETIO standard reduces I/O switching noise

• Full 3.3V ± 10% compatibility and hot swap compliance

• 622+ Mb/s data transfer rate per differential I/O

• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

• Enhanced Double Data Rate (DDR) support

• DDR/DDR2 SDRAM support up to 333 Mb/s

• Fully compliant 32-/64-bit, 33/66 MHz PCI support

• Abundant, flexible logic resources

• Densities up to 53712 logic cells, including optional shift register

• Efficient wide multiplexers, wide logic, fast carry logic

• IEEE 1149.1/1532 JTAG programming/debug port

• Eight Digital Clock Managers (DCMs)

• Clock skew elimination (delay locked loop)

• Frequency synthesis, multiplication, division

• High-resolution phase shifting

• Wide frequency range (5 MHz to over 320 MHz)

• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing

• Configuration interface to industry-standard PROMs

• Low-cost, space-saving SPI serial Flash PROM

• x8 or x8/x16 BPI parallel NOR Flash PROM

• Low-cost Xilinx® Platform Flash

• Unique Device DNA identifier for design authentication

• Load multiple bitstreams under FPGA control

• Post-configuration CRC checking

with JTAG

• MicroBlaze™ and PicoBlaze™ embedded processor cores

• BGA and CSP packaging with Pb-free options

• Common footprints support easy density migration

• XA Automotive version available

Table 1: Summary of Spartan-3A DSP FPGA Attributes

Device

XC3SD1800A 1800K 37,440 88 48 4,160 16,640 260K 1512K 84 8 519 227 XC3SD3400A 3400K 53,712 104 58 5,968 23,872 373K 2268K 126 8 469 213

Notes:

1. By convention, one Kb is equivalent to 1,024 bits.

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

System

Gates

Equivalent

Logic Cells

CLB Array (One CLB = Four Slices)

Tot al

CLBs

Tot al

Slices

Distributed

RAM

Bits

Block

RAM

(1)

Bits

(1)

DSP48As DCMs

Maximum

User I/O

Maximum

Differential

I/O PairsRows Columns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 2

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

CLB

Block RAM

DCM

IOBs

DS610-1_01_031207

IOBs

DCM

Block RAM / DSP48A Slice

DCM

CLBs

IOBs

DSP48A Slice

Notes:

1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A columns of the 4 or 5 columns in the selected device, as shown in the diagram above.

2. A detailed diagram of the DSP48A can be found in UG431

: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.

Architectural Overview

The Spartan-3A DSP family architecture consists of five fundamental programmable functional elements:

• XtremeDSP™ DSP48A Slice provides an 18-bit x 18-bit multiplier, 18-bit pre-adder, 48-bit post-adder/accumulator, and cascade capabilities for various DSP applications.

• Block RAM provides data storage in the form of 18-Kbit dual-port blocks.

• Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data.

• Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included.

X-Ref Target - Figure 1

• Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.

These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. The XC3SD1800A has four columns of DSP48As, and the XC3SD3400A has five columns of DSP48As. Each DSP48A has an associated block RAM. The DCMs are positioned in the center with two at the top and two at the bottom of the device and in the two outer columns of the 4 or 5 columns of block RAM and DSP48As.

The Spartan-3A DSP family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 3

Figure 1: Spartan-3A DSP Family Architecture

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

Configuration

Spartan-3A DSP FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of seven different modes:

• Master Serial from a Xilinx Platform Flash PROM

• Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash

• Byte Peripheral Interface (BPI) Up from an industry-standard x8 or x8/x16 parallel NOR Flash

• Slave Serial, typically downloaded from a processor

• Slave Parallel, typically downloaded from a processor

• Boundary Scan (JTAG), typically downloaded from a processor or system tester

Furthermore, Spartan-3A DSP FPGAs support MultiBoot configuration, allowing two or more FPGA configuration bitstreams to be stored in a single SPI serial Flash or a BPI parallel NOR Flash. The FPGA application controls which configuration to load next and when to load it.

Additionally, each Spartan-3A DSP FPGA contains a unique, factory-programmed Device DNA identifier useful for tracking purposes, anti-cloning designs, or IP protection.

I/O Capabilities

The Spartan-3A DSP FPGA SelectIO interface supports many popular single-ended and differential standards.

Ta bl e 2 shows the number of user I/Os as well as the

number of differential I/O pairs available for each device/package combination. Some of the user I/Os are unidirectional input-only pins as indicated in Tab l e 2 .

Spartan-3A DSP FPGAs support the following single-ended standards:

• 3.3V low-voltage TTL (LVTTL)

• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,

1.5V, or 1.2V

• 3.3V PCI at 33 MHz or 66 MHz

• HSTL I, II, and III at 1.5V and 1.8V, commonly used in memory applications

• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used for memory applications

• Spartan-3A DSP FPGAs support the following differential standards:

• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or

3.3V

• Bus LVDS I/O at 2.5V

• TMDS I/O at 3.3V

• Differential HSTL and SSTL I/O

• LVPECL inputs at 2.5V or 3.3V

Tab le 2 : Available User I/Os and Differential (Diff) I/O Pairs

CS484

(1)

CSG484

140

(78)

140 (78)

519

(110)

469

(60)

Device

User Diff User Diff

XC3SD1800A

XC3SD3400A

Notes:

1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs.

309

(60)

309

(60)

FG676

FGG676

227

(131)

213

(117)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 4

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

-4 CS 484 LI

Device Type

Speed Grade

Power/Temperature Range

Package Type

Number of Pins

Example:

DS610-1_05_021009

XC3SD1800A

Package Marking

Figure 2 shows the top marking for Spartan-3A DSP FPGAs. The “5C” and “4I” Speed Grade/Temperature Range part

combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range.

X-Ref Target - Figure 2

BGA Ball A1

Device Type

Package

Low-Power

(optional)

Speed Grade

Operating Range

R

SPARTAN

R

XC3SD1800A CSG484XGQ####

X#######X

L4 I

Mask Revision

Fabrication/ Process Code

Date Code Lot Code

DS610-1_02_070607

Figure 2: Spartan-3A DSP FPGA Package Marking Example

Ordering Information

Spartan-3A DSP FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a ‘G’ character in the ordering code.

Device Speed Grade Package Type / Number of Pins

XC3SD1800A -4 Standard Performance CS484/

484-ball Chip-Scale Ball Grid Array (CSBGA) C Commercial (0°C to 85°C)

Power/Temperature Range

CSG484

XC3SD3400A -5 High Performance

FG676/

676-ball Fine-Pitch Ball Grid Array (FBGA) I Industrial (–40°C to 100°C)

(1)

FGG676

LI Low-power Industrial

Notes:

1. The -5 speed grade is exclusively available in the Commercial temperature range.

2. The low-power option (LI) is exclusively available in the CS(G)484 package and industrial temperature range.

3. See DS705

, XA Spartan-3A DSP Automotive FPGA Family Data Sheet for the XA Automotive Spartan-3A DSP FPGAs.

(T

)

J

(–40°C to 100°C)

(2)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 5

Spartan-3A DSP FPGA Family: Introduction and Ordering Information

Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/07 1.0 Initial Xilinx release.

05/25/07 1.0.1 Minor edits.

06/18/07 1.2 Updated for Production release.

07/16/07 2.0 Added Low-power options.

06/02/08 2.1 Added reference to SCD 4103 for 750 Mbps performance. Add dual mark clarification to Package

Marking. Updated links.

03/11/09 2.2 Simplified ordering information. Removed reference to SCD 4103.

10/04/10 3.0 Updated the Notice of Disclaimer section.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

CRITICAL APPLICATIONS DISCLAIMER

XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.

AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

. THIS LIMITED

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 6

8

Spartan-3A DSP FPGA Family:

Functional Description

DS610 (v3.0) October 4, 2010 Product Specification

Spartan-3A DSP FPGA Design Documentation

The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. The topics covered in each guide are listed.

• DS706

• UG331

• Clocking Resources

• Digital Clock Managers (DCMs)

• Block RAM

• Configurable Logic Blocks (CLBs)

• I/O Resources

• Programmable Interconnect

• ISE® Software Design Tools

•IP Cores

• Embedded Processing and Control Solutions

• Pin Types and Package Overview

• Package Drawings

• Powering FPGAs

• Power Management

• UG332

Guide

• Configuration Overview

• Detailed Descriptions by Mode

• ISE iMPACT Programming Examples

• MultiBoot Reconfiguration

• Design Authentication using Device DNA

: Extended Spartan-3A Family Overview

: Spartan-3 Generation FPGA User Guide

- Distributed RAM

- SRL16 Shift Registers

- Carry and Arithmetic Logic

: Spartan-3 Generation Configuration User

- Configuration Pins and Behavior

- Bitstream Sizes

- Master Serial Mode using Xilinx Platform Flash

PROM

- Master SPI Mode using Commodity SPI Serial Flash PROM

- Master BPI Mode using Commodity Parallel NOR Flash PROM

- Slave Parallel (SelectMAP) using a Processor

- Slave Serial using a Processor

- JTAG Mode

• UG431

FPGAs User Guide

• XtremeDSP DSP48A Slices

• XtremeDSP DSP48A Pre-Adder

For specific hardware examples, please see the Spartan-3A DSP FPGA Starter Kit board web pages.

• XtremeDSP Starter Platform—Spartan-3A DSP

1800A Edition

http://www.xilinx.com/products/devkits /HW-SD1800A-DSP-SB-UNI-G.htm

• XtremeDSP Starter Kit—Spartan-3A DSP 1800A

Edition

http://www.xilinx.com/products/devkits /DO-SD1800A-DSP-SK-UNI-G.htm

• XtremeDSP Video Starter Kit—Spartan-3A DSP

Edition

http://www.xilinx.com/products/devkits /DO-S3ADSP-VIDEO-SK-UNI-G.htm

• Embedded Development HW/SW Kit—Spartan-3A

DSP S3D1800A MicroBlaze Processor Edition

http://www.xilinx.com/products/devkits /DO-SD1800A-EDK-DK-UNI-G.htm

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated.

• Sign Up for Alerts on Xilinx.com

https://secure.xilinx.com/webreg/register.do?group=my profile&languageID=1

: XtremeDSP DSP48A for Spartan-3A DSP

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 7

Spartan-3A DSP FPGA Family: Functional Description

Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/07 1.0 Initial Xilinx release.

05/25/07 1.0.1 Minor edits.

06/18/07 1.2 Updated for Production release.

07/16/07 2.0 Added Low-power options; no changes to this module.

06/02/08 2.1 Updated links.

03/11/09 2.2 Added link to DS706 on Extended Spartan-3A family.

10/04/10 3.0 Updated link to sign up for Alerts and updated Notice of Disclaimer.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

CRITICAL APPLICATIONS DISCLAIMER

XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.

AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

. THIS LIMITED

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 8

61

Spartan-3A DSP FPGA Family:

DC and Switching Characteristics

DS610 (v3.0) October 4, 2010 Product Specification

DC Electrical Characteristics

In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:

Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics of other families. Values are subject to change. Use as estimates, not for production.

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless

otherwise noted, the published parameter values apply to all Spartan®-3A DSP devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.

Absolute Maximum Ratings

Preliminary: Based on characterization. Further changes

are not expected.

Stresses beyond those listed under Ta bl e 3 : Absolute Maximum Ratings may cause permanent damage to the

Production: These specifications are approved once the silicon has been characterized over numerous production lots. Parameter values are considered stable with no future changes expected.

device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time adversely affects device reliability.

Tab le 3 : Absolute Maximum Ratings

Symbol Description Conditions Min Max Units

V

CCINT

V

CCAUX

V

CCO

V

REF

V

I

V

ESD

T

STG

Notes:

1. Upper clamp applies only when using PCI IOSTANDARDs.

2. For soldering guidelines, see UG112 Guidelines for Pb-Free Packages.

Internal supply voltage –0.5 1.32 V

Auxiliary supply voltage –0.5 3.75 V

Output driver supply voltage –0.5 3.75 V

Input reference voltage –0.5 V

Voltage applied to all User I/O pins and

IN

Dual-Purpose pins

Voltage applied to all Dedicated pins –0.5 4.6 V

Input clamp current per I/O pin –0.5V < VIN<(V

IK

Electrostatic Discharge Voltage Human body model ±2000 V–

Junction temperature –125°C

J

Storage temperature –65 150 °C

: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow

Driver in a high-impedance state

CCO

Charged device model

Machine model

+0.5V)

(1)

–0.95 4.6 V

–±100mA

–±500V

–±200V

+0.5 V

CCO

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 9

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Power Supply Specifications

Tab le 4 : Supply Voltage Thresholds for Power-On Reset

Symbol Description Min Max Units

V

CCINTT

V

CCAUXT

V

CCO2T

Notes:

1. V

, V

CCINT

Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply V information).

CCAUX

CCINT

2. To ensure successful power-on, V no dips at any point.

Tab le 5 : Supply Voltage Ramp Rate

Symbol Description Min Max Units

V

CCINTR

V

CCAUXR

V

CCO2R

Notes:

1. V

2. To ensure successful power-on, V

Tab le 6 :

, V

CCINT

Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply V information).

CCAUX

CCINT

no dips at any point.

Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM Data

Symbol Description Min Units

V

DRINT

V

DRAUX

Threshold for the V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI

CCO

supply 0.4 1.0 V

CCINT

supply 1.0 2.0 V

CCAUX

Bank 2 supply 1.0 2.0 V

CCO

last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more

, V

CCINT

Ramp rate from GND to valid V

, and V

supplies to the FPGA can be applied in any order. However, the FPGA configuration source (Platform Flash, SPI

CCO

Bank 2, and V

CCO

CCINT

CCAUX

CCO

supplies must rise through their respective threshold-voltage ranges with

CCAUX

supply level 0.2 100 ms

Bank 2 supply level 0.2 100 ms

last for lowest overall power consumption (see the UG331 chapter titled "Powering Spartan-3 Generation FPGAs" for more

, V

CCINT

V

level required to retain CMOS Configuration Latch (CCL) and RAM data 1.0 V

CCINT

V

level required to retain CMOS Configuration Latch (CCL) and RAM data 2.0 V

CCAUX

Bank 2, and V

CCO

supplies must rise through their respective threshold-voltage ranges with

CCAUX

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 10

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

General Recommended Operating Conditions

Tab le 7 : General Recommended Operating Conditions

Symbol Description Min Nominal Max Units

T

J

V

CCINT

(1)

V

CCO

V

CCAUX

(3)

V

IN

T

IN

Notes:

1. This V range specific to each of the single-ended I/O standards, and Ta bl e 1 2 lists that specific to the differential standards.

2. Define V

range spans the lowest and highest operating voltages for all supported I/O standards. Tab l e 10 lists the recommended V

CCO

CCAUX

3. See XAPP459

4. For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331

5. Measured between 10% and 90% V

Junction temperature Commercial 0 –85°C

Industrial –40 –100°C

Internal supply voltage 1.14 1.20 1.26 V

Output driver supply voltage 1.10 –3.60V

Auxiliary supply voltage

Input voltage PCI™ IOSTANDARD –0.5 –V

Input signal transition time

(2)

V

CCAUX

V

CCAUX

All other IOSTANDARDs

(5)

= 2.5 2.25 2.50 2.75 V

= 3.3 3.00 3.30 3.60 V

CCO

IP or IO_# –0.5 –4.10V

IO_Lxxy_#

(4)

–0.5 –4.10V

– – 500 ns

selection using CONFIG VCCAUX constraint.

, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3 Families.

of –0.2V to –0.5V is supported but can cause increased leakage

, Spartan-3 Generation FPGA User Guide.

. Follow Signal Integrity recommendations.

CCO

IN

+0.5 V

CCO

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 11

General DC Characteristics for I/O Pins

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 8 : General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins

(1)

Symbol Description Test Conditions Min Typ Max Units

(2)

I

RPU

R

I

RPD

R

I

PU

PD

Leakage current at User I/O,

L

Input-only, Dual-Purpose, and Dedicated pins, FPGA powered

Leakage current on pins during

HS

hot socketing, FPGA unpowered

(3)

Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins. Dedicated pins are powered by V

.

CCAUX

(3)

Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on I

(3)

Current through pull-down

per Note 2)

RPU

resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins

(3)

Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on I

per Note 2)

RPD

Driver is in a high-impedance state, V

=0V or V

IN

max, sample-tested

CCO

All pins except INIT_B, PROG_B, DONE, and JTAG pins when PUDC_B = 1.

INIT_B, PROG_B, DONE, and JTAG pins or other pins when PUDC_B = 0.

VIN = GND V

= GND V

V

IN

V

CCAUX

VIN = V

CCO

= 3.0V to 3.6V VIN = 3.0V to 3.6V 5.5 10.4 20.8 kΩ

V

CCO

V

or V

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCO

V

CCAUX

= 3.0V to 3.6V –151 –315 –710 µA

CCAUX

= 2.3V to 2.7V –82 –182 –437 µA

CCAUX

= 1.7V to 1.9V –36 –88 –226 µA

= 1.4V to 1.6V –22 –56 –148 µA

= 1.14V to 1.26V –11 –31 –83 µA

= 3.0V to 3.6V 5.1 11.4 23.9 kΩ

= 2.3V to 2.7V 6.2 14.8 33.1 kΩ

= 1.7V to 1.9V 8.4 21.6 52.6 kΩ

= 1.4V to 1.6V 10.8 28.4 74.0 kΩ

= 1.14V to 1.26V 15.3 41.1 119.4 kΩ

= 3.0V to 3.6V 167 346 659 µA

= 2.25V to 2.75V

VIN = 2.3V to 2.7V 4.1 7.8 15.7 kΩ

VIN = 1.7V to 1.9V 3.0 5.7 11.1 kΩ

V

= 1.4V to 1.6V 2.7 5.1 9.6 kΩ

IN

–10

–+10µA

–10 –+10µA

Add I

HS

+ I

RPU

µA

100 225 457 µA

VIN = 1.14V to 1.26V 2.4 4.5 8.1 kΩ

= 2.25V to 2.75V VIN = 3.0V to 3.6V 7.9 16.0 35.0 kΩ

CCAUX

V

= 2.3V to 2.7V 5.9 12.0 26.3 kΩ

IN

= 1.7V to 1.9V 4.2 8.5 18.6 kΩ

V

IN

V

= 1.4V to 1.6V 3.6 7.2 15.7 kΩ

IN

V

= 1.14V to 1.26V 3.0 6.0 12.5 kΩ

IN

levels –10 –+10µA

CCO

V

= 3.3V ± 10% LVDS_33, MINI_LVDS_33,

CCO

V

= 2.5V ± 10% LVDS_25, MINI_LVDS_25,

CCO

RSDS_33

RSDS_25

90 100 115 Ω

90 110 – Ω

I

REF

C

R

V

current per pin All V

REF

Input capacitance – – –10pF

IN

Resistance of optional

DT

differential termination circuit within a differential I/O pair. Not available on Input-only pairs.

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 .

2. For single-ended signals that are placed on a differential-capable I/O, V between the two pins. See Parasitic Leakage in UG331

3. This parameter is based on characterization. The pull-up resistance R

, Spartan-3 Generation FPGA User Guide.

of –0.2V to –0.5V is supported but can cause increased leakage

IN

PU

= V

CCO/IRPU

. The pull-down resistance RPD=VIN/I

RPD

.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 12

Quiescent Current Requirements

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 9 : Quiescent Supply Current Characteristics

Symbol Description Device Power Typical

I

CCINTQ

Quiescent V

supply current XC3SD1800A C,I 41 390 500 mA

CCINT

(1)

LI 36

(2)

Commercial

Maximum

(2)

Industrial

Maximum

– 175 mA

(2)

Units

XC3SD3400A C,I 64 550 725 mA

I

CCOQ

Quiescent V

LI 55

supply current XC3SD1800A C,I 0.4 4 5 mA

CCO

– 300 mA

LI 0.2 –5mA

XC3SD3400A C,I 0.4 4 5 mA

I

CCAUXQ

Quiescent V

LI 0.2

supply current XC3SD1800A C,I 25 90 110 mA

CCAUX

–5mA

LI 24 –72mA

XC3SD3400A C,I 39 130 160 mA

LI 38

– 105 mA

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 .

2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (T = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with V with no functional elements instantiated). For conditions other than those described above (for example, a design including functional elements), measured quiescent current levels will be different than the values in the table.

3. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3A DSP FPGA XPower Estimator typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.

4. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.

5. For information on the power-saving Suspend mode, see XAPP480 typically saves 40% total power consumption compared to quiescent current.

CCINT

= 1.26V, V

= 3.6V, and V

CCO

= 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design

CCAUX

: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode

of 25°C at V

J

CCINT

= 1.2V, V

provides quick, approximate,

= 3.3V, and V

CCO

CCAUX

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 13

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Single-Ended I/O Standards

Tab le 1 0 : Recommended Operating Conditions for User I/Os Using Single-Ended Standards

V

for Drivers

IOSTANDARD

Attribute

Min (V) Nom (V) Max (V) Min (V) Nom (V) Max (V) Max (V) Min (V)

CCO

LV TT L 3 .0 3 .3 3 . 6

LV CM OS 33

LV CM OS 25

(4)

(4,5)

3.0 3.3 3.6 0.8 2.0

2.3 2.5 2.7 0.7 1.7

LVCMOS18 1.65 1.8 1.95 0.4 0.8

LVCMOS15 1.4 1.5 1.6 0.4 0.8

LVCMOS12 1.1 1.2 1.3 0.4 0.7

PCI33_3

PCI66_3

(6)

3.0 3.3 3.6 0.3 • V

HSTL_I 1.4 1.5 1.6 0.68 0.75 0.9 V

HSTL_III 1.4 1.5 1.6

HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 V

HSTL_II_18 1.7 1.8 1.9 –0.9–V

HSTL_III_18 1.7 1.8 1.9

SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 V

SSTL18_II 1.7 1.8 1.9 0.833 0.900 0.969 V

SSTL2_I 2.3 2.5 2.7 1.13 1.25 1.38 V

SSTL2_II 2.3 2.5 2.7 1.13 1.25 1.38 V

SSTL3_I 3.0 3.3 3.6 1.3 1.5 1.7 V

SSTL3_II 3.0 3.3 3.6 1.3 1.5 1.7 V

Notes:

1. Descriptions of the symbols used in this table are as follows: V

—the supply voltage for output drivers

CCO

V

—the reference voltage for setting the input switching threshold

REF

V

—the input voltage that indicates a Low logic level

IL

V

—the input voltage that indicates a High logic level

IH

2. In general, the V and for PCI I/O standards.

rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V

CCO

3. For device operation, the maximum signal voltage (V

4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.

5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V LVCMOS33 standard depending on V using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V

CCAUX

throughout configuration.

6. For information on PCI IP solutions, see www.xilinx.com/pci IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.

(2)

V

REF

V

IL

0.8 2.0

V

is not used for

REF

these I/O standards

CCAUX

0.5 • V

REF

= 3.3V range

CCO

–0.1 V

REF

–0.9–V

–1.1–V

max) can be as high as VIN max. See Ta bl e 7 .

IH

. The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When

lines of Banks 0, 1, and 2 at power-on as well as

CCO

CCAUX

–0.1 V

REF

–0.1 V

REF

–0.1 V

REF

–0.1 V

REF

–0.125 V

REF

–0.125 V

REF

–0.150 V

REF

–0.150 V

REF

–0.2 V

REF

–0.2 V

REF

rail and use the LVCMOS25 or

. The PCI IOSTANDARD is not supported on input-only pins. The PCIX

(3)

V

IH

CCO

+0.1

+0.125

+0.150

+0.2

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 14

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 1 1 : DC Characteristics of User I/Os Using Single-Ended Standards

IOSTANDARD

Attribute

(3)

LV TT L

LV CM OS 33

LV CM OS 25

LV CM OS 18

LV CM OS 15

LV CM OS 12

Tes t

Conditions

I

OL

(mA)

OH

(mA)

2 2 –2 0.4 2.4

44–4

66–6

88–8

12 12 –12

16 16 –16

24 24 –24

(3)

2 2 –2 0.4 V

44–4

66–6

88–8

12 12 –12

16 16 –16

(5)

24

(3)

24 –24

2 2 –2 0.4 V

44–4

66–6

88–8

12 12 –12

(5)

16

24

(3)

16 –16

(5)

24 –24

2 2 –2 0.4 V

44–4

66–6

88–8

(5)

12

16

(3)

12 –12

(5)

16 –16

2 2 –2 0.4 V

44–4

66–6

(5)

8

12

(3)

4

6

8–8

(5)

12 –12

2 2 –2 0.4 V

(5)

4–4

(5)

6–6

Logic Level

Characteristics

V

OL

Max (V)

Min (V)

CCO

V

OH

– 0.4

Tab l e 1 1: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)

Test

IOSTANDARD

Attribute

PCI33_3

PCI66_3

HSTL_I

HSTL_III

(4)

(5)

Conditions

I

OL

(mA)

OH

(mA)

1.5 –0.5 10% V

8–8 0.4 V

24 –8 0.4 V

HSTL_I_18 8 –8 0.4 V

HSTL_II_18

(5)

16 –16 0.4 V

HSTL_III_18 24 –8 0.4 V

SSTL18_I 6.7 –6.7 V

SSTL18_II

(5)

13.4 –13.4 V

SSTL2_I 8.1 –8.1 V

SSTL2_II

(5)

16.2 –16.2 V

SSTL3_I 8 –8 V

SSTL3_II

(5)

16 –16 V

Notes:

1. The numbers in this table are based on the conditions set forth in

Ta bl e 7 and Ta bl e 1 0 .

2. Descriptions of the symbols used in this table are as follows: I

—the output current condition under which VOL is tested

OL

I

—the output current condition under which VOH is tested

OH

V

— the output voltage that indicates a Low logic level

OL

V

—the output voltage that indicates a High logic level

OH

V

—the supply voltage for output drivers

CCO

V

—the voltage applied to a resistor termination

TT

3. For the LVCMOS and LVTTL standards: the same V limits apply for the Fast, Slow, and QUIETIO slew attributes.

4. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/products/

design_resources/conn_central/protocols/pci_pcix.htm. The

PCIX IOSTANDARD is available and has equivalent characteristics but no PCI-X IP is supported.

5. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the Using I/O Resources chapter in UG331

.

Logic Level

Characteristics

V

OL

Max (V)

CCO

– 0.475 V

TT

– 0.603 V

TT

– 0.61 V

TT

– 0.81 V

TT

– 0.6 V

TT

– 0.8 V

TT

V

OH

Min (V)

90% V

CCO

+ 0.475

TT

+ 0.603

TT

+0.61

TT

+0.81

TT

and VOH

OL

CCO

– 0.4

+0.6

+0.8

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 15

DS610-3_03_061507

V

INN

V

INN

V

INP

V

INP

GND level

50%

V

ICM

V

ICM

= Input common mode voltage =

V

ID

Internal

Logic

Differential I/O Pair Pins

N

P

2

V

INP

+

V

INN

V

ID

= Differential input voltage =

V

INP

-

V

INN

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Differential I/O Standards

Differential Input Pairs

X-Ref Target - Figure 3

Figure 3: Differential Input Voltages

Tab le 1 2 : Recommended Operating Conditions for User I/Os Using Differential Signal Standards

V

for Drivers

IOSTANDARD Attribute

LV DS _ 25

LV DS _ 33

BLVDS_25

MINI_LVDS_25

MINI_LVDS_33

LVPECL_25

LVPECL_33

RSDS_25

RSDS_33

TMDS_33

PPDS_25

PPDS_33

(3)

(4)

(3)

(5)

(3)

(3,4,7)

(3)

Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V)

CCO

2.25 2.5 2.75 100 350 600 0.3 1.25 2.35

3.0 3.3 3.6 100 350 600 0.3 1.25 2.35

2.25 2.5 2.75 100 300 –0.31.32.35

2.25 2.5 2.75 200 – 600 0.3 1.2 1.95

3.0 3.3 3.6 200 – 600 0.3 1.2 1.95

Inputs Only 100 800 1000 0.3 1.2 1.95

Inputs Only 100 800 1000 0.3 1.2 2.8

2.25 2.5 2.75 100 200 –0.31.21.5

3.0 3.3 3.6 100 200 –0.31.21.5

3.14 3.3 3.47 150 – 1200 2.7 –3.23

2.25 2.5 2.75 100 – 400 0.2 –2.3

3.0 3.3 3.6 100 – 400 0.2 –2.3

DIFF_HSTL_I_18 1.7 1.8 1.9 100

DIFF_HSTL_II_18

(8)

1.7 1.8 1.9 100 – –0.8–1.1

DIFF_HSTL_III_18 1.7 1.8 1.9 100

DIFF_HSTL_I 1.4 1.5 1.6 100

DIFF_HSTL_III 1.4 1.5 1.6 100

DIFF_SSTL18_I 1.7 1.8 1.9 100

DIFF_SSTL18_II

(8)

1.7 1.8 1.9 100 – –0.7–1.1

DIFF_SSTL2_I 2.3 2.5 2.7 100

DIFF_SSTL2_II

DIFF_SSTL3_I 3.0 3.3 3.6 100

DIFF_SSTL3_II 3.0 3.3 3.6 100

Notes:

1. The V

2. V

ICM

3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331

4. See "External Termination Requirements for Differential I/O."

5. LVPECL is supported on inputs only, not outputs. LVPECL_33 requires V

6. LVPECL_33 maximum V

7. Requires V

8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331

9. All standards except for LVPECL and TMDS can have VCCAUX at either 2.5V or 3.3V. Define your VCCAUX level using the CONFIG VCCAUX constraint.

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 16

(8)

rails supply only differential output drivers, not input circuits.

CCO

must be less than V

CCAUX

ICM

=3.3V±10%. (V

2.3 2.5 2.7 100 – –1.0–1.5

.

= the lower of 2.8V or V

CCAUX

-300 mV)≤ V

CCAUX

ICM

(1)

–(VID/2). ≤ (V

CCAUX

- 37 mV).

=3.3V ± 10%.

V

ID

– –0.8–1.1

– –0.68–0.9

– – –0.9–

– –0.7–1.1

– –1.0–1.5

– –1.1–1.9

(2)

V

ICM

.

(6)

Differential Output Pairs

V

OUTN

V

OUTP

GND level

50%

V

OCM

V

OCM

V

OD

V

OL

V

OH

V

OUTP

Internal

Logic

V

OUTN

N

P

= Output common mode voltage =

2

V

OUTP+VOUTN

V

OD

= Output differential voltage =

V

OH

= Output voltage indicating a High logic level

V

OL

= Output voltage indicating a Low logic level

V

OUTP-VOUTN

Differential I/O Pair Pins

DS312-3_03_090510

X-Ref Target - Figure 4

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Figure 4: Differential Output Voltages

Tab le 1 3 : DC Characteristics of User I/Os Using Differential Signal Standards

V

IOSTANDARD Attribute

Min (mV) Typ (mV) Max (mV) Min (V) Typ (V) Max (V) Min (V) Max (V)

OD

LVDS_25 247 350 454 1.125

LVDS_33 247 350 454 1.125

BLVDS_25 240 350 460

MINI_LVDS_25 300

MINI_LVDS_33 300

RSDS_25 100

RSDS_33 100

TMDS_33 400

PPDS_25 100

PPDS_33 100

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DIFF_HSTL_I

DIFF_HSTL_III

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL3_I

DIFF_SSTL3_II

Notes:

1. The numbers in this table are based on the conditions set forth in Ta bl e 7 and Tab l e 12 .

2. See "External Termination Requirements for Differential I/O."

3. Output voltage measurements for all differential standards are made with a termination resistor (R

4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25, PPDS_25 when

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 17

V

=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when V

CCO

– – – – – –V

– – – – – – V

– – – – – –

– 600 1.0 –1.4 – –

– 400 1.0 –1.4 – –

–800V

– 400 0.5 0.8 1.4 – –

–1.30– – –

– 0.405 –V

CCO

=3.3V

CCO

V

OCM

V

OH

–1.375 – –

– 0.190 – –

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

– 0.4 0.4

CCO

+ 0.475 VTT – 0.475

TT

+ 0.603 VTT – 0.603

TT

+ 0.61 VTT – 0.61

TT

+ 0.81 VTT – 0.81

TT

+ 0.6 VTT - 0.6

TT

V

+ 0.8 VTT - 0.8

TT

) of 100Ω across the N and P pins of the differential signal pair.

T

V

OL

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Z0 = 50Ω

Z

0 = 50Ω

100Ω

DS529-3_09_020107

a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint

Z0 = 50Ω

Z

0 = 50Ω

b) Differential pairs using DIFF_TERM=Yes constraint

DIFF_TERM=No

DIFF_TERM=Yes

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

LVD S_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33, PPDS_25

CAT16-PT4F4

Part Number

/ th of Bourns

1

4

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

No VCCO Restrictions

R

LVD S_33, MINI_LVDS_33, RSDS_33, PPDS_33

VCCO = 3.3V

LVD S_25, MINI_LVDS_25, RSDS_25, PPDS_25

VCCO = 2.5V

DT

Bank 0

Bank 2

Bank 0

Bank 2

Bank 3

Bank 1

Bank 0 and 2 Any Bank

Z0 = 50Ω

Z

0 = 50Ω

140Ω

165Ω

100Ω

VCCO = 2.5V

No VCCO Requirement

DS529-3_07_020107

BLVDS_25

CAT16-LV4F12

Part Number

/ th of Bourns

1

4

CAT16-PT4F4

Part Number

/ th of Bourns

1

4

Bank 0

Bank 2

Bank 3

Bank 1

Any Bank

Bank 0

Bank 2

Bank 3

Bank 1

Any Bank

External Termination Requirements for Differential I/O

LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

X-Ref Target - Figure 5

Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards

BLVDS_25 I/O Standard

X-Ref Target - Figure 6

Figure 6: External Output and Input Termination Resistors for BLVDS_25 I/O Standard

TMDS_33 I/O Standard

X-Ref Target - Figure 7

Bank 0 and 2

Bank 0

3.3V

Bank 2

50Ω

VCCO = 3.3V

TMDS_33 TMDS_33

Device DNA Read Endurance

Tab le 1 4 : Device DNA Identifier Memory Characteristics

Symbol Description Minimum Units

DNA_CYCLES

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 18

Figure 7: External Input Resistors Required for TMDS_33 I/O Standard

Number of READ operations or JTAG ISC_DNA read operations. Unaffected by HOLD or SHIFT operations.

Any Bank

Bank 0

Bank 3

Bank 2

50Ω

VCCAUX = 3.3V

DS529-3_08_020107DVI/HDMI cable

Bank 1

30,000,000

Read

cycles

Switching Characteristics

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

All Spartan-3A DSP FPGAs ship in two speed grades: –4 and the higher performance –5. Switching characteristics in this document are designated as Advance, Preliminary, or Production, as shown in Tab l e 1 5. Each category is defined as follows:

Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.

Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data.

Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.

Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated.

• Sign Up for Alerts on Xilinx.com

http://www.xilinx.com/support/answers/18683.htm

Timing parameters and their representative values are selected for inclusion below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3A DSP FPGA speed files (v1.32), part of the Xilinx Development Software, are the original source for many but not all of the values. The speed grade designations for these files are shown in Ta bl e 1 5 . For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.

Tab l e 1 5: Spartan-3A DSP v1.32 Speed Grade Designations

Device Advance Preliminary Production

XC3SD1800A -4, -5

XC3SD3400A

-4, -5

Software Version Requirements

Production-quality systems must use FPGA designs compiled using a speed file designated as PRODUCTION status. FPGAs designs using a less mature speed file designation should only be used during system prototyping or pre-production qualification. FPGA designs with speed files designated as Preview, Advance, or Preliminary should not be used in a production-quality system.

Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx® ISE® software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.

Production designs will require updating the Xilinx ISE development software with a future version and/or Service Pack.

All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless

otherwise noted, the published parameter values apply to all Spartan-3A DSP devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades.

Ta bl e 1 6 provides the recent history of the Spartan-3A DSP

FPGA speed files.

Tab l e 1 6: Spartan-3A DSP Speed File Version History

Version

1.32 ISE 10.1.02

1.31 ISE 10.1 Added Automotive support

1.30 ISE 9.2.03i Added absolute minimum values

1.29 ISE 9.2.01i

1.28 ISE 9.2i Minor updates

1.27 ISE 9.1.03i Advance Speed Files for -4 speed grade

ISE

Release

Description

Updated DSP timing model to reflect higher performance for some implementations

Production Speed Files for -4 and -5 speed grades

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 19

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

I/O Timing

Pin-to-Pin Clock-to-Output Times

Tab le 1 7 : Pin-to-Pin Clock-to-Output Times for the IOB Output Path

Speed Grade

Symbol Description Conditions Device

Max Max

Clock-to-Output Times

T

ICKOFDCM

When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global

LV CM OS 25 output drive, Fast slew rate, with DCM

(2)

, 12 mA

(3)

XC3SD1800A 3.28 3.51 ns

XC3SD3400A 3.36 3.82 ns

Clock pin to data appearing at the Output pin. The DCM is in use.

T

ICKOF

When reading from OFF, the time from the active transition on the Global Clock pin to data appearing

LV CM OS 25 output drive, Fast slew rate, without DCM

(2)

, 12 mA

XC3SD1800A 5.23 5.58 ns

XC3SD3400A 5.51 6.13 ns

at the Output pin. The DCM is not in use.

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Tab le 2 2 . If the latter is true, add the appropriate Output adjustment from Ta bl e 2 5 .

3. DCM output jitter is included in all measurements.

Units-5 -4

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 20

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Pin-to-Pin Setup and Hold Times

Tab le 1 8 : Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)

Symbol Description Conditions Device

Setup Times

(4)

(2)

(3)

,

XC3SD1800A 2.65 3.11 ns

XC3SD3400A 2.25 2.49 ns

,

XC3SD1800A 2.98 3.39 ns

XC3SD3400A 2.78 3.08 ns

,

XC3SD1800A –0.38 –0.38 ns

XC3SD3400A –0.26 –0.26 ns

,

XC3SD1800A –0.71 –0.71 ns

XC3SD3400A –0.65 –0.65 ns

T

PSDCM

T

PSFD

Hold Times

T

PHDCM

T

PHFD

When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is in use. No Input Delay is programmed.

When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not in use. The Input Delay is programmed.

When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is in use. No Input Delay is programmed.

When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not in use. The Input Delay is programmed.

LV CM OS 25 IFD_DELAY_VALUE = 0, with DCM

LV CM OS 25 IFD_DELAY_VALUE = 6, without DCM

LV CM OS 25 IFD_DELAY_VALUE = 0, with DCM

LV CM OS 25 IFD_DELAY_VALUE = 6, without DCM

Speed Grade

Units-5 -4

Max Max

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Ta bl e 2 2 . If this is true of the data Input, add the appropriate Input adjustment from the same table.

3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Ta bl e 2 2 . If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge.

4. DCM output jitter is included in all measurements.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 21

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Setup and Hold Times

Tab le 1 9 : Setup and Hold Times for the IOB Input Path

Symbol Description Conditions

Setup Times

T

IOPICK

T

IOPICKD

Hold Times

T

IOICKP

Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed.

Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). The Input Delay is programmed.

Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. No Input Delay is programmed.

LV CM OS 25

DELAY_

VALUE

Device

-5 -4

Min Min

Speed

(2)

IFD_DELAY_VALUE=0 XC3SD1800A 1.65 1.81 ns

XC3SD3400A 1.51 1.88 ns

(2)

1 XC3SD1800A 2.09 2.24 ns

2 2.67 2.83 ns

3 3.25 3.64 ns

4 3.75 4.20 ns

5 3.69 4.16 ns

6 4.47 5.09 ns

7 5.27 6.02 ns

8 5.79 6.63 ns

1 XC3SD3400A 2.07 2.44 ns

2 2.57 3.02 ns

3 3.44 3.81 ns

4 4.01 4.39 ns

5 3.89 4.26 ns

6 4.43 5.08 ns

7 5.20 5.95 ns

8 5.70 6.55 ns

(3)

0 XC3SD1800A –0.63 –0.52 ns

XC3SD3400A –0.56 –0.56

Units

ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 22

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 1 9 : Setup and Hold Times for the IOB Input Path (Cont’d)

Symbol Description Conditions

T

IOICKPD

Time from the active transition at the ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed.

Set/Reset Pulse Width

T

RPW_IOB

Minimum pulse width to SR control input on IOB

LV CM OS 25

(3)

– – All 1.33 1.61 ns

DELAY_

VALUE

Device

-5 -4

Min Min

1 XC3SD1800A –1.40 –1.40 ns

2 –2.11 –2.11 ns

3 –2.48 –2.48 ns

4 –2.77 –2.77 ns

5 –2.62 –2.62 ns

6 –3.06 –3.06 ns

7 –3.42 –3.42 ns

8 –3.65 –3.65 ns

1 XC3SD3400A –1.31 –1.31 ns

2 –1.88 –1.88 ns

3 –2.44 –2.44 ns

4 –2.89 –2.89 ns

5 –2.83 –2.83 ns

6 –3.33 –3.33 ns

7 –3.63 –3.63 ns

8 –3.96 –3.96 ns

Speed

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Tab l e 2 2.

3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Tab l e 2 2. When the hold time is negative, it is possible to change the data before the clock’s active edge.

Tab le 2 0 : Sample Window (Source Synchronous)

Symbol Description Max Units

T

SAMP

Setup and hold capture window of an IOB flip-flop.

The input capture sample window value is highly specific to a particular application, device, package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the appropriate Xilinx Answer Record for application-specific values.

• Answer Record 30879

ps

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 23

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Propagation Times

Tab le 2 1 : Propagation Times for the IOB Input Path

Symbol Description Conditions DELAY_VALUE Device

Propagation Times

T

IOPI

T

IOPID

The time it takes for data to travel from the Input pin to the I output with no input delay programmed

The time it takes for data to travel from the Input pin to the I output with the input delay programmed

LV CM OS 25

(2)

IBUF_DELAY_VALUE=0

(2)

1 XC3SD1800A 1.29 1.62 ns

2 1.67 2.08 ns

3 1.92 2.36 ns

4 2.38 2.89 ns

5 2.61 3.17 ns

6 2.98 3.55 ns

7 3.30 3.92 ns

8 3.63 4.37 ns

9 3.31 4.02 ns

10 3.69 4.47 ns

11 3.94 4.77 ns

12 4.41 5.27 ns

13 4.67 5.56 ns

14 5.03 5.94 ns

15 5.36 6.31 ns

16 5.64 6.73 ns

1 XC3SD3400A 1.56 1.99 ns

2 1.92 2.44 ns

3 2.18 2.72 ns

4 2.66 3.19 ns

5 2.91 3.43 ns

6 3.27 3.81 ns

7 3.59 4.17 ns

8 3.87 4.58 ns

9 3.52 4.22 ns

10 3.87 4.65 ns

11 4.14 4.94 ns

12 4.68 5.40 ns

13 4.93 5.66 ns

14 5.29 6.06 ns

15 5.61 6.43 ns

16 5.88 6.80 ns

XC3SD1800A 0.51 0.53 ns

XC3SD3400A 0.73 0.93 ns

Speed Grade

-5 -4

Max Max

Units

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 24

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 1 : Propagation Times for the IOB Input Path (Cont’d)

Symbol Description Conditions DELAY_VALUE Device

T

IOPLI

T

IOPLID

The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed

The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed

LV CM OS 25

(2)

0 XC3SD1800A 1.79 2.04 ns

XC3SD3400A 1.65 2.11 ns

1 XC3SD1800A 2.23 2.47 ns

2 2.81 3.06 ns

3 3.39 3.86 ns

4 3.89 4.43 ns

5 3.83 4.39 ns

6 4.61 5.32 ns

7 5.40 6.24 ns

8 5.93 6.86 ns

1 XC3SD3400A 2.21 2.67 ns

2 2.71 3.25 ns

3 3.58 4.04 ns

4 4.15 4.62 ns

5 4.03 4.49 ns

6 4.57 5.31 ns

7 5.34 6.18 ns

8 5.84 6.78 ns

Speed Grade

-5 -4

Max Max

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Ta bl e 2 2 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 25

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Input Timing Adjustments

Tab le 2 2 : Input Timing Adjustments by IOSTANDARD

Convert Input Time from

LVCMOS25 to the

Following Signal Standard

(IOSTANDARD)

Single-Ended Standards

LV TT L 0 .6 2 0 .6 2 n s

LVCMOS33 0.54 0.54 ns

LVCMOS25 0.00 0.00 ns

LVCMOS18 0.83 0.83 ns

LVCMOS15 0.60 0.60 ns

LVCMOS12 0.31 0.31 ns

PCI33_3 0.41 0.41 ns

PCI66_3 0.41 0.41 ns

HSTL_I 0.72 0.72 ns

HSTL_III 0.77 0.77 ns

HSTL_I_18 0.69 0.69 ns

HSTL_II_18 0.69 0.69 ns

HSTL_III_18 0.79 0.79 ns

SSTL18_I 0.71 0.71 ns

SSTL18_II 0.71 0.71 ns

SSTL2_I 0.68 0.68 ns

SSTL2_II 0.68 0.68 ns

SSTL3_I 0.78 0.78 ns

SSTL3_II 0.78 0.78 ns

Add the

Adjustment Below

Speed Grade

-5 -4

Units

Tab l e 2 2: Input Timing Adjustments by IOSTANDARD

Convert Input Time from

LVCMOS25 to the

Following Signal Standard

(IOSTANDARD)

Differential Standards

LV DS _ 25 0 .7 6 0 .7 6 n s

LV DS _ 33 0 .7 9 0 .7 9 n s

BLVDS_25 0.79 0.79 ns

MINI_LVDS_25 0.78 0.78 ns

MINI_LVDS_33 0.79 0.79 ns

LVPECL_25 0.78 0.78 ns

LVPECL_33 0.79 0.79 ns

RSDS_25 0.79 0.79 ns

RSDS_33 0.77 0.77 ns

TMDS_33 0.79 0.79 ns

PPDS_25 0.79 0.79 ns

PPDS_33 0.79 0.79 ns

DIFF_HSTL_I_18 0.74 0.74 ns

DIFF_HSTL_II_18 0.72 0.72 ns

DIFF_HSTL_III_18 1.05 1.05 ns

DIFF_HSTL_I 0.72 0.72 ns

DIFF_HSTL_III 1.05 1.05 ns

DIFF_SSTL18_I 0.71 0.71 ns

DIFF_SSTL18_II 0.71 0.71 ns

DIFF_SSTL2_I 0.74 0.74 ns

DIFF_SSTL2_II 0.75 0.75 ns

DIFF_SSTL3_I 1.06 1.06 ns

DIFF_SSTL3_II 1.06 1.06 ns

Add the

Adjustment Below

Speed Grade

-5 -4

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in Ta bl e 7 , Ta b le 1 0, and Ta b le 1 2 .

2. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 26

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Output Propagation Times

Tab le 2 3 : Timing for the IOB Output Path

Symbol Description Conditions Device

Clock-to-Output Times

T

IOCKP

When reading from the Output Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output pin

Propagation Times

T

IOOP

The time it takes for data to travel from the IOB’s O input to the Output pin

Set/Reset Times

T

IOSRP

Time from asserting the OFF’s SR input to setting/resetting data at the Output pin

T

IOGSRQ

Time from asserting the Global Set Reset (GSR) input on the STARTUP_SPARTAN3A primitive to setting/resetting data at the Output pin

LV CM O S2 5 drive, Fast slew rate

(2)

, 12 mA output

(2)

, 12 mA output

(2)

, 12 mA output

Speed Grade

Units-5 -4

Max Max

All 2.87 3.13 ns

All 2.78 2.91 ns

All 3.63 3.89 ns

8.62 9.65 ns

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Ta bl e 2 5 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 27

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Three-State Output Propagation Times

Tab le 2 4 : Timing for the IOB Three-State Path

Symbol Description Conditions Device

Synchronous Output Enable/Disable Times

T

IOCKHZ

IOCKON

(2)

T

Asynchronous Output Enable/Disable Times

T

GTS

Set/Reset Times

T

IOSRHZ

IOSRON

(2)

T

Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state

Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data

Time from asserting the Global Three State (GTS) input on the STARTUP_SPARTAN3A primitive to when the Output pin enters the high-impedance state

Time from asserting TFF’s SR input to when the Output pin enters a high-impedance state

Time from asserting TFF’s SR input at TFF to when the Output pin drives valid data

LVCMOS25, 12 mA output drive, Fast slew rate

Speed Grade

Units-5 -4

Max Max

All 1.13 1.39 ns

All 3.08 3.35 ns

All 9.47 10.36 ns

All 1.61 1.86 ns

All 3.57 3.82 ns

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in

Ta bl e 7 and Ta b le 10 .

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Ta bl e 2 5 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 28

Output Timing Adjustments

Tab le 2 5 : Output Timing Adjustments for IOB

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

Single-Ended Standards

LVTTL Slow 2 mA 5.58 5.58 ns

4 mA 3.16 3.16 ns

6 mA 3.17 3.17 ns

8 mA 2.09 2.09 ns

12 mA 1.62 1.62 ns

16 mA 1.24 1.24 ns

24 mA 2.74

Fast 2 mA 3.03 3.03 ns

4 mA 1.71 1.71 ns

6 mA 1.71 1.71 ns

8 mA 0.53 0.53 ns

12 mA 0.53 0.53 ns

16 mA 0.59 0.59 ns

24 mA 0.60 0.60 ns

QuietIO 2 mA 27.67 27.67 ns

4 mA 27.67 27.67 ns

6 mA 27.67 27.67 ns

8 mA 16.71 16.71 ns

12 mA 16.67 16.67 ns

16 mA 16.22 16.22 ns

24 mA 12.11 12.11 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.74

Units

(3)

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab l e 2 5: Output Timing Adjustments for IOB (Cont’d)

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.55

(3)

Units

ns

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS33 Slow 2 mA 5.58 5.58 ns

4 mA 3.17 3.17 ns

6 mA 3.17 3.17 ns

8 mA 2.09 2.09 ns

12 mA 1.24 1.24 ns

16 mA 1.15 1.15 ns

24 mA 2.55

Fast 2 mA 3.02 3.02 ns

4 mA 1.71 1.71 ns

6 mA 1.72 1.72 ns

8 mA 0.53 0.53 ns

12 mA 0.59 0.59 ns

16 mA 0.59 0.59 ns

24 mA 0.51 0.51 ns

QuietIO 2 mA 27.67 27.67 ns

4 mA 27.67 27.67 ns

6 mA 27.67 27.67 ns

8 mA 16.71 16.71 ns

12 mA 16.29 16.29 ns

16 mA 16.18 16.18 ns

24 mA 12.11 12.11 ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 29

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 5 : Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS25 Slow 2 mA 5.33 5.33 ns

4 mA 2.81 2.81 ns

6 mA 2.82 2.82 ns

8 mA 1.14 1.14 ns

12 mA 1.10 1.10 ns

16 mA 0.83 0.83 ns

24 mA 2.26

Fast 2 mA 4.36 4.36 ns

4 mA 1.76 1.76 ns

6 mA 1.25 1.25 ns

8 mA 0.38 0.38 ns

12 mA 0.00 0.00 ns

16 mA 0.01 0.01 ns

24 mA 0.01 0.01 ns

QuietIO 2 mA 25.92 25.92 ns

4 mA 25.92 25.92 ns

6 mA 25.92 25.92 ns

8 mA 15.57 15.57 ns

12 mA 15.59 15.59 ns

16 mA 14.27 14.27 ns

24 mA 11.37 11.37 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

(3)

2.26

Units

(3)

ns

Tab l e 2 5: Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS18 Slow 2 mA 4.48 4.48 ns

4 mA 3.69 3.69 ns

6 mA 2.91 2.91 ns

8 mA 1.99 1.99 ns

12 mA 1.57 1.57 ns

16 mA 1.19 1.19 ns

Fast 2 mA 3.96 3.96 ns

4 mA 2.57 2.57 ns

6 mA 1.90 1.90 ns

8 mA 1.06 1.06 ns

12 mA 0.83 0.83 ns

16 mA 0.63 0.63 ns

QuietIO 2 mA 24.97 24.97 ns

4 mA 24.97 24.97 ns

6 mA 24.08 24.08 ns

8 mA 16.43 16.43 ns

12 mA 14.52 14.52 ns

16 mA 13.41 13.41 ns

LVCMOS15 Slow 2 mA 5.82 5.82 ns

4 mA 3.97 3.97 ns

6 mA 3.21 3.21 ns

8 mA 2.53 2.53 ns

12 mA 2.06 2.06 ns

Fast 2 mA 5.23 5.23 ns

4 mA 3.05 3.05 ns

6 mA 1.95 1.95 ns

8 mA 1.60 1.60 ns

12 mA 1.30 1.30 ns

QuietIO 2 mA 34.11 34.11 ns

4 mA 25.66 25.66 ns

6 mA 24.64 24.64 ns

8 mA 22.06 22.06 ns

12 mA 20.64 20.64 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

Units

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 30

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 5 : Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

LVCMOS12 Slow 2 mA 7.14 7.14 ns

4 mA 4.87 4.87 ns

6 mA 5.67 5.67 ns

Fast 2 mA 6.77 6.77 ns

4 mA 5.02 5.02 ns

6 mA 4.09 4.09 ns

QuietIO 2 mA 50.76 50.76 ns

4 mA 43.17 43.17 ns

6 mA 37.31 37.31 ns

PCI33_3 0.34 0.34 ns

PCI66_3 0.34 0.34 ns

HSTL_I 0.78 0.78 ns

HSTL_III 1.16 1.16 ns

HSTL_I_18 0.35 0.35 ns

HSTL_II_18 0.30 0.30 ns

HSTL_III_18 0.47 0.47 ns

SSTL18_I 0.40 0.40 ns

SSTL18_II 0.30 0.30 ns

SSTL2_I 0.00 0.00 ns

SSTL2_II –0.05 –0.05 ns

SSTL3_I 0.00 0.00 ns

SSTL3_II 0.17 0.17 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

Units

Tab l e 2 5: Output Timing Adjustments for IOB (Cont’d)

Convert Output Time from

LVCMOS25 with 12mA Drive

and Fast Slew Rate to the

Following Signal Standard

(IOSTANDARD)

Differential Standards

LVDS_25 1.16 1.16 ns

LVDS_33 0.46 0.46 ns

BLVDS_25 0.11 0.11 ns

MINI_LVDS_25 0.75 0.75 ns

MINI_LVDS_33 0.40 0.40 ns

LVPECL_25 Inputs Only

LVPECL_33

RSDS_25 1.42 1.42 ns

RSDS_33 0.58 0.58 ns

TMDS_33 0.46 0.46 ns

PPDS_25 1.07 1.07 ns

PPDS_33 0.63 0.63 ns

DIFF_HSTL_I_18 0.43 0.43 ns

DIFF_HSTL_II_18 0.41 0.41 ns

DIFF_HSTL_III_18 0.36 0.36 ns

DIFF_HSTL_I 1.01 1.01 ns

DIFF_HSTL_III 0.54 0.54 ns

DIFF_SSTL18_I 0.49 0.49 ns

DIFF_SSTL18_II 0.41 0.41 ns

DIFF_SSTL2_I 0.82 0.82 ns

DIFF_SSTL2_II 0.09 0.09 ns

DIFF_SSTL3_I 1.16 1.16 ns

DIFF_SSTL3_II 0.28 0.28 ns

Add the

Adjustment

Below

Speed Grade

-5 -4

Units

Notes:

1. The numbers in this table are tested using the methodology presented in Ta bl e 2 6 and are based on the operating conditions set forth in Ta bl e 7 , Ta b le 10 , and Ta bl e 1 2 .

2. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state.

3. Note that 16 mA drive is faster than 24 mA drive for the Slow slew rate.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 31

Timing Measurement Methodology

Notes:

1. The names shown in parentheses are used in the IBIS file.

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Ta bl e 26 lists the conditions to use for each standard.

The method for measuring Input timing is as follows: A signal that swings between a Low logic level of V High logic level of V

is applied to the Input under test.

H

and a

L

Some standards also require the application of a bias voltage to the V

pins of a given bank to properly set the

REF

input-switching threshold. The measurement point of the Input signal (V and V

.

H

) is commonly located halfway between VL

M

LVCMOS, LVTTL), then R open connection, and V measurement point (V

T

) that was used at the Input is also

M

used at the Output.

X-Ref Target - Figure 8

FPGA Output

is set to 1MΩ to indicate an

T

is set to zero. The same

V

(V

REF

R

T

C

L

(R

(C

)

V

REF

(V

M

REF

)

MEAS

)

T

The Output test setup is shown in Figure 8. A termination voltage V

is applied to the termination resistor RT, the other

T

DS312-3_04_102406

end of which is connected to the Output. For each standard, R

and VT generally take on the standard values

T

recommended for minimizing signal reflections. If the standard does not ordinarily use terminations (for example,

Tab le 2 6 : Test Methods for Timing Measurement at I/Os

Signal Standard

(IOSTANDARD)

(V) VL (V) VH (V) RT (Ω)V

V

REF

Single-Ended

LV TT L – 0 3.3 1M 0 1.4

LV CM OS 33 – 0 3.3 1M 0 1.65

LV CM OS 25

– 0 2.5 1M 0 1.25

LV CM OS 18 – 0 1.8 1M 0 0.9

LV CM OS 15 – 0 1.5 1M 0 0.75

LV CM OS 12

– 0 1.2 1M 0 0.6

PCI33_3 Rising –Note 3 Note 3 25 0 0.94

Falling 25 3.3 2.03

PCI66_3 Rising

–Note 3 Note 3 25 0 0.94

Falling 25 3.3 2.03

HSTL_I 0.75 V

HSTL_III 0.9 V

HSTL_I_18 0.9 V

HSTL_II_18 0.9 V

HSTL_III_18 1.1 V

SSTL18_I 0.9 V

SSTL18_II 0.9 V

SSTL2_I 1.25 V

SSTL2_II 1.25 V

SSTL3_I 1.5 V

SSTL3_II 1.5 V

Inputs Outputs

– 0.5 V

REF

– 0.5 V

REF

– 0.5 V

REF

– 0.5 V

REF

– 0.5 V

REF

– 0.5 V

REF

– 0.5 V

REF

– 0.75 V

REF

– 0.75 V

REF

– 0.75 V

REF

– 0.75 V

REF

+ 0.5 50 0.75 V

REF

+ 0.5 50 1.5 V

REF

+ 0.5 50 0.9 V

REF

+ 0.5 25 0.9 V

REF

+ 0.5 50 1.8 V

REF

+ 0.5 50 0.9 V

REF

+ 0.5 25 0.9 V

REF

+ 0.75 50 1.25 V

REF

+ 0.75 25 1.25 V

REF

+ 0.75 50 1.5 V

REF

+ 0.75 25 1.5 V

REF

Figure 8: Output Test Setup

(2)

(V) VM (V)

T

Inputs and

Outputs

REF

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 32

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 6 : Test Methods for Timing Measurement at I/Os (Cont’d)

Signal Standard

(IOSTANDARD)

V

(V) VL (V) VH (V) RT (Ω)V

REF

Differential

LVDS_25

–V

LVDS_33 –V

BLVDS_25 –V

MINI_LVDS_25 –V

MINI_LVDS_33 –V

LVPECL_25 –V

LVPECL_33 –V

RSDS_25 –V

RSDS_33 –V

TMDS_33 –V

PPDS_25 –V

PPDS_33 –V

DIFF_HSTL_I_18 –V

DIFF_HSTL_II_18 –V

DIFF_HSTL_III_18 –V

DIFF_HSTL_I –V

DIFF_HSTL_III –V

DIFF_SSTL18_I –V

DIFF_SSTL18_II –V

DIFF_SSTL2_I –V

DIFF_SSTL2_II –V

DIFF_SSTL3_I –V

DIFF_SSTL3_II –V

Notes:

1. Descriptions of the relevant symbols are: V

– The reference voltage for setting the input switching threshold

REF

V

– The common mode input voltage

ICM

V

– Voltage of measurement point on signal transition

M

V

– Low-level test voltage at Input pin

L

V

– High-level test voltage at Input pin

H

R

– Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required

T

V

– Termination voltage

T

2. The load capacitance (C

) at the Output pin is 0 pF for all signal standards.

L

3. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/pci has equivalent characteristics but no PCI-X IP is supported.

Inputs Outputs

– 0.125 V

ICM

– 0.125 V

ICM

– 0.125 V

ICM

– 0.125 V

ICM

– 0.125 V

ICM

– 0.3 V

ICM

– 0.3 V

ICM

– 0.1 V

ICM

– 0.1 V

ICM

– 0.1 V

ICM

– 0.1 V

ICM

– 0.1 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

– 0.5 V

ICM

+ 0.125 50 1.2 V

ICM

+ 0.125 50 1.2 V

ICM

+ 0.125 1M 0 V

ICM

+ 0.125 50 1.2 V

ICM

+ 0.125 50 1.2 V

ICM

+ 0.3 N/A N/A V

ICM

+ 0.3 N/A N/A V

ICM

+ 0.1 50 1.2 V

ICM

+ 0.1 50 1.2 V

ICM

+ 0.1 50 3.3 V

ICM

+ 0.1 50 0.8 V

ICM

+ 0.1 50 0.8 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 1.8 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 0.9 V

ICM

+ 0.5 50 1.25 V

ICM

+ 0.5 50 1.25 V

ICM

+ 0.5 50 1.5 V

ICM

+ 0.5 50 1.5 V

ICM

(2)

(V) VM (V)

T

Inputs and

Outputs

ICM

. The PCIX IOSTANDARD is available and

The capacitive load (CL) is connected between the output and GND. The Output timing for all standards, as published in the

speed files and the data sheet, is always based on a C

value of zero. High-impedance probes (less than 1 pF) are used for

L

all measurements. Any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 33

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Using IBIS Models to Simulate Load Conditions in Application

IBIS models permit the most accurate prediction of timing delays for a given application. The parameters found in the IBIS model (V with the parameters used in Ta bl e 2 6 (V not confuse V model with V table. A fourth parameter, C

, R

REF

, and V

REF

(the termination voltage) from the IBIS

(the input-switching threshold) from the

REF

) correspond directly

MEAS

, RT, and VM). Do

T

, is always zero. The four parameters describe all relevant output test conditions. IBIS models are found in the Xilinx development software as well as at the following link:

www.xilinx.com/support/download/index.htm

Delays for a given application are simulated according to its specific load conditions as follows:

1. Simulate the desired signal standard with the output

driver connected to the test setup shown in Figure 8. Use parameter values V C

is zero.

REF

2. Record the time to V

, RT, and VM from Ta bl e 2 6.

T

.

M

3. Simulate the same signal standard with the output

driver connected to the PCB trace with load. Use the appropriate IBIS model (including V and V

values) or capacitive value to represent the

MEAS

REF

, R

REF

, C

REF

,

load.

4. Record the time to V

MEAS

.

5. Compare the results of steps 2 and 4. Add (or subtract)

the increase (or decrease) in delay to (or from) the appropriate Output standard adjustment (Tab le 2 5) to yield the worst-case delay of the PCB trace.

Simultaneously Switching Output Guidelines

This section provides guidelines for the recommended maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins of a given output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.

and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.

Ta bl e 2 7 and Ta b le 2 8 provide the essential SSO

guidelines. For each device/package combination, Ta b le 2 7 provides the number of equivalent V

/GND pairs. The

CCO

equivalent number of pairs is based on characterization and may not match the physical number of pairs. For each output signal standard and drive strength, Ta b le 2 8 recommends the maximum number of SSOs, switching in the same direction, allowed per V

/GND pair within an

CCO

I/O bank. The guidelines in Ta bl e 2 8 are categorized by package style, slew rate, and output drive current. Furthermore, the number of SSOs is specified by I/O bank. Generally, the left and right I/O banks (Banks 1 and 3) support higher output drive current.

Multiply the appropriate numbers from Tab le 2 7 and

Ta bl e 2 8 to calculate the maximum number of SSOs

allowed within an I/O bank. Exceeding these SSO guidelines might result in increased power or ground bounce, degraded signal integrity, or increased system jitter.

SSO

/IO Bank = Ta b le 2 7 x Ta bl e 2 8

MAX

The recommended maximum SSO values assumes that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.

The SSO values assume that the V

3.3V. Setting V

to 2.5V provides better SSO

CCAUX

is powered at

CCAUX

characteristics.

Tab l e 2 7: Equivalent V

Device

XC3SD1800A 6 9

XC3SD3400A 6 10

/GND Pairs per Bank

CCO

Package Style (including Pb-free)

CS484 FG676

Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the V

CCO

rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame,

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 34

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 8 : Recommended Simultaneously Switching Outputs per V

/GND Pair (V

CCO

CCAUX

=3.3V)

Package Type

Signal Standard

(IOSTANDARD)

CS484, FG676

Top, Bottom

(Banks 0, 2)

Left, Right

(Banks 1, 3)

Single-Ended Standards

LVTTL Slow 2 60 60

441 41

629 29

822 22

12 13 13

16 11 11

24 9 9

Fast 2 10 10

46 6

65 5

83 3

12 3 3

16 3 3

24 2 2

QuietIO 2 80 80

448 48

636 36

827 27

12 16 16

16 13 13

24 12 12

Tab l e 2 8: Recommended Simultaneously Switching Outputs per V

Signal Standard

(IOSTANDARD)

LV CM OS 33 S lo w 2 76 7 6

/GND Pair (V

CCO

CCAUX

=3.3V) (Cont’d)

Package Type

CS484, FG676

Top, Bottom

(Banks 0, 2)

446 46

627 27

820 20

12 13 13

16 10 10

24

–9

Fast 2 10 10

48 8

65 5

84 4

12 4 4

16 2 2

24

–2

QuietIO 2 76 76

446 46

632 32

826 26

12 18 18

16 14 14

24

–10

Left, Right

(Banks 1, 3)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 35

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 8 : Recommended Simultaneously Switching Outputs per V

Signal Standard

(IOSTANDARD)

LV CM OS 25 S lo w 2 76 7 6

/GND Pair (V

CCO

CCAUX

=3.3V) (Cont’d)

Package Type

CS484, FG676

Top, Bottom

(Banks 0, 2)

446 46

633 33

824 24

12 18 18

16

24 –7

Fast 2 18 18

414 14

66 6

86 6

12 3 3

16

24 –2

QuietIO 2 76 76

460 60

648 48

836 36

12 36 36

16

24 –8

–11

–3

–36

Left, Right

(Banks 1, 3)

Tab l e 2 8: Recommended Simultaneously Switching Outputs per V

Signal Standard

(IOSTANDARD)

LV CM OS 18 S lo w 2 64 6 4

LV CM OS 15 S lo w 2 55 5 5

/GND Pair (V

CCO

CCAUX

=3.3V) (Cont’d)

Package Type

CS484, FG676

Top, Bottom

(Banks 0, 2)

434 34

622 22

818 18

12

16

Fast 2 18 18

49 9

67 7

84 4

12

16 –3

QuietIO 2 64 64

464 64

648 48

836 36

12

16 –24

431 31

618 18

8

12

Fast 2 25 25

410 10

66 6

8

12

QuietIO 2 70 70

440 40

631 31

8

12 –20

–13

–10

–4

–36

–15

–10

–4

–3

–31

Left, Right

(Banks 1, 3)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 36

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 2 8 : Recommended Simultaneously Switching Outputs per V

Signal Standard

(IOSTANDARD)

LV CM OS 12 S lo w 2 40 4 0

PCI33_3 16 16

PCI66_3 –13

HSTL_I –20

HSTL_III

HSTL_I_18 17 17

HSTL_II_18 –5

HSTL_III_18 10 8

SSTL18_I 7 15

SSTL18_II

SSTL2_I 18 18

SSTL2_II

SSTL3_I 8 10

SSTL3_II 6 7

/GND Pair (V

CCO

CCAUX

=3.3V) (Cont’d)

Package Type

CS484, FG676

Top, Bottom

(Banks 0, 2)

4

6

–25

–18

Fast 2 31 31

4

6

–13

–9

QuietIO 2 55 55

4

6

–36

–8

–9

Left, Right

(Banks 1, 3)

Tab l e 2 8: Recommended Simultaneously Switching Outputs per V

Signal Standard

(IOSTANDARD)

Differential Standards (Number of I/O Pairs or Channels)

LV DS _2 5 2 2

LV DS _3 3 2 7 –

BLVDS_25 4 4

MINI_LVDS_25 22

MINI_LVDS_33 27 –

LVPECL_25

LVPECL_33 Inputs Only

RSDS_25 22 –

RSDS_33 27

TMDS_33 27 –

PPDS_25 22 –

PPDS_33 27 –

DIFF_HSTL_I_18 8 8

DIFF_HSTL_II_18

DIFF_HSTL_III_18 5 4

DIFF_HSTL_I

DIFF_HSTL_III –4

DIFF_SSTL18_I 3 7

DIFF_SSTL18_II

DIFF_SSTL2_I 9 9

DIFF_SSTL2_II –4

DIFF_SSTL3_I 4 5

DIFF_SSTL3_II 3 3

/GND Pair (V

CCO

CCAUX

=3.3V) (Cont’d)

Package Type

CS484, FG676

Top, Bottom

(Banks 0, 2)

Left, Right

(Banks 1, 3)

Inputs Only

–2

–10

–4

–

Notes:

1. Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in top or bottom banks (I/O banks 0 and 2). Refer to UG331 Generation FPGA User Guide for additional information.

2. The numbers in this table are recommendations that assume sound board lay out practice. This table assumes the following parasitic factors: combined PCB trace and land inductance per V

and GND pin of 1.0 nH, receiver capacitive load of 15 pF.

CCO

Test limits are the V standard.

3. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689 Large FPGAs for information on how to perform weighted average SSO calculations.

voltage limits for the respective I/O

IL/VIH

: Managing Ground Bounce in

: Spartan-3

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 37

Configurable Logic Block (CLB) Timing

Tab le 2 9 : CLB (SLICEM) Timing

Symbol Description

Clock-to-Output Times

T

CKO

Setup Times

T

AS

T

DICK

Hold Times

T

AH

T

CKDI

Clock Timing

T

CH

T

CL

F

TOG

Propagation Times

T

ILO

Set/Reset Pulse Width

T

RPW_CLB

When reading from the FFX (FFY) Flip-Flop, the time from the active transition at the CLK input to data appearing at the XQ (YQ) output

Time from the setup of data at the F or G input to the active transition at the CLK input of the CLB

Time from the setup of data at the BX or BY input to the active transition at the CLK input of the CLB

Time from the active transition at the CLK input to the point where data is last held at the F or G input

Time from the active transition at the CLK input to the point where data is last held at the BX or BY input

The High pulse width of the CLB’s CLK signal 0.63 –0.75–ns

The Low pulse width of the CLK signal 0.63 –0.75–ns

Toggle frequency (for export control) 0 770 0 667 MHz

The time it takes for data to travel from the CLB’s F (G) input to the X (Y) output

The minimum allowable pulse width, High or Low, to the CLB’s SR input

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Speed Grade

Units-5 -4

Min Max Min Max

–0.60–0.68ns

0.18 –0.36–ns

1.58 –1.88–ns

0.00 –0.00–ns

–0.62–0.71ns

1.33 –1.61–ns

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 38

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 3 0 : CLB Distributed RAM Switching Characteristics

Symbol Description

Clock-to-Output Times

T

SHCKO

Setup Times

T

DS

T

AS

T

WS

Hold Times

T

DH

T

AH, TWH

Clock Pulse Width

T

, T

WPH

WPL

Tab le 3 1 : CLB Shift Register Switching Characteristics

Symbol Description

Clock-to-Output Times

T

REG

Setup Times

T

SRLDS

Hold Times

T

SRLDH

Clock Pulse Width

T

, T

WPH

WPL

Time from the active edge at the CLK input to data appearing on the distributed RAM output

Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM

Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM

Setup time of the write enable input before the active transition at the CLK input of the distributed RAM

Hold time of the BX and BY data inputs after the active transition at the CLK input of the distributed RAM

Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM

Minimum High or Low pulse width at CLK input 0.88 –1.01–ns

Time from the active edge at the CLK input to data appearing on the shift register output

Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register

Hold time of the BX or BY data input after the active transition at the CLK input of the shift register

Minimum High or Low pulse width at CLK input 0.90 –1.01–ns

Speed Grade

Units-5 -4

Min Max Min Max

–1.44–1.72ns

–0.07 – –0.02 –ns

0.18 –0.36–ns

0.30 –0.59–ns

0.13 –0.13–ns

0.01 –0.01–ns

Speed Grade

Units-5 -4

Min Max Min Max

–4.11–4.82ns

0.13 –0.18–ns

0.16 –0.16–ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 39

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Clock Buffer/Multiplexer Switching Characteristics

Tab le 3 2 : Clock Distribution Switching Characteristics

Symbol Description Minimum

T

GIO

T

GSI

F

BUFG

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay

Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input

Frequency of signals distributed on global buffers (all sides) 0 350 334 MHz

Maximum

UnitsSpeed Grade

-5 -4

–0.220.23ns

–0.560.63ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 40

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Block RAM Timing

Tab le 3 3 : Block RAM Timing

Symbol Description

Clock-to-Output Times

T

RCKO_DOA_NC

T

RCKO_DOA

Setup Times

T

RCCK_ADDR

T

RDCK_DIB

T

RCCK_ENB

T

RCCK_WEB

T

RCCK_REGCE

T

RCCK_RST

Hold Times

T

RCKC_ADDR

T

RCKC_DIB

T

RCKC_ENB

T

RCKC_WEB

T

RCKC_REGCE

T

RCKC_RST

Clock Timing

T

BPWH

T

BPWL

Clock Frequency

F

BRAM

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

When reading from block RAM, the delay from the active transition at the CLK input to data appearing at the DOUT output

Clock CLK to DOUT output (with output register) –1.24–1.45ns

Setup time for the ADDR inputs before the active transition at the CLK input of the block RAM

Setup time for data at the DIN inputs before the active transition at the CLK input of the block RAM

Setup time for the EN input before the active transition at the CLK input of the block RAM

Setup time for the WE input before the active transition at the CLK input of the block RAM

Setup time for the CE input before the active transition at the CLK input of the block RAM

Setup time for the RST input before the active transition at the CLK input of the block RAM

Hold time on the ADDR inputs after the active transition at the CLK input

Hold time on the DIN inputs after the active transition at the CLK input 0.09 –0.10–ns

Hold time on the EN input after the active transition at the CLK input 0.09 –0.10–ns

Hold time on the WE input after the active transition at the CLK input 0.09 –0.10–ns

Hold time on the CE input after the active transition at the CLK input 0.09 –0.10–ns

Hold time on the RST input after the active transition at the CLK input 0.09 –0.10–ns

High pulse width of the CLK signal 1.56 –1.79–ns

Low pulse width of the CLK signal 1.56 –1.79–ns

Block RAM clock frequency 0 320 0 280 MHz

Speed Grade

Units-5 -4

Min Max Min Max

–2.38–2.80ns

0.40 –0.46–ns

0.29 –0.33–ns

0.51 –0.60–ns

0.64 –0.75–ns

0.34 –0.40–ns

0.22 –0.25–ns

0.09 –0.10–ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 41

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

DSP48A Timing

To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.

Tab le 3 4 : Setup Times for the DSP48A

Speed Grade

Symbol Description Pre-adder Multiplier Post-adder

Min Min

Setup Times of Data/Control Pins to the Input Register Clock

T

DSPDCK_AA

T

DSPDCK_DB

T

DSPDCK_CC

T

DSPDCK_DD

T

DSPDCK_OPB

T

DSPDCK_OPOP

A input to A register CLK – – – 0.04 0.04 ns

D input to B register CLK Yes – – 1.64 1.88 ns

C input to C register CLK – – – 0.05 0.05 ns

D input to D register CLK – – – 0.04 0.04 ns

OPMODE input to B register CLK Yes – – 0.37 0.42 ns

OPMODE input to OPMODE register CLK – – – 0.06 0.06 ns

Setup Times of Data Pins to the Pipeline Register Clock

T

DSPDCK_AM

T

DSPDCK_BM

A input to M register CLK –Yes– 3.30 3.79 ns

B input to M register CLK Yes Yes – 4.33 4.97 ns

No Yes – 3.30 3.79 ns

T

DSPDCK_DM

T

DSPDCK_OPM

D input to M register CLK Yes Yes – 4.41 5.06 ns

OPMODE to M register CLK Yes Yes – 4.72 5.42 ns

Setup Times of Data/Control Pins to the Output Register Clock

T

DSPDCK_AP

T

DSPDCK_BP

A input to P register CLK – Yes Yes 4.78 5.49 ns

B input to P register CLK Yes Yes Yes 5.87 6.74 ns

No Yes Yes 4.77 5.48 ns

T

DSPDCK_DP

T

DSPDCK_CP

T

DSPDCK_OPP

D input to P register CLK Yes Yes Yes 5.95 6.83 ns

C input to P register CLK – – Yes 1.90 2.18 ns

OPMODE input to P register CLK Yes Yes Yes 6.25 7.18 ns

Notes:

1. "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not applicable.

2. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

Units-5 -4

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Product Specification 42

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 3 5 : Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A

Speed Grade

Symbol Description Pre-adder Multiplier Post-adder

Max Max

Clock to Out from Output Register Clock to Output Pin

T

DSPCKO_PP

CLK (PREG) to P output – – – 1.26 1.44 ns

Clock to Out from Pipeline Register Clock to Output Pins

T

DSPCKO_PM

CLK (MREG) to P output – Yes Yes 3.16 3.63 ns

– Yes No 1.94 2.23 ns

Clock to Out from Input Register Clock to Output Pins

T

DSPCKO_PA

T

DSPCKO_PB

T

DSPCKO_PC

T

DSPCKO_PD

CLK (AREG) to P output – Yes Yes 6.33 7.27 ns

CLK (BREG) to P output Yes Yes Yes 7.45 8.56 ns

CLK (CREG) to P output – – Yes 3.37 3.87 ns

CLK (DREG) to P output Yes Yes Yes 7.33 8.42 ns

Combinatorial Delays from Input Pins to Output Pins

T

DSPDO_AP

T

DSPDO_BP

A or B input to P output – No Yes 2.78 3.19 ns

– Yes No 4.60 5.28 ns

– Yes Yes 5.65 6.49 ns

T

DSPDO_BP

B input to P output Yes No No 3.49 4.01 ns

Yes Yes No 5.79 6.65 ns

Ye s Ye s Ye s 6 . 7 4 7 . 7 4 n s

T

DSPDO_CP

T

DSPDO_DP

T

DSPDO_OPP

C input to P output – – Yes 2.76 3.17 ns

D input to P output Yes Yes Yes 6.81 7.82 ns

OPMODE input to P output Yes Yes Yes 7.12 8.18 ns

Maximum Frequency

F

MAX

All registers used Yes Yes Yes 287 250 MHz

Notes:

1. To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide.

2. "Yes" means that the component is in the path. "No" means that the component is being bypassed. “–“ means that no path exists, so it is not applicable.

3. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

Units-5 -4

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 43

Digital Clock Manager (DCM) Timing

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS).

Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the

Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period.

Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the

mean value is zero. DLL tables (Ta bl e 36 and Ta bl e 37 ) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Ta bl e 3 8 through Ta b l e 4 1 ) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Ta bl e 3 6 and Ta bl e 37 .

Spread Spectrum

DCMs accept typical spread spectrum clocks as long as

they meet the input requirements. The DLL will track the

frequency changes created by the spread spectrum clock to

drive the global clocks to the FPGA logic. See XAPP469

Spread-Spectrum Clocking Reception for Displays for

details.

Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value.

Delay-Locked Loop (DLL)

Tab le 3 6 : Recommended Operating Conditions for the DLL

Symbol Description

Input Frequency Ranges

F

CLKIN

Input Pulse Requirements

CLKIN_PULSE CLKIN pulse width as a

Input Clock Jitter Tolerance and Delay Path Variation

CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the

CLKIN_CYC_JITT_DLL_HF F

CLKIN_PER_JITT_DLL Period jitter at the CLKIN input

CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay

CLKIN_FREQ_DLL Frequency of the CLKIN clock input 5

F

< 150 MHz 40% 60% 40% 60% – percentage of the CLKIN period

(4)

CLKIN input

from the DCM output to the CLKFB input

CLKIN

F

> 150 MHz 45% 55% 45% 55% –

CLKIN

F

< 150 MHz –±300–±300ps

CLKIN

> 150 MHz –±150–±150ps

CLKIN

:

Speed Grade

Units-5 -4

Min Max Min Max

(2)

–±1–±1ns

280

(3)

(2)

5

250

(3)

MHz

Notes:

1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Tab l e 3 8 .

3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.

4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.

5. The DCM specifications are guaranteed when both adjacent DCMs are locked.

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Product Specification 44

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 3 7 : Switching Characteristics for the DLL

Speed Grade

Symbol Description Device

Min Max Min Max

Output Frequency Ranges

CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs All 5 280 5 250 MHz

CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 5 200 MHz

CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs 10 334 10 334 MHz

CLKOUT_FREQ_DV Frequency for the CLKDV output 0.3125 186 0.3125 166 MHz

Output Clock Jitter

(2)(3)(4)

CLKOUT_PER_JITT_0 Period jitter at the CLK0 output All –±100–±100ps

CLKOUT_PER_JITT_90 Period jitter at the CLK90 output –±150–±150ps

CLKOUT_PER_JITT_180 Period jitter at the CLK180 output

–±150–±150ps

CLKOUT_PER_JITT_270 Period jitter at the CLK270 output –±150–±150ps

CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs – ±[0.5%

– ±[0.5%

of

CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing

CLKIN

period

+ 100]

–±150–±150ps

CLKIN

period + 100]

integer division

CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing

non-integer division

Duty Cycle

CLKOUT_DUTY_CYCLE_ DLL

(4)

Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion

Phase Alignment

(4)

– ±[0.5%

of

CLKIN

period

+ 100]

All –±[1% of

CLKIN

period

+ 350]

– ±[0.5%

CLKIN

period + 100]

–±[1% of

CLKIN

period + 350]

CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs All –±150–±150ps

CLKOUT_PHASE_DLL Phase offset between DLL

outputs

CLK0 to CLK2X (not CLK2X180)

All others

–±[1% of

CLKIN

period

+ 100]

–±[1% of

CLKIN

period

+ 150]

–±[1% of

CLKIN

period + 100]

–±[1% of

CLKIN

period + 150]

Lock Time

LOCK_DLL

(3)

When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED

5 MHz < FCLKIN <

15 MHz

FCLKIN > 15 MHz

All

–5–5ms

– 600 – 600 µs

output. When the DCM is locked, the CLKIN and CLKFB signals are in phase

Units-5 -4

ps

of

ps

of

ps

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 45

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 3 7 : Switching Characteristics for the DLL (Cont’d)

Speed Grade

Symbol Description Device

Units-5 -4

Min Max Min Max

Delay Lines

DCM_DELAY_STEP

(5)

Finest delay resolution, averaged over all steps All 15 35 15 35 ps

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 and Ta bl e 3 6 .

2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.

3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.

4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of ±[1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.

5. The typical delay step size is 23 ps.

Digital Frequency Synthesizer (DFS)

Tab le 3 8 : Recommended Operating Conditions for the DFS

Speed Grade

Symbol Description

Min Max Min Max

Input Frequency Ranges

F

CLKIN

CLKIN_FREQ_FX Frequency for the CLKIN input 0.2 333

Input Clock Jitter Tolerance

CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the

CLKIN_CYC_JITT_FX_HF F

(2)

(3)

CLKIN input, based on CLKFX output frequency

(5)

0.2 333

F

< 150 MHz –±300–±300ps

CLKFX

> 150 MHz –±150–±150ps

CLKFX

CLKIN_PER_JITT_FX Period jitter at the CLKIN input –±1–±1ns

Notes:

1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.

2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Ta bl e 3 6 .

3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.

4. The DCM specifications are guaranteed when both adjacent DCMs are locked.

5. To support double the maximum effective F clock frequency by two as it enters the DCM.

limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming

CLKIN

(5)

Units-5 -4

MHz

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 46

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 3 9 : Switching Characteristics for the DFS

Symbol Description

Output Frequency Ranges

(6)

(2)

Frequency for the CLKFX and CLKFX180 outputs All 5 350 5 311 MHz

(3)(4)

CLKIN

CLKFX180 outputs.

≤ 20 MHz

CLKIN

> 20 MHz

outputs, including the BUFGMUX and clock tree duty-cycle distortion

DLL CLK0 output when both the DFS and DLL are used

the DLL CLK0 output when both the DFS and DLL are used

The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are

5 MHz <

15 MHz

<

F

CLKIN

15 MHz

F

CLKIN

>

valid. If using both the DLL and the DFS, use the longer locking time.

CLKOUT_FREQ_FX

Output Clock Jitter

CLKOUT_PER_JITT_FX Period jitter at the CLKFX and

Duty Cycle

(5)(6)

CLKOUT_DUTY_CYCLE_FXDuty cycle precision for the CLKFX and CLKFX180

Phase Alignment

CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the

CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and

Lock Time

LOCK_FX

(2)(3)

Speed Grade

Device

Units-5 -4

Min Max Min Max

All Typ Max Typ Max

Use the Spartan-3A Jitter Calculator:

www.xilinx.com/support/documentation/

data_sheets/s3a_jitter_calc.zip

±[1% of CLKFX

period + 100]

All –±[1% of

±[1% of

CLKFX

period + 200]

CLKFX

period + 350]

±[1% of

CLKFX

period + 100]

–±[1% of

±[1% of CLKFX

period + 200]

CLKFX

period + 350]

All –±200–±200ps

All

–±[1% of

CLKFX

period + 200]

All

–5–5ms

–±[1% of

CLKFX

period + 200]

– 450 – 450 µs

ps

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 and Ta bl e 3 8 .

2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.

3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.

4. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching) on an FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.

5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.

6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 47

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Phase Shifter (PS)

Tab le 4 0 : Recommended Operating Conditions for the PS in Variable Phase Mode

Speed Grade

Symbol Description

Min Max Min Max

Operating Frequency Ranges

PSCLK_FREQ (FPSCLK)

Frequency for the PSCLK input 1 167 1 167 MHz

Input Pulse Requirements

PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period 40% 60% 40% 60% –

Tab le 4 1 : Switching Characteristics for the PS in Variable Phase Mode

Symbol Description Phase Shift Amount Units

Phase Shifting Range

MAX_STEPS

FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting ±[MAX_STEPS •

FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±[MAX_STEPS •

(2,3)

Maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE, double the effective clock period.

CLKIN < 60 MHz ±[INTEGER(10 • (T

CLKIN ≥ 60 MHz ±[INTEGER(15 • (T

DCM_DELAY_STEP_MIN]

DCM_DELAY_STEP_MAX]

– 3 ns))] steps

CLKIN

– 3 ns))]

CLKIN

Units-5 -4

ns

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta b le 7 and Ta b l e 4 0 .

2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the PHASE_SHIFT attribute is set to 0.

3. The DCM_DELAY_STEP values are provided at the bottom of Tab l e 37 .

Miscellaneous DCM Timing

Tab le 4 2 : Miscellaneous DCM Timing

Symbol Description Min Max Units

DCM_RST_PW_MIN Minimum duration of a RST pulse width 3 –CLKIN

cycles

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Product Specification 48

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

DNA Port Timing

Tab le 4 3 : DNA_PORT Interface Timing

Symbol Description Min Max Units

T

DNASSU

T

DNASH

T

DNADSU

T

DNADH

T

DNARSU

T

DNARH

T

DNADCKO

T

DNACLKF

T

DNACLKH

T

DNACLKL

Notes:

1. The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 μs.

Setup time on SHIFT before the rising edge of CLK 1.0 –ns

Hold time on SHIFT after the rising edge of CLK 0.5 –ns

Setup time on DIN before the rising edge of CLK 1.0 –ns

Hold time on DIN after the rising edge of CLK 0.5 –ns

Setup time on READ before the rising edge of CLK 5.0 10,000 ns

Hold time on READ after the rising edge of CLK 0.0 –ns

Clock-to-output delay on DOUT after rising edge of CLK 0.5 1.5 ns

CLK frequency 0.0 100 MHz

CLK High time 1.0 ∞ ns

CLK Low time 1.0 ∞ ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 49

Suspend Mode Timing

DS610-3_08_061207

Blocked

t

SUSPEND_DISABLE

t

SUSPEND_GWE

t

SUSPENDHIGH_AWAKE

t

AWAKE_GWE

t

AWAKE_GTS

t

SUSPEND_GTS

SUSPEND Input

AWAKE Output

Flip-Flops, Block RAM,

Distributed RAM

FPGA Outputs

FPGA Inputs, Interconnect

Write Protected

Defined by SUSPEND constraint

Entering Suspend Mode Exiting Suspend Mode

sw_gts_cycle

sw_gwe_cycle

t

SUSPEND_ENABLE

t

SUSPENDLOW_AWAKE

X-Ref Target - Figure 9

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Figure 9: Suspend Mode Timing

Tab le 4 4 : Suspend Mode Timing Parameters

Symbol Description Min Typ Max Units

Entering Suspend Mode

T

SUSPENDHIGH_AWAKE

T

SUSPENDFILTER

T

SUSPEND_GTS

T

SUSPEND_GWE

T

SUSPEND_DISABLE

Exiting Suspend Mode

T

SUSPENDLOW_AWAKE

T

SUSPEND_ENABLE

T

AWAKE_GWE1

T

AWAKE_GWE512

T

AWAKE_GTS1

T

AWAKE_GTS512

Notes:

1. These parameters based on characterization.

2. For information on using the Spartan-3A DSP Suspend feature, see XAPP480

Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter (suspend_filter:No)

Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled (suspend_filter:Yes)

Rising edge of SUSPEND pin until FPGA output pins drive their defined SUSPEND constraint behavior

Rising edge of SUSPEND pin to write-protect lock on all writable clocked elements

Rising edge of the SUSPEND pin to FPGA input pins and interconnect disabled

Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not include DCM lock time.

Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-enabled

Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.

Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.

Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.

Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512.

: Using Suspend Mode in Spartan-3 Generation FPGAs.

–7–ns

+160 +300 +600 ns

–10–ns

–<5–ns

– 340 –ns

– 4 to 108 – μs

– 3.7 to 109 – μs

–67–ns

–14–µs

–57–ns

–14–µs

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 50

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Notes:

1. The V

CCINT

, V

CCAUX

, and V

CCO

supplies can be applied in any order.

2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.

3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

Configuration and JTAG Timing

General Configuration Power-On/Reconfigure Timing

X-Ref Target - Figure 10

V

CCINT

(Supply)

V

CCAUX

(Supply)

V

Bank 2

CCO

(Supply)

PROG_B

(Input)

INIT_B

(Open-Drain)

CCLK

(Output)

1.0V

2.0V

T

POR

PROG

1.2V

2.5V

or

3.3V

2.5V

or

3.3V

T

PL

T

ICCK

DS529-3_01_052708

Figure 10: Waveforms for Power-On and the Beginning of Configuration

Tab le 4 5 : Power-On Timing and the Beginning of Configuration

Symbol Description Device

T

POR

(2)

The time from the application of V Bank 2 supply voltage ramps (whichever occurs last) to the

CCINT

, V

CCAUX

, and V

CCO

All

rising transition of the INIT_B pin

T

PROG

T

PL

T

INIT

T

ICCK

(2)

(3)

The width of the low-going pulse on the PROG_B pin All 0.5 –µs

The time from the rising edge of the PROG_B pin to the

All –2ms

rising transition on the INIT_B pin

Minimum Low pulse width on INIT_B output All 300 –ns

The time from the rising edge of the INIT_B pin to the

All 0.5 4 µs generation of the configuration clock signal at the CCLK output pin

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 . This means power must be applied to all V and V

CCAUX

lines.

2. Power-on reset and the clearing of configuration memory occurs during this period.

3. This specification applies only to the Master Serial, SPI, and BPI modes.

4. For details on configuration, see UG332

Spartan-3 Generation Configuration User Guide.

All Speed Grades

Min Max

–18ms

CCINT

Units

, V

CCO

,

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 51

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Configuration Clock (CCLK) Characteristics

Tab le 4 6 : Master Mode CCLK Output Period by ConfigRate Option Setting

Symbol Description

T

CCLK1

T

CCLK3

T

CCLK6

T

CCLK7

T

CCLK8

T

CCLK10

T

CCLK12

T

CCLK13

T

CCLK17

T

CCLK22

T

CCLK25

T

CCLK27

T

CCLK33

T

CCLK44

T

CCLK50

T

CCLK100

CCLK clock period by

ConfigRate setting

ConfigRate

Setting

(1)

1

(power-on value)

3

6

(default)

7

8

10

12

13

17

22

25

27

33

44

50

100

Temperature

Range

Commercial 1,254

Industrial 1,180 ns

Commercial 413

Industrial 390 ns

Commercial 207

Industrial 195 ns

Commercial 178

Industrial 168 ns

Commercial 156

Industrial 147 ns

Commercial 123

Industrial 116 ns

Commercial 103

Industrial 97 ns

Commercial 93

Industrial 88 ns

Commercial 72

Industrial 68 ns

Commercial 54

Industrial 51 ns

Commercial 47

Industrial 45 ns

Commercial 44

Industrial 42 ns

Commercial 36

Industrial 34 ns

Commercial 26

Industrial 25 ns

Commercial 22

Industrial 21 ns

Commercial 11.2

Industrial 10.6 ns

Minimum Maximum Units

2,500

833

417

357

313

250

208

192

147

114

100

93

76

57

50

25

ns

Notes:

1. Set the ConfigRate option value when generating a configuration bitstream.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 52

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 4 7 : Master Mode CCLK Output Frequency by ConfigRate Option Setting

Symbol Description

F

CCLK1

F

CCLK3

F

CCLK6

F

CCLK7

F

CCLK8

F

CCLK10

F

CCLK12

F

CCLK13

F

CCLK17

F

CCLK22

F

CCLK25

F

CCLK27

F

CCLK33

F

CCLK44

F

CCLK50

F

CCLK100

Equivalent CCLK clock frequency by ConfigRate setting

ConfigRate

Setting

1

(power-on value)

3

6

(default)

7

8

10

12

13

17

22

25

27

33

44

50

100

Temperature

Range

Commercial

Industrial 0.847 MHz

Commercial

Industrial 2.57 MHz

Commercial

Industrial 5.13 MHz

Commercial

Industrial 5.96 MHz

Commercial

Industrial 6.81 MHz

Commercial

Industrial 8.63 MHz

Commercial

Industrial 10.31 MHz

Commercial

Industrial 11.37 MHz

Commercial

Industrial 14.61 MHz

Commercial

Industrial 19.61 MHz

Commercial

Industrial 22.23 MHz

Commercial

Industrial 23.81 MHz

Commercial

Industrial 29.23 MHz

Commercial

Industrial 40.00 MHz

Commercial

Industrial 47.66 MHz

Commercial

Industrial 94.34 MHz

Minimum Maximum Units

0.400

1.20

2.40

2.80

3.20

4.00

4.80

5.20

6.80

8.80

10.00

10.80

13.20

17.60

20.00

40.00

0.797 MHz

2.42 MHz

4.83 MHz

5.61 MHz

6.41 MHz

8.12 MHz

9.70 MHz

10.69 MHz

13.74 MHz

18.44 MHz

20.90 MHz

22.39 MHz

27.48 MHz

37.60 MHz

44.80 MHz

88.68 MHz

Tab le 4 8 : Master Mode CCLK Output Minimum Low and High Time

Symbol Description

T

MCCL,

T

MCCH

Master Mode

CCLK

Minimum

Low and High

Commercial 595 196 98.3 84.5 74.1 58.4 48.9 44.1 34.2 25.6 22.3 20.9 17.1 12.3 10.4 5.3 ns

Industrial 560 185 92.6 79.8 69.8 55.0 46.0 41.8 32.3 24.2 21.4 20.0 16.2 11.9 10.0 5.0 ns

Time

1 3 6 7 8 10121317222527334450100

ConfigRate Setting

Units

Tab le 4 9 : Slave Mode CCLK Input Low and High Time

Symbol Description Min Max Units

T

SCCL

T

SCCH

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 53

CCLK Low and High time 5 ∞ ns

Master Serial and Slave Serial Mode Timing

DS312-3_05_103105

Bit 0 Bit 1

Bit n

Bit n+1

Bit n-64

Bit n-63

1/F

CCSER

T

SCCL

T

DCC

T

CCD

T

SCCH

T

CCO

PROG_B

(Input)

DIN

(Input)

DOUT

(Output)

(Open-Drain)

INIT_B

(Input/Output)

CCLK

T

MCCL

T

MCCH

X-Ref Target - Figure 11

Figure 11: Waveforms for Master Serial and Slave Serial Configuration

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Tab le 5 0 : Timing for the Master Serial and Slave Serial Configuration Modes

Clock-to-Output Times

T

Setup Times

T

Hold Times

T

Clock Timing

T

F

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.

Symbol Description

CCO

DCC

CCD

CCH

CCL

CCSER

The time from the falling transition on the CCLK pin to data appearing at the DOUT pin

The time from the setup of data at the DIN pin to the rising transition at the CCLK pin

The time from the rising transition at the CCLK pin to the point when data is last held at the DIN pin

High pulse width at the CCLK input pin Master See Ta b le 4 8

Low pulse width at the CCLK input pin Master See Ta b le 4 8

Frequency of the clock signal at the CCLK input pin

(2)

No bitstream compression Slave 0 100 MHz

With bitstream compression 0 100 MHz

Slave/

Master

All Speed Grades

Units

Min Max

Both 1.5 10 ns

Both 7 –ns

Master 0.0 –ns

Slave 1.0

–ns

Slave See Ta b le 4 9

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 54

Slave Parallel Mode Timing

DS529-3_02_051607

Byte 0 Byte 1 Byte n Byte n+1

T

SMWCC

1/F

CCPAR

T

SMCCCS

T

SCCH

T

SMCCW

T

SMCCD

T

SMCSCC

T

SMDCC

PROG_B

(Input)

(Open-Drain)

INIT_B

(Input)

CSI_B

RDWR_B

(Input)

CCLK

(Inputs)

D0 - D7

T

MCCH

T

SCCL

T

MCCL

Notes:

1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B switches High, be careful to avoid contention on the D0–D7 bus.

2. To pause configuration, pause CCLK instead of de-asserting CSI_B. See UG332,

Chapter 7, section “Non-Continuous SelectMAP Data

Loading” for more details.

X-Ref Target - Figure 12

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Figure 12: Waveforms for Slave Parallel Configuration

Tab le 5 1 : Timing for the Slave Parallel Configuration Mode

Symbol Description

Setup Times

SMDCC

SMCSCC

SMCCW

SMCCD

SMCCCS

SMWCC

CCH

CCL

CCPAR

(2)

The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin 7 –ns

Setup time on the CSI_B pin before the rising transition at the CCLK pin 7 –ns

Setup time on the RDWR_B pin before the rising transition at the CCLK pin 17 –ns

The time from the rising transition at the CCLK pin to the point when data is last held at the D0-D7 pins

The time from the rising transition at the CCLK pin to the point when a logic level is last held at the CSO_B pin

The time from the rising transition at the CCLK pin to the point when a logic level is last held at the RDWR_B pin

The High pulse width at the CCLK input pin 5 –ns

The Low pulse width at the CCLK input pin 5 –ns

Frequency of the clock signal at the CCLK input pin No bitstream compression 0 80 MHz

With bitstream compression 0 80 MHz

T

Hold Times

T

Clock Timing

T

F

Notes:

1. The numbers in this table are based on the operating conditions set forth in Tab l e 7 .

2. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 55

All Speed Grades

Min Max

1 –ns

0 –ns

Units

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Serial Peripheral Interface (SPI) Configuration Timing

X-Ref Target - Figure 13

PROG_B

(Input)

PUDC_B

(Input)

VS[2:0]

(Input)

M[2:0]

(Input)

INIT_B

(Open-Drain)

CCLK

DIN

(Input)

CSO_B

MOSI

T

MINIT

PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.

<1:1:1>

Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point these pins become user-I/O pins.

<0:0:1>

T

INITM

New ConfigRate active

T

MCCL

T

CCLK1

T

MCCL1TMCCH1

T

CCLK1

n

T

V

Data Data Data Data

T

CSS

T

CCO

Command

(msb)

T

DSU

Command

(msb-1)

T

DH

T

DCC

T

CCLK

T

MCCH

CCD

n

Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.

Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.

Shaded values indicate specifications on attached SPI Flash PROM.

DS529-3_06_102506

Figure 13: Waveforms for Serial Peripheral Interface (SPI) Configuration

Tab le 5 2 : Timing for Serial Peripheral Interface (SPI) Configuration Mode

Symbol Description Minimum Maximum Units

T

CCLK1

T

CCLKn

T

MINIT

T

INITM

T

CCO

T

DCC

T

CCD

Initial CCLK clock period See Tab l e 4 6

CCLK clock period after FPGA loads ConfigRate setting See Ta bl e 4 6

Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the

50 –ns

rising edge of INIT_B

Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the

0 –ns

rising edge of INIT_B

MOSI output valid delay after CCLK falling edge See Ta bl e 5 0

Setup time on DIN data input before CCLK rising edge See Ta b le 5 0

Hold time on DIN data input after CCLK rising edge See Tab l e 5 0

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 56

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

T

CCS

T

MCCL1TCCO

–≤

T

DSU

T

MCCL1TCCO

–≤

T

DHTMCCH1

≤

T

V

T

MCCLnTDCC

–≤

f

C

1

T

CCLKn min()

-------------------------------- -

≥

Tab le 5 3 : Configuration Timing Requirements for Attached SPI Serial Flash

Symbol Description Requirement Units

T

CCS

SPI serial Flash PROM chip-select time ns

T

f

DSU

DH

V

C

or f

R

SPI serial Flash PROM data input setup time ns

SPI serial Flash PROM data input hold time ns

SPI serial Flash PROM data clock-to-output time ns

Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used)

Notes:

1. These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.

2. Subtract additional printed circuit board routing delay as required by the application.

MHz

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 57

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

(Input)

PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.

Data DataData

AddressAddress

Data

Address

Byte 0

000_0000

INIT_B

<0:1:0>

M[2:0]

T

MINIT

T

INITM

LDC[2:0]

HDC

CSO_B

Byte 1

000_0001

CCLK

A[25:0]

D[7:0]

T

DCC

T

CCD

T

AVQV

T

CCLK1

(Input)

T

INITADDR

T

CCLKn

T

CCLK1

T

CCO

PUDC_B

New ConfigRate active

Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.

Pin initially high-impedance (Hi-Z) if PUDC_B input is High.

Mode input pins M[2:0] are sampled when INIT_B goes High. After this point, input values do not matter until DONE goes High, at which point the mode pins become user-I/O pins.

(Input)

PROG_B

(Input)

DS529-3_05_090610

(Open-Drain)

Shaded values indicate specifications on attached parallel NOR Flash PROM.

Byte Peripheral Interface (BPI) Configuration Timing

X-Ref Target - Figure 14

Tab le 5 4 : Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 58

Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration

Symbol Description Minimum Maximum Units

T

CCLK1

T

CCLKn

T

MINIT

T

INITM

T

INITADDR

T

CCO

T

DCC

T

CCD

Initial CCLK clock period See Ta bl e 4 6

CCLK clock period after FPGA loads ConfigRate setting See Ta bl e 4 6

Setup time on M[2:0] mode pins before the rising edge of INIT_B 50 –ns

Hold time on M[2:0] mode pins after the rising edge of INIT_B 0 –ns

Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted and valid

Address A[25:0] outputs valid after CCLK falling edge See Ta b le 5 0

Setup time on D[7:0] data inputs before CCLK rising edge See T

Hold time on D[7:0] data inputs after CCLK rising edge 0 –ns

55T

SMDCC

in Ta bl e 5 1

cycles

CCLK1

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

T

CETINITADDR

≤

T

OE

T

INITADDR

≤

T

ACC

50%T

CCLKn min()TCCOTDCC

PCB–––≤

BYTE

T

INITADDR

≤

Tab le 5 5 : Configuration Timing Requirements for Attached Parallel NOR BPI Flash

Symbol Description Requirement Units

T

CE

(t

)

ELQV

T

OE

(t

)

GLQV

T

ACC

(t

)

AVQ V

T

BYTE

(t

FLQV, tFHQV

Notes:

1. These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.

2. Subtract additional printed circuit board routing delay as required by the application.

3. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s PUDC_B pin is High or Low.

Parallel NOR Flash PROM chip-select time ns

Parallel NOR Flash PROM output-enable time ns

Parallel NOR Flash PROM read access time ns

For x8/x16 PROMs only: BYTE# to output valid time

(3)

)

ns

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 59

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

IEEE 1149.1/1532 JTAG Test Access Port Timing

X-Ref Target - Figure 15

TCK

(Input)

T

TMSTCK

TMS

(Input)

T

TCKTMS

T

CCH

1/F

TCK

T

CCL

T

TDITCK

TDI

(Input)

TDO

(Output)

Figure 15: JTAG Waveforms

(2)

Tab le 5 6 : Timing for the JTAG

Symbol Description

Clock-to-Output Times

T

TCKTDO

Setup Times

T

TDITCK

T

TMSTCK

Hold Times

T

TCKTDI

T

TCKTMS

Clock Timing

T

CCH

T

CCL

T

CCHDNA

T

CCLDNA

F

TCK

The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns

The time from the setup of data at the TDI pin to the rising transition at the TCK pin

The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 –ns

The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin

The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin

The High pulse width at the TCK pin All functions except ISC_DNA command 5 –ns

The Low pulse width at the TCK pin 5 –ns

The High pulse width at the TCK pin During ISC_DNA command 10 10,000 ns

The Low pulse width at the TCK pin 10 10,000 ns

Frequency of the TCK signal BYPASS or HIGHZ instructions 0 33 MHz

Test Access Port

All functions except those shown below 7.0

Boundary scan commands (INTEST, EXTEST, SAMPLE)

All functions except those shown below 0 –ns

Configuration commands (CFG_IN, ISC_PROGRAM) 3.5

All operations except for BYPASS or HIGHZ instructions 20

T

TCKTDI

T

TCKTDO

DS099_06_090610

All Speed

Grades

Units

Min Max

–ns

13.0

0 –ns

Notes:

1. The numbers in this table are based on the operating conditions set forth in Ta bl e 7 .

2. For details on JTAG, see Chapter 9, “JTAG Configuraton Mode and Boundary-Scan” in UG332 Guide.

: Spartan-3 Generation Configuration User

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 60

Spartan-3A DSP FPGA Family: DC and Switching Characteristics

Revision History

The following table shows the revision history for this document.

Date Version Revision

04/02/07 1.0 Initial Xilinx release.

05/25/07 1.0.1 Minor edits.

06/18/07 1.2 Updated for v1.29 production speed files. Noted banking rules in Ta b le 1 1 and Ta b le 1 2. Added

07/16/07 2.0 Added Low-power options and updated typical values for quiescent current in Ta bl e 9 . Updated DSP48A

06/02/08 2.1 Improved V

03/11/09 2.2 Changed typical quiescent current temperature from ambient to quiescent. Updated selected I/O standard

10/04/10 3.0 Added I

DIFF_HSTL_I and DIFF_HSTL_III to Ta bl e 1 2 , Ta bl e 1 3 , and Ta bl e 2 6. Updated TMDS DC characteristics in Ta bl e 1 3 . Updated I/O Test Method values in Ta bl e 2 6 . Added Simultaneously Switching Output limits in

Ta bl e 2 8 . Updated DSP48A timing symbols, descriptions, and values in Tab le 3 4 . Added power-on timing in Ta bl e 4 5 . Added CCLK specifications for Commercial in Ta bl e 4 6 through Ta bl e 4 8. Updated Slave Parallel

timing in Ta bl e 5 1 . Updated JTAG specifications in Ta bl e 5 6.

timing in Ta bl e 3 4 and Ta bl e 3 5 .

and V

and I

min to V

CCAUXT

CCAUXQ

CCO

quiescent current values by 20%-44% in Tab le 9 . Increased VIL max to 0.4V for

–0.4V for LVCMOS15/18 in Ta b le 1 1 . Added reference to V

V

to Recommended Operating Conditions in Ta b l e 7 and added reference to XAPP459, “Eliminating I/O

IN

Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins.” Reduced typical I

CCINTQ

LVCMOS12/15/18 and improved V V

OH

Switching Output Guidelines. Removed DNA_RETENTION limit of 10 years in Ta bl e 1 4 since number of

POR minimum in Tab l e 4 and updated V

CCO2T

min to 0.7V for LVCMOS12 in Ta b l e 1 0 . Changed VOL max to 0.4V and

IH

POR levels in Figure 10. Added

CCO

in Simultaneously

CCAUX

Read cycles is the only unique limit. Updated speed files to v1.31 in Ta b le 1 6 and elsewhere. Updated IOB Setup and Hold times with device-specific values in Ta bl e 1 9 . Added reference to Sample Window in

Ta bl e 2 0 . Updated IOB Propagation times with device-specific values in Ta bl e 2 1. Improved SSTL_18_II

SSO value in Tab le 2 8. Improved F performance via SCD 4103 in Ta b le 3 2 ,Tab l e 3 7, Ta b le 3 8 , and Tab l e 3 9 . Added explanatory footnotes to

DSP48A Timing tables. Simplified DSP48A F

FBUFG in Ta bl e 3 2 for -4 speed grade. Updated CCLK output maximum period in Ta b le 4 6 to match

for -4 to 334 MHz in Tab l e 3 2 . Added references to 375 MHz

BUFG

to value with all registers used in Ta bl e 3 5 . Improved

MAX

minimum frequency in Ta bl e 4 7 . Replaced BPI with SPI specification descriptions in Ta b l e 5 2 . Corrected BPI

Figure 14 and Ta bl e 54 from falling edge to rising edge. Added references to Spartan-3 Generation User

Guides. Updated links.

DC characteristics. Removed PCIX IOSTANDARD due to limited PCIX interface support. Added T T

to Ta bl e 2 1 . Updated BPI configuration waveforms in Figure 14 and updated Ta b le 5 5. Removed

IOPID

references to SCD 4103.

to Ta bl e 3 . Updated description for VIN in Ta b le 7 including adding note 4. Also, added note 2 to IL in Ta bl e 8 to note potential leakage between pins of a differential pair. Added note 6 to Ta bl e 1 0. Updated notes 5 and 6 in Ta b le 1 2 . Corrected symbols for T

IK

SUSPEND_GTS

and T

SUSPEND_GWE

in Ta bl e 4 4.

IOPI

and

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 61

101

Spartan-3A DSP FPGA Family:

Pinout Descriptions

DS610 (v3.0) October 4, 2010 Product Specification

Introduction

This section describes how the various pins on a Spartan®-3A DSP FPGA connect within the supported component packages and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see the Packaging section in UG331

Spartan-3A DSP FPGAs are available in both standard and Pb-free, RoHS versions of each package, with the Pb-free version adding a “G” to the middle of the package code. Except for the thermal characteristics, all information for the standard package applies equally to the Pb-free package.

Pin Types

Most pins on a Spartan-3A DSP FPGA are general-purpose, user-defined I/O pins. There are, however, up to 12 different functional types of pins on Spartan-3A DSP packages, as outlined in Tab l e 5 7 . In the package footprint drawings that follow, the individual pins are color-coded according to pin type as in the table.

Tab le 5 7 : Types of Pins on Spartan-3A DSP FPGAs

Type/Color

Code

I/O

INPUT

DUAL

VREF

CLK

CONFIG

Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os.

Unrestricted, general-purpose input-only pin. This pin does not have an output structure, differential termination resistor, or PCI clamp diode.

Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. See UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals.

Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other VREF pins in the same bank, provides a reference voltage input for certain I/O standards. If used for a reference voltage within a bank, all VREF pins within the bank must be connected.

Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global clock inputs that optionally clock the entire device. The RHCLK inputs optionally clock the right half of the device. The LHCLK inputs optionally clock the left half of the device. See the Using Global Clock Resources chapter in UG331 additional information on these signals.

Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See the UG332 Spartan-3 Generation Configuration User Guide for additional information on the DONE and PROG_B signals.

: Spartan-3 Generation FPGA User Guide.

Description Pin Name(s) in Type

IO_# IO_Lxxy_#

IP_# IP_Lxxy_#

M[2:0] PUDC_B CCLK MOSI/CSI_B D[7:1] D0/DIN CSO_B RDWR_B INIT_B A[25:0] VS[2:0] LDC[2:0] HDC

IP/VREF_# IP_Lxxy_#/VREF_# IO/VREF_# IO_Lxxy_#/VREF_#

IO_Lxxy_#/GCLK[15:0], IO_Lxxy_#/LHCLK[7:0], IO_Lxxy_#/RHCLK[7:0]

: Spartan-3 Generation FPGA User Guide for

DONE, PROG_B

:

© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 62

Tab le 5 7 : Types of Pins on Spartan-3A DSP FPGAs (Cont’d)

Type/Color

Code

PWR

MGMT

JTAG

GND

VCCAUX

VCCINT

VCCO

N.C.

Notes:

1. # = I/O bank number, an integer between 0 and 3.

Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and is powered by VCCAUX. AWAKE is a dual-purpose pin. Unless Suspend mode is enabled in the application, AWAKE is available as a user-I/O pin.

Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX.

Dedicated ground pin. The number of GND pins depends on the package used. All must be connected.

Dedicated auxiliary power supply pin. The number of VCCAUX pins depends on the package used. All must be connected. Set on board and using CONFIG VCCAUX constraint.

Dedicated internal core logic power supply pin. The number of VCCINT pins depends on the package used. All must be connected to +1.2V.

Along with all the other VCCO pins in the same bank, this pin supplies power to the output buffers within the I/O bank and sets the input threshold voltage for some I/O standards. All must be connected.

This package pin is not connected in this specific device/package combination but may be connected in larger devices in the same package.

Description Pin Name(s) in Type

Spartan-3A DSP FPGA Family: Pinout Descriptions

SUSPEND, AWAKE

TDI, TMS, TCK, TDO

GND

VCCAUX

VCCINT

VCCO_#

N.C.

Package Pins by Type

Each package has three separate voltage supply inputs—VCCINT, VCCAUX, and VCCO—and a common ground return, GND. The numbers of pins dedicated to these functions vary by package, as shown in Ta b le 5 8 .

Tab le 5 8 : Power and Ground Supply Pins by Package

Package Device VCCINT VCCAUX VCCO GND

CS484

FG676

XC3SD1800A

XC3SD3400A 36 24 24 84

XC3SD1800A

XC3SD3400A

A majority of package pins are user-defined I/O or input pins. However, the numbers and characteristics of these I/O depend on the device type and the package in which it is available, as shown in Ta b le 59 . The table shows the maximum number of single-ended I/O pins available,

Tab le 5 9 : Maximum User I/O by Package

Package Device

CS484

FG676

XC3SD1800A 309 60 140 156 41 52 28 32

XC3SD3400A 309 60 140 156 41 52 28 32 0

XC3SD1800A 519 110 227 314 82 52 39 32

XC3SD3400A 469 60 213 314 34 52 37 32

36 24 24 84

23 14 36 77

36 24 40 100

Maximum

User I/Os and

Input-Only

Maximum

Input-Only

Differential

assuming that all I/O-, INPUT-, DUAL-, VREF-, and

CLK-type pins are used as general-purpose I/O. AWAKE is

counted here as a dual-purpose I/O pin. Likewise, the table shows the maximum number of differential pin-pairs available on the package. Finally, the table shows how the total maximum user-I/Os are distributed by pin type, including the number of unconnected—N.C.—pins on the device.

Not all I/O standards are supported on all I/O banks. The left and right banks (I/O banks 1 and 3) support higher output drive current than the top and bottom banks (I/O banks 0 and 2). Similarly, true differential output standards, such as LVDS, RSDS, PPDS, miniLVDS, and TMDS, are only supported in the top or bottom banks (I/O banks 0 and 2). Inputs are unrestricted. For more details, see the Using I/O Resources chapter in UG331

Maximum

Pairs

I/O INPUT DUAL VREF

All Possible I/Os by Type

.

(1)

CLK N.C.

0

Notes:

1. Some VREFs are on INPUT pins. See pinout tables for details.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 63

Spartan-3A DSP FPGA Family: Pinout Descriptions

Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx® website. Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily parsed by most scripting programs. www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip

Package Overview

Ta bl e 6 0 shows the two low-cost, space-saving production package styles for the Spartan-3A DSP family.

Tab le 6 0 : Spartan-3A DSP Family Package Options

Package Leads Type

CS484 / CSG484 484 Chip-Scale Ball Grid Array (CS) 309 0.8 19 x 19 1.80 1.4

FG676 / FGG676 676 Fine-pitch Ball Grid Array (FBGA) 519 1.0 27 x 27 2.60 3.4

Notes:

1. Package mass is ±10%.

Maximum

I/O

Lead Pitch

(mm)

Footprint

Area (mm)

Height

(mm)

Each package style is available as a standard and an environmentally friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the package style name. For example, the standard “CS484” package becomes “CSG484” when ordered as the Pb-free option. The mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical drawings provided in Ta bl e 6 1.

Mass

(g)

(1)

For additional package information, see UG112

: Device Package User Guide.

Mechanical Drawings

Detailed mechanical drawings for each package type are available from the Xilinx web site at the specified location in

Ta bl e 6 1.

Material Declaration Data Sheets (MDDS) are also available on the Xilinx web site

Tab le 6 1 : Xilinx Package Documentation

Package Drawing MDDS

CS484 Package Drawing PK230_CS484

CSG484 PK231_CSG484

FG676 Package Drawing PK155_FG676

FGG676 PK111_FGG676

for each package.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 64

Spartan-3A DSP FPGA Family: Pinout Descriptions

Package Thermal Characteristics

The power dissipated by an FPGA application has implications on package selection and system design. The power consumed by a Spartan-3A DSP FPGA is reported using either the XPower Power Estimator calculator integrated in the Xilinx ISE®

development software. Tab le 6 2 provides the thermal characteristics for the various

Spartan-3A DSP device package offerings. This information is also available using the Thermal Query tool

or the XPower Analyzer

.

The junction-to-case thermal resistance (θ body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ reports the difference between the board and junction temperature. The junction-to-ambient (θ temperature difference between the ambient environment and the junction temperature. The θ

) indicates the difference between the temperature measured on the package

JC

) value reports the

JA

value is reported at

JA

) value similarly

JB

different air velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θ system without a fan. The thermal resistance drops with increasing air flow.

Tab le 6 2 : Spartan-3A DSP FPGA Package Thermal Characteristics

JA

)

Package Device

CS484

CSG484

FG676

FGG676

XC3SD1800A 4.1 6.8 18.0 13.3 12.3 11.5 °C/W

XC3SD3400A 3.5 5.6 16.9 12.2 11.0 10.4 °C/W

XC3SD1800A 4.7 7.8 15.9 11.6 10.6 10.0 °C/W

XC3SD3400A 3.8 6.4 14.7 10.5 9.4 8.9 °C/W

Junction-to-Case

(θ

)

JC

Junction-to-

Board (θJB)

Still Air (0 LFM)

Junction-to-Ambient (θ

at Different Air Flows

250 LFM 500 LFM 750 LFM

value in a

JA

Units

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 65

CS484: 484-Ball Chip-Scale Ball Grid Array

Spartan-3A DSP FPGA Family: Pinout Descriptions

The 484-ball chip-scale ball grid array, CS484, supports both the XC3SD1800A and XC3SD3400A FPGAs. There are no pinout differences between the two devices.

Ta bl e 6 3 lists all the CS484 package pins. They are sorted

by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at

www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip

Pinout Table

Tab le 6 3 : Spartan-3A DSP CS484 Pinout

Bank Pin Name

0 IO_L30N_0 A3 I/O

0 IO_L28N_0 A4 I/O

0 IO_L25N_0 A5 I/O

0 IO_L25P_0 A6 I/O

0 IO_L24N_0/VREF_0 A7 VREF

0 IO_L20P_0/GCLK10 A8 GCLK

0 IO_L18P_0/GCLK6 A9 GCLK

0 IP_0 A10 INPUT

0 IO_L15N_0 A11 I/O

0 IP_0 A12 INPUT

0 IO_L11P_0 A13 I/O

0 IO_L10P_0 A14 I/O

0 IP_0 A15 INPUT

0 IO_L06P_0/VREF_0 A16 VREF

0 IO_L06N_0 A17 I/O

0 IP_0 A18 INPUT

0 IO_L07N_0 A19 I/O

0 IO_0 A20 I/O

0 IO_L30P_0 B3 I/O

0 IO_L28P_0 B4 I/O

0 IO_L24P_0 B6 I/O

0 IO_L20N_0/GCLK11 B8 GCLK

0 IO_L18N_0/GCLK7 B9 GCLK

0 IO_L15P_0 B11 I/O

0 IO_L11N_0 B13 I/O

0 IO_L10N_0 B15 I/O

0 IO_L03P_0 B17 I/O

0 IO_L02N_0 B19 I/O

CS484

Ball

Typ e

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

0 IO_L07P_0 B20 I/O

0 IO_L29N_0 C4 I/O

0 IP_0 C5 INPUT

0 IO_L21P_0 C6 I/O

0 IO_L26P_0 C7 I/O

0 IO_L22P_0 C8 I/O

0 IO_L16P_0 C9 I/O

0 IP_0 C10 INPUT

0 IP_0/VREF_0 C11 VREF

0 IO_L14N_0 C12 I/O

0 IO_L14P_0 C13 I/O

0 IP_0 C14 INPUT

0 IO_L12N_0/VREF_0 C15 VREF

0 IO_L08N_0 C16 I/O

0 IO_L03N_0 C17 I/O

0 IO_L02P_0/VREF_0 C18 VREF

0 IO_L01N_0 C19 I/O

0 IO_L29P_0 D5 I/O

0 IO_L21N_0 D6 I/O

0 IO_L26N_0 D7 I/O

0 IO_L22N_0 D9 I/O

0 IO_L16N_0 D10 I/O

0 IO_L09N_0 D13 I/O

0 IO_L12P_0 D14 I/O

0 IO_L08P_0 D15 I/O

0 IP_0 D17 INPUT

0 IP_0 D18 INPUT

0 IO_L01P_0 D19 I/O

0 IP_0 E6 INPUT

0 IO_L31P_0/VREF_0 E7 VREF

0 IO_L27N_0 E8 I/O

0 IP_0 E10 INPUT

0 IO_L19N_0/GCLK9 E11 GCLK

0 IO_L17P_0/GCLK4 E12 GCLK

0 IO_L09P_0 E13 I/O

0 IO_L05P_0 E15 I/O

0 IO_L04P_0 E16 I/O

0 IP_0 E17 INPUT

0 IO_L31N_0/PUDC_B F7 DUAL

0 IO_L27P_0 F8 I/O

0 IO_L23N_0 F9 I/O

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 66

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 3 : Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

0 IO_L19P_0/GCLK8 F10 GCLK

0 IO_L17N_0/GCLK5 F11 GCLK

0 IP_0 F12 INPUT

0 IO_L13N_0 F13 I/O

0 IO_L13P_0 F14 I/O

0 IO_L05N_0 F15 I/O

0 IO_L04N_0 F16 I/O

0 IO_L23P_0 G8 I/O

0 VCCO_0 B5 VCCO

0 VCCO_0 B10 VCCO

0 VCCO_0 B14 VCCO

0 VCCO_0 B18 VCCO

0 VCCO_0 E9 VCCO

0 VCCO_0 E14 VCCO

1 IO_L02N_1/LDC0 AA22 DUAL

1 IP_L39N_1 C21 INPUT

1 IP_L39P_1/VREF_1 C22 VREF

1 IO_L36P_1/A20 D20 DUAL

1 IO_L37P_1/A22 D21 DUAL

1 IO_L37N_1/A23 D22 DUAL

1 IO_L36N_1/A21 E19 DUAL

1 IO_L35N_1 E20 I/O

1 IO_L33N_1 E22 I/O

1 IO_L38N_1/A25 F18 DUAL

1 IO_L38P_1/A24 F19 DUAL

1 IO_L30N_1/A19 F20 DUAL

1 IO_L35P_1 F21 I/O

1 IO_L33P_1 F22 I/O

1 IO_L34P_1 G17 I/O

1 IO_L34N_1 G18 I/O

1 IO_L30P_1/A18 G19 DUAL

1 IP_L31N_1 G20 INPUT

1 IO_L28N_1 G22 I/O

1 IO_L26P_1/A14 H17 DUAL

1 IO_L26N_1/A15 H18 DUAL

1 IO_L32N_1 H20 I/O

1 IP_L31P_1/VREF_1 H21 VREF

1 IO_L28P_1 H22 I/O

1 IO_L29N_1/A17 J17 DUAL

1 IO_L32P_1 J19 I/O

1 IO_L25N_1/A13 J20 DUAL

1 IP_L27P_1 J21 INPUT

CS484

Ball

Typ e

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

1 IP_L27N_1 J22 INPUT

1 IO_L29P_1/A16 K16 DUAL

1 IP_L23N_1 K17 INPUT

1 IO_L24N_1 K18 I/O

1 IO_L24P_1 K19 I/O

1 IO_L25P_1/A12 K20 DUAL

1 IO_L22N_1/A11 K22 DUAL

1 IO_L21N_1/RHCLK7 L17 RHCLK

1 IP_L23P_1/VREF_1 L18 VREF

1 IO_L20N_1/RHCLK5 L20 RHCLK

1 IO_L20P_1/RHCLK4 L21 RHCLK

1 IO_L22P_1/A10 L22 DUAL

1 IO_L18N_1/RHCLK1 M17 RHCLK

1 IO_L21P_1/IRDY1/RHCLK6 M18 RHCLK

1 IO_L19N_1/TRDY1/RHCLK3 M20 RHCLK

1 IO_L17N_1/A9 M22 DUAL

1 IO_L13P_1/A2 N17 DUAL

1 IO_L18P_1/RHCLK0 N18 RHCLK

1 IO_L15N_1/A7 N19 DUAL

1 IO_L15P_1/A6 N20 DUAL

1 IO_L19P_1/RHCLK2 N21 RHCLK

1 IO_L17P_1/A8 N22 DUAL

1 IO_L13N_1/A3 P16 DUAL

1 IP_L12N_1/VREF_1 P17 VREF

1 IO_L10P_1 P19 I/O

1 IP_L16N_1 P20 INPUT

1 IO_L14N_1/A5 P22 DUAL

1 IP_L12P_1 R17 INPUT

1 IO_L10N_1 R18 I/O

1 IO_L07P_1 R19 I/O

1 IO_L07N_1 R20 I/O

1 IP_L16P_1/VREF_1 R21 VREF

1 IO_L14P_1/A4 R22 DUAL

1 IO_L05N_1 T17 I/O

1 IO_L05P_1 T18 I/O

1 IO_L09N_1 T20 I/O

1 IO_L11N_1/VREF_1 T22 VREF

1 IO_L01P_1/HDC U18 DUAL

1 IO_L01N_1/LDC2 U19 DUAL

1 IO_L09P_1 U20 I/O

1 IP_L08N_1/VREF_1 U21 VREF

1 IO_L11P_1 U22 I/O

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 67

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 3 : Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

1 IO_L03N_1/A1 V20 DUAL

1 IP_L08P_1 V22 INPUT

1 IO_L03P_1/A0 W19 DUAL

1 IP_L04N_1/VREF_1 W20 VREF

1 IP_L04P_1 W21 INPUT

1 IO_L06P_1 W22 I/O

1 IO_L02P_1/LDC1 Y21 DUAL

1 IO_L06N_1 Y22 I/O

1 VCCO_1 E21 VCCO

1 VCCO_1 J18 VCCO

1 VCCO_1 K21 VCCO

1 VCCO_1 P18 VCCO

1 VCCO_1 P21 VCCO

1 VCCO_1 V21 VCCO

2 IO_L01P_2/M1 AA3 DUAL

2 IO_L04N_2 AA4 I/O

2 IP_2 AA6 INPUT

2 IO_L08N_2 AA8 I/O

2 IO_L12N_2/D6 AA10 DUAL

2 IO_L16P_2/GCLK14 AA12 GCLK

2 IO_L18N_2/GCLK3 AA14 GCLK

2 IO_L19P_2 AA15 I/O

2 IO_L22P_2/AWAKE AA17

2 IO_L27N_2 AA19 I/O

2 IO_L30P_2 AA20 I/O

2 IP_2/VREF_2 AB2 VREF

2 IO_L01N_2/M0 AB3 DUAL

2 IO_L04P_2 AB4 I/O

2 IO_L05P_2 AB5 I/O

2 IO_L05N_2 AB6 I/O

2 IO_L08P_2 AB7 I/O

2 IO_L09P_2/VS1 AB8 DUAL

2 IO_L09N_2/VS0 AB9 DUAL

2 IO_L12P_2/D7 AB10 DUAL

2 IP_2/VREF_2 AB11 VREF

2 IO_L16N_2/GCLK15 AB12 GCLK

2 IO_L18P_2/GCLK2 AB13 GCLK

2 IO_L19N_2 AB14 I/O

2 IP_2 AB15 INPUT

2 IO_L22N_2/DOUT AB16 DUAL

2 IO_L23P_2 AB17 I/O

2 IO_L23N_2 AB18 I/O

CS484

Ball

Typ e

PWRMGMT

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

2 IO_L27P_2 AB19 I/O

2 IO_L30N_2 AB20 I/O

2 IO_L02N_2/CSO_B U7 DUAL

2 IO_L11N_2 U8 I/O

2 IO_L10N_2 U9 I/O

2 IO_L14N_2/D4 U10 DUAL

2 IO_L17P_2/GCLK0 U12 GCLK

2 IO_L20P_2 U13 I/O

2 IO_L25P_2 U14 I/O

2 IO_L25N_2 U15 I/O

2 IO_L28P_2 U16 I/O

2 IO_L02P_2/M2 V6 DUAL

2 IO_L11P_2 V7 I/O

2 IO_L06N_2 V8 I/O

2 IO_L10P_2 V10 I/O

2 IO_L14P_2/D5 V11 DUAL

2 IO_L17N_2/GCLK1 V12 GCLK

2 IO_L20N_2/MOSI/CSI_B V13 DUAL

2 IP_2/VREF_2 V15 VREF

2 IO_L28N_2 V16 I/O

2 IO_L31N_2/CCLK V17 DUAL

2 IP_2/VREF_2 W4 VREF

2 IO_L03P_2 W5 I/O

2 IO_L07N_2/VS2 W6 DUAL

2 IO_L06P_2 W8 I/O

2 IP_2/VREF_2 W9 VREF

2 IP_2 W10 INPUT

2 IP_2/VREF_2 W13 VREF

2 IO_L21N_2 W14 I/O

2 IO_L24P_2/INIT_B W15 DUAL

2 IO_L31P_2/D0/DIN/MISO W17 DUAL

2 IP_2/VREF_2 W18 VREF

2 IO_L03N_2 Y4 I/O

2 IO_L07P_2/RDWR_B Y5 DUAL

2 IP_2 Y6 INPUT

2 IP_2 Y7 INPUT

2 IO_L13P_2 Y8 I/O

2 IO_L13N_2 Y9 I/O

2 IO_L15N_2/GCLK13 Y10 GCLK

2 IO_L15P_2/GCLK12 Y11 GCLK

2 IP_2 Y12 INPUT

2 IO_L21P_2 Y13 I/O

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 68

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 3 : Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

2 IP_2/VREF_2 Y14 VREF

2 IO_L24N_2/D3 Y15 DUAL

2 IO_L29N_2 Y16 I/O

2 IO_L29P_2 Y17 I/O

2 IO_L26P_2/D2 Y18 DUAL

2 IO_L26N_2/D1 Y19 DUAL

2 VCCO_2 AA5 VCCO

2 VCCO_2 AA9 VCCO

2 VCCO_2 AA13 VCCO

2 VCCO_2 AA18 VCCO

2 VCCO_2 V9 VCCO

2 VCCO_2 V14 VCCO

3 IP_L39N_3/VREF_3 AA1 VREF

3 IO_L02N_3 C1 I/O

3 IO_L02P_3 C2 I/O

3 IP_L04P_3 D1 INPUT

3 IP_L08P_3 D3 INPUT

3 IP_L08N_3 D4 INPUT

3 IP_L04N_3/VREF_3 E1 VREF

3 IO_L09P_3 E3 I/O

3 IO_L09N_3 E4 I/O

3 IO_L06N_3 F1 I/O

3 IO_L06P_3 F2 I/O

3 IO_L01P_3 F3 I/O

3 IO_L03P_3 F4 I/O

3 IO_L03N_3 F5 I/O

3 IO_L11P_3 G1 I/O

3 IO_L01N_3 G3 I/O

3 IO_L07P_3 G5 I/O

3 IO_L07N_3 G6 I/O

3 IO_L11N_3 H1 I/O

3 IO_L14P_3 H2 I/O

3 IO_L05P_3 H3 I/O

3 IO_L05N_3 H4 I/O

3 IO_L10P_3 H5 I/O

3 IO_L10N_3 H6 I/O

3 IO_L14N_3/VREF_3 J1 VREF

3 IP_L16P_3 J3 INPUT

3 IP_L16N_3 J4 INPUT

3 IP_L12P_3 J6 INPUT

3 IP_L12N_3/VREF_3 J7 VREF

3 IO_L19P_3/LHCLK2 K1 LHCLK

CS484

Ball

Typ e

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

3 IO_L17P_3 K2 I/O

3 IO_L17N_3 K3 I/O

3 IO_L13P_3 K4 I/O

3 IO_L13N_3 K5 I/O

3 IO_L15P_3 K6 I/O

3 IO_L19N_3/IRDY2/LHCLK3 L1 LHCLK

3 IO_L20P_3/LHCLK4 L3 LHCLK

3 IO_L15N_3 L5 I/O

3 IO_L18P_3/LHCLK0 L6 LHCLK

3 IO_L22P_3/VREF_3 M1 VREF

3 IO_L20N_3/LHCLK5 M2 LHCLK

3 IP_L23P_3 M3 INPUT

3 IO_L18N_3/LHCLK1 M5 LHCLK

3 IO_L21P_3/TRDY2/LHCLK6 M6 LHCLK

3 IO_L22N_3 N1 I/O

3 IP_L31P_3 N3 INPUT

3 IP_L23N_3 N4 INPUT

3 IO_L24N_3 N5 I/O

3 IO_L24P_3 N6 I/O

3 IO_L21N_3/LHCLK7 N7 LHCLK

3 IO_L25P_3 P1 I/O

3 IO_L25N_3 P2 I/O

3 IP_L31N_3 P3 INPUT

3 IO_L32P_3/VREF_3 P4 VREF

3 IO_L26P_3 P6 I/O

3 IO_L28N_3 R1 I/O

3 IO_L28P_3 R2 I/O

3 IO_L34P_3 R3 I/O

3 IO_L32N_3 R5 I/O

3 IO_L26N_3 R6 I/O

3 IO_L30P_3 T1 I/O

3 IP_L27P_3 T3 INPUT

3 IO_L34N_3 T4 I/O

3 IO_L29N_3 T5 I/O

3 IO_L29P_3 T6 I/O

3 IO_L30N_3 U1 I/O

3 IO_L33P_3 U2 I/O

3 IP_L27N_3 U3 INPUT

3 IO_L38P_3 U4 I/O

3 IO_L38N_3 U5 I/O

3 IO_L33N_3 V1 I/O

3 IO_L36N_3 V3 I/O

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 69

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 3 : Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

3 IO_L36P_3 V4 I/O

3 IO_L35N_3 W1 I/O

3 IO_L37N_3 W2 I/O

3 IO_L37P_3 W3 I/O

3 IO_L35P_3 Y1 I/O

3 IP_L39P_3 Y2 INPUT

3 VCCO_3 E2 VCCO

3 VCCO_3 J2 VCCO

3 VCCO_3 J5 VCCO

3 VCCO_3 N2 VCCO

3 VCCO_3 P5 VCCO

3 VCCO_3 V2 VCCO

GND GND A1 GND

GND GND A22 GND

GND GND AA7 GND

GND GND AA11 GND

GND GND AA16 GND

GND GND AB1 GND

GND GND AB22 GND

GND GND B7 GND

GND GND B12 GND

GND GND B16 GND

GND GND C3 GND

GND GND C20 GND

GND GND D8 GND

GND GND D11 GND

GND GND D16 GND

GND GND F6 GND

GND GND F17 GND

GND GND G2 GND

GND GND G4 GND

GND GND G9 GND

GND GND G11 GND

GND GND G13 GND

GND GND G15 GND

GND GND G21 GND

GND GND H7 GND

GND GND H8 GND

GND GND H10 GND

GND GND H12 GND

GND GND H14 GND

GND GND H16 GND

CS484

Ball

Typ e

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

GND GND H19 GND

GND GND J9 GND

GND GND J11 GND

GND GND J13 GND

GND GND J15 GND

GND GND K8 GND

GND GND K10 GND

GND GND K12 GND

GND GND K14 GND

GND GND L2 GND

GND GND L7 GND

GND GND L9 GND

GND GND L11 GND

GND GND L13 GND

GND GND L15 GND

GND GND L19 GND

GND GND M4 GND

GND GND M8 GND

GND GND M10 GND

GND GND M12 GND

GND GND M14 GND

GND GND M16 GND

GND GND M21 GND

GND GND N9 GND

GND GND N11 GND

GND GND N13 GND

GND GND N15 GND

GND GND P8 GND

GND GND P10 GND

GND GND P12 GND

GND GND P14 GND

GND GND R4 GND

GND GND R7 GND

GND GND R9 GND

GND GND R11 GND

GND GND R13 GND

GND GND R15 GND

GND GND R16 GND

GND GND T2 GND

GND GND T8 GND

GND GND T10 GND

GND GND T12 GND

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 70

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 3 : Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

GND GND T14 GND

GND GND T15 GND

GND GND T19 GND

GND GND T21 GND

GND GND U6 GND

GND GND U11 GND

GND GND U17 GND

GND GND W7 GND

GND GND W12 GND

GND GND W16 GND

GND GND Y3 GND

GND GND Y20 GND

VCCAUX SUSPEND V19 PWRMGMT

VCCAUX PROG_B A2 CONFIG

VCCAUX DONE AB21 CONFIG

VCCAUX TCK A21 JTAG

VCCAUX TMS B1 JTAG

VCCAUX TDO B22 JTAG

VCCAUX TDI D2 JTAG

VCCAUX VCCAUX AA2 VCCAUX

VCCAUX VCCAUX AA21 VCCAUX

VCCAUX VCCAUX B2 VCCAUX

VCCAUX VCCAUX B21 VCCAUX

VCCAUX VCCAUX D12 VCCAUX

VCCAUX VCCAUX E5 VCCAUX

VCCAUX VCCAUX E18 VCCAUX

VCCAUX VCCAUX G10 VCCAUX

VCCAUX VCCAUX G12 VCCAUX

VCCAUX VCCAUX G14 VCCAUX

VCCAUX VCCAUX J16 VCCAUX

VCCAUX VCCAUX K7 VCCAUX

VCCAUX VCCAUX L4 VCCAUX

VCCAUX VCCAUX L16 VCCAUX

VCCAUX VCCAUX M7 VCCAUX

VCCAUX VCCAUX M19 VCCAUX

VCCAUX VCCAUX N16 VCCAUX

VCCAUX VCCAUX P7 VCCAUX

VCCAUX VCCAUX T9 VCCAUX

VCCAUX VCCAUX T11 VCCAUX

VCCAUX VCCAUX T13 VCCAUX

VCCAUX VCCAUX V5 VCCAUX

VCCAUX VCCAUX V18 VCCAUX

CS484

Ball

Typ e

Tab l e 6 3: Spartan-3A DSP CS484 Pinout (Cont’d)

Bank Pin Name

VCCAUX VCCAUX W11 VCCAUX

VCCINT VCCINT G7 VCCINT

VCCINT VCCINT G16 VCCINT

VCCINT VCCINT H9 VCCINT

VCCINT VCCINT H11 VCCINT

VCCINT VCCINT H13 VCCINT

VCCINT VCCINT H15 VCCINT

VCCINT VCCINT J8 VCCINT

VCCINT VCCINT J10 VCCINT

VCCINT VCCINT J12 VCCINT

VCCINT VCCINT J14 VCCINT

VCCINT VCCINT K9 VCCINT

VCCINT VCCINT K11 VCCINT

VCCINT VCCINT K13 VCCINT

VCCINT VCCINT K15 VCCINT

VCCINT VCCINT L8 VCCINT

VCCINT VCCINT L10 VCCINT

VCCINT VCCINT L12 VCCINT

VCCINT VCCINT L14 VCCINT

VCCINT VCCINT M9 VCCINT

VCCINT VCCINT M11 VCCINT

VCCINT VCCINT M13 VCCINT

VCCINT VCCINT M15 VCCINT

VCCINT VCCINT N8 VCCINT

VCCINT VCCINT N10 VCCINT

VCCINT VCCINT N12 VCCINT

VCCINT VCCINT N14 VCCINT

VCCINT VCCINT P9 VCCINT

VCCINT VCCINT P11 VCCINT

VCCINT VCCINT P13 VCCINT

VCCINT VCCINT P15 VCCINT

VCCINT VCCINT R8 VCCINT

VCCINT VCCINT R10 VCCINT

VCCINT VCCINT R12 VCCINT

VCCINT VCCINT R14 VCCINT

VCCINT VCCINT T7 VCCINT

VCCINT VCCINT T16 VCCINT

CS484

Ball

Typ e

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 71

Spartan-3A DSP FPGA Family: Pinout Descriptions

User I/Os by Bank

Table 64 and Ta b l e 6 5 indicates how the user-I/O pins are distributed between the four I/O banks on the CS484 package.

The AWAKE pin is counted as a dual-purpose I/O.

Tab le 6 4 : User I/Os Per Bank for the XC3SD1800A in the CS484 Package

Package

Edge

To p 0 77 49 13 1 6 8

Right 1 78 23 9 30 8 8

Bottom 2 76 33 6 21 8 8

Left 3 78 51 13 0 6 8

TOTAL 309 156 41 52 28 32

Notes:

1. 19 VREF are on INPUT pins.

I/O Bank

Maximum I/Os

and

Input-Only

I/O INPUT DUAL VREF

Tab le 6 5 : User I/Os Per Bank for the XC3SD3400A in the CS484 Package

Package

Edge

To p 0 77 49 13 1 6 8

Right 1 78 23 9 30 8 8

Bottom 2 76 33 6 21 8 8

Left 3 78 51 13 0 6 8

TOTAL 309 156 41 52 28 32

I/O Bank

Maximum I/O

and

Input-Only

I/O INPUT DUAL VREF

All Possible I/O Pins by Type

(1)

CLK

Notes:

1. 19 VREF are on INPUT pins.

Footprint Migration Differences

There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 72

CS484 Footprint

1234567891011

A

GND

PROG_

B

L30N_0

L28N_0

L25N_0

L25P_0

VREF_0

GCLK10

GCLK6

INPUT

L15N_0

B

TMS

VCCAUX

L30P_0

L28P_0

VCCO_0

L24P_0

GND

GCLK11

GCLK7

VCCO_0

L15P_0

C

L02N_3

L02P_3

GND

L29N_0

INPUT

L21P_0

L26P_0

L22P_0

L16P_0

INPUT

VREF_0

D

L04P_3

TDI

L08P_3

L08N_3

L29P_0

L21N_0

L26N_0

GND

L22N_0

L16N_0

GND

E

VREF_3

VCCO_3

L09P_3

L09N_3

VCCAUX

INPUT

VREF_0

L27N_0

VCCO_0

INPUT

GCLK9

F

L06N_3

L06P_3

L01P_3

L03P_3

L03N_3

GND

PUDC_B

L27P_0

L23N_0

GCLK8

GCLK5

G

L11P_3

GND

L01N_3

GND

L07P_3

L07N_3

VCCINT

L23P_0

GND

VCCAUX

GND

H

L11N_3

L14P_3

L05P_3

L05N_3

L10P_3

L10N_3

GND GND VCCINT GND VCCINT

J

VREF_3

VCCO_3

L16P_3

L16N_3

VCCO_3

L12P_3

VREF_3

VCCINT GND VCCINT GND

K

LHCLK2

L17P_3

L17N_3

L13P_3

L13N_3

L15P_3

VCCAUX

GND VCCINT GND VCCINT

L

GND

LHCLK4

VCCAUX

L15N_3

LHCLK0

GND VCCINT GND VCCINT GND

M

VREF_3

LHCLK5

L23P_3

GND

LHCLK1

VCCAUX

GND VCCINT GND VCCINT

N

L22N_3

VCCO_3

L31P_3

L23N_3

L24N_3

L24P_3

LHCLK7

VCCINT GND VCCINT GND

P

L25P_3

L25N_3

L31N_3

VREF_3

VCCO_3

L26P_3

VCCAUX

GND VCCINT GND VCCINT

R

L28N_3

L28P_3

L34P_3

GND

L32N_3

L26N_3

GND VCCINT GND VCCINT GND

T

L30P_3

GND

L27P_3

L34N_3

L29N_3

L29P_3

VCCINT GND

VCCAUX

GND

VCCAUX

U

L30N_3

L33P_3

L27N_3

L38P_3

L38N_3

GND

CSO_B

L11N_2

D4

GND

V

L33N_3

VCCO_3

L36N_3

L36P_3

VCCAUX

M2

L11P_2

L06N_2

VCCO_2

D5

Bank 3

Bank 0

W

L35N_3

L37N_3

L37P_3

VREF_2

L03P_2

VS2

GND

L06P_2

VREF_2

INPUT

VCCAUX

Y

L35P_3

L39P_3

GND

L03N_2

RDWR_B

INPUT INPUT

L13P_2

L13N_2

GCLK13

GCLK12

A A

VREF_3

VCCAUX

M1

L04N_2

VCCO_2

INPUT

GND

L08N_2

VCCO_2

D6

GND

A B

GND

VREF_2

M0

L04P_2

L05P_2

L05N_2

L08P_2

VS1

VS0

D7

VREF_2

Bank 2

Spartan-3A DSP FPGA Family: Pinout Descriptions

Left Half of Package (Top View)

I/O: Unrestricted,

general-purpose user I/O.

156

INPUT: Unrestricted,

general-purpose input pin.

41

DUAL: Configuration

pins, then possible user

51

I/O.

VREF: User I/O or input

voltage reference for bank.

28

CLK: User I/O, input, or

clock buffer input.

32

2

configuration pin

SUSPEND: Dedicated SUSPEND and

s.

CONFIG: Dedicated

dual-purpose AWAKE Power Managem

ent pins.

INPUT

L04N_3

L14N_3

L19P_3

L19N_3

IRDY2

L22P_3

I/O

L20N_3

I/O

INPUT

I/O

INPUT

I/O

L20P_3

INPUT

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/O

L32P_3

I/O

L18N_3

I/O

INPUT

I/O

L18P_3

I/O

L21P_3 TRDY2

I/O

L24N_0

I/O

L31P_0

I/O

L31N_0

INPUT

L12N_3

I/O

L21N_3

I/O

L20P_0

I/O

L20N_0

I/O

L18P_0

I/O

L18N_0

I/O

L19P_0

I/O

INPUT

0

I/O

L19N_0

I/O

L17N_0

INPUT

L39N_3

I/O

JTAG: Dedicated JTAG

4

84

24

36

24

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 73

port pins.

GND: Ground.

VCCO: Output voltage

supply for bank.

VCCINT: Internal core

supply voltage (+1.2V).

VCCAUX: Auxiliary

supply voltage

Figure 15: CS484 Package Footprint (Top View–Left Half)

I/O

INPUT

2

INPUT

I/O

L01P_2

I/O

L01N_2

I/O

INPUT

2

I/O

L07P_2

I/O

L02P_2

I/O

L07N_2

I/O

L02N_2

I/O

L09P_2

I/O

L10N_2

INPUT

2

I/O

L09N_2

I/O

L14N_2

I/O

L10P_2

I/O

L15N_2

I/O

L12N_2

I/O

L12P_2

I/O

L14P_2

I/O

L15P_2

INPUT

2

Spartan-3A DSP FPGA Family: Pinout Descriptions

12 13 14 15 16 17 18 19 20 21 22

INPUT

L11P_0

L10P_0

INPUT

VREF_0

L06N_0

INPUT

L07N_0

0

TCK GND

A

GND

L11N_0

VCCO_0

L10N_0

GND

L03P_0

VCCO_0

L02N_0

L07P_0

VCCAUX

TDO

B

L14N_0

L14P_0

INPUT

VREF_0

L08N_0

L03N_0

VREF_0

L01N_0

GND

L39N_1

VREF_1

C

VCCAUX

L09N_0

L12P_0

L08P_0

GND

INPUT INPUT

L01P_0

A20

A22

A23

D

GCLK4

L09P_0

VCCO_0

L05P_0

L04P_0

INPUT

VCCAUX

A21

L35N_1

VCCO_1

L33N_1

E

INPUT

L13N_0

L13P_0

L05N_0

L04N_0

GND

A25

A24

A19

L35P_1

L33P_1

F

VCCAUX

GND

VCCAUX

GND VCCINT

L34P_1

L34N_1

A18

L31N_1

GND

L28N_1

G

GND VCCINT GND VCCINT GND

A14

A15

GND

L32N_1

VREF_1

L28P_1

H

VCCINT GND VCCINT GND

VCCAUX

A17

VCCO_1

L32P_1

A13

L27P_1

L27N_1

J

GND VCCINT GND VCCINT

A16

L23N_1

L24N_1

L24P_1

A12

VCCO_1

A11

K

VCCINT GND VCCINT GND

VCCAUX

RHCLK7

VREF_1

GND

RHCLK5

RHCLK4

A10

L

GND VCCINT GND VCCINT GND

RHCLK1

VCCAUX

GND

A9

M

VCCINT GND VCCINT GND

VCCAUX

A2

RHCLK0

A7

A6

RHCLK2

A8

N

GND VCCINT GND VCCINT

A3

VREF_1

VCCO_1

L10P_1

L16N_1

VCCO_1

A5

P

VCCINT GND VCCINT GND GND

L12P_1

L10N_1

L07P_1

L07N_1

VREF_1

A4

R

GND

VCCAUX

GND GND VCCINT

L05N_1

L05P_1

GND

L09N_1

GND

VREF_1

T

GCLK0

L20P_2

L25P_2

L25N_2

L28P_2

GND

HDC

LDC2

L09P_1

VREF_1

L11P_1

U

GCLK1

VCCO_2

VREF_2

L28N_2

CCLK

VCCAUX

SUSPEN

D

A1

VCCO_1

L08P_1

V

Bank 0

GCLK0

L20P_2

L25P_2

L25N_2

L28P_2

GND

HDC

LDC2

L09P_1

VREF_1

L11P_1

U

GCLK1

VCCO_2

VREF_2

L28N_2

CCLK

VCCAUX

SUSPEN

D

A1

VCCO_1

L08P_1

V

GND

VREF_2

L21N_2

INIT_B

GND

VREF_2

A0

VREF_1

L04P_1

L06P_1

W

INPUT

L21P_2

VREF_2

D3

L29N_2

L29P_2

D2

D1

GND

LDC1

L06N_1

Y

GCLK14

VCCO_2

GCLK3

L19P_2

GND

AWAKE

VCCO_2

L27N_2

L30P_2

VCCAUX

LDC0

A A

GCLK15

GCLK2

L19N_2

INPUT

DOUT

L23P_2

L23N_2

L27P_2

L30N_2

DONE GND

A B

Bank 2

I/O

L17P_0

I/O

L12N_0

I/O

L17P_2

I/O

L17N_2

I/O

L16P_2

I/O

L16N_2

I/O

L20N_2

MOSI

INPUT

2

I/O

L18P_2

I/O

INPUT

2

I/O

L18N_2

I/O

INPUT

L24P_2

L24N_2

I/O

L06P_0

I/O

L29P_1

I/O

L13N_1

I/O

2

I/O

L22N_2

I/O

L26P_1

I/O

L29N_1

INPUT

I/O

L21N_1

I/O

L18N_1

I/O

L13P_1

INPUT

L12N_1

INPUT

I/O

L31N_2

I/O

L31P_2

D0

I/O

L22P_2

I/O

L02P_0

I/O

L38N_1

I/O

L26N_1

I/O

INPUT

L23P_1

I/O

L21P_1

IRDY1

I/O

L18P_1

I/O

L01P_1

INPUT

2

I/O

L26P_2

I/O

L36N_1

I/O

L38P_1

I/O

L30P_1

I/O

L15N_1

I/O

L01N_1

I/O

L03P_1

I/O

L26N_2

I/O

L36P_1

L30N_1

INPUT

L25N_1

L25P_1

L20N_1

L19N_1 TRDY1

L15P_1

INPUT

L03N_1

INPUT

L04N_1

I/O

INPUT

I/O

L37P_1

I/O

INPUT

L31P_1

INPUT

I/O

L20P_1

I/O

L19P_1

INPUT

L16P_1

INPUT

L08N_1

INPUT

I/O

L02P_1

INPUT

L39P_1

I/O

L37N_1

I/O

INPUT

I/O

L22N_1

I/O

L22P_1

I/O

L17N_1

I/O

L17P_1

I/O

L14N_1

I/O

L14P_1

I/O

L11N_1

I/O

INPUT

I/O

L02N_1

Right Half of CS484 Package (Top View)

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 74

Figure 16: CS484 Package Footprint (Top View–Right Half)

Spartan-3A DSP FPGA Family: Pinout Descriptions

FG676: 676-Ball Fine-Pitch Ball Grid Array

The 676-ball fine-pitch ball grid array, FG676, supports both the XC3SD1800A and the XC3SD3400A FPGAs. There are multiple pinout differences between the two devices. For a list of differences and migration advice, see the Footprint

Migration Differences section.

XC3SD1800A FPGA

Ta bl e 6 6 lists all the FG676 package pins for the XC3SD1800A FPGA. They are sorted by bank number and then by pin

name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.

Pinout Table

Note: The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices.

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA

Bank XC3SD1800A Pin Name

0 IO_L43N_0 K11 I/O

0 IO_L39N_0 K12 I/O

0 IO_L25P_0/GCLK4 K14 GCLK

0 IO_L12N_0 K16 I/O

0 IP_0 J10 INPUT

0 IO_L43P_0 J11 I/O

0 IO_L39P_0 J12 I/O

0 IP_0 J13 INPUT

0 IO_L25N_0/GCLK5 J14 GCLK

0 IP_0 J15 INPUT

0 IO_L12P_0 J16 I/O

0 IP_0/VREF_0 J17 VREF

0 IO_L47N_0 H9 I/O

0 IO_L46N_0 H10 I/O

0 IO_L35N_0 H12 I/O

0 IP_0 H13 INPUT

0 IO_L16N_0 H15 I/O

0 IO_L08P_0 H17 I/O

0 IP_0 H18 INPUT

0 IO_L52N_0/PUDC_B G8 DUAL

0 IO_L47P_0 G9 I/O

0 IO_L46P_0 G10 I/O

0 IP_0/VREF_0 G11 VREF

0 IO_L35P_0 G12 I/O

0 IO_L27N_0/GCLK9 G13 GCLK

0 IP_0 G14 INPUT

0 IO_L16P_0 G15 I/O

0 IO_L08N_0 G17 I/O

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

0 IO_L02P_0/VREF_0 G19 VREF

0 IO_L01P_0 G20 I/O

0 IO_L48P_0 F7 I/O

0 IO_L52P_0/VREF_0 F8 VREF

0 IO_L31N_0 F12 I/O

0 IO_L27P_0/GCLK8 F13 GCLK

0 IO_L24N_0 F14 I/O

0 IO_L20P_0 F15 I/O

0 IO_L13P_0 F17 I/O

0 IO_L02N_0 F19 I/O

0 IO_L01N_0 F20 I/O

0 IO_L48N_0 E7 I/O

0 IO_L37P_0 E10 I/O

0 IP_0 E11 INPUT

0 IO_L31P_0 E12 I/O

0 IO_L24P_0 E14 I/O

0 IO_L20N_0/VREF_0 E15 VREF

0 IO_L13N_0 E17 I/O

0 IP_0 E18 INPUT

0 IO_L10P_0 E21 I/O

0 IO_L44N_0 D6 I/O

0 IP_0/VREF_0 D7 VREF

0 IO_L40N_0 D8 I/O

0 IO_L37N_0 D9 I/O

0 IO_L34N_0 D10 I/O

0 IO_L32N_0/VREF_0 D11 VREF

0 IP_0 D12 INPUT

0 IO_L30P_0 D13 I/O

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 75

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

0 IP_0/VREF_0 D14 VREF

0 IO_L22P_0 D16 I/O

0 IO_L21P_0 D17 I/O

0 IO_L17P_0 D18 I/O

0 IO_L11P_0 D20 I/O

0 IO_L10N_0 D21 I/O

0 IO_L05P_0 D22 I/O

0 IO_L06P_0 D23 I/O

0 IO_L44P_0 C5 I/O

0 IO_L41N_0 C6 I/O

0 IO_L42N_0 C7 I/O

0 IO_L40P_0 C8 I/O

0 IO_L34P_0 C10 I/O

0 IO_L32P_0 C11 I/O

0 IO_L30N_0 C12 I/O

0 IO_L28N_0/GCLK11 C13 GCLK

0 IO_L22N_0 C15 I/O

0 IO_L21N_0 C16 I/O

0 IO_L19P_0 C17 I/O

0 IO_L17N_0 C18 I/O

0 IO_L11N_0 C20 I/O

0 IO_L09P_0 C21 I/O

0 IO_L05N_0 C22 I/O

0 IO_L06N_0 C23 I/O

0 IO_L51N_0 B3 I/O

0 IO_L45N_0 B4 I/O

0 IO_L41P_0 B6 I/O

0 IO_L42P_0 B7 I/O

0 IO_L38N_0 B8 I/O

0 IO_L36N_0 B9 I/O

0 IO_L33N_0 B10 I/O

0 IO_L29N_0 B12 I/O

0 IO_L28P_0/GCLK10 B13 GCLK

0 IO_L26P_0/GCLK6 B14 GCLK

0 IO_L23P_0 B15 I/O

0 IO_L19N_0 B17 I/O

0 IO_L18P_0 B18 I/O

0 IO_L15P_0 B19 I/O

0 IO_L14P_0/VREF_0 B20 VREF

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

0 IO_L09N_0 B21 I/O

0 IO_L07P_0 B23 I/O

0 IO_L51P_0 A3 I/O

0 IO_L45P_0 A4 I/O

0 IP_0 A7 INPUT

0 IO_L38P_0 A8 I/O

0 IO_L36P_0 A9 I/O

0 IO_L33P_0 A10 I/O

0 IO_L29P_0 A12 I/O

0 IP_0 A13 INPUT

0 IO_L26N_0/GCLK7 A14 GCLK

0 IO_L23N_0 A15 I/O

0 IP_0 A17 INPUT

0 IO_L18N_0 A18 I/O

0 IO_L15N_0 A19 I/O

0 IO_L14N_0 A20 I/O

0 IO_L07N_0 A22 I/O

0 IP_0 G16 INPUT

0 IP_0 E9 INPUT

0 IP_0 D15 INPUT

0 IP_0 D19 INPUT

0 IP_0 B24 INPUT

0 IP_0 A5 INPUT

0 IP_0 A23 INPUT

0 IP_0 F9 INPUT

0 IP_0 E20 INPUT

0 IP_0 A24 INPUT

0 IP_0 G18 INPUT

0 IP_0 F10 INPUT

0 IP_0 F18 INPUT

0 IP_0 E6 INPUT

0 IP_0 D5 INPUT

0 IP_0 C4 INPUT

0 VCCO_0 H11 VCCO

0 VCCO_0 H16 VCCO

0 VCCO_0 E8 VCCO

0 VCCO_0 E13 VCCO

0 VCCO_0 E19 VCCO

0 VCCO_0 B5 VCCO

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 76

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

0 VCCO_0 B11 VCCO

0 VCCO_0 B16 VCCO

0 VCCO_0 B22 VCCO

1 IO_L01P_1/HDC Y20 DUAL

1IO_L01N_1/LDC2 Y21DUAL

1 IO_L13P_1 Y22 I/O

1 IO_L13N_1 Y23 I/O

1 IO_L15P_1 Y24 I/O

1 IO_L15N_1 Y25 I/O

1 IP_L16N_1 Y26 INPUT

1 IO_L04P_1 W20 I/O

1 IO_L04N_1 W21 I/O

1 IO_L18P_1 W23 I/O

1 IO_L08P_1 V18 I/O

1 IO_L08N_1 V19 I/O

1 IO_L10P_1 V21 I/O

1 IO_L18N_1 V22 I/O

1 IO_L21P_1 V23 I/O

1 IO_L19P_1 V24 I/O

1 IO_L19N_1 V25 I/O

1 IP_L20N_1/VREF_1 V26 VREF

1 IO_L12N_1 U18 I/O

1 IO_L12P_1 U19 I/O

1 IO_L10N_1 U20 I/O

1 IO_L14P_1 U21 I/O

1 IO_L21N_1 U22 I/O

1 IO_L23P_1 U23 I/O

1 IO_L23N_1/VREF_1 U24 VREF

1 IP_L24N_1/VREF_1 U26 VREF

1 IO_L17N_1 T17 I/O

1 IO_L17P_1 T18 I/O

1 IO_L14N_1 T20 I/O

1 IO_L26P_1/A4 T23 DUAL

1 IO_L26N_1/A5 T24 DUAL

1 IO_L27N_1/A7 R17 DUAL

1 IO_L27P_1/A6 R18 DUAL

1 IO_L22P_1 R19 I/O

1 IO_L22N_1 R20 I/O

1 IO_L25P_1/A2 R21 DUAL

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

1 IO_L25N_1/A3 R22 DUAL

1 IP_L28P_1/VREF_1 R23 VREF

1 IP_L28N_1 R24 INPUT

1 IO_L29P_1/A8 R25 DUAL

1 IO_L29N_1/A9 R26 DUAL

1

1 IO_L30N_1/RHCLK1 P20 RHCLK

1 IO_L30P_1/RHCLK0 P21 RHCLK

1 IO_L37P_1 P22 I/O

1 IO_L33P_1/RHCLK4 P23 RHCLK

1

1 IO_L31P_1/RHCLK2 P26 RHCLK

1 IO_L39N_1/A15 N17 DUAL

1 IO_L39P_1/A14 N18 DUAL

1 IO_L34N_1/RHCLK7 N19 RHCLK

1 IO_L42P_1/A16 N20 DUAL

1 IO_L37N_1 N21 I/O

1 IP_L36N_1 N23 INPUT

1 IO_L33N_1/RHCLK5 N24 RHCLK

1 IP_L32N_1 N25 INPUT

1 IP_L32P_1 N26 INPUT

1 IO_L47N_1 M18 I/O

1 IO_L47P_1 M19 I/O

1 IO_L42N_1/A17 M20 DUAL

1 IO_L45P_1 M21 I/O

1 IO_L45N_1 M22 I/O

1 IO_L38N_1/A13 M23 DUAL

1 IP_L36P_1/VREF_1 M24 VREF

1 IO_L35N_1/A11 M25 DUAL

1 IO_L35P_1/A10 M26 DUAL

1 IO_L55N_1 L17 I/O

1 IO_L55P_1 L18 I/O

1 IO_L53P_1 L20 I/O

1 IO_L50P_1 L22 I/O

1 IP_L40N_1 L23 INPUT

1 IO_L38P_1/A12 L24 DUAL

1 IO_L57N_1 K18 I/O

1 IO_L57P_1 K19 I/O

1 IO_L53N_1 K20 I/O

IO_L34P_1/IRDY1/RHCLK6

IO_L31N_1/TRDY1/RHCLK3

FG676

Ball

P18 RHCLK

P25 RHCLK

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 77

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

1 IO_L50N_1 K21 I/O

1 IO_L46N_1 K22 I/O

1 IO_L46P_1 K23 I/O

1 IP_L40P_1 K24 INPUT

1 IO_L41P_1 K25 I/O

1 IO_L41N_1 K26 I/O

1 IO_L59P_1 J19 I/O

1 IO_L59N_1 J20 I/O

1 IO_L62P_1/A20 J21 DUAL

1 IO_L49N_1 J22 I/O

1 IO_L49P_1 J23 I/O

1 IO_L43N_1/A19 J25 DUAL

1 IO_L43P_1/A18 J26 DUAL

1 IO_L64P_1/A24 H20 DUAL

1 IO_L62N_1/A21 H21 DUAL

1 IP_L48N_1 H24 INPUT

1 IP_L44N_1 H25 INPUT

1 IP_L44P_1/VREF_1 H26 VREF

1 IO_L64N_1/A25 G21 DUAL

1 IO_L58N_1 G22 I/O

1 IO_L51P_1 G23 I/O

1 IO_L51N_1 G24 I/O

1 IP_L52N_1/VREF_1 G25 VREF

1 IO_L58P_1/VREF_1 F22 VREF

1 IO_L56N_1 F23 I/O

1 IO_L54N_1 F24 I/O

1 IO_L54P_1 F25 I/O

1 IO_L56P_1 E24 I/O

1 IO_L60P_1 E26 I/O

1 IO_L61N_1 D24 I/O

1 IO_L61P_1 D25 I/O

1 IO_L60N_1 D26 I/O

1 IO_L63N_1/A23 C25 DUAL

1 IO_L63P_1/A22 C26 DUAL

1 IP_L65P_1/VREF_1 B26 VREF

1 IO_L02P_1/LDC1 AE26 DUAL

1 IO_L02N_1/LDC0 AD25 DUAL

1 IO_L05P_1 AD26 I/O

1 IO_L03P_1/A0 AC23 DUAL

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

1 IO_L03N_1/A1 AC24 DUAL

1 IO_L05N_1 AC25 I/O

1 IO_L06P_1 AC26 I/O

1 IO_L07P_1 AB23 I/O

1 IO_L07N_1/VREF_1 AB24 VREF

1 IO_L06N_1 AB26 I/O

1 IO_L09P_1 AA22 I/O

1 IO_L09N_1 AA23 I/O

1 IO_L11P_1 AA24 I/O

1 IO_L11N_1 AA25 I/O

1 IP_L16P_1 W25 INPUT

1 IP_L24P_1 U25 INPUT

1 IP_L65N_1 B25 INPUT

1 IP_L20P_1 W26 INPUT

1 IP_L48P_1 H23 INPUT

1 IP_L52P_1 G26 INPUT

1 VCCO_1 W22 VCCO

1 VCCO_1 T19 VCCO

1 VCCO_1 T25 VCCO

1 VCCO_1 N22 VCCO

1 VCCO_1 L19 VCCO

1 VCCO_1 L25 VCCO

1 VCCO_1 H22 VCCO

1 VCCO_1 E25 VCCO

1 VCCO_1 AB25 VCCO

2 IO_L02P_2/M2 Y7 DUAL

2 IO_L05N_2 Y9 I/O

2 IO_L12P_2 Y10 I/O

2 IO_L17P_2/RDWR_B Y12 DUAL

2 IO_L25N_2/GCLK13 Y13 GCLK

2 IO_L27P_2/GCLK0 Y14 GCLK

2 IO_L34N_2/D3 Y15 DUAL

2 IP_2/VREF_2 Y16 VREF

2 IO_L43N_2 Y17 I/O

2 IO_L05P_2 W9 I/O

2 IO_L09N_2 W10 I/O

2 IO_L16N_2 W12 I/O

2 IO_L20N_2 W13 I/O

2 IO_L31N_2 W15 I/O

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 78

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

2 IO_L46P_2 W17 I/O

2 IO_L09P_2 V10 I/O

2 IO_L13P_2 V11 I/O

2 IO_L16P_2 V12 I/O

2 IO_L20P_2 V13 I/O

2 IO_L31P_2 V14 I/O

2 IO_L35P_2 V15 I/O

2 IO_L42P_2 V16 I/O

2 IO_L46N_2 V17 I/O

2 IO_L13N_2 U11 I/O

2 IO_L35N_2 U15 I/O

2 IO_L42N_2 U16 I/O

2 IO_L06N_2 AF3 I/O

2 IO_L07N_2 AF4 I/O

2 IO_L10P_2 AF5 I/O

2 IP_2 AF7 INPUT

2 IO_L18N_2 AF8 I/O

2 IO_L19N_2/VS0 AF9 DUAL

2 IO_L22N_2/D6 AF10 DUAL

2 IO_L24P_2/D5 AF12 DUAL

2 IO_L26P_2/GCLK14 AF13 GCLK

2 IO_L28P_2/GCLK2 AF14 GCLK

2 IP_2/VREF_2 AF15 VREF

2 IP_2/VREF_2 AF17 VREF

2 IO_L36P_2/D2 AF18 DUAL

2 IO_L37P_2 AF19 I/O

2 IO_L39P_2 AF20 I/O

2 IP_2/VREF_2 AF22 VREF

2 IO_L48P_2 AF23 I/O

2 IO_L52P_2/D0/DIN/MISO AF24 DUAL

2 IO_L51P_2 AF25 I/O

2 IO_L06P_2 AE3 I/O

2 IO_L07P_2 AE4 I/O

2 IO_L10N_2 AE6 I/O

2 IO_L11N_2 AE7 I/O

2 IO_L18P_2 AE8 I/O

2 IO_L19P_2/VS1 AE9 DUAL

2 IO_L22P_2/D7 AE10 DUAL

2 IO_L24N_2/D4 AE12 DUAL

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

2 IO_L26N_2/GCLK15 AE13 GCLK

2 IO_L28N_2/GCLK3 AE14 GCLK

2 IO_L32N_2/DOUT AE15 DUAL

2 IO_L33P_2 AE17 I/O

2 IO_L36N_2/D1 AE18 DUAL

2 IO_L37N_2 AE19 I/O

2 IO_L39N_2 AE20 I/O

2 IO_L44P_2 AE21 I/O

2 IO_L48N_2 AE23 I/O

2 IO_L52N_2/CCLK AE24 DUAL

2 IO_L51N_2 AE25 I/O

2 IO_L01N_2/M0 AD4 DUAL

2 IO_L08N_2 AD6 I/O

2 IO_L11P_2 AD7 I/O

2 IP_2 AD9 INPUT

2 IP_2 AD10 INPUT

2 IO_L23P_2 AD11 I/O

2 IP_2/VREF_2 AD12 VREF

2 IO_L29P_2 AD14 I/O

2 IO_L32P_2/AWAKE AD15

2 IP_2 AD16 INPUT

2 IO_L33N_2 AD17 I/O

2 IO_L40P_2 AD19 I/O

2 IO_L41P_2 AD20 I/O

2 IO_L44N_2 AD21 I/O

2 IO_L45P_2 AD22 I/O

2 IO_L01P_2/M1 AC4 DUAL

2 IO_L08P_2 AC6 I/O

2 IO_L14P_2 AC8 I/O

2 IO_L15N_2 AC9 I/O

2 IP_2/VREF_2 AC10 VREF

2 IO_L23N_2 AC11 I/O

2 IO_L21N_2 AC12 I/O

2 IP_2 AC13 INPUT

2 IO_L29N_2 AC14 I/O

2 IO_L30P_2 AC15 I/O

2 IO_L38P_2 AC16 I/O

2 IP_2 AC17 INPUT

2 IO_L40N_2 AC19 I/O

FG676

Ball

Type

PWRMGMT

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 79

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

2 IO_L41N_2 AC20 I/O

2 IO_L45N_2 AC21 I/O

2 IO_2 AC22 I/O

2 IP_2/VREF_2 AB6 VREF

2 IO_L14N_2 AB7 I/O

2 IO_L15P_2 AB9 I/O

2 IO_L21P_2 AB12 I/O

2 IP_2 AB13 INPUT

2 IO_L30N_2/MOSI/CSI_B AB15 DUAL

2 IO_L38N_2 AB16 I/O

2 IO_L47P_2 AB18 I/O

2 IO_L02N_2/CSO_B AA7 DUAL

2 IP_2/VREF_2 AA9 VREF

2 IO_L12N_2 AA10 I/O

2 IO_L17N_2/VS2 AA12 DUAL

2 IO_L25P_2/GCLK12 AA13 GCLK

2 IO_L27N_2/GCLK1 AA14 GCLK

2 IO_L34P_2/INIT_B AA15 DUAL

2 IO_L43P_2 AA17 I/O

2 IO_L47N_2 AA18 I/O

2 IP_2/VREF_2 AA20 VREF

2 IP_2 AD5 INPUT

2 IP_2 AD23 INPUT

2 IP_2 AC5 INPUT

2 IP_2 AC7 INPUT

2 IP_2 AC18 INPUT

2 IP_2/VREF_2 AB10 VREF

2 IP_2 AB20 INPUT

2 IP_2 AA19 INPUT

2 IP_2 AF2 INPUT

2 IP_2 AB17 INPUT

2 IP_2 Y8 INPUT

2 IP_2 Y11 INPUT

2 IP_2 Y18 INPUT

2 IP_2/VREF_2 Y19 VREF

2 IP_2 W18 INPUT

2 IP_2 AA8 INPUT

2 VCCO_2 W11 VCCO

2 VCCO_2 W16 VCCO

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

2 VCCO_2 AE5 VCCO

2 VCCO_2 AE11 VCCO

2 VCCO_2 AE16 VCCO

2 VCCO_2 AE22 VCCO

2 VCCO_2 AB8 VCCO

2 VCCO_2 AB14 VCCO

2 VCCO_2 AB19 VCCO

3 IO_L53P_3 Y1 I/O

3 IO_L53N_3 Y2 I/O

3 IP_L54P_3 Y3 INPUT

3 IO_L57P_3 Y5 I/O

3 IO_L57N_3 Y6 I/O

3 IP_L50P_3 W1 INPUT

3 IP_L50N_3/VREF_3 W2 VREF

3 IO_L52P_3 W3 I/O

3 IO_L52N_3 W4 I/O

3 IO_L63N_3 W6 I/O

3 IO_L63P_3 W7 I/O

3 IO_L47P_3 V1 I/O

3 IO_L47N_3 V2 I/O

3 IP_L46N_3 V4 INPUT

3 IO_L49N_3 V5 I/O

3 IO_L59N_3 V6 I/O

3 IO_L59P_3 V7 I/O

3 IO_L61N_3 V8 I/O

3 IO_L44P_3 U1 I/O

3 IO_L44N_3 U2 I/O

3 IP_L46P_3 U3 INPUT

3 IO_L42N_3 U4 I/O

3 IO_L49P_3 U5 I/O

3 IO_L51N_3 U6 I/O

3 IO_L56P_3 U7 I/O

3 IO_L56N_3 U8 I/O

3 IO_L61P_3 U9 I/O

3 IO_L38P_3 T3 I/O

3 IO_L38N_3 T4 I/O

3 IO_L42P_3 T5 I/O

3 IO_L51P_3 T7 I/O

3 IO_L48N_3 T9 I/O

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 80

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

3 IO_L48P_3 T10 I/O

3 IO_L36P_3/VREF_3 R1 VREF

3 IO_L36N_3 R2 I/O

3 IO_L37P_3 R3 I/O

3 IO_L37N_3 R4 I/O

3 IO_L40P_3 R5 I/O

3 IO_L40N_3 R6 I/O

3 IO_L45N_3 R7 I/O

3 IO_L45P_3 R8 I/O

3 IO_L43N_3 R9 I/O

3 IO_L43P_3/VREF_3 R10 VREF

3 IO_L33P_3/LHCLK2 P1 LHCLK

3

3 IO_L34N_3/LHCLK5 P3 LHCLK

3 IO_L34P_3/LHCLK4 P4 LHCLK

3 IO_L39N_3 P6 I/O

3 IO_L39P_3 P7 I/O

3 IO_L41P_3 P8 I/O

3 IO_L41N_3 P9 I/O

3 IO_L35N_3/LHCLK7 P10 LHCLK

3 IO_L31P_3 N1 I/O

3 IO_L31N_3 N2 I/O

3 IO_L30N_3 N4 I/O

3 IO_L30P_3 N5 I/O

3 IO_L32P_3/LHCLK0 N6 LHCLK

3 IO_L32N_3/LHCLK1 N7 LHCLK

3

3 IO_L29N_3/VREF_3 M1 VREF

3 IO_L29P_3 M2 I/O

3 IO_L27N_3 M3 I/O

3 IO_L27P_3 M4 I/O

3 IO_L28P_3 M5 I/O

3 IO_L28N_3 M6 I/O

3 IO_L26N_3 M7 I/O

3 IO_L26P_3 M8 I/O

3 IO_L21N_3 M9 I/O

3 IO_L21P_3 M10 I/O

3 IO_L25N_3 L3 I/O

3 IO_L25P_3 L4 I/O

IO_L33N_3/IRDY2/LHCLK3

IO_L35P_3/TRDY2/LHCLK6

FG676

Ball

P2 LHCLK

N9 LHCLK

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

3 IO_L18N_3 L7 I/O

3 IO_L15N_3 L9 I/O

3 IO_L15P_3 L10 I/O

3 IP_L24N_3 K1 INPUT

3 IO_L23N_3 K2 I/O

3 IO_L23P_3 K3 I/O

3 IO_L22N_3 K4 I/O

3 IO_L22P_3 K5 I/O

3 IO_L18P_3 K6 I/O

3 IO_L13P_3 K7 I/O

3 IO_L05N_3 K8 I/O

3 IO_L05P_3 K9 I/O

3 IP_L24P_3 J1 INPUT

3 IP_L20N_3/VREF_3 J2 VREF

3 IP_L20P_3 J3 INPUT

3 IO_L19N_3 J4 I/O

3 IO_L19P_3 J5 I/O

3 IO_L13N_3 J6 I/O

3 IO_L10P_3 J7 I/O

3 IO_L01P_3 J8 I/O

3 IO_L01N_3 J9 I/O

3 IO_L17N_3 H1 I/O

3 IO_L17P_3 H2 I/O

3 IP_L12N_3/VREF_3 H4 VREF

3 IO_L10N_3 H6 I/O

3 IO_L03N_3 H7 I/O

3 IP_L16N_3 G1 INPUT

3 IO_L14P_3 G3 I/O

3 IO_L09N_3 G4 I/O

3 IO_L03P_3 G6 I/O

3 IO_L11N_3 F2 I/O

3 IO_L14N_3 F3 I/O

3 IO_L07N_3 F4 I/O

3 IO_L09P_3 F5 I/O

3 IO_L11P_3 E1 I/O

3 IO_L07P_3 E3 I/O

3 IO_L06N_3 E4 I/O

3 IO_L06P_3 D3 I/O

3 IP_L04N_3/VREF_3 C1 VREF

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 81

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

3 IP_L04P_3 C2 INPUT

3 IO_L02N_3 B1 I/O

3 IO_L02P_3 B2 I/O

3 IP_L66P_3 AE1 INPUT

3 IP_L66N_3/VREF_3 AE2 VREF

3 IO_L65P_3 AD1 I/O

3 IO_L65N_3 AD2 I/O

3 IO_L60N_3 AC1 I/O

3 IO_L64P_3 AC2 I/O

3 IO_L64N_3 AC3 I/O

3 IO_L60P_3 AB1 I/O

3 IO_L55P_3 AA2 I/O

3 IO_L55N_3 AA3 I/O

3 IP_L58N_3/VREF_3 AA5 VREF

3 IP_L16P_3 G2 INPUT

3 IP_L12P_3 G5 INPUT

3 IP_L08P_3 D2 INPUT

3 IP_L62P_3 AB3 INPUT

3 IP_L58P_3 AA4 INPUT

3 IP_L08N_3 D1 INPUT

3 IP_L62N_3 AB4 INPUT

3 IP_L54N_3 Y4 INPUT

3 VCCO_3 W5 VCCO

3 VCCO_3 T2 VCCO

3 VCCO_3 T8 VCCO

3 VCCO_3 P5 VCCO

3 VCCO_3 L2 VCCO

3 VCCO_3 L8 VCCO

3 VCCO_3 H5 VCCO

3 VCCO_3 E2 VCCO

3 VCCO_3 AB2 VCCO

GND GND W8 GND

GND GND W14 GND

GND GND W19 GND

GND GND W24 GND

GND GND V3 GND

GND GND U10 GND

GND GND U13 GND

GND GND U17 GND

FG676

Ball

Typ e

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

GND GND T1 GND

GND GND T6 GND

GND GND T12 GND

GND GND T14 GND

GND GND T16 GND

GND GND T21 GND

GND GND T26 GND

GND GND R11 GND

GND GND R13 GND

GND GND R15 GND

GND GND P12 GND

GND GND P16 GND

GND GND P19 GND

GND GND P24 GND

GND GND N3 GND

GND GND N8 GND

GND GND N11 GND

GND GND N15 GND

GND GND M12 GND

GND GND M14 GND

GND GND M16 GND

GND GND L1 GND

GND GND L6 GND

GND GND L11 GND

GND GND L13 GND

GND GND L15 GND

GND GND L21 GND

GND GND L26 GND

GND GND K10 GND

GND GND K17 GND

GND GND J24 GND

GND GND H3 GND

GND GND H8 GND

GND GND H14 GND

GND GND H19 GND

GND GND F1 GND

GND GND F6 GND

GND GND F11 GND

GND GND F16 GND

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 82

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 6 : Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

GND GND F21 GND

GND GND F26 GND

GND GND C3 GND

GND GND C9 GND

GND GND C14 GND

GND GND C19 GND

GND GND C24 GND

GND GND AF1 GND

GND GND AF6 GND

GND GND AF11 GND

GND GND AF16 GND

GND GND AF21 GND

GND GND AF26 GND

GND GND AD3 GND

GND GND AD8 GND

GND GND AD13 GND

GND GND AD18 GND

GND GND AD24 GND

GND GND AA1 GND

GND GND AA6 GND

GND GND AA11 GND

GND GND AA16 GND

GND GND AA21 GND

GND GND AA26 GND

GND GND A1 GND

GND GND A6 GND

GND GND A11 GND

GND GND A16 GND

GND GND A21 GND

GND GND A26 GND

VCCAUX SUSPEND V20

VCCAUX DONE AB21 CONFIG

VCCAUX PROG_B A2 CONFIG

VCCAUX TDI G7 JTAG

VCCAUX TDO E23 JTAG

VCCAUX TMS D4 JTAG

VCCAUX TCK A25 JTAG

VCCAUX VCCAUX V9 VCCAUX

VCCAUX VCCAUX U14 VCCAUX

FG676

Ball

Typ e

PWRMGMT

Tab l e 6 6: Spartan-3A DSP FG676 Pinout for XC3SD1800A FPGA (Cont’d)

Bank XC3SD1800A Pin Name

VCCAUX VCCAUX T22 VCCAUX

VCCAUX VCCAUX P17 VCCAUX

VCCAUX VCCAUX N10 VCCAUX

VCCAUX VCCAUX L5 VCCAUX

VCCAUX VCCAUX K13 VCCAUX

VCCAUX VCCAUX J18 VCCAUX

VCCAUX VCCAUX E5 VCCAUX

VCCAUX VCCAUX E16 VCCAUX

VCCAUX VCCAUX E22 VCCAUX

VCCAUX VCCAUX AB5 VCCAUX

VCCAUX VCCAUX AB11 VCCAUX

VCCAUX VCCAUX AB22 VCCAUX

VCCINT VCCINT U12 VCCINT

VCCINT VCCINT T11 VCCINT

VCCINT VCCINT T13 VCCINT

VCCINT VCCINT T15 VCCINT

VCCINT VCCINT R12 VCCINT

VCCINT VCCINT R14 VCCINT

VCCINT VCCINT R16 VCCINT

VCCINT VCCINT P11 VCCINT

VCCINT VCCINT P13 VCCINT

VCCINT VCCINT P14 VCCINT

VCCINT VCCINT P15 VCCINT

VCCINT VCCINT N12 VCCINT

VCCINT VCCINT N13 VCCINT

VCCINT VCCINT N14 VCCINT

VCCINT VCCINT N16 VCCINT

VCCINT VCCINT M11 VCCINT

VCCINT VCCINT M13 VCCINT

VCCINT VCCINT M15 VCCINT

VCCINT VCCINT M17 VCCINT

VCCINT VCCINT L12 VCCINT

VCCINT VCCINT L14 VCCINT

VCCINT VCCINT L16 VCCINT

VCCINT VCCINT K15 VCCINT

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 83

Spartan-3A DSP FPGA Family: Pinout Descriptions

User I/Os by Bank

Table 67 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The

AWAKE pin is counted as a dual-purpose I/O.

Tab le 6 7 : User I/Os Per Bank for the XC3SD1800A in the FG676 Package

Package

Edge

To p 0 128 82 28 1 9 8

Right 1 130 67 15 30 10 8

Bottom 2 129 68 21 21 11 8

Left 3 132 97 18 0 9 8

TOTAL 519 314 82 52 39 32

Notes:

1. 28 VREF are on INPUT pins.

I/O Bank

Maximum I/Os

and

Input-Only

I/O INPUT DUAL VREF

All Possible I/O Pins by Type

(1)

CLK

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 84

FG676 Footprint –

12345678910111213

A

GND

PROG_

B

L51P_0

L45P_0

∇

GND

∇

L38P_0

L36P_0

L33P_0

GND

L29P_0

INPUT

B

L02N_3

L02P_3

L51N_0

L45N_0

VCCO_0

L41P_0

L42P_0

L38N_0

L36N_0

L33N_0

VCCO_0

L29N_0

GCLK10

C

INPUT

VREF_3

∇

GND

∇

L44P_0

L41N_0

L42N_0

L40P_0

GND

L34P_0

L32P_0

L30N_0

GCLK11

D

∇

L06P_3

TMS

∇

L44N_0

VREF_0

L40N_0

L37N_0

L34N_0

VREF_0

INPUT

L30P_0

E

L11P_3

VCCO_3

L07P_3

L06N_3

VCCAUX

∇

L48N_0

VCCO_0

∇

L37P_0

INPUT

L31P_0

VCCO_0

F

GND

L11N_3

L14N_3

L07N_3

L09P_3

GND

L48P_0

VREF_0

∇

GND

L31N_0

GCLK8

G

∇

L14P_3

L09N_3

∇

L03P_3

TDI

PUDC_B

L47P_0

L46P_0

VREF_0

L35P_0

GCLK9

H

L17N_3

L17P_3

GND

INPUT

VREF_3

VCCO_3

L10N_3

L03N_3

GND

L47N_0

L46N_0

VCCO_0

L35N_0

INPUT

J

L24P_3

VREF_3

L20P_3

L19N_3

L19P_3

L13N_3

L10P_3

L01P_3

L01N_3

INPUT

L43P_0

L39P_0

INPUT

K

L24N_3

L23N_3

L23P_3

L22N_3

L22P_3

L18P_3

L13P_3

L05N_3

L05P_3

GND

L43N_0

L39N_0

VCCAUX

L

GND

VCCO_3

L25N_3

L25P_3

VCCAUX

GND

L18N_3

VCCO_3

L15N_3

L15P_3

GND VCCINT GND

M

VREF_3

L29P_3

L27N_3

L27P_3

L28P_3

L28N_3

L26N_3

L26P_3

L21N_3

L21P_3

VCCINT GND VCCINT

N

L31P_3

L31N_3

GND

L30N_3

L30P_3

LHCLK0

LHCLK1

GND

VCCAUX

GND VCCINT VCCINT

P

LHCLK2

LHCLK5

LHCLK4

VCCO_3

L39N_3

L39P_3

L41P_3

L41N_3

LHCLK7

VCCINT GND VCCINT

R

VREF_3

L36N_3

L37P_3

L37N_3

L40P_3

L40N_3

L45N_3

L45P_3

L43N_3

VREF_3

GND VCCINT GND

T

GND

VCCO_3

L38P_3

L38N_3

L42P_3

GND

L51P_3

VCCO_3

L48N_3

L48P_3

VCCINT GND VCCINT

U

L44P_3

L44N_3

L46P_3

L42N_3

L49P_3

L51N_3

L56P_3

L56N_3

L61P_3

GND

L13N_2

VCCINT GND

Bank 0

Bank 3

V

L47P_3

L47N_3

GND

L46N_3

L49N_3

L59N_3

L59P_3

L61N_3

VCCAUX

L09P_2

L13P_2

L16P_2

L20P_2

W

L50P_3

VREF_3

L52P_3

L52N_3

VCCO_3

L63N_3

L63P_3

GND

L05P_2

L09N_2

VCCO_2

L16N_2

L20N_2

Y

L53P_3

L53N_3

∇

L57P_3

L57N_3

M2

∇

L05N_2

L12P_2

∇

RDWR_B

GCLK13

A A

GND

L55P_3

L55N_3

∇

INPUT

VREF_3

GND

CSO_B

∇

VREF_2

L12N_2

GND

VS2

GCLK12

A B

L60P_3

VCCO_3

∇

VCCAUX

VREF_2

L14N_2

VCCO_2

L15P_2

∇

VCCAUX

L21P_2

INPUT

A C

L60N_3

L64P_3

L64N_3

M1

∇

L08P_2

∇

L14P_2

L15N_2

VREF_2

L23N_2

L21N_2

INPUT

A D

L65P_3

L65N_3

GND

M0

∇

L08N_2

L11P_2

GND

INPUT INPUT

L23P_2

VREF_2

GND

A E

L66P_3

VREF_3

L06P_2

L07P_2

VCCO_2

L10N_2

L11N_2

L18P_2

VS1

D7

VCCO_2

D4

GCLK15

A

F

GND

∇

L06N_2

L07N_2

L10P_2

GND

∇

L18N_2

VS0

D6

GND

D5

GCLK14

Bank 2

XC3SD1800A FPGA

Left Half of Package (Top View)

I/O: Unrestricted,

general-purpose user I/O.

314

INPUT: Unrestricted,

general-purpose input pin.

82

DUAL: Configuration pins,

then possible user I/O.

51

VREF: User I/O or input

voltage reference for bank.

39

CLK: User I/O, input, or

clock buffer input.

32

I/O

L04N_3

INPUT

L08N_3

I/O

INPUT

L16N_3

I/O

INPUT

I/O

INPUT

L04P_3

INPUT

L08P_3

I/O

INPUT

L16P_3

I/O

INPUT

L20N_3

I/O

Spartan-3A DSP FPGA Family: Pinout Descriptions

I/O

INPUT

I/O

INPUT

I/O

L12N_3

I/O

INPUT

I/O

INPUT

I/O

INPUT

L12P_3

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/O

L52P_0

I/O

L52N_0

I/O

INPUT

I/O

INPUT ∇INPUT

I/O

L32N_0

INPUT

I/O

L28P_0

I/O

L28N_0

I/O

L27P_0

I/O

L27N_0

I/O

L35P_3 TRDY2 LHCLK6

I/O

INPUT

I/O

L19P_2

I/O

L19N_2

I/O

L35N_3

I/O

L43P_3

I/O

INPUT

VREF_2

INPUT

I/O

L22P_2

I/O

L22N_2

I/O

INPUT

I/O

CONFIG: Dedicated

2

configuration pins

JTAG: Dedicated JTAG

port pins.

4

77

36

23

14

Note: The boxes with triangles

inside indicate pin differences from the XC3SD3400A device. Please see the Footprint Migration

Differences section for more

information.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 85

SUSPEND: Dedicated

2

SUSPEND and dual-purpose AWAKE Power Management pins

GND: Ground

VCCO: Output voltage

supply for bank.

VCCINT: Internal core

supply voltage (+1.2V).

VCCAUX: Auxiliary

supply voltage.

.

Figure 16: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Left Half)

L29N_3

I/O

L33P_3

I/O

L36P_3

I/O

INPUT

I/O

INPUT

I/O

L33N_3

IRDY2

LHCLK3

I/O

INPUT

L50N_3

I/O

INPUT

L66N_3

INPUT

I/O

L34N_3

I/O

INPUT

I/O

INPUT

L54P_3

I/O

INPUT

L62P_3

I/O

L34P_3

I/O

INPUT

I/O

INPUT

L54N_3

INPUT

L58P_3

INPUT

L62N_3

I/O

L01P_2

I/O

L01N_2

I/O

L58N_3

INPUT

I/O

L32P_3

I/O

INPUT

I/O

L32N_3

I/O

L02P_2

I/O

L02N_2

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/O

L17P_2

I/O

L17N_2

I/O

INPUT

I/O

L24N_2

I/O

L24P_2

I/O

L25N_2

I/O

L25P_2

I/O

L26N_2

I/O

L26P_2

Spartan-3A DSP FPGA Family: Pinout Descriptions

14 15 16 17 18 19 20 21 22 23 24 25 26

GCLK7

L23N_0

GND

INPUT

L18N_0

L15N_0

L14N_0

GND

L07N_0

∇

TCK GND

A

GCLK6

L23P_0

VCCO_0

L19N_0

L18P_0

L15P_0

VREF_0

L09N_0

VCCO_0

L07P_0

∇

INPUT

B

GND

L22N_0

L21N_0

L19P_0

L17N_0

GND

L11N_0

L09P_0

L05N_0

L06N_0

GND

A23

A22

C

VREF_0

∇

L22P_0

L21P_0

L17P_0

∇

L11P_0

L10N_0

L05P_0

L06P_0

L61N_1

L61P_1

L60N_1

D

L24P_0

VREF_0

VCCAUX

L13N_0

INPUT

VCCO_0

∇

L10P_0

VCCAUX

TDO

L56P_1

VCCO_1

L60P_1

E

L24N_0

L20P_0

GND

L13P_0

∇

L02N_0

L01N_0

GND

VREF_1

L56N_1

L54N_1

L54P_1

GND

F

INPUT

L16P_0

∇

L08N_0

∇

VREF_0

L01P_0

A25

L58N_1

L51P_1

L51N_1

INPUT

∇

G

GND

L16N_0

VCCO_0

L08P_0

INPUT

GND

A24

A21

VCCO_1

∇

INPUT

H

GCLK5

INPUT

L12P_0

VREF_0

VCCAUX

L59P_1

L59N_1

A20

L49N_1

L49P_1

GND

A19

A18

J

GCLK4

VCCINT

L12N_0

GND

L57N_1

L57P_1

L53N_1

L50N_1

L46N_1

L46P_1

L40P_1

L41P_1

L41N_1

K

VCCINT GND VCCINT

L55N_1

L55P_1

VCCO_1

L53P_1

GND

L50P_1

L40N_1

A12

VCCO_1

GND

L

GND VCCINT GND VCCINT

L47N_1

L47P_1

A17

L45P_1

L45N_1

A13

VREF_1

A11

A10

M

VCCINT GND VCCINT

A15

A14

RHCLK7

A16

L37N_1

VCCO_1

L36N_1

RHCLK5

L32N_1

L32P_1

N

VCCINT VCCINT GND

VCCAUX

GND

RHCLK1

RHCLK0

L37P_1

RHCLK4

GND

RHCLK2

P

VCCINT GND VCCINT

A7

A6

L22P_1

L22N_1

A2

A3

VREF_1

L28N_1

A8

A9

R

GND VCCINT GND

L17N_1

L17P_1

VCCO_1

L14N_1

GND

VCCAUX

A4

A5

VCCO_1

GND

T

VCCAUX

L35N_2

L42N_2

GND

L12N_1

L12P_1

L10N_1

L14P_1

L21N_1

L23P_1

VREF_1

∇

INPUT

U

Bank 0

Bank 1

L31P_2

L35P_2

L42P_2

L46N_2

L08P_1

L08N_1

SUSPEND

L10P_1

L18N_1

L21P_1

L19P_1

L19N_1

INPUT

V

GND

L31N_2

VCCO_2

L46P_2

∇

GND

L04P_1

L04N_1

VCCO_1

L18P_1

GND

∇

W

GCLK0

D3

VREF_2

L43N_2

∇

HDC

LDC2

L13P_1

L13N_1

L15P_1

L15N_1

∇

Y

GCLK1

INIT_B

GND

L43P_2

L47N_2

∇

VREF_2

GND

L09P_1

L09N_1

L11P_1

L11N_1

GND

A A

VCCO_2

_

L38N_2

∇

L47P_2

VCCO_2

∇

DONE

VCCAUX

L07P_1

VREF_1

VCCO_1

L06N_1

A B

L29N_2

L30P_2

L38P_2

INPUT

∇

L40N_2

L41N_2

L45N_2

2

A0

A1

L05N_1

L06P_1

A C

L29P_2

AWAKE

INPUT

L33N_2

GND

L40P_2

L41P_2

L44N_2

L45P_2

∇

GND

LDC0

L05P_1

A D

GCLK3

DOUT

VCCO_2

L33P_2

D1

L37N_2

L39N_2

L44P_2

VCCO_2

L48N_2

CCLK

L51N_2

LDC1

A E

GCLK2

VREF_2

GND

VREF_2

D2

L37P_2

L39P_2

GND

VREF_2

L48P_2

L51P_2

GND

A F

Bank 2

I/O

L26N_0

I/O

L26P_0

I/O

INPUT

I/O

L20N_0

I/O

INPUT

I/O

L25N_0

I/O

L25P_0

I/O

L27P_2

I/O

L27N_2

I/O

L28N_2

I/O

L28P_2

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 86

I/O

L34N_2

I/O

L34P_2

I/O

L30N_2

MOSI

B

CSI

I/O

L32P_2

I/O

L32N_2

INPUT

I/O

INPUT

I/O

Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Right Half)

I/O

INPUT

I/O

L39N_1

I/O

L27N_1

I/O

INPUT

I/O

INPUT

I/O

INPUT

I/O

L39P_1

I/O

L34P_1

IRDY1

RHCLK6

I/O

L27P_1

I/O

INPUT

I/O

INPUT

I/O

L36N_2

I/O

L36P_2

I/O

INPUT

I/O

L02P_0

I/O

L34N_1

I/O

INPUT

VREF_2

∇

INPUT

I/O

L14P_0

I/O

INPUT

I/O

L64P_1

I/O

L42N_1

I/O

L42P_1

I/O

L30N_1

I/O

L01P_1

INPUT

I/O

L64N_1

I/O

L62N_1

I/O

L62P_1

I/O

L30P_1

I/O

L25P_1

I/O

L01N_1

I/O

L58P_1

I/O

L25N_1

I/O

INPUT

INPUT ∇INPUT

I/O

INPUT

L48P_1

I/O

INPUT

I/O

L38N_1

INPUT

I/O

L33P_1

INPUT

L28P_1

I/O

L26P_1

I/O

L03P_1

INPUT

I/O

INPUT

I/O

INPUT

L48N_1

INPUT

I/O

L38P_1

INPUT

L36P_1

I/O

L33N_1

INPUT

I/O

L26N_1

I/O

L23N_1

I/O

L07N_1

I/O

L03N_1

I/O

L52N_2

I/O

L52P_2

D0

DIN/MISO

Right Half of FG676 Package (Top View)

L65P_1

VREF_1

I/O

L63P_1

I/O

INPUT

L65N_1

I/O

L63N_1

I/O

INPUT

L52N_1

L52P_1

VREF_1

L44P_1

VREF_1

I/O

L43P_1

I/O

L35P_1

INPUT

I/O

L31P_1

I/O

L29N_1

INPUT

L44N_1

I/O

L43N_1

I/O

L35N_1

INPUT

I/O

L31N_1

TRDY1

RHCLK3

I/O

L29P_1

INPUT

L24P_1

I/O

INPUT

L16P_1

I/O

L24N_1

VREF_1

L20N_1

VREF_1

INPUT

L20P_1

INPUT

L16N_1

I/O

L02N_1

I/O

L02P_1

I/O

Spartan-3A DSP FPGA Family: Pinout Descriptions

XC3SD3400A FPGA

Ta bl e 6 8 lists all the FG676 package pins for the XC3SD3400A FPGA. They are sorted by bank number and then by pin

name. Pairs of pins that form a differential I/O pair appear together in the table. Ta bl e 6 8 also shows the pin number for each pin and the pin type, as defined earlier.

An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:

www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip

Pinout Table

Note: The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices.

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA

Bank XC3SD3400A Pin Name

0 IO_L43N_0 K11 I/O

0 IO_L39N_0 K12 I/O

0 IO_L25P_0/GCLK4 K14 GCLK

0 IO_L12N_0 K16 I/O

0 IP_0 J10 INPUT

0 IO_L43P_0 J11 I/O

0 IO_L39P_0 J12 I/O

0 IP_0 J13 INPUT

0 IO_L25N_0/GCLK5 J14 GCLK

0 IP_0 J15 INPUT

0 IO_L12P_0 J16 I/O

0 IP_0/VREF_0 J17 VREF

0 IO_L47N_0 H9 I/O

0 IO_L46N_0 H10 I/O

0 IO_L35N_0 H12 I/O

0 IP_0 H13 INPUT

0 IO_L16N_0 H15 I/O

0 IO_L08P_0 H17 I/O

0 IP_0 H18 INPUT

0 IO_L52N_0/PUDC_B G8 DUAL

0 IO_L47P_0 G9 I/O

0 IO_L46P_0 G10 I/O

0 IP_0/VREF_0 G11 VREF

0 IO_L35P_0 G12 I/O

0 IO_L27N_0/GCLK9 G13 GCLK

0 IP_0 G14 INPUT

0 IO_L16P_0 G15 I/O

0 IO_L08N_0 G17 I/O

0 IO_L02P_0/VREF_0 G19 VREF

0 IO_L01P_0 G20 I/O

FG676

Ball

Typ e

.

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

0 IO_L48P_0 F7 I/O

0 IO_L52P_0/VREF_0 F8 VREF

0 IO_L31N_0 F12 I/O

0 IO_L27P_0/GCLK8 F13 GCLK

0 IO_L24N_0 F14 I/O

0 IO_L20P_0 F15 I/O

0 IO_L13P_0 F17 I/O

0 IO_L02N_0 F19 I/O

0 IO_L01N_0 F20 I/O

0 IO_L48N_0 E7 I/O

0 IO_L37P_0 E10 I/O

0 IP_0 E11 INPUT

0 IO_L31P_0 E12 I/O

0 IO_L24P_0 E14 I/O

0 IO_L20N_0/VREF_0 E15 VREF

0 IO_L13N_0 E17 I/O

0 IP_0 E18 INPUT

0 IO_L10P_0 E21 I/O

0 IO_L44N_0 D6 I/O

0 IP_0/VREF_0 D7 VREF

0 IO_L40N_0 D8 I/O

0 IO_L37N_0 D9 I/O

0 IO_L34N_0 D10 I/O

0 IO_L32N_0/VREF_0 D11 VREF

0 IP_0 D12 INPUT

0 IO_L30P_0 D13 I/O

0 IP_0/VREF_0 D14 VREF

0 IO_L22P_0 D16 I/O

0 IO_L21P_0 D17 I/O

0 IO_L17P_0 D18 I/O

0 IO_L11P_0 D20 I/O

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 87

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

0 IO_L10N_0 D21 I/O

0 IO_L05P_0 D22 I/O

0 IO_L06P_0 D23 I/O

0 IO_L44P_0 C5 I/O

0 IO_L41N_0 C6 I/O

0 IO_L42N_0 C7 I/O

0 IO_L40P_0 C8 I/O

0 IO_L34P_0 C10 I/O

0 IO_L32P_0 C11 I/O

0 IO_L30N_0 C12 I/O

0 IO_L28N_0/GCLK11 C13 GCLK

0 IO_L22N_0 C15 I/O

0 IO_L21N_0 C16 I/O

0 IO_L19P_0 C17 I/O

0 IO_L17N_0 C18 I/O

0 IO_L11N_0 C20 I/O

0 IO_L09P_0 C21 I/O

0 IO_L05N_0 C22 I/O

0 IO_L06N_0 C23 I/O

0 IO_L51N_0 B3 I/O

0 IO_L45N_0 B4 I/O

0 IO_L41P_0 B6 I/O

0 IO_L42P_0 B7 I/O

0 IO_L38N_0 B8 I/O

0 IO_L36N_0 B9 I/O

0 IO_L33N_0 B10 I/O

0 IO_L29N_0 B12 I/O

0 IO_L28P_0/GCLK10 B13 GCLK

0 IO_L26P_0/GCLK6 B14 GCLK

0 IO_L23P_0 B15 I/O

0 IO_L19N_0 B17 I/O

0 IO_L18P_0 B18 I/O

0 IO_L15P_0 B19 I/O

0 IO_L14P_0/VREF_0 B20 VREF

0 IO_L09N_0 B21 I/O

0 IO_L07P_0 B23 I/O

0 IO_L51P_0 A3 I/O

0 IO_L45P_0 A4 I/O

0 IO_L38P_0 A8 I/O

FG676

Ball

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

0 IO_L36P_0 A9 I/O

0 IO_L33P_0 A10 I/O

0 IO_L29P_0 A12 I/O

0 IP_0 A13 INPUT

0 IO_L26N_0/GCLK7 A14 GCLK

0 IO_L23N_0 A15 I/O

0 IP_0 A17 INPUT

0 IO_L18N_0 A18 I/O

0 IO_L15N_0 A19 I/O

0 IO_L14N_0 A20 I/O

0 IO_L07N_0 A22 I/O

0 VCCO_0 H11 VCCO

0 VCCO_0 H16 VCCO

0 VCCO_0 E8 VCCO

0 VCCO_0 E13 VCCO

0 VCCO_0 E19 VCCO

0 VCCO_0 B5 VCCO

0 VCCO_0 B11 VCCO

0 VCCO_0 B16 VCCO

0 VCCO_0 B22 VCCO

0 VCCO_0 A7 VCCO

1 IO_L01P_1/HDC Y20 DUAL

1 IO_L01N_1/LDC2 Y21 DUAL

1 IO_L13P_1 Y22 I/O

1 IO_L13N_1 Y23 I/O

1 IO_L15P_1 Y24 I/O

1 IO_L15N_1 Y25 I/O

1 IP_1 Y26 INPUT

1 IO_L04P_1 W20 I/O

1 IO_L04N_1 W21 I/O

1 IO_L18P_1 W23 I/O

1 IO_L08P_1 V18 I/O

1 IO_L08N_1 V19 I/O

1 IO_L10P_1 V21 I/O

1 IO_L18N_1 V22 I/O

1 IO_L21P_1 V23 I/O

1 IO_L19P_1 V24 I/O

1 IO_L19N_1 V25 I/O

1 IP_1/VREF_1 V26 VREF

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 88

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

1 IO_L12N_1 U18 I/O

1 IO_L12P_1 U19 I/O

1 IO_L10N_1 U20 I/O

1 IO_L14P_1 U21 I/O

1 IO_L21N_1 U22 I/O

1 IO_L23P_1 U23 I/O

1 IO_L23N_1/VREF_1 U24 VREF

1 IP_1/VREF_1 U26 VREF

1 IO_L17N_1 T17 I/O

1 IO_L17P_1 T18 I/O

1 IO_L14N_1 T20 I/O

1 IO_L26P_1/A4 T23 DUAL

1 IO_L26N_1/A5 T24 DUAL

1 IO_L27N_1/A7 R17 DUAL

1 IO_L27P_1/A6 R18 DUAL

1 IO_L22P_1 R19 I/O

1 IO_L22N_1 R20 I/O

1 IO_L25P_1/A2 R21 DUAL

1 IO_L25N_1/A3 R22 DUAL

1 IP_L28P_1/VREF_1 R23 VREF

1 IP_L28N_1 R24 INPUT

1 IO_L29P_1/A8 R25 DUAL

1 IO_L29N_1/A9 R26 DUAL

1 IO_L34P_1/IRDY1/RHCLK6 P18 RHCLK

1 IO_L30N_1/RHCLK1 P20 RHCLK

1 IO_L30P_1/RHCLK0 P21 RHCLK

1 IO_L37P_1 P22 I/O

1 IO_L33P_1/RHCLK4 P23 RHCLK

IO_L31N_1/TRDY1/RHCLK3

1

1 IO_L31P_1/RHCLK2 P26 RHCLK

1 IO_L39N_1/A15 N17 DUAL

1 IO_L39P_1/A14 N18 DUAL

1 IO_L34N_1/RHCLK7 N19 RHCLK

1 IO_L42P_1/A16 N20 DUAL

1 IO_L37N_1 N21 I/O

1 IP_L36N_1 N23 INPUT

1 IO_L33N_1/RHCLK5 N24 RHCLK

1 IP_L32N_1 N25 INPUT

1 IP_L32P_1 N26 INPUT

FG676

Ball

P25 RHCLK

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

1 IO_L47N_1 M18 I/O

1 IO_L47P_1 M19 I/O

1 IO_L42N_1/A17 M20 DUAL

1 IO_L45P_1 M21 I/O

1 IO_L45N_1 M22 I/O

1 IO_L38N_1/A13 M23 DUAL

1 IP_L36P_1/VREF_1 M24 VREF

1 IO_L35N_1/A11 M25 DUAL

1 IO_L35P_1/A10 M26 DUAL

1 IO_L55N_1 L17 I/O

1 IO_L55P_1 L18 I/O

1 IO_L53P_1 L20 I/O

1 IO_L50P_1 L22 I/O

1 IP_L40N_1 L23 INPUT

1 IO_L38P_1/A12 L24 DUAL

1 IO_L57N_1 K18 I/O

1 IO_L57P_1 K19 I/O

1 IO_L53N_1 K20 I/O

1 IO_L50N_1 K21 I/O

1 IO_L46N_1 K22 I/O

1 IO_L46P_1 K23 I/O

1 IP_L40P_1 K24 INPUT

1 IO_L41P_1 K25 I/O

1 IO_L41N_1 K26 I/O

1 IO_L59P_1 J19 I/O

1 IO_L59N_1 J20 I/O

1 IO_L62P_1/A20 J21 DUAL

1 IO_L49N_1 J22 I/O

1 IO_L49P_1 J23 I/O

1 IO_L43N_1/A19 J25 DUAL

1 IO_L43P_1/A18 J26 DUAL

1 IO_L64P_1/A24 H20 DUAL

1 IO_L62N_1/A21 H21 DUAL

1 IP_1 H24 INPUT

1 IP_1/VREF_1 H26 VREF

1 IO_L64N_1/A25 G21 DUAL

1 IO_L58N_1 G22 I/O

1 IO_L51P_1 G23 I/O

1 IO_L51N_1 G24 I/O

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 89

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

1 IP_1/VREF_1 G25 VREF

1 IO_L58P_1/VREF_1 F22 VREF

1 IO_L56N_1 F23 I/O

1 IO_L54N_1 F24 I/O

1 IO_L54P_1 F25 I/O

1 IO_L56P_1 E24 I/O

1 IO_L60P_1 E26 I/O

1 IO_L61N_1 D24 I/O

1 IO_L61P_1 D25 I/O

1 IO_L60N_1 D26 I/O

1 IO_L63N_1/A23 C25 DUAL

1 IO_L63P_1/A22 C26 DUAL

1 IP_1/VREF_1 B26 VREF

1 IO_L02P_1/LDC1 AE26 DUAL

1 IO_L02N_1/LDC0 AD25 DUAL

1 IO_L05P_1 AD26 I/O

1 IO_L03P_1/A0 AC23 DUAL

1 IO_L03N_1/A1 AC24 DUAL

1 IO_L05N_1 AC25 I/O

1 IO_L06P_1 AC26 I/O

1 IO_L07P_1 AB23 I/O

1 IO_L07N_1/VREF_1 AB24 VREF

1 IO_L06N_1 AB26 I/O

1 IO_L09P_1 AA22 I/O

1 IO_L09N_1 AA23 I/O

1 IO_L11P_1 AA24 I/O

1 IO_L11N_1 AA25 I/O

1 VCCO_1 W22 VCCO

1 VCCO_1 T19 VCCO

1 VCCO_1 T25 VCCO

1 VCCO_1 N22 VCCO

1 VCCO_1 L19 VCCO

1 VCCO_1 L25 VCCO

1 VCCO_1 H22 VCCO

1 VCCO_1 H25 VCCO

1 VCCO_1 E25 VCCO

1 VCCO_1 AB25 VCCO

2 IO_L02P_2/M2 Y7 DUAL

2 IO_L05N_2 Y9 I/O

FG676

Ball

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

2 IO_L12P_2 Y10 I/O

2 IO_L17P_2/RDWR_B Y12 DUAL

2 IO_L25N_2/GCLK13 Y13 GCLK

2 IO_L27P_2/GCLK0 Y14 GCLK

2 IO_L34N_2/D3 Y15 DUAL

2 IP_2/VREF_2 Y16 VREF

2 IO_L43N_2 Y17 I/O

2 IO_L05P_2 W9 I/O

2 IO_L09N_2 W10 I/O

2 IO_L16N_2 W12 I/O

2 IO_L20N_2 W13 I/O

2 IO_L31N_2 W15 I/O

2 IO_L46P_2 W17 I/O

2 IO_L09P_2 V10 I/O

2 IO_L13P_2 V11 I/O

2 IO_L16P_2 V12 I/O

2 IO_L20P_2 V13 I/O

2 IO_L31P_2 V14 I/O

2 IO_L35P_2 V15 I/O

2 IO_L42P_2 V16 I/O

2 IO_L46N_2 V17 I/O

2 IO_L13N_2 U11 I/O

2 IO_L35N_2 U15 I/O

2 IO_L42N_2 U16 I/O

2 IO_L06N_2 AF3 I/O

2 IO_L07N_2 AF4 I/O

2 IO_L10P_2 AF5 I/O

2 IO_L18N_2 AF8 I/O

2 IO_L19N_2/VS0 AF9 DUAL

2 IO_L22N_2/D6 AF10 DUAL

2 IO_L24P_2/D5 AF12 DUAL

2 IO_L26P_2/GCLK14 AF13 GCLK

2 IO_L28P_2/GCLK2 AF14 GCLK

2 IP_2/VREF_2 AF15 VREF

2 IP_2/VREF_2 AF17 VREF

2 IO_L36P_2/D2 AF18 DUAL

2 IO_L37P_2 AF19 I/O

2 IO_L39P_2 AF20 I/O

2 IP_2/VREF_2 AF22 VREF

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 90

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

2 IO_L48P_2 AF23 I/O

2 IO_L52P_2/D0/DIN/MISO AF24 DUAL

2 IO_L51P_2 AF25 I/O

2 IO_L06P_2 AE3 I/O

2 IO_L07P_2 AE4 I/O

2 IO_L10N_2 AE6 I/O

2 IO_L11N_2 AE7 I/O

2 IO_L18P_2 AE8 I/O

2 IO_L19P_2/VS1 AE9 DUAL

2 IO_L22P_2/D7 AE10 DUAL

2 IO_L24N_2/D4 AE12 DUAL

2 IO_L26N_2/GCLK15 AE13 GCLK

2 IO_L28N_2/GCLK3 AE14 GCLK

2 IO_L32N_2/DOUT AE15 DUAL

2 IO_L33P_2 AE17 I/O

2 IO_L36N_2/D1 AE18 DUAL

2 IO_L37N_2 AE19 I/O

2 IO_L39N_2 AE20 I/O

2 IO_L44P_2 AE21 I/O

2 IO_L48N_2 AE23 I/O

2 IO_L52N_2/CCLK AE24 DUAL

2 IO_L51N_2 AE25 I/O

2 IO_L01N_2/M0 AD4 DUAL

2 IO_L08N_2 AD6 I/O

2 IO_L11P_2 AD7 I/O

2 IP_2 AD9 INPUT

2 IP_2 AD10 INPUT

2 IO_L23P_2 AD11 I/O

2 IP_2/VREF_2 AD12 VREF

2 IO_L29P_2 AD14 I/O

2 IO_L32P_2/AWAKE AD15

2 IP_2 AD16 INPUT

2 IO_L33N_2 AD17 I/O

2 IO_L40P_2 AD19 I/O

2 IO_L41P_2 AD20 I/O

2 IO_L44N_2 AD21 I/O

2 IO_L45P_2 AD22 I/O

2 IO_L01P_2/M1 AC4 DUAL

2 IO_L08P_2 AC6 I/O

FG676

Ball

Typ e

PWRMGMT

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

2 IO_L14P_2 AC8 I/O

2 IO_L15N_2 AC9 I/O

2 IP_2/VREF_2 AC10 VREF

2 IO_L23N_2 AC11 I/O

2 IO_L21N_2 AC12 I/O

2 IP_2 AC13 INPUT

2 IO_L29N_2 AC14 I/O

2 IO_L30P_2 AC15 I/O

2 IO_L38P_2 AC16 I/O

2 IP_2 AC17 INPUT

2 IO_L40N_2 AC19 I/O

2 IO_L41N_2 AC20 I/O

2 IO_L45N_2 AC21 I/O

2 IO_2 AC22 I/O

2 IP_2/VREF_2 AB6 VREF

2 IO_L14N_2 AB7 I/O

2 IO_L15P_2 AB9 I/O

2 IO_L21P_2 AB12 I/O

2 IP_2 AB13 INPUT

2 IO_L30N_2/MOSI/CSI_B AB15 DUAL

2 IO_L38N_2 AB16 I/O

2 IO_L47P_2 AB18 I/O

2 IO_L02N_2/CSO_B AA7 DUAL

2 IP_2/VREF_2 AA9 VREF

2 IO_L12N_2 AA10 I/O

2 IO_L17N_2/VS2 AA12 DUAL

2 IO_L25P_2/GCLK12 AA13 GCLK

2 IO_L27N_2/GCLK1 AA14 GCLK

2 IO_L34P_2/INIT_B AA15 DUAL

2 IO_L43P_2 AA17 I/O

2 IO_L47N_2 AA18 I/O

2 IP_2/VREF_2 AA20 VREF

2 VCCO_2 W11 VCCO

2 VCCO_2 W16 VCCO

2 VCCO_2 AF7 VCCO

2 VCCO_2 AE5 VCCO

2 VCCO_2 AE11 VCCO

2 VCCO_2 AE16 VCCO

2 VCCO_2 AE22 VCCO

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 91

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

2 VCCO_2 AB8 VCCO

2 VCCO_2 AB14 VCCO

2 VCCO_2 AB19 VCCO

3 IO_L53P_3 Y1 I/O

3 IO_L53N_3 Y2 I/O

3 IP_3 Y3 INPUT

3 IO_L57P_3 Y5 I/O

3 IO_L57N_3 Y6 I/O

3 IP_L50P_3 W1 INPUT

3 IP_L50N_3/VREF_3 W2 VREF

3 IO_L52P_3 W3 I/O

3 IO_L52N_3 W4 I/O

3 IO_L63N_3 W6 I/O

3 IO_L63P_3 W7 I/O

3 IO_L47P_3 V1 I/O

3 IO_L47N_3 V2 I/O

3 IP_L46N_3 V4 INPUT

3 IO_L49N_3 V5 I/O

3 IO_L59N_3 V6 I/O

3 IO_L59P_3 V7 I/O

3 IO_L61N_3 V8 I/O

3 IO_L44P_3 U1 I/O

3 IO_L44N_3 U2 I/O

3 IP_L46P_3 U3 INPUT

3 IO_L42N_3 U4 I/O

3 IO_L49P_3 U5 I/O

3 IO_L51N_3 U6 I/O

3 IO_L56P_3 U7 I/O

3 IO_L56N_3 U8 I/O

3 IO_L61P_3 U9 I/O

3 IO_L38P_3 T3 I/O

3 IO_L38N_3 T4 I/O

3 IO_L42P_3 T5 I/O

3 IO_L51P_3 T7 I/O

3 IO_L48N_3 T9 I/O

3 IO_L48P_3 T10 I/O

3 IO_L36P_3/VREF_3 R1 VREF

3 IO_L36N_3 R2 I/O

3 IO_L37P_3 R3 I/O

FG676

Ball

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

3 IO_L37N_3 R4 I/O

3 IO_L40P_3 R5 I/O

3 IO_L40N_3 R6 I/O

3 IO_L45N_3 R7 I/O

3 IO_L45P_3 R8 I/O

3 IO_L43N_3 R9 I/O

3 IO_L43P_3/VREF_3 R10 VREF

3 IO_L33P_3/LHCLK2 P1 LHCLK

3 IO_L33N_3/IRDY2/LHCLK3 P2 LHCLK

3 IO_L34N_3/LHCLK5 P3 LHCLK

3 IO_L34P_3/LHCLK4 P4 LHCLK

3 IO_L39N_3 P6 I/O

3 IO_L39P_3 P7 I/O

3 IO_L41P_3 P8 I/O

3 IO_L41N_3 P9 I/O

3 IO_L35N_3/LHCLK7 P10 LHCLK

3 IO_L31P_3 N1 I/O

3 IO_L31N_3 N2 I/O

3 IO_L30N_3 N4 I/O

3 IO_L30P_3 N5 I/O

3 IO_L32P_3/LHCLK0 N6 LHCLK

3 IO_L32N_3/LHCLK1 N7 LHCLK

3 IO_L35P_3/TRDY2/LHCLK6 N9 LHCLK

3 IO_L29N_3/VREF_3 M1 VREF

3 IO_L29P_3 M2 I/O

3 IO_L27N_3 M3 I/O

3 IO_L27P_3 M4 I/O

3 IO_L28P_3 M5 I/O

3 IO_L28N_3 M6 I/O

3 IO_L26N_3 M7 I/O

3 IO_L26P_3 M8 I/O

3 IO_L21N_3 M9 I/O

3 IO_L21P_3 M10 I/O

3 IO_L25N_3 L3 I/O

3 IO_L25P_3 L4 I/O

3 IO_L18N_3 L7 I/O

3 IO_L15N_3 L9 I/O

3 IO_L15P_3 L10 I/O

3 IP_L24N_3 K1 INPUT

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 92

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

3 IO_L23N_3 K2 I/O

3 IO_L23P_3 K3 I/O

3 IO_L22N_3 K4 I/O

3 IO_L22P_3 K5 I/O

3 IO_L18P_3 K6 I/O

3 IO_L13P_3 K7 I/O

3 IO_L05N_3 K8 I/O

3 IO_L05P_3 K9 I/O

3 IP_L24P_3 J1 INPUT

3 IP_L20N_3/VREF_3 J2 VREF

3 IP_L20P_3 J3 INPUT

3 IO_L19N_3 J4 I/O

3 IO_L19P_3 J5 I/O

3 IO_L13N_3 J6 I/O

3 IO_L10P_3 J7 I/O

3 IO_L01P_3 J8 I/O

3 IO_L01N_3 J9 I/O

3 IO_L17N_3 H1 I/O

3 IO_L17P_3 H2 I/O

3 IP_3/VREF_3 H4 VREF

3 IO_L10N_3 H6 I/O

3 IO_L03N_3 H7 I/O

3 IP_3 G1 INPUT

3 IO_L14P_3 G3 I/O

3 IO_L09N_3 G4 I/O

3 IO_L03P_3 G6 I/O

3 IO_L11N_3 F2 I/O

3 IO_L14N_3 F3 I/O

3 IO_L07N_3 F4 I/O

3 IO_L09P_3 F5 I/O

3 IO_L11P_3 E1 I/O

3 IO_L07P_3 E3 I/O

3 IO_L06N_3 E4 I/O

3 IO_L06P_3 D3 I/O

3 IP_3/VREF_3 C1 VREF

3 IO_L02N_3 B1 I/O

3 IO_L02P_3 B2 I/O

3 IP_L66P_3 AE1 INPUT

3 IP_L66N_3/VREF_3 AE2 VREF

FG676

Ball

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

3 IO_L65P_3 AD1 I/O

3 IO_L65N_3 AD2 I/O

3 IO_L60N_3 AC1 I/O

3 IO_L64P_3 AC2 I/O

3 IO_L64N_3 AC3 I/O

3 IO_L60P_3 AB1 I/O

3 IO_L55P_3 AA2 I/O

3 IO_L55N_3 AA3 I/O

3 IP_3/VREF_3 AA5 VREF

3 VCCO_3 W5 VCCO

3 VCCO_3 T2 VCCO

3 VCCO_3 T8 VCCO

3 VCCO_3 P5 VCCO

3 VCCO_3 L2 VCCO

3 VCCO_3 L8 VCCO

3 VCCO_3 H5 VCCO

3 VCCO_3 E2 VCCO

3 VCCO_3 C2 VCCO

3 VCCO_3 AB2 VCCO

GND GND W8 GND

GND GND W14 GND

GND GND W19 GND

GND GND W24 GND

GND GND W25 GND

GND GND V3 GND

GND GND U10 GND

GND GND U13 GND

GND GND U17 GND

GND GND U25 GND

GND GND T1 GND

GND GND T6 GND

GND GND T12 GND

GND GND T14 GND

GND GND T16 GND

GND GND T21 GND

GND GND T26 GND

GND GND R11 GND

GND GND R13 GND

GND GND R15 GND

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 93

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

GND GND P12 GND

GND GND P16 GND

GND GND P19 GND

GND GND P24 GND

GND GND N3 GND

GND GND N8 GND

GND GND N11 GND

GND GND N15 GND

GND GND M12 GND

GND GND M14 GND

GND GND M16 GND

GND GND L1 GND

GND GND L6 GND

GND GND L11 GND

GND GND L13 GND

GND GND L15 GND

GND GND L21 GND

GND GND L26 GND

GND GND K10 GND

GND GND K17 GND

GND GND J24 GND

GND GND H3 GND

GND GND H8 GND

GND GND H14 GND

GND GND H19 GND

GND GND G2 GND

GND GND G5 GND

GND GND G16 GND

GND GND F1 GND

GND GND F6 GND

GND GND F11 GND

GND GND F16 GND

GND GND F21 GND

GND GND F26 GND

GND GND E9 GND

GND GND D2 GND

GND GND D15 GND

GND GND D19 GND

GND GND C3 GND

FG676

Ball

Typ e

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

GND GND C9 GND

GND GND C14 GND

GND GND C19 GND

GND GND C24 GND

GND GND B24 GND

GND GND B25 GND

GND GND AF1 GND

GND GND AF6 GND

GND GND AF11 GND

GND GND AF16 GND

GND GND AF21 GND

GND GND AF26 GND

GND GND AD3 GND

GND GND AD5 GND

GND GND AD8 GND

GND GND AD13 GND

GND GND AD18 GND

GND GND AD23 GND

GND GND AD24 GND

GND GND AC5 GND

GND GND AC7 GND

GND GND AC18 GND

GND GND AB3 GND

GND GND AB10 GND

GND GND AB20 GND

GND GND AA1 GND

GND GND AA4 GND

GND GND AA6 GND

GND GND AA11 GND

GND GND AA16 GND

GND GND AA19 GND

GND GND AA21 GND

GND GND AA26 GND

GND GND A1 GND

GND GND A5 GND

GND GND A6 GND

GND GND A11 GND

GND GND A16 GND

GND GND A21 GND

FG676

Ball

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 94

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 6 8 : Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

GND GND A23 GND

GND GND A26 GND

VCCAUX SUSPEND V20

VCCAUX DONE AB21 CONFIG

VCCAUX PROG_B A2 CONFIG

VCCAUX TDI G7 JTAG

VCCAUX TDO E23 JTAG

VCCAUX TMS D4 JTAG

VCCAUX TCK A25 JTAG

VCCAUX VCCAUX W26 VCCAUX

VCCAUX VCCAUX V9 VCCAUX

VCCAUX VCCAUX U14 VCCAUX

VCCAUX VCCAUX T22 VCCAUX

VCCAUX VCCAUX P17 VCCAUX

VCCAUX VCCAUX N10 VCCAUX

VCCAUX VCCAUX L5 VCCAUX

VCCAUX VCCAUX K13 VCCAUX

VCCAUX VCCAUX J18 VCCAUX

VCCAUX VCCAUX H23 VCCAUX

VCCAUX VCCAUX G26 VCCAUX

VCCAUX VCCAUX F9 VCCAUX

VCCAUX VCCAUX E5 VCCAUX

VCCAUX VCCAUX E16 VCCAUX

VCCAUX VCCAUX E20 VCCAUX

VCCAUX VCCAUX E22 VCCAUX

VCCAUX VCCAUX D1 VCCAUX

VCCAUX VCCAUX AF2 VCCAUX

VCCAUX VCCAUX AB4 VCCAUX

VCCAUX VCCAUX AB5 VCCAUX

VCCAUX VCCAUX AB11 VCCAUX

VCCAUX VCCAUX AB17 VCCAUX

VCCAUX VCCAUX AB22 VCCAUX

VCCAUX VCCAUX A24 VCCAUX

VCCINT VCCINT Y4 VCCINT

VCCINT VCCINT Y8 VCCINT

VCCINT VCCINT Y11 VCCINT

VCCINT VCCINT Y18 VCCINT

VCCINT VCCINT Y19 VCCINT

VCCINT VCCINT W18 VCCINT

FG676

Ball

Typ e

PWRMGMT

Tab l e 6 8: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d)

Bank XC3SD3400A Pin Name

VCCINT VCCINT U12 VCCINT

VCCINT VCCINT T11 VCCINT

VCCINT VCCINT T13 VCCINT

VCCINT VCCINT T15 VCCINT

VCCINT VCCINT R12 VCCINT

VCCINT VCCINT R14 VCCINT

VCCINT VCCINT R16 VCCINT

VCCINT VCCINT P11 VCCINT

VCCINT VCCINT P13 VCCINT

VCCINT VCCINT P14 VCCINT

VCCINT VCCINT P15 VCCINT

VCCINT VCCINT N12 VCCINT

VCCINT VCCINT N13 VCCINT

VCCINT VCCINT N14 VCCINT

VCCINT VCCINT N16 VCCINT

VCCINT VCCINT M11 VCCINT

VCCINT VCCINT M13 VCCINT

VCCINT VCCINT M15 VCCINT

VCCINT VCCINT M17 VCCINT

VCCINT VCCINT L12 VCCINT

VCCINT VCCINT L14 VCCINT

VCCINT VCCINT L16 VCCINT

VCCINT VCCINT K15 VCCINT

VCCINT VCCINT G18 VCCINT

VCCINT VCCINT F10 VCCINT

VCCINT VCCINT F18 VCCINT

VCCINT VCCINT E6 VCCINT

VCCINT VCCINT D5 VCCINT

VCCINT VCCINT

FG676

Ball

C4

AA8

VCCINT

Type

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 95

Spartan-3A DSP FPGA Family: Pinout Descriptions

User I/Os by Bank

Table 69 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The

AWAKE pin is counted as a dual-purpose I/O.

Tab le 6 9 : User I/Os Per Bank for the XC3SD3400A in the FG676 Package

Package

Edge

To p 0 111 82 11 1 9 8

Right 1 123 67 8 30 10 8

Bottom 2 112 68 6 21 9 8

Left 3 123 97 9 0 9 8

TOTAL 469 314 34 52 37 32

Notes:

1. 26 VREF are on INPUT pins.

I/O Bank

Maximum I/Os

and

Input-Only

I/O INPUT DUAL VREF

All Possible I/O Pins by Type

(1)

CLK

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 96

FG676 Footprint –

12345678910111213

A

GND

PROG_

B

L51P_0

L45P_0

∇

GND

∇

L38P_0

L36P_0

L33P_0

GND

L29P_0

INPUT

B

L02N_3

L02P_3

L51N_0

L45N_0

VCCO_0

L41P_0

L42P_0

L38N_0

L36N_0

L33N_0

VCCO_0

L29N_0

GCLK10

C

VREF_3

∇

GND

∇

L44P_0

L41N_0

L42N_0

L40P_0

GND

L34P_0

L32P_0

L30N_0

GCLK11

D

∇

L06P_3

TMS

∇

L44N_0

VREF_0

L40N_0

L37N_0

L34N_0

VREF_0

INPUT

L30P_0

E

L11P_3

VCCO_3

L07P_3

L06N_3

VCCAUX

∇

L48N_0

VCCO_0

∇

L37P_0

INPUT

L31P_0

VCCO_0

F

GND

L11N_3

L14N_3

L07N_3

L09P_3

GND

L48P_0

VREF_0

∇

GND

L31N_0

GCLK8

G

INPUT

∇

L14P_3

L09N_3

∇

L03P_3

TDI

PUDC_B

L47P_0

L46P_0

VREF_0

L35P_0

GCLK9

H

L17N_3

L17P_3

GND

VREF_3

∇

VCCO_3

L10N_3

L03N_3

GND

L47N_0

L46N_0

VCCO_0

L35N_0

INPUT

J

L24P_3

VREF_3

L20P_3

L19N_3

L19P_3

L13N_3

L10P_3

L01P_3

L01N_3

INPUT

L43P_0

L39P_0

INPUT

K

L24N_3

L23N_3

L23P_3

L22N_3

L22P_3

L18P_3

L13P_3

L05N_3

L05P_3

GND

L43N_0

L39N_0

VCCAUX

L

GND

VCCO_3

L25N_3

L25P_3

VCCAUX

GND

L18N_3

VCCO_3

L15N_3

L15P_3

GND VCCINT GND

M

VREF_3

L29P_3

L27N_3

L27P_3

L28P_3

L28N_3

L26N_3

L26P_3

L21N_3

L21P_3

VCCINT GND VCCINT

N

L31P_3

L31N_3

GND

L30N_3

L30P_3

LHCLK0

LHCLK1

GND

VCCAUX

GND VCCINT VCCINT

P

LHCLK2

LHCLK5

LHCLK4

VCCO_3

L39N_3

L39P_3

L41P_3

L41N_3

LHCLK7

VCCINT GND VCCINT

R

VREF_3

L36N_3

L37P_3

L37N_3

L40P_3

L40N_3

L45N_3

L45P_3

L43N_3

VREF_3

GND VCCINT GND

T

GND

VCCO_3

L38P_3

L38N_3

L42P_3

GND

L51P_3

VCCO_3

L48N_3

L48P_3

VCCINT GND VCCINT

U

L44P_3

L44N_3

L46P_3

L42N_3

L49P_3

L51N_3

L56P_3

L56N_3

L61P_3

GND

L13N_2

VCCINT GND

Bank 0

Bank 3

V

L47P_3

L47N_3

GND

L46N_3

L49N_3

L59N_3

L59P_3

L61N_3

VCCAUX

L09P_2

L13P_2

L16P_2

L20P_2

W

L50P_3

VREF_3

L52P_3

L52N_3

VCCO_3

L63N_3

L63P_3

GND

L05P_2

L09N_2

VCCO_2

L16N_2

L20N_2

Y

L53P_3

L53N_3

INPUT

∇

L57P_3

L57N_3

M2

∇

L05N_2

L12P_2

∇

RDWR_B

GCLK13

A A

GND

L55P_3

L55N_3

∇

VREF_3

∇

GND

CSO_B

∇

VREF_2

L12N_2

GND

VS2

GCLK12

A B

L60P_3

VCCO_3

∇

VCCAUX

VREF_2

L14N_2

VCCO_2

L15P_2

∇

VCCAUX

L21P_2

INPUT

A C

L60N_3

L64P_3

L64N_3

M1

∇

L08P_2

∇

L14P_2

L15N_2

VREF_2

L23N_2

L21N_2

INPUT

A D

L65P_3

L65N_3

GND

M0

∇

L08N_2

L11P_2

GND

INPUT INPUT

L23P_2

VREF_2

GND

A E

L66P_3

VREF_3

L06P_2

L07P_2

VCCO_2

L10N_2

L11N_2

L18P_2

VS1

D7

VCCO_2

D4

GCLK15

A

F

GND

∇

L06N_2

L07N_2

L10P_2

GND

∇

L18N_2

VS0

D6

GND

D5

GCLK14

Bank 2

XC3SD3400A FPGA

Left Half of Package (Top View)

I/O: Unrestricted, general-purpose user I/O.

314

I/O

INPUT

VCCAUX

I/O

VCCO_3

GND

Spartan-3A DSP FPGA Family: Pinout Descriptions

I/O

VCCO_0

I/O

INPUT

I/O

L32N_0

I/O

VCCINT

GND

I/O

VCCINT

I/O

L28P_0

I/O

L28N_0

I/O

GND

I/O

INPUT

GND

I/O

VCCINT

I/O

L32P_3

I/O

INPUT

I/O

L32N_3

I/O

L02P_2

I/O

L02N_2

I/O

GND

I/O

VCCO_2

INPUT: Unrestricted, general-purpose input pin.

34

I/O

DUAL: Configuration pins, then possible user I/O.

51

VREF: User I/O or input voltage reference for bank.

37

CLK: User I/O, input, or clock buffer input.

32

CONFIG: Dedicated

2

configuration pins.

SUSPEND: Dedicated SUSPEND and

2

dual-purpose AWAKE Power Management pins

100

40

36

24

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 97

JTAG: Dedicated JTAG

port pins.

4

GND: Ground

VCCO: Output voltage

supply for bank.

VCCINT: Internal core supply voltage (+1.2V).

VCCAUX: Auxiliary supply voltage.

Note: The boxes with

question marks inside indicate pin differences from the XC3SD1800A device. Please see the

Footprint Migration Differences section for more

information.

Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Left Half)

I/O

INPUT

I/O

L29N_3

I/O

L33P_3

I/O

L36P_3

I/O

INPUT

I/O

INPUT

I/O

GND

I/O

INPUT

L20N_3

I/O

L33N_3

IRDY2

LHCLK3

I/O

INPUT

L50N_3

I/O

INPUT

L66N_3

VCCAUX

I/O

INPUT

I/O

L34N_3

I/O

INPUT

I/O

GND

I/O

INPUT

I/O

L34P_3

I/O

INPUT

I/O

VCCINT

GND

VCCAUX

I/O

L01P_2

I/O

L01N_2

I/O

L52P_0

I/O

L52N_0

I/O

VCCINT

I/O

GND

VCCAUX

I/O

L35P_3 TRDY2

LHCLK6

I/O

INPUT

I/O

L19P_2

I/O

L19N_2

I/O

VCCINT

I/O

L35N_3

I/O

L43P_3

I/O

GND

INPUT

I/O

L22P_2

I/O

L22N_2

INPUT

I/O

VCCINT

I/O

L17P_2

I/O

L17N_2

I/O

INPUT

I/O

L24N_2

I/O

L24P_2

I/O

L27P_0

I/O

L27N_0

I/O

L25N_2

I/O

L25P_2

I/O

L26N_2

I/O

L26P_2

Spartan-3A DSP FPGA Family: Pinout Descriptions

14 15 16 17 18 19 20 21 22 23 24 25 26

GCLK7

L23N_0

GND

INPUT

L18N_0

L15N_0

L14N_0

GND

L07N_0

∇

TCK GND

A

GCLK6

L23P_0

VCCO_0

L19N_0

L18P_0

L15P_0

VREF_0

L09N_0

VCCO_0

L07P_0

∇

B

GND

L22N_0

L21N_0

L19P_0

L17N_0

GND

L11N_0

L09P_0

L05N_0

L06N_0

GND

A23

A22

C

VREF_0

∇

L22P_0

L21P_0

L17P_0

∇

L11P_0

L10N_0

L05P_0

L06P_0

L61N_1

L61P_1

L60N_1

D

L24P_0

VREF_0

VCCAUX

L13N_0

INPUT

VCCO_0

∇

L10P_0

VCCAUX

TDO

L56P_1

VCCO_1

L60P_1

E

L24N_0

L20P_0

GND

L13P_0

∇

L02N_0

L01N_0

GND

VREF_1

L56N_1

L54N_1

L54P_1

GND

F

INPUT

L16P_0

∇

L08N_0

∇

VREF_0

L01P_0

A25

L58N_1

L51P_1

L51N_1

VREF_1

∇

G

GND

L16N_0

VCCO_0

L08P_0

INPUT

GND

A24

A21

VCCO_1

∇

INPUT

∇

VREF_1

∇

H

GCLK5

INPUT

L12P_0

VREF_0

VCCAUX

L59P_1

L59N_1

A20

L49N_1

L49P_1

GND

A19

A18

J

GCLK4

VCCINT

L12N_0

GND

L57N_1

L57P_1

L53N_1

L50N_1

L46N_1

L46P_1

L40P_1

L41P_1

L41N_1

K

VCCINT GND VCCINT

L55N_1

L55P_1

VCCO_1

L53P_1

GND

L50P_1

L40N_1

A12

VCCO_1

GND

L

GND VCCINT GND VCCINT

L47N_1

L47P_1

A17

L45P_1

L45N_1

A13

VREF_1

A11

A10

M

VCCINT GND VCCINT

A15

A14

RHCLK7

A16

L37N_1

VCCO_1

L36N_1

RHCLK5

L32N_1

L32P_1

N

VCCINT VCCINT GND

VCCAUX

GND

RHCLK1

RHCLK0

L37P_1

RHCLK4

GND

RHCLK2

P

VCCINT GND VCCINT

A7

A6

L22P_1

L22N_1

A2

A3

VREF_1

L28N_1

A8

A9

R

GND VCCINT GND

L17N_1

L17P_1

VCCO_1

L14N_1

GND

VCCAUX

A4

A5

VCCO_1

GND

T

VCCAUX

L35N_2

L42N_2

GND

L12N_1

L12P_1

L10N_1

L14P_1

L21N_1

L23P_1

VREF_1

∇

VREF_1

∇

U

Bank 0

Bank 1

L31P_2

L35P_2

L42P_2

L46N_2

L08P_1

L08N_1

SUSPEN

D

L10P_1

L18N_1

L21P_1

L19P_1

L19N_1

VREF_1

∇

V

GND

L31N_2

VCCO_2

L46P_2

∇

GND

L04P_1

L04N_1

VCCO_1

L18P_1

GND

∇

W

GCLK0

D3

VREF_2

L43N_2

∇

HDC

LDC2

L13P_1

L13N_1

L15P_1

L15N_1

INPUT

∇

Y

GCLK1

INIT_B

GND

L43P_2

L47N_2

∇

VREF_2

GND

L09P_1

L09N_1

L11P_1

L11N_1

GND

A A

VCCO_2

_

L38N_2

∇

L47P_2

VCCO_2

∇

DONE

VCCAUX

L07P_1

VREF_1

VCCO_1

L06N_1

A B

L29N_2

L30P_2

L38P_2

INPUT

∇

L40N_2

L41N_2

L45N_2

2

A0

A1

L05N_1

L06P_1

A C

L29P_2

AWAKE

INPUT

L33N_2

GND

L40P_2

L41P_2

L44N_2

L45P_2

∇

GND

LDC0

L05P_1

A D

GCLK3

DOUT

VCCO_2

L33P_2

D1

L37N_2

L39N_2

L44P_2

VCCO_2

L48N_2

CCLK

L51N_2

LDC1

A E

GCLK2

VREF_2

GND

VREF_2

D2

L37P_2

L39P_2

GND

VREF_2

L48P_2

L51P_2

GND

A F

Bank 2

I/O

L26N_0

I/O

L26P_0

I/O

GND

INPUT

I/O

L20N_0

I/O

GND

I/O

L25N_0

I/O

L25P_0

I/O

L27P_2

L34N_2

I/O

L27N_2

L34P_2

L30N_2

I/O

L32P_2

I/O

L28N_2

L32N_2

I/O

INPUT

L28P_2

DS610 (v3.0) October 4, 2010 www.xilinx.com Product Specification 98

I/O

MOSI

B

CSI

I/O

INPUT

I/O

VCCAUX

I/O

VCCINT

I/O

VCCINT

I/O

INPUT

I/O

L39N_1

L39P_1

I/O

L34P_1 IRDY1

RHCLK6

I/O

L27N_1

L27P_1

I/O

VCCINT

I/O

VCCINT ∇VCCINT

I/O

GND

I/O

L36N_2

I/O

L36P_2

INPUT

Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Right Half)

I/O

GND

I/O

L02P_0

I/O

L34N_1

I/O

GND

I/O

L14P_0

I/O

VCCAUX

I/O

L64P_1

I/O

L42N_1

I/O

L42P_1

I/O

L30N_1

I/O

L01P_1

INPUT

GND

I/O

L64N_1

I/O

L62N_1

I/O

L62P_1

I/O

L30P_1

I/O

L25P_1

I/O

L01N_1

I/O

L58P_1

I/O

L25N_1

I/O

INPUT

GND

I/O

VCCAUX

I/O

INPUT

I/O

L38N_1

INPUT

I/O

L33P_1

INPUT

L28P_1

I/O

L26P_1

I/O

L03P_1

GND

I/O

VCCAUX

GND ∇GND

I/O

L63N_1

I/O

INPUT

I/O

VCCO_1

I/O

L43N_1

INPUT

I/O

L38P_1

INPUT

I/O

L36P_1

L35N_1

I/O

INPUT

L33N_1

I/O

L31N_1 TRDY1

RHCLK3

I/O

INPUT

L29P_1

I/O

L26N_1

I/O

GND

L23N_1

I/O

GND

I/O

L07N_1

I/O

L03N_1

I/O

L02N_1

I/O

L52N_2

I/O

L52P_2

D0

Right Half of FG676 Package (Top View)

INPUT

VREF_1

I/O

L63P_1

I/O

VCCAUX

INPUT

I/O

L43P_1

I/O

L35P_1

INPUT

I/O

L31P_1

I/O

L29N_1

INPUT

VCCAUX

I/O

L02P_1

Spartan-3A DSP FPGA Family: Pinout Descriptions

Footprint Migration Differences

There are multiple migration footprint differences between the XC3SD1800A and the XC3SD3400A in the FG676 package. These migration footprint differences are shown in Ta bl e 7 0 . Migration from the XC3S1400A Spartan-3A device in the FG676 package to a Spartan-3A DSP device in the FG676 package is also possible. The XC3S1800A pin migration differences have been added to Ta bl e 7 0 for designs migrating between these devices.

Tab le 7 0 : FG676 Footprint Migration Differences

FG676

Ball

G16 IP_0 0 IP_0 0 GND GND G16

G18 N.C. N.C. IP_0 0 VCCINT VCCINT G18

F9 N.C. N.C. IP_0 0 VCCAUX VCCAUX F9

F10 IP_0 0 IP_0 0 VCCINT VCCINT F10

F18 N.C. N.C. IP_0 0 VCCINT VCCINT F18

E6 N.C. N.C. IP_0 0 VCCINT VCCINT E6

E9 N.C. N.C. IP_0 0 GND GND E9

E20 IP_0 0 IP_0 0 VCCAUX VCCAUX E20

D5 N.C. N.C. IP_0 0 VCCINT VCCINT D5

D15 IP_0 0 IP_0 0 GND GND D15

D19 IP_0 0 IP_0 0 GND GND D19

C4 IP_0 0 IP_0 0 VCCINT VCCINT C4

B24 N.C. N.C. IP_0 0 GND GND B24

A5 IP_0 0 IP_0 0 GND GND A5

A7 IP_0 0 IP_0 0 VCCO_0 0 A7

A23 IP_0 0 IP_0 0 GND GND A23

A24 N.C. N.C. IP_0 0 VCCAUX VCCAUX A24

Y26 IP_L16N_1 1 IP_L16N_1 1 IP_1 1 Y26

W25 IP_L16P_1 1 IP_L16P_1 1 GND GND W25

W26 IP_L20P_1 1 IP_L20P_1 1 VCCAUX VCCAUX W26

V26 IP_L20N_1/

U25 IP_L24P_1 1 IP_L24P_1 1 GND GND U25

U26 IP_L24N_1/

H23 IP_L48P_1 1 IP_L48P_1 1 VCCAUX VCCAUX H23

H24 IP_L48N_1 1 IP_L48N_1 1 IP_1 1 H24

H25 IP_L44N_1 1 IP_L44N_1 1 VCCO_1 1 H25

H26 IP_L44P_1/

G25 IP_L52N_1/

G26 IP_L52P_1 1 IP_L52P_1 1 VCCAUX VCCAUX G26

B25 IP_L65N_1 1 IP_L65N_1 1 GND GND B25

B26 IP_L65P_1/

XC3S1400A

Spartan-3A Spartan-3A DSP Spartan-3A DSP

Type

VREF_1

XC3S1400A

Bank

1 IP_L20N_1/

1 IP_L24N_1/

1 IP_L44P_1/

1 IP_L52N_1/

1 IP_L65P_1/

XC3SD1800A

Type

VREF_1

XC3SD1800A

Bank

1 IP_1/VREF_1 1 V26

1 IP_1/VREF_1 1 U26

1 IP_1/VREF_1 1 H26

1 IP_1/VREF_1 1 G25

1 IP_1/VREF_1 1 B26

XC3SD3400A

Typ e

XC3SD3400A

Bank

FG676

Ball

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 99

Spartan-3A DSP FPGA Family: Pinout Descriptions

Tab le 7 0 : FG676 Footprint Migration Differences (Cont’d)

FG676

Ball

Y8 N.C. N.C. IP_2 2 VCCINT VCCINT Y8

Y11 IP_2 2 IP_2 2 VCCINT VCCINT Y11

Y18 N.C. N.C. IP_2 2 VCCINT VCCINT Y18

Y19 N.C. N.C. IP_2/VREF_2 2 VCCINT VCCINT Y19

W18 N.C. N.C. IP_2 2 VCCINT VCCINT W18

AF2 IP_2 2 IP_2 2 VCCAUX VCCAUX AF2

AF7 IP_2 2 IP_2 2 VCCO_2 2 AF7

AD5 N.C. N.C. IP_2 2 GND GND AD5

AD23 N.C. N.C. IP_2 2 GND GND AD23

AC5 N.C. N.C. IP_2 2 GND GND AC5

AC7 IP_2 2 IP_2 2 GND GND AC7

AC18 IP_2 2 IP_2 2 GND GND AC18

AB10 IP_2/VREF_2 2 IP_2/VREF_2 2 GND GND AB10

AB17 IP_2 2 IP_2 2 VCCAUX VCCAUX AB17

AB20 IP_2 2 IP_2 2 GND GND AB20

AA8 N.C. N.C. IP_2 2 VCCINT VCCINT AA8

AA19 IP_2 2 IP_2 2 GND GND AA19

AC22N.C.N.C.IO_22IO_22AC22

Y3 IP_L54P_3 3 IP_L54P_3 3 IP_3 3 Y3

Y4 IP_L54N_3 3 IP_L54N_3 3 VCCINT VCCINT Y4

H4 IP_L12N_3/

G1 IP_L16N_3 3 IP_L16N_3 3 IP_3 3 G1

G2 IP_L16P_3 3 IP_L16P_3 3 GND GND G2

G5 IP_L12P_3 3 IP_L12P_3 3 GND GND G5

D1 IP_L08N_3 3 IP_L08N_3 3 VCCAUX VCCAUX D1

D2 IP_L08P_3 3 IP_L08P_3 3 GND GND D2

C1 IP_L04N_3/

C2 IP_L04P_3 3 IP_L04P_3 3 VCCO_3 3 C2

AB3 IP_L62P_3 3 IP_L62P_3 3 GND GND AB3

AB4 IP_L62N_3 3 IP_L62N_3 3 VCCAUX VCCAUX AB4

AA4 IP_L58P_3 3 IP_L58P_3 3 GND GND AA4

AA5 IP_L58N_3/

XC3S1400A

Spartan-3A Spartan-3A DSP Spartan-3A DSP

Type

VREF_3

XC3S1400A

Bank

3 IP_L12N_3/

3 IP_L04N_3/

3 IP_L58N_3/

XC3SD1800A

Type

VREF_3

XC3SD1800A

Bank

3 IP_3/VREF_3 3 H4

3 IP_3/VREF_3 3 C1

3 IP_3/VREF_3 3 AA5

XC3SD3400A

Typ e

XC3SD3400A

Bank

FG676

Ball

Migration Recommendations

There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package. Please note the differences between the two devices from Ta bl e 7 0 and take the necessary precautions.

DS610 (v3.0) October 4, 2010 www.xilinx.com

Product Specification 100

Xilinx DS610 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Introduction and Ordering Information

Introduction

Features

Architectural Overview

Configuration

I/O Capabilities

Package Marking

Ordering Information

Revision History

Notice of Disclaimer

Functional Description

Spartan-3A DSP FPGA Design Documentation

Revision History

Notice of Disclaimer

DC and Switching Characteristics

DC Electrical Characteristics

Absolute Maximum Ratings

Power Supply Specifications

General Recommended Operating Conditions

General DC Characteristics for I/O Pins

Quiescent Current Requirements

Single-Ended I/O Standards

Differential I/O Standards

Differential Input Pairs

Differential Output Pairs

External Termination Requirements for Differential I/O

Device DNA Read Endurance

Switching Characteristics

Software Version Requirements

I/O Timing

Pin-to-Pin Clock-to-Output Times

Pin-to-Pin Setup and Hold Times

Input Setup and Hold Times

Input Propagation Times

Input Timing Adjustments

Output Propagation Times

Three-State Output Propagation Times

Output Timing Adjustments

Timing Measurement Methodology

Using IBIS Models to Simulate Load Conditions in Application

Simultaneously Switching Output Guidelines

Configurable Logic Block (CLB) Timing

Clock Buffer/Multiplexer Switching Characteristics

Block RAM Timing

DSP48A Timing

Digital Clock Manager (DCM) Timing

Spread Spectrum

Delay-Locked Loop (DLL)

Digital Frequency Synthesizer (DFS)

Phase Shifter (PS)

Miscellaneous DCM Timing

DNA Port Timing

Suspend Mode Timing

Configuration and JTAG Timing

General Configuration Power-On/Reconfigure Timing

Configuration Clock (CCLK) Characteristics

Master Serial and Slave Serial Mode Timing

Slave Parallel Mode Timing

Serial Peripheral Interface (SPI) Configuration Timing

Byte Peripheral Interface (BPI) Configuration Timing

IEEE 1149.1/1532 JTAG Test Access Port Timing

Revision History

Pinout Descriptions

Introduction

Pin Types

Package Pins by Type

Package Overview

Mechanical Drawings

Package Thermal Characteristics

CS484: 484-Ball Chip-Scale Ball Grid Array

Pinout Table

User I/Os by Bank

Footprint Migration Differences

CS484 Footprint

FG676: 676-Ball Fine-Pitch Ball Grid Array

XC3SD1800A FPGA