Xilinx Development System User Manual

Development System Reference Guide

8.2i

Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

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IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

Copyright © 1995-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

Development System Reference Guide www.xilinx.com

About This Guide

The Development System Reference Guide contains information about the command line software programs in the Xilinx Development System. Most chapters are organized as follows:

• A brief summary of program functions

• A syntax statement

• A description of the input files used and the output files generated by the program

• A listing of the commands, options, or parameters used by the program

• Examples of how to use the program

For an overview of the Xilinx Development System describing how these programs are used in the design flow, see Chapter 2, “Design Flow”.

Preface

Guide Contents

The Development System Reference Guide provides detailed information about converting, implementing, and verifying designs with the Xilinx command line tools. Check the program chapters for information on what program works with each family of Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). Following is a brief overview of the contents and organization of the Development System Reference Guide:

Note:

• Chapter 1, “Introduction” —This chapter describes some basics that are common to

• Chapter 2, “Design Flow”—This chapter describes the basic design processes: design

• Chapter 3, “Tcl”—Tcl is designed to complement and extend the graphical user

• Chapter 4, “PARTGen”—PARTGen allows you to obtain information about installed

• Chapter 5, “Logical Design Rule Check”—The Logical Design Rule Check (DRC)

• Chapter 6, “NGDBuild”—NGDBuild performs all of the steps necessary to read a

For information on timing constraints, UCF files, and PCF files, see the Constraints Guide.

the different Xilinx Development System modules.

entry, synthesis, implementation, and verification.

interface (GUI). Xilinx Tcl commands provide a batch interface that makes it convenient to execute the exact same script or steps over and over again.

devices and families.

comprises a series of tests run to verify the logical design described by the Native Generic Database (NGD) file.

netlist file in EDIF format and create an NGD (Native Generic Database) file describing the logical design reduced to Xilinx primitives.

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Preface: About This Guide

• Chapter 7, “MAP”—MAP packs the logic defined by an NGD file into FPGA elements

• Chapter 8, “Physical Design Rule Check”—The physical Design Rule Check (DRC)

• Chapter 9, “PAR”—PAR places and routes FPGA designs.

• Chapter 10, “XPower”—XPower is a power and thermal analysis tool that generates

• Chapter 11, “PIN2UCF,”—PIN2UCF generates pin-locking constraints in a UCF file

• Chapter 12, “TRACE”—Timing Reporter and Circuit Evaluator (TRACE) performs

• Chapter 13, “Speedprint”— Speedprint lists block delays for a specified device and its

• Chapter 14, “BitGen”—BitGen creates a configuration bitstream for an FPGA design.

• Chapter 15, “BSDLAnno”—BSDLAnno automatically modifies a BSDL file for post-

• Chapter 16, “PROMGen” —PROMGen converts a configuration bitstream (BIT) file

• Chapter 17, “IBISWriter”—IBISWriter creates a list of pins used by the design, the

• Chapter 18, “CPLDfit” —CPLDfit reads in an NGD file and fits the design into the

• Chapter 19, “TSIM” — TSIM formats an implemented CPLD design (VM6) into a

• Chapter 20, “TAEngine” —TAEngine performs static timing analysis on a successfully

• Chapter 21, “Hprep6” —Hprep6 takes an implemented CPLD design (VM6) from

• Chapter 22, “NetGen”—NetGen reads in applicable Xilinx implementation files,

• Chapter 23, “XFLOW”—XFLOW automates the running of Xilinx implementation

• Chapter 24, “Data2MEM”—Data2MEM transforms CPU execution code, or pure data,

• “Appendix A”—This appendix gives an alphabetic listing of the files used by the

• “Appendix B” —This appendix describes the netlist reader, EDIF2NGD, and how it

such as CLBs, IOBs, and TBUFs.

comprises a series of tests run to discover physical errors in your design.

power and thermal estimates after the PAR or CPLDfit stage of the design.

by reading a a placed NCD file for FPGAs or GYD file for CPLDs.

static timing analysis of a physical design based on input timing constraints.

speed grades.

configuration interconnect testing.

into a file that can be downloaded to a PROM. PROMGen also combines multiple BIT files for use in a daisy chain of FPGA devices.

signals inside the device that connect those pins, and the IBIS buffer model that applies to the IOB connected to the pins.

selected CPLD architecture.

format usable by the NetGen timing simulation flow, which produces a backannotated timing file for simulation.

implemented Xilinx CPLD design (VM6).

CPLDfit and generates a JEDEC (JED) programming file.

extracts design data, and generates netlists that are used with supported third-party simulation, equivalence checking, and static timing analysis tools.

and simulation flows.

into Block RAM initialization records.

Xilinx Development System.

interacts with NGDBuild.

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Additional Resources

To find additional documentation, see the Xilinx website at:

Additional Resources

Conventions

Typographical

http://www.xilinx.com/literature

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support

This document uses the following conventions. An example illustrates each convention.

The following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier font Messages, prompts, and

program files that the system displays

Courier bold Literal commands that you

enter in a syntactical statement

Helvetica bold Commands that you select

from a menu

speed grade: - 100

ngdbuild design_name

File → Open

Keyboard shortcuts Ctrl+C

Italic font Variables in a syntax

statement for which you must supply values

References to other manuals See the Development System

Emphasis in text If a wire is drawn so that it

Square brackets [ ] An optional entry or

parameter. However, in bus specifications, such as bus[7:0], they are required.

Braces { } A list of items from which you

must choose one or more

Vertical bar | Separates items in a list of

choices

ngdbuild design_name

Reference Guide for more

information.

overlaps the pin of a symbol, the two nets are not connected.

ngdbuild [ option_name] design_name

lowpwr ={on|off}

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Preface: About This Guide

Convention Meaning or Use Example

Vertical ellipsis

. . .

Horizontal ellipsis . . . Repetitive material that has

Online Document

The following conventions are used in this document:

Convention Meaning or Use Example

Blue text Cross-reference link to a

Red text Cross-reference link to a

Blue, underlined text

Repetitive material that has been omitted

IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’

. . .

allow block block_name

been omitted

loc1 loc2 ... locn;

See the section “Additional location in the current file or in another file in the current document

Resources” for details.

Refer to “Title Formats” in

Chapter 1 for details.

See Figure 2-5 in the Virtex-II location in another document

Handbook.

Hyperlink to a website (URL) Go to http://www.xilinx.com

for the latest speed files.

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Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: Introduction

Command Line Program Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

–h (Help) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Invoking Command Line Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 2: Design Flow

Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Design Entry and Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Schematic Entry Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Library Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CORE Generator Tool (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HDL Entry and Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mapping Constraints (FPGAs Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Block Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Netlist Translation Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Mapping (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Placing and Routing (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Bitstream Generation (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Back-Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

NetGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Schematic-Based Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

HDL-Based Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Static Timing Analysis (FPGAs Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

In-Circuit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Design Rule Checker (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Xilinx Design Download Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Probe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

ChipScope ILA and ChipScope PRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

FPGA Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Design Size and Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Global Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Data Feedback and Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Other Synchronous Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 3: Tcl

Tcl Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Xilinx Tcl Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Accessing Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Tcl Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Xilinx Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Xilinx Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Tcl Commands for General Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

partition (support design preservation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

delete (delete a partition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

get (get partition properties). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

new (create a new partition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

properties (list available partition properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

rerun (force partition synthesis and implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . 61

set (set partition preserve property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

process (run and manage project processes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

run (run process task) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

project (create and manage projects). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

clean (remove system-generated project files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

close (close the ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

get (get project properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

get_processes (get project processes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

new (create a new ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

open (open an ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

properties (list project properties). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

set (set project properties, values, and options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

set device (set device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

set family (set device family) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

set package (set device package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

set speed (set device speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

set top (set the top-level module/entity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

timing_analysis (generate timing analysis reports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

delete (delete timing analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

disable_constraints (disable timing constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

disable_cpt (disable components for path tracing control) . . . . . . . . . . . . . . . . . . . . . . . 71

enable_constraints (enable constraints for analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

enable_cpt (enable components for path tracing control) . . . . . . . . . . . . . . . . . . . . . . . . 72

get (get analysis property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

new (new timing analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

reset (reset path filters and constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

run (run analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

saveas (save analysis report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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set (set analysis properties). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

set_constraint (set constraint for custom analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

set_endpoints (set source and destination endpoints) . . . . . . . . . . . . . . . . . . . . . . . . . . 78

set_filter (set filter for analysis). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

set_query (set up net or timegroup report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

show_settings (generate settings report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

xfile (manage project files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

add (add file to project). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

get (get project file properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

remove (remove file from project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Tcl Commands for Advanced Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

collection (create and manage a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

append_to (add objects to a collection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

copy (copy a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

equal (compare two collections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

foreach (iterate over elements in a collection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

get (get collection property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

index (extract a collection object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

properties (list available collection properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

remove_from (remove objects from a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

set (set the property for all collections). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

sizeof (show the number of objects in a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

object (get object information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

get (get object properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

name (name of the object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

properties (list object properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

type (type of object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

search (search and return matching objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Project Properties and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Example Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Sample Tcl Script for General Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Sample Tcl Script for Advanced Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Chapter 4: PARTGen

PARTGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PARTGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PARTGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PARTGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PARTGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

–arch (Print Information for Specified Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . 102

–i (Print a List of Devices, Packages, and Speeds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–p (Creates Package file and Partlist Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–nopkgfile (No Package File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–v (Creates Package and Partlist Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Partlist File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Device Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

PKG File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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Chapter 5: Logical Design Rule Check

Logical DRC Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Logical DRC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Block Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Net Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Pad Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Clock Buffer Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Name Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Primitive Pin Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 6: NGDBuild

NGDBuild Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Converting a Netlist to an NGD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

NGDBuild Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

NGDBuild Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

NGDBuild Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

NGDBuild Intermediate Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

NGDBuild Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

–a (Add PADs to Top-Level Port Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

–aul (Allow Unmatched LOCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

–bm (Specify BMM Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

–dd (Destination Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

–i (Ignore UCF File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

–insert_keep_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

–l (Libraries to Search) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

–modular assemble (Module Assembly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

–modular initial (Initial Budgeting of Modular Design) . . . . . . . . . . . . . . . . . . . . . . . 124

–modular module (Active Module Implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . 125

–nt (Netlist Translation Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

–r (Ignore LOC Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

–sd (Search Specified Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

–u (Allow Unexpanded Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

–uc (User Constraints File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

–ur (Read User Rules File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

–verbose (Report All Messages). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Chapter 7: MAP

MAP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

MAP Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

MAP Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

MAP Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

MAP Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

–bp (Map Slice Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

–c (Pack CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

–cm (Cover Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

–detail (Write Out Detailed MAP Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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–equivalent_register_removal (Remove Redundant Registers) . . . . . . . . . . . . . . . . . 134

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

–gf (Guide NCD File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

–global_opt (Global Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

–gm (Guide Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

–gm incremental (Guide Mode incremental) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

–ignore_keep_hierarchy (Ignore KEEP_HIERARCHY Properties) . . . . . . . . . . . . . . 136

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

–ir (Do Not Use RLOCs to Generate RPMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

–ise (ISE Project File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

–k (Map to Input Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

–l (No logic replication). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

–o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

–ol (Overall Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

–pr (Pack Registers in I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

–r (No Register Ordering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

–register_duplication (Duplicate Registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

–retiming (Register Retiming During Global Optimization). . . . . . . . . . . . . . . . . . . . 139

–t (Start Placer Cost Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

–timing (Timing-Driven Packing and Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

–tx (Transform Buses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

–u (Do Not Remove Unused Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

–xe (Extra Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

MAP Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Register Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Guided Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Simulating Map Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

MAP Report (MRP) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Halting MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Chapter 8: Physical Design Rule Check

DRC Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

DRC Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Input File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–e (Error Report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–o (Output file) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–s (Summary Report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–v (Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–z (Report Incomplete Programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DRC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DRC Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Chapter 9: PAR

Place and Route Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

PAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Placing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Timing-driven PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Command Line Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Guided PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

PCI Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

PAR Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Detailed Listing of Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–gf (Guide NCD File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–gm (Guide Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–k (Re-Entrant Routing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–m (Multi-Tasking Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–n (Number of PAR Iterations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–nopad (No Pad). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–ol (Overall Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–p (No Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–pl (Placer Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–power (Power Aware PAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–r (No Routing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–rl (Router Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–s (Number of Results to Save) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–t (Starting Placer Cost Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–ub (Use Bonded I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–x (Performance Evaluation Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

–xe (Extra Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

PAR Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Place and Route Report File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Multi Pass Place and Route (MPPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Select I/O Utilization and Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Importing the PAD File Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Guide Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Xplorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Best Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Timing Closure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Xplorer Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Xplorer Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

ReportGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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Turns Engine (PAR Multi-Tasking Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Turns Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Turns Engine Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Turns Engine Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Turns Engine Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Turns Engine Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Screen Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Halting PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 10: XPower

XPower Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Files Used by XPower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XPower Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

FPGA Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

CPLD Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Using XPower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

VCD Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Other Methods of Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

-l (Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

-ls (List Supported Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

-o (Rename Power Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

-s (Specify VCD file). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

-tb (Turn On Time Based Reporting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

-v (Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

-wx (Write XML File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

-x (Specify Settings (XML) Input File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Command Line Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Power Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Standard Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Detailed Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Advanced Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Chapter 11: PIN2UCF

PIN2UCF Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

PIN2UCF Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

–o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

–r (Write to a Report File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

PIN2UCF Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

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Chapter 12: TRACE

TRACE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

TRACE Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

TRACE Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Input files to TRACE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

TRACE Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

TRACE Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

–a (Advanced Analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

–e (Generate an Error Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

–fastpaths (Report Fastest Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

–ise (ISE Project File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

–l (Limit Timing Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

–nodatasheet (No Data Sheet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

–o (Output Timing Report File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

–run (Run Timing Analyzer Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

–s (Change Speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

–skew (Analyze Clock Skew for All Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

–stamp (Generates STAMP timing model files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

–u (Report Uncovered Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

–v (Generate a Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

–xml (XML Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

TRACE Command Line Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

TRACE Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

Timing Verification with TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Net Delay Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Net Skew Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Path Delay Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Clock Skew and Setup Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Reporting with TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Data Sheet Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

Report Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Guaranteed Setup and Hold Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Setup Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Summary Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Summary Report (Without a Physical Constraints File Specified) . . . . . . . . . . . . . . . . 231

Error Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Verbose Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

OFFSET Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

OFFSET IN Constraint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

OFFSET IN Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

OFFSET IN Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

OFFSET IN Detailed Path Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

OFFSET IN Detail Path Clock Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

OFFSET In with Phase Shifted Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

OFFSET OUT Constraint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

OFFSET OUT Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

OFFSET OUT Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

OFFSET OUT Detail Clock Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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OFFSET OUT Detail Path Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PERIOD Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PERIOD Constraints Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PERIOD Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PERIOD Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PERIOD Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

PERIOD Constraint with PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Halting TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Chapter 13: Speedprint

Speedprint Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Speedprint Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Speedprint Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–min (Display Minimum Speed Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–s (Speed Grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–t (Specify Temperature). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–v (Specify Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Speedprint Example Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Speedprint Example Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 14: BitGen

BitGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

BitGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

BitGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

BitGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

BitGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

–b (Create Rawbits File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

–bd (Update Block Rams) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–d (Do Not Run DRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–g (Set Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–g (Set Configuration—Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3/-3E) . . . . 261

ActivateGCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

ActiveReconfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

CclkPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Compress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

ConfigRate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

DCIUpdateMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DCMShutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DebugBitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DisableBandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DONE_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DonePin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DonePipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DriveDone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Encrypt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

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Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

GSR_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

GWE_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

GTS_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

HswapenPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Key0, Key1, Key2, Key3, Key4, Key5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

KeyFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5. . . . . . . . . . . . . . . . . . . . . . . 268

LCK_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

M0Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

M1Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

M2Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Match_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

PartialGCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

PartialMask0, PartialMask1, PartialMask2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

PartialLeft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

PartialRight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Persist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

PowerdownPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

ProgPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

ReadBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

SEURepair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

StartCBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

StartKey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

StartupClk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

TckPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

TdiPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

TdoPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

TmsPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

UnusedPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

UserID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

–j (No BIT File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

–l (Create a Logic Allocation File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

–m (Generate a Mask File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

–r (Create a Partial Bit File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

–w (Overwrite Existing Output File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Chapter 15: BSDLAnno

BSDLAnno Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

BSDLAnno Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

–s (Specify BSDL file). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

BSDLAnno File Composition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Entity Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Generic Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Logical Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Package Pin-Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

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USE Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Scan Port Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

TAP Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

Boundary Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Modifications to the DESIGN_WARNING Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Header Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Boundary Scan Behavior in Xilinx Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Chapter 16: PROMGen

PROMGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PROMGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PROMGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PROMGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PROMGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–b (Disable Bit Swapping—HEX Format Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–c (Checksum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–d (Load Downward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–i (Select Initial Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–l (Disable Length Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–n (Add BIT FIles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

–o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

–p (PROM Format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

–r (Load PROM File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

–s (PROM Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–t (Template File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–u (Load Upward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–ver (Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–w (Overwrite Existing Output File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–x (Specify Xilinx PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

–z (Enable Compression) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Bit Swapping in PROM Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

PROMGen Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Chapter 17: IBISWriter

IBISWriter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

IBISWriter Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

IBISWriter Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

IBISWriter Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

IBISWriter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

–allmodels (Include all available buffer models for this architecture). . . . . . . . . . . . 295

–g (Set Reference Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

–ml (Multilingual Support). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

–pin (Generate Package Parasitics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

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Chapter 18: CPLDfit

CPLDfit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

CPLDfit Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

CPLDfit Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

CPLDfit Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

CPLDfit Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–blkfanin (Specify Maximum Fanin for Function Blocks) . . . . . . . . . . . . . . . . . . . . . . 301

–exhaust (Enable Exhaustive Fitting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–ignoredatagate (Ignore DATA_GATE Attributes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–ignoretspec (Ignore Timing Specifications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–init (Set Power Up Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–inputs (Number of Inputs to Use During Optimization) . . . . . . . . . . . . . . . . . . . . . . 302

–iostd (Specify I/O Standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

–keepio (Prevent Optimization of Unused Inputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

–loc (Keep Specified Location Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

–localfbk (Use Local Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

–log (Specify Log File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

–nofbnand (Disable Use of Foldback NANDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–nogclkopt (Disable Global Clock Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–nogsropt (Disable Global Set/Reset Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–nogtsopt (Disable Global Output-Enable Optimization) . . . . . . . . . . . . . . . . . . . . . . 303

–noisp (Turn Off Reserving ISP Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–nom1opt (Disable Multi-level Logic Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–nouim (Disable FASTConnect/UIM Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–ofmt (Specify Output Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

–optimize (Optimize Logic for Density or Speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

–p (Specify Xilinx Part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

–pinfbk (Use Pin Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

–power (Set Power Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

–pterms (Number of Pterms to Use During Optimization) . . . . . . . . . . . . . . . . . . . . . 304

–slew (Set Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

–terminate (Set to Termination Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

–unused (Set Termination Mode of Unused I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

–wysiwyg (Do Not Perform Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Chapter 19: TSIM

TSIM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

TSIM Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

TSIM Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

TSIM Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Chapter 20: TAEngine

TAEngine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

TAEngine Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

TAEngine Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

TAEngine Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

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TAEngine Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

–detail (Detail Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

–iopath (Trace Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

–l (Specify Output Filename) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Chapter 21: Hprep6

Hprep6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Hprep6 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Hprep6 Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Hprep6 Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

Hprep6 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

–autosig (Automatically Generate Signature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

–n (Specify Signature Value for Readback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

–nopullup (Disable Pullups) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

–s (Produce ISC File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

–tmv (Specify Test Vector File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Chapter 22: NetGen

NetGen Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

NetGen Supported Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

NetGen Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

NetGen Functional Simulation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Notes on Functional Simulation for UNISIM-based Netlists . . . . . . . . . . . . . . . . . . . . 320

Syntax for NetGen Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Output files for NetGen Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

NetGen Timing Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

Syntax for NetGen Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

FPGA Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Output files for FPGA Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Input files for CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Output files for CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Options for NetGen Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–gp (Bring Out Global Reset Net as Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–insert_pp_buffers (Insert Path Pulse Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

–mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

–module (Simulation of Active Module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

–ofmt (Output Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

–pcf (PCF File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

–s (Change Speed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

–sim (Generate Simulation Netlist). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

–tb (Generate Testbench Template File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

–ti (Top Instance Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

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–tp (Bring Out Global 3-State Net as Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

Verilog-Specific Options for Functional and Timing Simulation . . . . . . . . . . . . . . . . 326

–insert_glbl (Insert glbl.v Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–ism (Include SimPrim Modules in Verilog File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–pf (Generate PIN File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–sdf_anno (Include $sdf_annotate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–sdf_path (Full Path to SDF File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–shm (Write $shm Statements in Test Fixture File). . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–ul (Write uselib Directive). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–vcd (Write $dump Statements In Test Fixture File). . . . . . . . . . . . . . . . . . . . . . . . . . . 328

VHDL-Specific Options for Functional and Timing Simulation. . . . . . . . . . . . . . . . . 328

–a (Architecture Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–ar (Rename Architecture Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–rpw (Specify the Pulse Width for ROC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–tpw (Specify the Pulse Width for TOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–xon (Select Output Behavior for Timing Violations) . . . . . . . . . . . . . . . . . . . . . . . . . . 329

NetGen Equivalence Checking Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Syntax for NetGen Equivalence Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Input files for NetGen Equivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

Output files for NetGen Equivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Options for NetGen Equivalence Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–ecn (Equivalence Checking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

–mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

–module (Verification of Active Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

–ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

–ngm (Design Correlation File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

–tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

–w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

NetGen Static Timing Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

Input files for Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Output files for Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Syntax for NetGen Static Timing Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Options for NetGen Static Timing Analysis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–module (Simulation of Active Module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

–ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

–pcf (PCF File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

–s (Change Speed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

–sta (Generate Static Timing Analysis Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

–tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

–w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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Preserving and Writing Hierarchy Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Testbench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Hierarchy Information File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Dedicated Global Signals in Back-Annotation Simulation . . . . . . . . . . . . . . . . . . 338

Global Signals in Verilog Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Global Signals in VHDL Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Chapter 23: XFLOW

XFLOW Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

XFLOW Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

XFLOW Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

XFLOW Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

XFLOW Flow Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

–assemble (Module Assembly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

–config (Create a BIT File for FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

–ecn (Create a File for Equivalence Checking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

–fit (Fit a CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

–fsim (Create a File for Functional Simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

–implement (Implement an FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

–initial (Initial Budgeting of Modular Design) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

–module (Active Module Implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

–mppr (Multi-Pass Place and Route for FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

–sta (Create a File for Static Timing Analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

–synth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Synthesis Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Option Files for -synth Flow Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

–tsim (Create a File for Timing Simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

Flow Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

Flow File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

User Command Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

XFLOW Option Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

Option File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

XFLOW Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–active (Active Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–ed (Copy Files to Export Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–f (Execute Commands File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–g (Specify a Global Variable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–log (Specify Log File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

–norun (Creates a Script File Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

–o (Change Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

–pd (PIMs Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

–rd (Copy Report Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

–wd (Specify a Working Directory). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Running XFLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Using XFLOW Flow Types in Combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Running “Smart Flow” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Using the SCR, BAT, or TCL File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

Using the XIL_XFLOW_PATH Environment Variable . . . . . . . . . . . . . . . . . . . . . . . . 365

Development System Reference Guide www.xilinx.com 21

Chapter 24: Data2MEM

Data2MEM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

Data2MEM Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Data2MEM Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Block RAM Memory Map (.bmm) files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Executable and Linkable Format (.elf) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

Debugging Information Format DWARF (.drf) files . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Memory (.mem) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Memory (.mem) Files as Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Bit (.bit) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Verilog (.v) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

VHDL (.vhd) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

UCF (.ucf) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

Data2MEM Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

A: Xilinx Development System Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

B: EDIF2NGD, and NGDBuild

EDIF2NGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

EDIF2NGD Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–a (Add PADs to Top-Level Port Signals). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–aul (Allow Unmatched LOCs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–l (Libraries to Search) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

–r (Ignore LOC Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

NGDBuild . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Converting a Netlist to an NGD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Bus Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Netlist Launcher (Netlister) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Netlist Launcher Rules Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules and System Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Value Types in Key Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

System Rules File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Rules File Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Example 1: EDF_RULE System Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Example 2: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Example 3: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Example 4: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

NGDBuild File Names and Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

22 www.xilinx.com Development System Reference Guide

Introduction

This chapter describes the command line programs for the Xilinx development system. The chapter contains the following sections:

• “Command Line Program Overview”

• “Command Line Syntax”

• “Command Line Options”

• “Invoking Command Line Programs”

Command Line Program Overview

Chapter 1

Xilinx command line programs allow you to implement and verify your design. The following table lists the programs you can use for each step in the design flow. For detailed information, see Chapter 2, “Design Flow”.

Table 1-1: Command Line Programs in the Design Flow

Design Flow Step Command Line Program

Design Implementation NGDBuild, MAP, PAR, Xplorer,

BitGen

Design Preservation TCL

Timing Simulation and Back Annotation

(Design Verification)

Static Timing Analysis

(Design Verification)

You can run these programs in the standard design flow or use special options to run the programs for design preservation. Each command line program has multiple options, which allow you to control how a program executes. For example, you can set options to change output file names, to set a part number for your design, or to specify files to read in when executing the program. You can also use options to create guide files and run guide mode to maintain the performance of a previously implemented design.

NetGen

TRACE

Some of the command line programs described in this manual underlie many of the Xilinx Graphical User Interfaces (GUIs). The GUIs can be used in conjunction with the command line programs or alone. For information on the GUIs, see the online Help provided with each Xilinx tool.

Development System Reference Guide www.xilinx.com 23

Chapter 1: Introduction

Command Line Syntax

Command line syntax always begins with the command line program name. The program name is followed by any options and then file names. Use the following rules when specifying command line options:

• Enter options in any order.

• Precede options with a hyphen (-) and separate them with spaces.

• Be consistent with upper case and lower case.

• When an option requires a parameter, separate the parameter from the option by

spaces or tabs. For example, the following shows the command line syntax for running PAR with the effort level set to medium:

♦ Correct: par -ol med

♦ Incorrect: par -ol med

• When using options that can be specified multiple times, precede the parameter with

the option letter. In this example, the -l option shows the list of libraries to search:

♦ Correct: -l xilinxun -l synopsys

♦ Incorrect: -l xilinxun synopsys

• Enter parameters that are bound to an option after the option.

♦ Correct: -f command_file

♦ Incorrect: command_file -f

Use the following rules when specifying file names:

• Enter file names in the order specified in the chapter that describes the command line program. In this example the correct order is program, input file, output file, and then physical constraints file.

♦ Correct: par input.ncd output.ncd freq.pcf

♦ Incorrect: par input.ncd freq.pcf output.ncd

• Use lower case for all file extensions (for example, .ncd).

Command Line Options

The following options are common to many of the command line programs in the Xilinx Development System.

–f (Execute Commands File)

For any Xilinx Development System program, you can store command line program options and file names in a command file. You can then execute the arguments by entering the program name with the –f option followed by the name of the command file. This is useful if you frequently execute the same arguments each time you execute a program or if the command line command becomes too long.

You can use the file in the following ways:

• To supply all the command options and file names for the program, as in the following example:

par -f

command_file

command_file is the name of the file that contains the command options and file names.

24 www.xilinx.com Development System Reference Guide

Command Line Options

• To insert certain command options and file names within the command line, as in the following example:

par -f placeoptions -s 4 -f routeoptions design_i.ncd design_o.ncd

placeoptions is the name of a file containing placement command parameters.

routeoptions is the name of a file containing routing command parameters.

You create the command file in ASCII format. Use the following rules when creating the command file:

• Separate program options and file names with spaces.

• Precede comments with the pound sign (#).

• Put new lines or tabs anywhere white space is allowed on the UNIX or DOS

command line.

• Put all arguments on the same line, one argument per line, or a combination of these.

• All carriage returns and other non-printable characters are treated as spaces and

ignored.

• No line length limitation exists within the file.

Following is an example of a command file:

–h (Help)

#command line options for par for design mine.ncd

-n 10

-w 0l 5

-s 2 #will save the two best results /home/yourname/designs/xilinx/mine.ncd #directory for output designs /home/yourname/designs/xilinx/output.dir #use timing constraints file /home/yourname/designs/xilinx/mine.pcf

When you enter a program name followed by –help or –h, a message displays that lists all the available options and their parameters as well as the file types for use with the program. The message also explains each of the options.

Following are descriptions for the symbols used in the help message:

Symbol Description

[ ] Encloses items that are optional.

{ } Encloses items that may be repeated.

< > Encloses a variable name or number for which you

must substitute information.

, Shows a range for an integer variable.

– Shows the start of an option name.

: Binds a variable name to a range.

Development System Reference Guide www.xilinx.com 25

Chapter 1: Introduction

Symbol Description

| Logical OR to show a choice of one out of many items.

The OR operator may only separate logical groups or literal keywords.

( ) Encloses a logical grouping for a choice between

subformats.

Following are examples of syntax used for file names:

• <infile[.ncd]> shows that typing the .ncd extension is optional but that the extension must be .ncd.

• <infile<.edn>> shows that the .edn extension is optional and is appended only if there is no other extension in the file name.

For architecture-specific programs, such as BitGen, you can enter the following to get a verbose help message for the specified architecture:

program_name

–h architecture_name

You can redirect the help message to a file to read later or to print out by entering the following:

program_name

–h > filename

On the UNIX command line, enter the following to redirect the help message to a file and return to the command prompt.

program_name –h > & filename

–intstyle (Integration Style)

You can limit screen output, based on the integration style that you are running, to warning and error messages only. When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent. The mode sets the way information is displayed in the following ways:

–intstyle {ise | xflow | silent}

–intstyle ise

This mode indicates the program is being run as part of an integrated design environment.

–intstyle xflow

This mode indicates the program is being run as part of an integrated batch flow.

–intstyle silent

This mode limits screen output to warning and error messages only.

Note:

as Project Navigator or XFLOW.

26 www.xilinx.com Development System Reference Guide

The -intstyle option is automatically invoked when running in an integrated environment, such

–p (Part Number)

You can use the –p option with the EDIF2NGD, NGDBuild, MAP, and XFLOW programs to specify the part into which your design will be implemented. You can specify a part number at the following different points in the design flow:

• In the input netlist (does not require the –p option)

• In a Netlist Constraints File (NCF) (does not require the –p option)

• With the –p option when you run a netlist reader (EDIF2NGD) User Constraints File

(UCF) (does not require the –p option)

• With the –p option when you run NGDBuild

By the time you run NGDBuild, you must have already specified a device architecture.

• With the –p option when you run MAP

When you run MAP, an architecture, device, and package must be specified, either on the MAP command line or earlier in the design flow. If you do not specify a speed, MAP selects a default speed. You can only run MAP using a part number from the architecture you specified when you ran NGDBuild.

Command Line Options

Note:

an earlier step. For example, a part specified when you run MAP overrides a part specified in the input netlist.

Part numbers specified in a later step of the design flow override a part number specified in

A complete Xilinx part number consists of the following elements:

• Architecture (for example, Spartan-3e)

• Device (for example, xc3s100e)

• Package (for example, vq100)

• Speed (for example, -4)

Note:

to specify a speed grade. If you do not specify a speed grade, Speedprint reports the default speed grade for the device you are targeting. See “–s (Speed Grade)” in Chapter 13 for details.

The Speedprint program lists block delays for device speed grades. The -s option allows you

The following table lists multiple ways to specify a part on the command line.

Table 1-2: Part Number Examples

Specification Examples

Architecture only virtex

virtex2

virtex2p

virtex4

spartan2

spartan2e

spartan 3

spartan 3e

xc9500

xpla3

Device only xc4vfx12

xc3s100e

Development System Reference Guide www.xilinx.com 27

Chapter 1: Introduction

Table 1-2: Part Number Examples

Specification Examples

DevicePackage xc4fx12sf363

xc3s100evq100

Device–Package xc4vfx12-sf363

xc3s100e-vq100

DeviceSpeed–Package xc4vfx1210-sf363

xc3s100e4-vq100

DevicePackage–Speed xc4fx12sf363-10

xc3s100evq100-4

Device–Speed–Package xc4vfx12-10-sf363

xc3s100e-4-vq100

Device–SpeedPackage xc4vfx12-10sf363

xc3s100e-4vq100

Invoking Command Line Programs

You start Xilinx Development System command line programs by entering a command at the UNIX appropriate syntax

Xilinx also offers the XFLOW program, which allows you to automate the running of several programs at one time. See Chapter 23, “XFLOW” for more information.

™

or DOS™ command line. See the program-specific chapters in this book for the

28 www.xilinx.com Development System Reference Guide

Design Flow

This chapter describes the process for creating, implementing, verifying, and downloading designs for FPGA and CPLD devices. For a complete description of FPGAs and CPLDs, refer to the Xilinx Data Sheets at

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

This chapter contains the following sections:

• “Design Flow Overview”

• “Design Entry and Synthesis”

• “Design Implementation”

• “Design Verification”

• “FPGA Design Tips”

Chapter 2

Design Flow Overview

The standard design flow comprises the following steps:

1. Design Entry and Synthesis—In this step of the design flow, you create your design using a Xilinx-supported schematic editor, a hardware description language (HDL) for text-based entry, or both. If you use an HDL for text-based entry, you must synthesize the HDL file into an EDIF file or, if you are using the Xilinx Synthesis Technology (XST) GUI, you must synthesize the HDL file into an NGC file.

2. Design Implementation—By implementing to a specific Xilinx architecture, you convert the logical design file format, such as EDIF, that you created in the design entry and synthesis stage into a physical file format. The physical information is contained in the native circuit description (NCD) file for FPGAs and the VM6 file for CPLDs. Then you create a bitstream file from these files and optionally program a PROM or EPROM for subsequent programming of your Xilinx device.

3. Design Verification—Using a gate-level simulator or cable, you ensure that your design meets your timing requirements and functions properly. See the iMPACT online help for information about Xilinx download cables and demonstration boards.

The full design flow is an iterative process of entering, implementing, and verifying your design until it is correct and complete. The Xilinx Development System allows quick design iterations through the design flow cycle. Because Xilinx devices permit unlimited reprogramming, you do not need to discard devices when debugging your design in circuit.

Development System Reference Guide www.xilinx.com 29

Chapter 2: Design Flow

The following figure shows the standard Xilinx design flow.

Design

Entry

Design

Synthesis

Design

Implementation

Optimization

FPGAs

Mapping Placement Routing

CPLDs

Fitting

Bitstream

Generation

Back

Annotation

Design Verification

Functional Simulation

Static Timing

Analysis

Timing

Simulation

Download to a

Xilinx Device

Figure 2-1: Xilinx Design Flow

In-Circuit

Verification

X9537

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Design Flow Overview

The following figure shows the Xilinx software flow chart for FPGA designs.

Floorplanner

CORE Generator

NGC

UCF

Constraints Editor

Symbol

Schematic

Libraries

Schematic Capture

EDIF 2 0 0 &

Constraints/NCF

TRACE &

Timing Analyzer

NGDBuild NGDBuildNGDBuild

NGD

MAP

NCD & PCF

PAR

NCD

Synthesis

Libraries

Synthesis Simulation

NGC

(XST Netlist)

NGM & PCF

HDL

V &

SDF 2.1

Simulation

Libraries

VHD &

SDF 2.1

NetGen

Testbench

Stimulus

EDIF 2 0 0

BitGen

BIT

PROMGen

iMPACT

Figure 2-2: Xilinx Software Design Flow (FPGAs)

X10293

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Chapter 2: Design Flow

The following figure shows the Xilinx software flow chart for CPLD designs.

CORE Generator

Symbol

NGC

Schematic

Libraries

Schematic Capture

EDIF 2 0 0 &

Constraints/NCF

GYD

HDL

NGDBuild NGDBuildNGDBuild

NGD

CPLD Fitter

JED VM6

iMPACT Timing Analyzer

Synthesis

Libraries

Synthesis Simulation

NGC

(XST Netlist)

Figure 2-3: Xilinx Software Design Flow (CPLDs)

V &

SDF 2.1

Simulation

Libraries

VHD &

SDF 2.1

NetGen

Testbench

Stimulus

EDIF 2 0 0

X10294

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Design Entry and Synthesis

You can enter a design with a schematic editor or a text-based tool. Design entry begins with a design concept, expressed as a drawing or functional description. From the original design, a netlist is created, then synthesized and translated into a native generic object (NGO) file. This file is fed into the Xilinx software program called NGDBuild, which produces a logical native generic database (NGD) file.

The following figure shows the design entry and synthesis process.

CORE Generator

Design Entry and Synthesis

Schematic

Libraries

Schematic Capture

UCF

Hierarchical Design

Design hierarchy is important in both schematic and HDL entry for the following reasons:

• Helps you conceptualize your design

• Adds structure to your design

• Promotes easier design debugging

• Makes it easier to combine different design entry methods (schematic, HDL, or state

editor) for different parts of your design

• Makes it easier to design incrementally, which consists of designing, implementing, and verifying individual parts of a design in stages

• Reduces optimization time

• Facilitates concurrent design, which is the process of dividing a design among a

number of people who develop different parts of the design in parallel.

EDIF 2 0 0 &

Constraints/NCF

NGDBuild

Figure 2-4: Design Entry Flow

Synthesis

Libraries

Synthesis

NGC

(XST Netlist)

HDL

X10295

Development System Reference Guide www.xilinx.com 33

Chapter 2: Design Flow

Schematic Entry Overview

In hierarchical designing, a specific hierarchical name identifies each library element, unique block, and instance you create. The following example shows a hierarchical name with a 2-input OR gate in the first instance of a multiplexer in a 4-bit counter:

/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2

Xilinx strongly recommends that you name the components and nets in your design. These names are preserved and used by the FPGA Editor tool. These names are also used for back-annotation and appear in the debug and analysis tools. If you do not name your components and nets, the schematic editor automatically generates the names. For example, if left unnamed, the software might name the previous example, as follows:

/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57

Note: It is difficult to analyze circuits with automatically generated names, because the names only

have meaning for Xilinx software.

Schematic tools provide a graphic interface for design entry. You can use these tools to connect symbols representing the logic components in your design. You can build your design with individual gates, or you can combine gates to create functional blocks. This section focuses on ways to enter functional blocks using library elements and the CORE Generator.

Library Elements

Primitives and macros are the “building blocks” of component libraries. Xilinx libraries provide primitives, as well as common high-level macro functions. Primitives are basic circuit elements, such as AND and OR gates. Each primitive has a unique library name, symbol, and description. Macros contain multiple library elements, which can include primitives and other macros.

You can use the following types of macros with Xilinx FPGAs:

• Soft macros have pre-defined functionality but have flexible mapping, placement, and routing. Soft macros are available for all FPGAs.

• Relationally placed macros (RPMs) have fixed mapping and relative placement. RPMs are available for all device families, except the XC9500 family.

Macros are not available for synthesis because synthesis tools have their own module generators and do not require RPMs. If you wish to override the module generation, you can instantiate CORE Generator modules. For most leading-edge synthesis tools, this does not offer an advantage unless it is for a module that cannot be inferred.

CORE Generator Tool (FPGAs Only)

The Xilinx CORE Generator design tool delivers parameterizable cores that are optimized for Xilinx FPGAs. The library includes cores ranging from simple delay elements to complex DSP (Digital Signal Processing) filters and multiplexers. For details, refer to the CORE Generator Guide. You can also refer to the Xilinx IP (Intellectual Property) Center Web site at http://www.xilinx.com/ipcenter solutions include design reuse tools, free reference designs, DSP and PCI solutions, IP implementation tools, cores, specialized system level services, and vertical application IP solutions.

, which offers the latest IP solutions. These

34 www.xilinx.com Development System Reference Guide

HDL Entry and Synthesis

A typical Hardware Description Language (HDL) supports a mixed-level description in which gate and netlist constructs are used with functional descriptions. This mixed-level capability enables you to describe system architectures at a high level of abstraction, then incrementally refine the detailed gate-level implementation of a design.

HDL descriptions offer the following advantages:

• You can verify design functionality early in the design process. A design written as an HDL description can be simulated immediately. Design simulation at this high level, at the gate-level before implementation, allows you to evaluate architectural and design decisions.

• An HDL description is more easily read and understood than a netlist or schematic description. HDL descriptions provide technology-independent documentation of a design and its functionality. Because the initial HDL design description is technology independent, you can use it again to generate the design in a different technology, without having to translate it from the original technology.

• Large designs are easier to handle with HDL tools than schematic tools.

After you create your HDL design, you must synthesize it. During synthesis, behavioral information in the HDL file is translated into a structural netlist, and the design is optimized for a Xilinx device. Xilinx supports HDL synthesis tools for several third-party synthesis vendors. In addition, Xilinx offers its own synthesis tool, Xilinx Synthesis Technology (XST). See the Xilinx Synthesis Technology (XST) User Guide for information. For detailed information on synthesis, see the Synthesis and Simulation Design Guide.

Design Entry and Synthesis

Functional Simulation

After you create your design, you can simulate it. Functional simulation tests the logic in your design to determine if it works properly. You can save time during subsequent design steps if you perform functional simulation early in the design flow. See “Simulation” for more information.

Constraints

You may want to constrain your design within certain timing or placement parameters. You can specify mapping, block placement, and timing specifications.

You can enter constraints manually or use the Constraints Editor, Floorplanner, or FPGA Editor, which are graphical user interface (GUI) tools provided by Xilinx. You can use the Timing Analyzer GUI or TRACE command line program to evaluate the circuit against these constraints by generating a static timing analysis of your design. See Chapter 12,

“TRACE” and the online Help provided with each GUI for information. See the Constraints

Guide for detailed information on constraints.

Mapping Constraints (FPGAs Only)

You can specify how a block of logic is mapped into CLBs using an FMAP for all Spartan FPGA and Virtex FPGA families. These mapping symbols can be used in your schematic. However, if you overuse these specifications, it may be difficult to route your design.

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Chapter 2: Design Flow

Block Placement

Timing Specifications

Netlist Translation Programs

Block placement can be constrained to a specific location, to one of multiple locations, or to a location range. Locations can be specified in the schematic, with synthesis tools, or in the User Constraints File (UCF). Poor block placement can adversely affect both the placement and the routing of a design. Only I/O blocks require placement to meet external pin requirements.

You can specify timing requirements for paths in your design. PAR uses these timing specifications to achieve optimum performance when placing and routing your design.

Two netlist translation programs allow you to read netlists into the Xilinx software tools. EDIF2NGD allows you to read an Electronic Data Interchange Format (EDIF) 2 0 0 file. The NGDBuild program automatically invokes these programs as needed to convert your EDIF file to an NGD file, the required format for the Xilinx software tools. NGC files output from the Xilinx XST synthesis tool are read in by NGDBuild directly.

You can find detailed descriptions of the EDIF2NGD, and NGDBuild programs in Chapter

6, “NGDBuild” and “Appendix B”.

Design Implementation

Design Implementation begins with the mapping or fitting of a logical design file to a specific device and is complete when the physical design is successfully routed and a bitstream is generated. You can alter constraints during implementation just as you did during the Design Entry step. See “Constraints” for information.

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Design Implementation

The following figure shows the design implementation process for FPGA designs:

Floorplanner

UCF

Constraints Editor

FPGA Editor

TRACE &

Timing Analyzer

NGDBuild

NGD

MAP

NCD & PCF

PAR

NCD

BitGen

BIT

PROMGen

iMPACT

Figure 2-5: Design Implementation Flow (FPGAs)

X10296

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Chapter 2: Design Flow

The following figure shows the design implementation process for CPLD designs:

NGDBuild

Logic Optimization

Pin Feedback Generation

Power/Slew Optimization

CPLD Fitter

NGD

Design Loader

Auto Device/Speed Selector

Logic Synthesis

Technology Mapping

Global Net Optimization

Partitioning

Export Level Generator

PTerm Mapping

Post-Mapping

Enhancements

Implementation Options

Exporting

Assignments

Routing

RPT

Fitter Report (Text)

GYD

VM6

HPLUSAS6

VM6

HPREP6

JED

iMPACT

Figure 2-6: Design Implementation Flow (CPLDs)

X9493

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Mapping (FPGAs Only)

For FPGAs, the MAP command line program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD file, which contains a logical description of the design in terms of both the hierarchical components used to develop the design and the lower-level Xilinx primitives, and any number of NMC (hard placed-and-routed macro) files, each of which contains the definition of a physical macro. MAP then maps the logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA.

The output design from MAP is an NCD file, which is a physical representation of the design mapped to the components in the Xilinx FPGA. The NCD file can then be placed and routed, using the PAR command line program. See Chapter 7, “MAP” for detailed information.

Placing and Routing (FPGAs Only)

For FPGAs, the PAR command line program takes a mapped NCD file as input, places and routes the design, and outputs a placed and routed NCD file, which is used by the bitstream generator, BitGen. The output NCD file can also act as a guide file when you reiterate placement and routing for a design to which minor changes have been made after the previous iteration. See Chapter 9, “PAR” for detailed information.

Design Implementation

You can also use the FPGA Editor GUI tool to do the following:

• Place and route critical components before running automatic place and route tools on an entire design

• Modify placement and routing manually; the editor allows both automatic and manual component placement and routing

Note:

For more information, see the online Help provided with the FPGA Editor.

Bitstream Generation (FPGAs Only)

For FPGAs, the BitGen command line program produces a bitstream for Xilinx device configuration. BitGen takes a fully routed NCD file as its input and produces a configuration bitstream—a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. See Chapter 14, “BitGen” for detailed information.

After you generate your BIT file, you can download it to a device using the iMPACT GUI. You can also format the BIT file into a PROM file using the PromGen command line program and then download it to a device using the iMPACT GUI. See Chapter 16,

“PROMGen” of this guide or the iMPACT online help for more information.

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Chapter 2: Design Flow

Design Verification

Design verification is testing the functionality and performance of your design. You can verify Xilinx designs in the following ways:

• Simulation (functional and timing)

• Static timing analysis

• In-circuit verification

The following table lists the different design tools used for each verification type.

Table 2-1: Verification Tools

Verification Type Tools

Simulation Third-party simulators (integrated and

non-integrated)

Static Timing Analysis

TRACE (command line program)

Timing Analyzer (GUI)

Mentor Graphics

TAU and Innoveda BLAST software for use with the STAMP file format (for I/O timing verification only)

In-Circuit Verification Design Rule Checker (command line

program)

Download cable

40 www.xilinx.com Development System Reference Guide

Simulation

Design Verification

Design verification procedures should occur throughout your design process, as shown in the following figures.

Input Stimulus

Simulation

Simulation Netlist

Translate to

Simulator Format

Timing Simulation Path

Integrated Tool

Functional Simulator

Paths

Translate to

Simulator Format

Translation

Back-Annotation

Basic Design Flow

Design Entry

NGD

Mapping, Placement

and Routing

NCD

BitGen

BIT

Static Timing

Static Timing Analysis

In-Circuit Verification

NGA

Xilinx FPGA

X9556

Figure 2-7: Three Verification Methods of the Design Flow (FPGAs)

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Chapter 2: Design Flow

Simulation

The following figure shows the verification methods of the design flow for CPLDs.

Input Stimulus

Simulation

Simulation Netlist

Translate to

Simulator Format

Timing Simulation Path

Integrated Tool

Functional Simulator

Paths

Translate to

Simulator Format

Translation

Back-Annotation

Basic Design Flow

Design Entry

NGD

Optimization and

Fitting

VM6

Programming

File Creation

Static Timing

Static Timing Analysis

In-Circuit Verification

Figure 2-8: Three Verification Methods of the Design Flow (CPLDs)

Simulation

Back-Annotation

JED

NGA

Xilinx CPLD

In-Circuit Verification

X9538

You can run functional or timing simulation to verify your design. This section describes the back-annotation process that must occur prior to timing simulation. It also describes the functional and timing simulation methods for both schematic and HDL-based designs.

Before timing simulation can occur, the physical design information must be translated and distributed back to the logical design. For FPGAs, this back-annotation process is done with a program called NetGen. For CPLDs, back-annotation is performed with the TSim Timing Simulator. These programs create a database, which translates the back-annotated information into a netlist format that can be used for timing simulation.

42 www.xilinx.com Development System Reference Guide

Design Verification

The following figures show the back-annotation flows:

NGD

Logical Design

MAP

NCD

Physical Design

(Mapped)

PAR

NCD

Physical Design

(Placed and Routed)

Figure 2-9: Back-Annotation Flow for FPGAs

NGD

Logical Design

Command line only

NCD

PCF

NetGen

Simulation Netlist

Equivalence Checking

Netlist

Static Timing Analysis

Netlist

X10298

EDIF

NetGen

SDF

VHD

SDF

Optimization

NGA

and Fitting

VM6

Physical Design

TSIM

Timing Simulator

X10297

Figure 2-10: Back-Annotation (CPLDs)

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Chapter 2: Design Flow

NetGen

NetGen is a command line program that distributes information about delays, setup and hold times, clock to out, and pulse widths found in the physical NCD design file back to the logical NGD file and generates a Verilog or VHDL netlist for use with supported timing simulation, equivalence checking, and static timing analysis tools.

NetGen reads an NCD as input. The NCD file can be a mapped-only design, or a partially or fully placed and routed design. An NGM file, created by MAP, is an optional source of input. NetGen merges mapping information from the optional NGM file with placement, routing, and timing information from the NCD file.

Note:

NetGen reads an NGA file as input to generate a timing simulation netlist for CPLD designs.

See Chapter 22, “NetGen” for detailed information.

Schematic-Based Simulation

Design simulation involves testing your design using software models. It is most effective when testing the functionality of your design and its performance under worst-case conditions. You can easily probe internal nodes to check the behavior of your circuit, and then use these results to make changes in your schematic.

Simulation is performed using third-party tools that are linked to the Xilinx Development System. Use the various CAE-specific interface user guides, which cover the commands and features of the Xilinx-supported simulators, as your primary reference.

The software models provided for your simulation tools are designed to perform detailed characterization of your design. You can perform functional or timing simulation, as described in the following sections.

Functional Simulation

Functional simulation determines if the logic in your design is correct before you implement it in a device. Functional simulation can take place at the earliest stages of the design flow. Because timing information for the implemented design is not available at this stage, the simulator tests the logic in the design using unit delays.

Note:

in the design flow.

It is usually faster and easier to correct design errors if you perform functional simulation early

You can use integrated and non-integrated simulation tools. Integrated tools, such as Mentor Graphics or Innoveda, often contain a built-in interface that links the simulator and a schematic editor, allowing the tools to use the same netlist. You can move directly from entry to simulation when using a set of integrated tools.

Functional simulation in schematic-based tools is performed immediately after design entry in the capture environment. The schematic capture tool requires a Xilinx Unified Library and the simulator requires a library if the tools are not integrated. Most of the schematic-based tools require translation from their native database to EDIF for implementation. The return path from implementation is usually EDIF with certain exceptions in which a schematic tool is tied to an HDL simulator.

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Design Verification

Timing Simulation

Timing simulation verifies that your design runs at the desired speed for your device under worst-case conditions. This process is performed after your design is mapped, placed, and routed for FPGAs or fitted for CPLDs. At this time, all design delays are known.

Timing simulation is valuable because it can verify timing relationships and determine the critical paths for the design under worst-case conditions. It can also determine whether or not the design contains set-up or hold violations.

Before you can simulate your design, you must go through the back-annotation process, as described in “Back-Annotation”. During this process, NetGen creates suitable formats for various simulators.

Note:

simulation. This allows you to find the nets in the simulations more easily than looking for a softwaregenerated name.

Naming the nets during your design entry is important for both functional and timing

HDL-Based Simulation

Xilinx supports functional and timing simulation of HDL designs at the following points:

• Register Transfer Level (RTL) simulation, which may include the following:

♦ Instantiated UniSim library components

♦ LogiCORE models

• Post-synthesis functional simulation with one of the following:

♦ Gate-level UniSim library components

♦ Gate-level pre-route SimPrim library components

• Post-implementation back-annotated timing simulation with the following:

♦ SimPrim library components

♦ Standard delay format (SDF) file

Development System Reference Guide www.xilinx.com 45

Chapter 2: Design Flow

The following figure shows when you can perform functional and timing simulation:

HDL

Design

UniSim Library

LogiBLOX

Modules

CORE Generator

Modules

SimPrim

Library

HDL RTL

Simulation

Synthesis

Post-Synthesis Gate-Level

Functional Simulation

Xilinx

Implementation

HDL Timing

Simulation

Figure 2-11: Simulation Points for HDL Designs

Testbench

Stimulus

X9243

The three primary simulation points can be expanded to allow for two post-synthesis simulations. These points can be used if the synthesis tool cannot write VHDL or Verilog, or if the netlist is not in terms of UniSim components. The following table lists all the simulation points available in the HDL design flow.

Table 2-2: Five Simulation Points in HDL Design Flow

Simulation UniSim SimPrim SDF

RTL X

Post-Synthesis X

Functional Post-NGDBuild (Optional) X

Functional Post-MAP (Optional) X X

Post-Route Timing X X

These simulation points are described in the “Simulation Points” section of the Synthesis and Simulation Design Guide.

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Design Verification

The libraries required to support the simulation flows are described in detail in the “VHDL/Verilog Libraries and Models” section of the Synthesis and Simulation Design Guide. The flows and libraries support close functional equivalence of initialization behavior between functional and timing simulations. This is due to the addition of new methodologies and library cells to simulate Global Set/Reset (GSR) and Global 3-State (GTS) behavior.

You must address the built-in reset circuitry behavior in your designs, starting with the first simulation, to ensure that the simulations agree at the three primary points. If you do not simulate GSR behavior prior to synthesis and place and route, your RTL and post-synthesis simulations may not initialize to the same state as your post-route timing simulation. If this occurs, your various design descriptions are not functionally equivalent and your simulation results do not match.

In addition to the behavioral representation for GSR, you must add a Xilinx implementation directive. This directive is specifies to the place and route tools to use the special purpose GSR net that is pre-routed on the chip, and not to use the local asynchronous set/reset pins. Some synthesis tools can identify the GSR net from the behavioral description, and place the STARTUP module on the net to direct the implementation tools to use the global network. However, other synthesis tools interpret behavioral descriptions literally and introduce additional logic into your design to implement a function. Without specific instructions to use device global networks, the Xilinx implementation tools use general-purpose logic and interconnect resources to redundantly build functions already provided by the silicon.

Even if GSR behavior is not described, the chip initializes during configuration, and the post-route netlist has a net that must be driven during simulation. The “Understanding the Global Signals for Simulation” section of the Synthesis and Simulation Design Guide includes the methodology to describe this behavior, as well as the GTS behavior for output buffers.

Xilinx VHDL simulation supports the VITAL standard. This standard allows you to simulate with any VITAL-compliant simulator. Built-in Verilog support allows you to simulate with the Cadence Verilog-XL and other compatible simulators. Xilinx HDL simulation supports all current Xilinx FPGA and CPLD devices. Refer to the Synthesis and Simulation Design Guide for the list of supported VHDL and Verilog standards.

Static Timing Analysis (FPGAs Only)

Static timing analysis is best for quick timing checks of a design after it is placed and routed. It also allows you to determine path delays in your design. Following are the two major goals of static timing analysis:

• Timing verification

This is verifying that the design meets your timing constraints.

• Reporting

This is enumerating input constraint violations and placing them into an accessible file. You can analyze partially or completely placed and routed designs. The timing information depends on the placement and routing of the input design.

You can run static timing analysis using the Timing Reporter and Circuit Evaluator (TRACE) command line program. See Chapter 12, “TRACE” for detailed information. You can also use the Timing Analyzer GUI to perform this function. See the online Help provided with the Timing Analyzer for additional information. Use either tool to evaluate how well the place and route tools met the input timing constraints.

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Chapter 2: Design Flow

In-Circuit Verification

As a final test, you can verify how your design performs in the target application. In-circuit verification tests the circuit under typical operating conditions. Because you can program your Xilinx devices repeatedly, you can easily load different iterations of your design into your device and test it in-circuit. To verify your design in-circuit, download your design bitstream into a device with the Parallel Cable IV or MultiPRO cable.

Note:

For information about Xilinx cables and hardware, see the iMPACT online help.

Design Rule Checker (FPGAs Only)

Before generating the final bitstream, it is important to use the DRC option in BitGen to evaluate the NCD file for problems that could prevent the design from functioning properly. DRC is invoked automatically unless you use the –d option. See Chapter 8,

“Physical Design Rule Check” and Chapter 14, “BitGen” and for detailed information.

Xilinx Design Download Cables

Xilinx provides the Parallel Cable IV or MultiPRO cable to download the configuration data containing the device design.

You can use the Xilinx download cables with the iMPACT Programming software for FPGA and CPLD design download and readback, and configuration data verification. The iMPACT Programming software cannot be used to perform real-time design functional verification.

Probe

The Xilinx PROBE function in FPGA Editor provides real-time debug capability good for analyzing a few signals at a time. Using PROBE a designer can quickly identify and route any internal signals to available I/O pins without having to replace and route the design. The real-time activity of the signal can then be monitored using normal lab test equipment such as logic/state analyzers and oscilloscopes.

ChipScope ILA and ChipScope PRO

The ChipScope toolset was developed to assist engineers working at the PCB level. ChipScope ILA actually embeds logic analyzer cores into your design. These logic cores allow the user to view all the internal signals and nodes within an FPGA. ChipScope ILA supports user selectable data channels from 1 to 256. The depth of the sample buffer ranges from 256 to 16384 in Virtex-II devices. Triggers are changeable in real-0time without affecting the user logic or requiring recompilation of the user design.

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FPGA Design Tips

The Xilinx FPGA architecture is best suited for synchronous design. Strict synchronous design ensures that all registers are driven from the same time base with no clock skew. This section describes several tips for producing high-performance synchronous designs.

Design Size and Performance

Information about design size and performance can help you to optimize your design. When you place and route your design, the resulting report files list the number of CLBs, IOBs, and other device resources available. A first pass estimate can be obtained by processing the design through the MAP program.

If you want to determine the design size and performance without running automatic implementation software, you can quickly obtain an estimate from a rough calculation based on the Xilinx FPGA architecture.

Global Clock Distribution

Xilinx clock networks guarantee small clock skew values. The following table lists the resources available for the Xilinx FPGA families.

FPGA Design Tips

Table 2-3: Global Clock Resources

FPGA Family Resource Number Destination Pins

Spartan BUFGS 4 Clock, control, or certain input

Virtex, Virtex-E, Spartan-II, Spartan-IIE

Virtex-II, Virtex-II Pro

Note:

If a design requires extensive routing, there may be extra routing delay to these loads.

In certain devices families, global clock buffers are connected to control pin and logic inputs.

BUFG 4 Clock

BUFGMUX 16 Clock

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Chapter 2: Design Flow

Data Feedback and Clock Enable

The following figure shows a gated clock. The gated clock’s corresponding timing diagram shows that this implementation can lead to clock glitches, which can cause the flip-flop to clock at the wrong time.

a) Gated Clock

Enable

Clock

Enable

b) Corresponding Timing Diagram

Clock

Enable

Clock

Enable

Output

X9201

Figure 2-12: Gated Clock

The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state.

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FPGA Design Tips

This circuit guarantees a minimum clock pulse width and it does not add skew to the clock. The Spartan-II, and Virtex families’ flip-flops have a built-in clock-enable (CE).

a) Using a Feedback Path

Counters

Enable

Clock

b) Corresponding Timing Diagram

Clock

Enable

Output

X9202

Figure 2-13: Synchronous Design Using Data Feedback

Cascading several small counters to create a larger counter is similar to a gated clock. For example, if two 8-bit counters are connected, the terminal counter (TC) of the first counter is a large AND function gating the second clock input.

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Chapter 2: Design Flow

The following figure shows how you can create a synchronous design using the CE input. In this case, the TC of the first stage is connected directly to the CE of the second stage.

a) 16-bit counter with TC connected to the clock.

7. . . .

IMPROPER METHOD

b) 16-bit counter with TC connected to the clock-enable.

7. . . .

CLK

Figure 2-14: Two 8-Bit Counters Connected to Create a 16-Bit Counter

Other Synchronous Design Considerations

Other considerations for achieving a synchronous design include the following:

• Use clock enables instead of gated clocks to control the latching of data into registers.

• If your design has more clocks than the number of global clock distribution networks,

try to redesign to reduce the number of clocks. Otherwise, put the clocks that have the lowest fanout onto normally routed nets, and specify a low MAXSKEW rating. A clock net routed through a normal net has skew.

• Use the Virtex low skew resources. Make sure the MAXSKEW rating is not specified when using these resources.

15. . . .

X2093

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Tcl

Xilinx Tcl commands are compatible with the following device families:

• Virtex

• Spartan

™

, Virtex™-E

™

-II

™

-II Pro, Virtex™-II Pro X

™

-4

™

-5 LX

™

-II, Spartan™-IIE

™

-3, Spartan™-3E, Spartan™-3L

Chapter 3

Tcl Overview

This chapter describes the Xilinx Tcl Shell (xtclsh) and the Xilinx Tcl commands. This chapter contains the following sections:

• “Tcl Overview”

• “Xilinx Tcl Shell”

• “Tcl Fundamentals”

• “Xilinx Tcl Commands”

• “Tcl Commands for General Usage”

• “Tcl Commands for Advanced Scripting”

• “Project Properties and Options”

• “Example Tcl Scripts”

Tool Command Language (Tcl) is an easy to use scripting language and an industry standard popular in the electronic design automation (EDA) industry.

The Xilinx Tcl command language is designed to complement and extend the graphical user interface (GUI). For new users and projects, the GUI provides an easy-to-use interface to set up a project, perform initial implementations, explore available options, set constraints, and visualize the design. Alternatively, for users that know exactly what options and implementation steps they wish to perform, the Xilinx Tcl commands provide a batch interface that makes it convenient to execute the exact same script or steps over and over again. By making the syntax of the Xilinx Tcl commands match the GUI interaction as closely as possible, Xilinx Tcl commands make it easy to transition from using the GUI to running the tools in script or batch mode. A list of available project properties and batch tool options can be found in the “Project Properties and Options” section of this chapter.

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Chapter 3: Tcl

Xilinx Tcl Shell

The Xilinx Tcl command language also supports more advanced scripting techniques. Xilinx Tcl commands provide support for collections and objects that allow advanced users to write scripts that query the design and implementation, and then to take appropriate actions based on the results. “Tcl Commands for Advanced Scripting” are described in more detail later in the this chapter.

Tcl commands are accessed from the Xilinx Tcl Shell (xtclsh), which is available from the command line, or from the Tcl Console tab in Project Navigator. Xilinx Tcl commands are categorized in two ways: general usage and advanced scripting. See the “Xilinx Tcl

Commands” section of this chapter for a detailed listing that includes a description,

syntax, an example, and the Tcl return for each command.

To access the Xilinx Tcl Shell (xtclsh) from Project Navigator, click the Tcl Console tab, which displays a window with the xtclsh prompt (%).

To access the xtclsh from the command line, type xtclsh from the command prompt to return the xtclsh prompt (%). Example:

> xtclsh

Command line syntax is based on the Tcl command and corresponding subcommand that you enter. For example:

% <tcl_command> <subcommand> <optional_arguments>

tcl_command is the name of the Xilinx Tcl command.

subcommand is the subcommand name for the Xilinx Tcl command.

optional_arguments are the arguments specific to each subcommand. Example syntax for all

Xilinx Tcl commands, subcommands, and their respective arguments is included in the

“Tcl Commands for General Usage” and “Tcl Commands for Advanced Scripting” sections

of this chapter.

Accessing Help

Use the help command to get detailed information on Xilinx-specific Tcl commands. From the xtclsh prompt (%), type help for a list and brief description of Xilinx Tcl commands. For help on a specific Tcl command, type the following:

% help <tcl_command>

You can also get information on a specific subcommand by typing the subcommand name after the Tcl command. For example, type the following to get help on creating a new ISE project:

% help project new

help is the command that calls the Tcl help information.

project specifies the name of the Xilinx Tcl command.

new specifies the name of the project subcommand you wish to obtain help information on.

In Project Navigator, Tcl help is accessed from the Tcl Console tab using the same syntax as described above.

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Tcl Fundamentals

This section provides some very basic information about the syntactic style of Xilinx Tcl commands. For more information about Tcl in general, please refer to Tcl documentation easily available on the internet, for example: http://www.tck.tk/doc for the Tcl Developer Xchange.

In general, Tcl commands are procedural. Each Tcl command is a series of words, with the first word being the command name. For Xilinx Tcl commands, the command name is either a noun (e.g., project) or a verb (e.g., search). For commands that are nouns, the second word on the command line is the verb (e.g., project open). This second word is called the subcommand.

Subsequent words on the command line are additional parameters to the command. For Xilinx Tcl commands, required parameters are positional, which means they must always be specified in an exact order and follow the subcommand. Optional parameters follow the required parameters, can be specified in any order, and always have a flag that starts with “-“to indicate the parameter name; for example, -instance <instance-name>.

Tcl is case sensitive. Xilinx Tcl command names are always lower case. If the name is two words, the words are joined with an underscore (_). Even though Tcl is case sensitive, most design data (e.g., an instance name), property names, and property values are case insensitive. To make it less burdensome to type at the command prompt, unique prefixes are recognized when typing a subcommand, which means only typing the first few letters of a command name is all that is required for it to be recognized. Unique prefixes are also recognized for partition properties and property values.

Tcl Fundamentals

, which is the website

The real power of Tcl is unleashed when it is used for nested commands and for scripting. The result of any command can be stored in a variable. Values are assigned to variables and properties with the set command. The set command takes two arguments. The first argument is the name of the variable and the second argument is the value. It is not necessary to declare Tcl variables before you use them. If one does not exist, it is created when the command is executed.

In Tcl, the dollar-sign ($) syntax is used to substitute a variable’s value for its name. For example, $foo in a Tcl command is replaced by the value of the variable foo.

The result of a command can also be substituted directly into another command. Tcl uses square brackets [ ] for these nested commands. Tcl interprets everything between square brackets [ ] as a command and substitutes the command result for the text within the square brackets [ ].

Tcl provides several ways to quote strings that contain spaces or other special characters and to manage substitution. Double quotes (“) allow some special characters ([ ] and $) for substitution. Curly braces { } perform no substitutions.

For very specific command line examples, please see the “Tcl Commands for General

Usage” and “Tcl Commands for Advanced Scripting” sections of this chapter.

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Chapter 3: Tcl

Xilinx Namespace

All Xilinx Tcl commands are part of the Tcl namespace ::xilinx::. If another Tcl package uses a command name that conflicts with a Xilinx-specific Tcl command name, the Xilinx namespace must be used to access the command. For example, type the following to create a new project using Xilinx-specific Tcl commands:

% xilinx::project new <project_name>

It is only necessary to specify the Xilinx namespace when you have more than one namespace installed.

Xilinx Tcl Commands

The following sections include detailed listings of Xilinx Tcl commands, which are divided into two parts:

• Tcl Commands for General Usage

• Tcl Commands for Advanced Scripting

Each detailed listing includes the description, syntax, an example, and the Tcl return for each command.

In most cases, the examples shown assume that a project has been created with the project new command or a project has been opened with the project open command. Project files are

added with the xfile add command.

To view how Xilinx Tcl commands can be used in a realistic way, see the

Scripts”

located at the end of this chapter.

“Example Tcl

The following tables summarize the Xilinx Tcl commands based on those for general usage and those for advanced scripting.

Table 3-1: Xilinx Tcl Commands for General Usage

Commands Subcommands

partition (support design preservation) delete

get

new

properties

rerun

set

process (run and manage project processes) run

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Xilinx Tcl Commands

Table 3-1: Xilinx Tcl Commands for General Usage

Commands Subcommands

project (create and manage projects) clean

delete

get

get_processes

new

open

properties

set

timing_analysis (generate timing analysis reports) delete

disable_constraints

disable_cpt

enable_constraints

enable_cpt

get

new

reset

run

saveas

set

set_constraint

set_endpoints

set_filter

set_query

show_settings

xfile (manage project files) add

get

remove

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Chapter 3: Tcl

Table 3-2: Xilinx Tcl Commands for Advanced Scripting

Commands Subcommands

collection (create and manage a collection) append_to

copy

equal

foreach

get

index

properties

remove_from

set

sizeof

object (get object information) get

name

properties

type

search (search and return matching objects)

Tcl Commands for General Usage

This section describes the Xilinx Tcl commands for general usage. To view a sample script of how these commands are used, see the “Sample Tcl Script for General Usage” at the end of this chapter.

partition (support design preservation)

The partition command is used to create and manage partitions, which are used for design preservation. A Partition is set on an instance in a design. The Partition indicates that the implementation for the instance should be preserved and reused when possible.

% partition <subcommand>

Partition names should follow the naming conventions of the HDL source. In general, the local name of a top-level partition is set to the name of the design, which is based on the top-level entity or module in the HDL source. The full hierarchical name of a top-level partition is a forward slash (/) followed by the local name. For example, if the design name is stopwatch, then the hierarchical name for the top-level instance is /stopwatch. It is always necessary to give the full name of any instance or partition that you specify on the command line. Partition names are case-sensitive.

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delete (delete a partition)

The partition delete command deletes the specified partition from the current ISE project. This command also deletes any properties on the partition; however, timing and other logic constraints on the instance are preserved.

Tcl Commands for General Usage

Note:

the partition should be specified for the partition you wish to delete.

A Partition name may not be unique to the project. In this case, the full hierarchical name of

% partition delete <partition_name>

partition is the name of the Xilinx Tcl command.

delete is the name of the partition subcommand.

partition_name specifies the full hierarchical name of the partition you wish to remove from

the project or the name of the

Example: % partition delete /stopwatch/Inst_dcm1

Description: In this example, the Inst_dcm1 partition is deleted and removed

from the project repository. Note that only the partition is deleted from the project not the instance that the partition is set on.

Tcl Return: The number of partitions deleted. In this example, 1 is returned.

get (get partition properties)

The partition get command returns the value of the specified partition property. Note that the preserve property is assigned with the partition set command.

% partition get <partition_name> <property_name>

partition is the name of the Xilinx Tcl command.

get is the name of the partition subcommand.

partition_name specifies the full hierarchical name of the partition or the collection. A

collection is specified using the dollar-sign syntax ($) with the name of the collection variable.

property_name specifies the name of the property you wish to get the value of. Valid partition property names and their Tcl returns are shown in the following table:

Table 3-3: Partition Property Names and Tcl Returns

Partition Property Name Tcl Return

name The name of the partition.

parent The name of the parent of the partition. If the partition

is the top-level partition, the returned name is empty.

children A collection of the child partitions. If the partition has

no children, the returned collection is empty.

preserve Routing, placement, synthesis, or inherit

preserve_effective Returns the inherited value for the preserve property.

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Chapter 3: Tcl

Table 3-3: Partition Property Names and Tcl Returns

Partition Property Name Tcl Return

up_to_date_synthesis True or false, based on the status of the synthesis

results.

up_to_date_implementation True or false, based on the status of the implementation

results.

Example: % partition get /stopwatch/Inst_dcm1 preserve

Description: In this example, the partition get command is used to obtain the

current value of the preserve property.

Tcl Return: The property value as a text string. In this example, the return will

be routing, placement, synthesis, or inherit.

new (create a new partition)

The partition new command creates a new partition on a specified instance or collection in the current design. A collection is specified using the dollar-sign syntax ($) with the name of the collection variable.

% partition new <partition_name>

partition is the name of the Xilinx Tcl command.

new is the name of the partition subcommand.

partition_name specifies the full hierarchical name of the instance you wish to create the

partition on, or the collection.

Example: % partition new /stopwatch/Inst_dcm1

Description: In this example, the partition new command is used to create a new

partition on the Inst_dcm1 instance in the current design. The full hierarchical name (/stopwatch/Inst_dcm1) is required to specify the instance. In this case, stopwatch is the name of the top-level entity in the VHDL source.

Tcl Return: The full hierarchical name of the newly created partition. In this

example, /stopwatch/Inst_dcm1 is returned.

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properties (list available partition properties)

The partition properties command displays a list of the supported properties for all partitions. You can set the value of any property with the partition set command.

% partition properties

partition is the name of the Xilinx Tcl command.

properties is the name of the partition subcommand.

Example: % partition properties

Description: In this example, the partition properties command is used to list the

properties available for all partitions in the current ISE project.

Tcl Return: The available partition properties as a Tcl list.

For a list of partition properties and their return values, see the “set (set partition preserve

property)” command in this chapter.

rerun (force partition synthesis and implementation)

Tcl Commands for General Usage

The partition rerun command forces re-synthesis or re-implementation of a specified partition. If synthesis is specified, synthesis (XST), translation (NGDBuild), packing (MAP), and placement and routing (PAR) are all performed the next time the process run command is specified. If implementation is specified, translation, packing, and placement and routing are performed.

% partition rerun <partition_name> {synthesis|implementation}

partition is the name of the Xilinx Tcl command.

rerun is the name of the partition subcommand.

partition_name specifies the full hierarchical name of the partition or the collection you

wish to force the re-synthesis or re-implementation of. A collection is specified using the dollar-sign syntax ($) with the name of the collection variable.

synthesis specifies re-synthesis of the partition starting with XST, then NGDBuild, MAP, and PAR.

implementation specifies re-implementing the partition starting with NGDBuild, then MAP and PAR.

Example:

% partition rerun implementation /stopwatch/Inst_dcm1

Description: In this example, the partition rerun command forces the re-

implementation of the /stopwatch/Inst_dcm1 partition.

Tcl Return: True if the command was successful; false otherwise.

Note:

project.

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This command is used with the process run command, which runs the processes of the

Chapter 3: Tcl

set (set partition preserve property)

The partition set command assigns the partition preserve property and value for the specified partition.

% partition set <partition> preserve <value>

partition is the name of the Xilinx Tcl command.

set is the name of the partition subcommand.

partition specifies the full hierarchical name of the partition or the collection you wish to set

the property for. A collection is specified using the dollar-sign syntax ($) with the name of the collection variable.

preserve is the property used to control the level of changes that can be made to the implementation of partitions that have not been re-implemented. Values for the preserve property are:

preserve {routing|placement|synthesis|inherit}

routing -- Most data preservation comes from routing. When the property value is set to routing, all implementation data is preserved, including synthesis, packing, placement, and routing. Routing is the default property value.

placement --This is the second-highest property value for the preserve property. With this setting, synthesis, packing, and placement are preserved. Routing is only reimplemented if another partition requires the resources.

synthesis -- This is the lowest-level preserve property value because only the netlist, which contains synthesis information, is preserved. With this setting, packing, placement and routing are open for re-implementation; however, placement and routing are only re-implemented if another partition requires the resources.

inherit -- This value specifies that the partition inherits the same preserve property value as its parent partition. Inherit is the default setting for all child partitions. This setting is not available for top-level partitions.

Example:

% partition set /stopwatch/Inst_dcm1 preserve synthesis

Description: In this example, the partition set command is used to specify the

preserve property for the Inst_dcm1 partition. The preserve value is set to synthesis, which means packing, placement, and routing will be re-implemented.

Tcl Return: The value of the previous preserve property.

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process (run and manage project processes)

The process command runs and manages all processes within the current ISE project.

run (run process task)

The process run command runs the synthesis and implementation tools based on the specified process task. Process tasks are entered on the command line as strings distinguished by double quotes (“). The exact text representation of the task in Project Navigator is required. For a complete list of process tasks, see Tab le 3- 4.

% process run <process_task> [-instance <instance_name>] [-force rerun|rerun_all]

process is the name of the Xilinx Tcl command.

run is the name of the process subcommand.

process_task specifies the name of one of the process tasks to run. Process tasks are listed in

the Process window in Project Navigator. Note that the list of available processes changes, based on the source file you select. You can also use the project get_processes command to view a list of available processes. See the process get_processes command for more information. Process tasks vary by device family.

instance_name specifies the name of the instance to force re-implementation of. This is only needed for processes that do not use the entire design.

Tcl Commands for General Usage

-force is the command to force the re-implementation of the specified process, regardless of

the partition preserve setting. See the partition set command for more information on setting preservation levels.

rerun reruns the processes and updates input data as necessary, by running any dependency processes that are out-of-date.

rerun_all reruns the processes and all dependency processes back to the source data, as defined by the specified process goal. All processes are run whether they are out of date or not.

Example:

% process run “Implement Design” -force rerun_all

Description: In this example, the process run command is used to force the re-

implementation of the entire design, regardless of whether all source files are up-to-date or not.

Tcl Return: True if the process was successful; false otherwise.

The following table lists the Tcl-supported process tasks, which are based on the GUI names in Project Navigator. Process tasks are entered as text strings, distinguished by double quotes (“), as shown in the table. Note that the source file determines what processes are available. This table lists all processes in order, beginning with synthesis.

Table 3-4: Process Tasks

“Synthesize - XST”

“Check Syntax”

“Generate Post-Synthesis Simulation Model”

“Implement Design”

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Chapter 3: Tcl

project (create and manage projects)

Table 3-4: Process Tasks

“Translate”

“Map”

“Generate Post-Map Static Timing”

“Generate Post-Map Simulation Model”

“Place & Route”

“Generate Primetime Netlist”

“Generate Post-Place & Route Static Timing”

“Generate Post-Place & Route Simulation Model”

“Generate IBIS Model”

“Back-Annotate Pin Locations”

“Generate Programming File”

The project command creates and manages ISE projects. A project contains all files and data related to a design. You can create a project to manage all of the design files and to enable different processes to work on the design.

% project <subcommand>

clean (remove system-generated project files)

The project clean command removes all of the temporary and system-generated files in the current ISE project. It does not remove any source files, like Verilog or VHDL, nor does it remove any user-modified files. For example, system generated design and report files like the NCD (.ncd) and map report (.mpr) are removed with the project clean command, unless they have been user-modified.

% project clean

project is the name of the Xilinx Tcl command.

clean is the name of the project subcommand.

Example: % project clean

Description: In this example, the current ISE project is cleaned. All temporary

and system generated files are removed, including design and report files, unless these have been user-modified.

Tcl Return: True if the project is cleaned successfully; false otherwise.

Caution!

current ISE project. These files include the NGD and NCD files generated by the implementation tools.

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The project clean command permanently deletes all system-generated files from the

close (close the ISE project)

The project close command closes the current ISE project. It is not necessary to specify the name of the project to close, since only one ISE project can be open at a time.

% project close

project is the name of the Xilinx Tcl command.

close is the name of the project subcommand.

Example: % project close

Description: In this example, the current ISE project is closed.

Tcl Return: True if the project is closed successfully; false otherwise.

get (get project properties)

The project get command returns the value of the specified project-level property or batch application option.

% project get <option_name|property_name>

Tcl Commands for General Usage

project is the name of the Xilinx Tcl command.

get is the name of the project subcommand.

option_name specifies the name of the batch application option you wish to get the value of.

For example, Map Effort Level. Batch application options are entered as strings distinguished by double quotes (“). The exact text representation of the option in Project Navigator is required. For a complete list of project properties and options, see the “Project

Properties and Options” section of this chapter.

property_name specifies the name of the property you wish to get the value of. Valid properties names are family, device, package, speed, and top.

Example: % project get speed

Description: In this example, the value of the speed grade that was set with the

project set speed command is returned.

Tcl Ret urn: T he propert y value as a tex t stri ng. In t his exa mple, the de vice sp eed

grade is returned.

get_processes (get project processes)

The project get_processes command lists the available processes for the specified instance.

% project get_processes [-instance <instance_name>]

project is the name of the Xilinx Tcl command.

get_processes is the name of the project subcommand.

-instance limits the properties listed to only those of the specified instance. If no instance is

specified, the top-level instance is used by default.

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Chapter 3: Tcl

instance_name specifies the name of the instance you wish to know the available processes for.

Example: % project get_processes [-instance Inst_dcm1]

Description: In this example, the project get_processes command is used to list all

of the available processes for only the instance, Inst_dcm1.

Tcl Return: The available processes as a text string. In this example, a list of

processes for Inst_dcm1 is returned.

new (create a new ISE project)

The project new command creates a new ISE project.

% project new <project_name>

project is the name of the Xilinx Tcl command.

new is the name of the project subcommand.

project_name specifies the name for the ISE project you wish to create.

Example: % project new watchver.ise

Description: In this example, a new ISE project named watchver.ise is created in

the current directory.

Tcl Return: The name of the new ISE project.

open (open an ISE project)

The project open command opens an existing ISE project. If the project does not exist, an error message to create a new project with the project new command appears.

% project open <project_name>

project is the name of the Xilinx Tcl command.

open is the name of the project subcommand.

project_name specifies the name for the ISE project you wish to open.

Example: % project open watchver.ise

Description: In this example, the watchver.ise project in the current directory is

opened.

Tcl Return: The name of the open ISE project.

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properties (list project properties)

The project properties command lists all of the project properties for the specified process or instance.

% project properties [-process <process_name>][-instance <instance_name]

project is the name of the Xilinx Tcl command.

properties is the name of the project subcommand.

-process <process_name> limits the properties listed to only those for the specified process.

By default, the properties for all synthesis and implementation processes are listed. You can also specify all to list the properties for all project processes.

-instance <instance_name> limits the properties listed to only those of the specified instance.

If no instance name is specified, the properties for the top-level instance are listed. You c an also specify top to specify the top-level instance.

You c an

Example: % project properties -process all

Description: In this example, the project properties command is used to list the

properties for all of the available processes for the current ISE project.

Tcl Commands for General Usage

Tcl Return: The available process properties as a Tcl list. In this example, a list

of all process properties.

Note:

command. To get property information for specific properties like family, device, and speed, see the project set options in this section for more information.

To get processes information for a specific instance, use the project get_processes

set (set project properties, values, and options)

The project set command is used to set properties and values for the current ISE project. In addition to setting family and device-specific properties and values, the project set command is also used to set options for the batch application tools, including XST, NGDBuild, MAP, PAR, TRACE, and BitGen.

The set subcommand uses two arguments. The first argument assigns the name of the property or variable; and the second argument assigns the value.

% project set <property_name> <property_value>

project is the name of the Xilinx Tcl command.

set is the name of the project subcommand.

property_name specifies the name of the property, variable or batch application option.

property_value specifies the value of the property, variable, or batch application option.

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Chapter 3: Tcl

Note: Some batch application options only work when other options are specified. For example, in

XST, the Synthesize Constraints File option only works if the Use Synthesis Constraints File option is also specified.

Example: % project set “Map Effort Level” high

Description: In this example, the project set command is used to set the map effort

level to high. Map Effort Level is the name of the MAP option. High is the value set for the option.

Tcl Return: The previous value of the newly set option. In this example, the Tcl

return would be medium, if the option value was previously set to medium.

Note: Batch application options are entered as strings distinguished by double quotes (“). The exact

text representation of the option (or property) in the Project Navigator GUI is required. For a complete list of project properties and options, see the “Project Properties and Options” section of this chapter.

set device (set device)

The project set device command specifies the target device for the current ISE project.

Note:

Navigator, or by utilizing the unique prefixes supported by Xilinx Tcl commands. For example, type project set device V to get an error message that enumerates all Virtex devices. Optionally, you can specify the partgen –arch command. From the Tcl prompt (%), type partgen –h for help using this command.

A list of available devices can be viewed in the Project Properties dialog box in Project

% project set device <device_name>

project is the name of the Xilinx Tcl command.

set device is the name of the project subcommand.

device_name specifies the target device for the current ISE project.

Example: % project set device xc2vp2

Description: In this example, the device for the current project is set to xc2vp2.

Tcl Return: The previous value. In this example, the previous device setting is

returned.

Note:

to set the device.

You must first use the set family command to set the device family before using this command

set family (set device family)

The project set family command specifies the device family for the current ISE project.

Note:

A list of available devices can be viewed in the Project Properties dialog box in Project

% project set family <device_family_name>

project is the name of the Xilinx Tcl command.

set family is the name of the project subcommand.

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device_family_name specifies the device family to use with the current ISE project.

Example: % project set family Virtex2p

Description: In this example, the device family for the current project is set to

Virtex2p.

Tcl Return: The previous value. In this example, the previous device family

setting is returned.

set package (set device package)

The project set package command specifies the device package for the current ISE project.

Tcl Commands for General Usage

Note:

A list of available devices can be viewed in the Project Properties dialog box in Project

% project set package <package_name>

project is the name of the Xilinx Tcl command.

set package is the name of the project subcommand.

package_name specifies the target device package for the current ISE project.

Example: % project set package fg256

Description: In this example, the device package for the current project is set to

fg256.

Tcl Return: The previous value. In this example, the previous device package

setting is returned.

set speed (set device speed)

The project set speed command specifies the device speed for the current ISE project.

Note:

A list of available devices can be viewed in the Project Properties dialog box in Project

% project set speed <speed_grade>

project is the name of the Xilinx Tcl command.

set speed is the name of the project subcommand.

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speed_grade specifies the speed for the target device of the current ISE project.

Example: % project set speed -7

Description: In this example, the device speed for the current project is set to -7.

Tcl Return: The previous value. In this example, the previous speed grade

setting is returned.

set top (set the top-level module/entity)

The project set top command specifies the top-level module or entity in the design hierarchy. To use this command, you must first add the module or entity to your project with the xfile add command.

% project set top <module_name>

project is the name of the Xilinx Tcl command.

set top is the name of the project subcommand.

module_name specifies the name for the top-level module for Verilog and EDIF-based

designs.

For VHDL designs, you must specify the architecture name and the entity name using the following syntax:

% project set top <architecture_name> [entity_name]

Example: % project set top pong_top

Description: In this Verilog example, the project set top command is used to set

pong_top as the top-level module in the design hierarchy.

Tcl Return: The name of the previous top-level module.

timing_analysis (generate timing analysis reports)

The timing_analysis command generates static timing analysis reports for an implemented design.

% timing_analysis <subcommand> <analysis_name>

delete (delete timing analysis)

The timing_analysis delete command removes a previously created analysis from the current ISE project.

% timing_analysis delete <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

delete is the name of the timing_analysis subcommand.

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analysis_name specifies the name of the analysis to delete.

Example: % timing_analysis delete stopwatch_timing

Description: In this example, the timing_analysis delete command is used to

remove the stopwatch_timing analysis, which was previously created with the timing_analysis new command.

Tcl Return: 0 if the analysis was deleted, 1 otherwise.

disable_constraints (disable timing constraints)

The timing_analysis disable_constraints command disables a physical timing constraint from the timing analysis.

timing_analysis disable_constraints <analysis_name> <timing_constraint_specs>

timing_analysis is the name of the Xilinx Tcl command.

disable_constraints is the name of the timing_analysis subcommand.

analysis_name specifies the name of an analysis created with the timing_analysis new

command.

Tcl Commands for General Usage

timing_constraint_specs specifies the names and specs to be disabled for analysis.

Example: % timing_analysis disable_constraints

stopwatch_timing “TS_clk=PERIOD TIMINGROUP\”sclk\”20 ns HIGH 50.00000%;”

Description: In this example, the specified timing constraints were disabled for

the analysis.

Tcl Return: Number of constraints that were disabled.

disable_cpt (disable components for path tracing control)

The timing_analysis disable_cpt command disables components associated with a path tracing control for a timing path analysis.

% timing_analysis disable_cpt <analysis_name> <cpt_symbol> <component_name>

timing_analysis is the name of the Xilinx Tcl command.

disable_cpt is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis generated previously with the timing_analysis new command.

cpt_symbol specifies a path tracing control that determines whether associated components

are considered for the timing path analysis.

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component_name specifies the name of the components to be disabled.

Example: % timing_analysis disable_cpt stopwatch_timing

reg_sr_clk “ureg_1 ureg_2 ureg_3”

Description: In this example, the specified components, ureg_1, ureg_2, and

ureg_3 are disabled for the timing path analysis.

Tcl Return: Number of components that were disabled.

enable_constraints (enable constraints for analysis)

The timing_analysis enable_constraints command enables the specified timing constraints for the analysis.

% timing_analysis enable_constraints <analysis_name> <timing_constraint_specs>

timing_analysis is the name of the Xilinx Tcl command.

enable_constraints is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis generated previously with the timing_analysis new command.

timing_constraint_specs specifies the names and specs of the constraints to be enabled for

analysis.

Example: % timing_analysis enable_constraints

stopwatch_timing “TS_clk=PERIOD TIMEGROUP\”sclk\” 20 ns HIGH 50.00000%;”

Description: In this example, the specified timing constraint is enabled for

analysis.

Tcl Return: Number of enabled constraints.

enable_cpt (enable components for path tracing control)

The timing_analysis enable_cpt command enables specified components associated with a path tracing control for a timing path analysis.

% timing_analysis enable_cpt <analysis_name> <cpt_symbol> <component_name>

timing_analysis is the name of the Xilinx Tcl command.

enable_cpt is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis generated previously with the timing_analysis new command.

cpt_symbol specifies a path tracing control that determines whether associated components

are considered for the timing path analysis.

component_name specifies the name of the components to enable.

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Example: % timing_analysis enable_cpt stopwatch_timing

Description: In this example, the specified components, ureg_1, ureg_2, and

Tcl Return: Number of components that were enabled.

get (get analysis property)

The timing_analysis get command returns the value of the specified property.

% timing_analysis get <analysis_name> <analysis_property>

timing_analysis is the name of the Xilinx Tcl command.

get is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis generated previously with the timing_analysis new command.

Tcl Commands for General Usage

reg_sr_clk “ureg_1 ureg_2 ureg_3”

ureg_3 are enabled for the timing path analysis.

analysis_property specifies the name of the analysis property to get the value of. See

Tab le 3 -5 for a list of analysis properties.

Example:

% timing_analysis get stopwatch_timing analysis_speed

Description: In this example, the timing_analysis get command is used to return

the speed grade that is currently set for the stopwatch_timing analysis.

Tcl Return: The value of the specified property.

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The following table lists the analysis properties for the timing_analysis command. A description of each analysis property is also included in the table.

Table 3-5: Timing Analysis Properties and Descriptions

Analysis Property Description

analysis_type Determines which of the following analysis

types will be run:

auto_generated—for an analysis that discards any constraints from the UCF/PCF and instead uses constraints automatically generated by the timing wizard.

clock_io—for an analysis that discards any constraints from the UCF/PCF and uses custom constraints as generated by the set_constraints subcommand.

endpoints—for an analysis that discards any constraints from the UCF/PCF and uses custom constraints as generated by the set_endpoints subcommand.

timing_constraint—for an analysis that uses the constraints form the UCF/PCF.

net—for an analysis on nets as specified by the set_query subcommand.

timegroup—for an analysis on timegroups as specified by the set_query subcommand.

omit_user_constraints Specifies whether to omit all timing constraints

from the UCF/PCF.

analyze_unconstrained_paths Specifies whether paths not covered by any

constraint should be analyzed and shown in the timing report.

analysis_temperature Specifies the prorating temperature for the

analysis.

analysis_voltage Specifies the prorating voltage for the analysis.

analysis_speed Specifies the speed grade for the analysis.

report_name Specifies the name for the report (XML or

ASCII).

report_format Specifies the format for the report.

report_datasheet Specifies whether the datasheet section is

generated for the timing report.

report_timegroups Specifies whether the timegroups table is

generated for the timing report.

paths_per_constraint Specifies how many paths per constraint are

reported.

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Table 3-5: Timing Analysis Properties and Descriptions

Analysis Property Description

show_longest_paths CPLD report option that determines whether

the longest paths are shown.

show_delay_over CPLD report option that specifies only paths

above the specified delay are shown in the report.

show_delay_under CPLD report option that specifies that only

paths below the specified delay are shown in the report.

display_info Specifies whether Timing Analyzer is run in

verbose mode.

display_physical_name Specifies whether physical names of path

elements in the timing report should be displayed in the Timing Analyzer report view.

display_site_location Specifies whether site locations of path

elements in the timing report should be displayed in the Timing Analyzer report view.

display_statistics Specifies whether the statistic section of the

timing report is shown in the Timing Analyzer report view.

new (new timing analysis)

The timing_analysis new command sets up a new analysis or query on an implemented design in the current ISE project. The timing_analysis set command is used to set properties and values for the new analysis. See “set (set analysis properties)” for more information.

% timing_analysis new analysis|query [-name <analysis_name>]

timing_analysis is the name of the Xilinx Tcl command.

new is the name of the timing_analysis subcommand.

analysis, if specified, sets up a timing analysis.

query, if specified, sets up a net or timegroup analysis.

-name <analysis_name> specifies the name for the analysis. If the -name command is used,

but no name is specified, an analysis is generated and has the name of the top-level module.

Example:

Description: In this example, the timing_analysis new command is used to create a

% timing_analysis new analysis [-name stopwatch_timing]

timing analysis named stopwatch_timing.

Tcl Return: A new timing analysis.

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reset (reset path filters and constraints)

The timing_analysis reset command resets all existing path filters and custom constraints for the analysis.

% timing_analysis reset <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

reset is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

Example: % timing_analysis reset stopwatch_timing

Description: In this example, the timing_analysis reset command is used to reset all

of the path filters and any custom constraints in the stopwatch_timing analysis.

Tcl Return: True if all path filters were cleared successfully, false otherwise.

run (run analysis)

The timing_analysis run command executes an analysis and returns the name of the timing, net, or timegroup report file. The analysis is based on the property settings assigned with the timing_analysis set command. An analysis is first created with the timing_analysis new command. See “set (set analysis properties)” and “new (new timing analysis)” for more information.

% timing_analysis run <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

run is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

Example: % timing_analysis run stopwatch_timing

Description: In this example, the timing_analysis run command is used to execute a

timing analysis and create a new analysis report.

Tcl Return: Name of the timing analysis.

saveas (save analysis report)

The timing_analysis saveas command saves the analysis to a specified file.

% timing_analysis saveas <analysis_name> <new_file_name>

timing_analysis is the name of the Xilinx Tcl command.

saveas is the name of the timing_analysis subcommand.

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Tcl Commands for General Usage

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

new_file_name specifies the file name for the analysis report.

Example:

% timing_analysis saveas stopwatch_timing stopwatch_report

Description: In this example, the timing_analysis saveas command is used to save

the stopwatch_timing analysis to a report file named stopwatch_report.

Tcl Return: Name of the report file.

set (set analysis properties)

The timing_analysis set command is used to set properties and values for an analysis.

% timing_analysis set <analysis_name> <property> <value>

timing_analysis is the name of the Xilinx Tcl command.

set is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

property specifies the analysis property that you wish to set the value for. See Ta bl e 3-5 for

a list of analysis properties.

value specifies the value for the specified property.

Example: % timing_analysis set stopwatch_timing

analysis_speed -11

Description: In this example, the timing_analysis set command is used to set the

value of the analysis_speed property to -11, for the stopwatch_timing analysis.

Tcl Return: Previous value of the specified property.

set_constraint (set constraint for custom analysis)

The timing_analysis set_constraint command is used to set constraints for a custom analysis.

% timing_analysis set_constraint <analysis_name> <constraint_type> <constraint_details>

timing_analysis is the name of the Xilinx Tcl command.

set_constraint is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

constraint_type specifies the type of constraint to set for the custom analysis. There are four

constraint types:

♦ maxdelay—pad-to-pad maximum delay

♦ period—period constraint on clock pad

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♦ padgroup—group definition on pad set

♦ offset—offset in/out constraint

constraint_details specifies the details for the specified constraint type as follows:

♦ maxdelay—timing in ns

♦ period—time in ns and clock pad

♦ padgroup—group name and pads to be included in group

♦ offset—[timegroup] P2S|C2P <clock_pad_name> <time_in_ns> [C2P|P2S

<clock_pad_name> <time_in_ns>] [<“data pad or pad group”>]

Note:

in constraint), and C2P, which is clock-to-pad (offset out constraint).

There are two types of offset constraints: P2S, which is pad-to-synchronous (offset

Example: % timing_analysis set_constraint stopwatch_timing

period “13 sclk”

Description: In this example, a period constraint is set for the stopwatch_timing

analysis. Note that the constraint details, “13 sclk”, are entered as a text string.

Tcl Return: 1 if the constraint was set successfully, 0 otherwise.

set_endpoints (set source and destination endpoints)

The timing_analysis set_endpoints command sets source and destination endpoints for a path endpoints analysis.

% timing_analysis set_endpoints <analysis name> <qualifier> <category> <items>

timing_analysis is the name of the Xilinx Tcl command.

set_endpoints is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

qualifier specifies whether source (from) or destination (to) points are being set for custom

analysis.

category specifies the resources type for the sources and destinations. These are family dependent.

items specifies the resource items to be put into path endpoint sources or destinations.

Example:

Description: In this example, the asterisk (*) was used as a wildcard to add all items

% timing_analysis set_endpoints stopwatch_timing from ffs *

in the flip-flop category to the sources for the path endpoints analysis.

Tcl Return: 1 if the endpoints were set successfully, 0 otherwise.

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set_filter (set filter for analysis)

The timing_analysis set_filter command sets a net filter to exclude or include the specified nets from a path analysis.

% timing_analysis set_filter <analysis_name> <filter_type> <filter_value> <filter_items>

timing_analysis is the name of the Xilinx Tcl command.

set_filter is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

filter_type specifies the type of analysis filter. Supported filter types are net and timegroup.

Tcl Commands for General Usage

filter_value specifies the value for the filter type

. Net filter values are include and exclude.

filter_items specifies the items to be filtered. For the net filter type, these are the names of nets in the current design.

Example: % timing_analysis set_filter stopwatch_timing nets

exclude “ureg_net_1 ureg_net_2 ureg_net_3”

Description: In this example, the specified nets are excluded from the

stopwatch_timing analysis. Note that the nets to exclude are entered as text strings, which are distinguished by double quotes (“).

Tcl Return: 1 if the filter is set successfully; 0 otherwise.

set_query (set up net or timegroup report)

The timing_analysis set_query command sets up a report that shows net delays and fanouts, or blocks associated with timegroups.

% timing_analysis set_query <analysis_name> <query_type> <query_items>

timing_analysis is the name of the Xilinx Tcl command.

set_query is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

query_type specifies the type of query. Supported queries are:

net—generates a report that shows the delay details for the specified query items.

timegroup—generates a report that shows blocks of the specified timegroups.

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query_items specifies the items to query. For example, -ld <number> specifies how many longest delay nets should be displayed in the report; -hf <number> specifies how many highest fanout nets should be displayed in the report. See the example below.

Example: % timing_anlaysis run stopwatch_timing

% timing_analysis set_query stopwatch_timing net “clk_net1 clk_net2” -ld 2 -hf 5

Description: In this example, a query is set up to report 2 nets with the longest

delay and 5 nets with the highest fanout. Delay details on the query items (clk_net1 and clknet_2) are reported in the detailed nets section of the report.

Note:

command is used to set up the query.

The net report is only generated after the timing_analysis run

Tcl Return: 1 if the command was executed successfully; 0 otherwise.

show_settings (generate settings report)

The timing_analysis show_settings command generates a settings report based on the analysis settings.

% timing_analysis show_settings <analysis_name>

timing_analysis is the name of the Xilinx Tcl command.

show_settings is the name of the timing_analysis subcommand.

analysis_name specifies the name of the analysis previously created with the timing_analysis new command.

Example: % timing_analysis show_settings stopwatch_timing

Description: In this example, a settings report is generated for the

stopwatch_timing analysis.

Tcl Return: The name of the settings report.

xfile (manage project files)

The xfile command is used to manage all of the source files within an ISE project. Use the xfile command to add, remove, and get information on any source files in the current ISE

project.

% xfile <subcommand> <file_name>

add (add file to project)

The xfile add command specifies the name of the file to add to the current ISE project. Files can be added to a project in any order.

% xfile add <file_name>

xfile is the name of the Xilinx Tcl command.

add is the name of the xfile subcommand.

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file_name specifies the name of the source file(s) you wish to add to the current ISE project. Path names and wildcards can be used to specify one or more files to add to the project. Tcl commands support two wildcard characters: asterisk (*) to indicate multiple characters, or a question mark (?) to indicate a single character.

Example: % xfile add *.vhd /mysource/mysub_dir timing.ucf

Description: In this example, the xfile add command is used to add all of the

Tcl Return: The name of the added file(s).

get (get project file properties)

The xfile get command returns information on the specified project file and its properties. There are two properties supported for this command: name and timestamp. For example, if name is the specified property, the Tcl return is the full name of the specified file. If timestamp is the specified property, the Tcl return is the timestamp of when the file was first added to the project with the xfile add command.

% xfile get <file_name> <name|timestamp>

Tcl Commands for General Usage

VHDL source files and the timing.ucf file to the current ISE project.

xfile is the name of the Xilinx Tcl command.

get is the name of the xfile subcommand.

file_name specifies the name of the source file to get the name or timestamp information on.

name if specified, returns the full path of the current project and the name of the specified

file.

timestamp if specified, returns the timestamp of when the file was first added to the project with the xfile add command.

Example: % xfile get timestamp stopwatch.vhd

Description: In this example, the xfile get command is used to get the timestamp

information for the stopwatch.vhd file.

Tcl Return: The value of the specified property as a text string. In this example,

the timestamp information of when the file was added to the project.

remove (remove file from project)

The xfile remove command removes the specified file from the current ISE project.

% xfile remove <file_name>

xfile is the name of the Xilinx Tcl command.

remove is the name of the xfile subcommand.

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file_name specifies the name of the file you wish to remove from the project.

Example: % xfile remove stopwatch.vhd

Description: In this example, the stopwatch.vhd file is removed from the current

ISE project.

Tcl Return: True if the file was removed; false otherwise.

Note: When you remove a file, objects within the current ISE project may be invalidated (e.g.,

partitions and instances).

Tcl Commands for Advanced Scripting

Xilinx Tcl commands for advanced scripting use objects and collections. An object can be any element in an ISE project, like an instance, file, or process. Collections return groups of objects, based on values that you assign to object and collection variables.

In Tcl, the set command is used to assign a value to a variable, which is returned with the dollar sign ($) syntax, as shown in many examples throughout this section. It is not necessary to declare a Tcl variable before it is used. When the variable does not exist, it is created when the command is executed.

The collection command and its relative subcommands are used to create and manage large groups of objects. The search command is used with the collection command to define the value of the collection.

This section describes the Xilinx Tcl commands for advanced scripting. To view a sample script of how these commands are used, see the “Sample Tcl Script for Advanced

Scripting” at the end of this chapter.

collection (create and manage a collection)

A collection is a group of Xilinx Tcl objects, similar to a list, that is exported to the Tcl interface. The collection command, in conjunction with its subcommands, is used to create and manage the objects in a specified collection.

A collection is referenced in Tcl by a collection variable, which is defined with the collection set command. Technically, the value of the collection variable is the collection.

The following syntax shows the collection command and its subcommands. Please refer to the description of each collection subcommand for an example of how the subcommand is used. Command line syntax is unique to each subcommand.

% collection <subcommand> <optional_arguments>

append_to (add objects to a collection)

The collection append_to command adds objects to a collection. This command treats a specified collection variable as a collection and appends all of the objects returned from a search, or from another collection, to the collection. If the collection variable does not exist, then it is created when the command is executed.

% collection append_to <collection_variable> <objects_to_append> [-unique]

collection is the name of the Xilinx Tcl command.

append_to is the name of the collection subcommand.

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collection_variable specifies the name of the collection variable, which references the collection. If the collection variable does not exist, then it is created.

objects_to_append specifies an object or a collection of objects to be added to the collection.

-unique optionally adds only objects that are not already in the collection. If the -unique

option is not used, then duplicate objects may be added to the collection.

Example:

% collection append_to colVar [search * -type instance]

Description: In this example, the collection append_to command is used to create

a new collection variable named colVar. The nested search command returns a collection of all the instances in the current design. These instances are objects that are added to the collection, referenced by the colVar collection variable.

Tcl Return: A collection of objects.

copy (copy a collection)

The collection copy command creates a duplicate of an existing collection. Alternatively, you can have more than one collection variable referencing a collection, rather than copying it. See Example 1 below.

In most cases, a second reference to a collection is all that is needed. However, if a separate copy is required, use the collection copy command to create the new collection as shown in Example 2 below.

collection copy <collection_variable>

collection is the name of the Xilinx Tcl command.

copy is the name of the collection subcommand.

collection_variable specifies the name of the collection to copy.

Example 1: % set colVar_1 [search * -type instance]

% set colVar_2 $colVar_1

Description: In this example, the Tcl set command in the first line creates a

collection assigned to the collection variable colVar_1. The second line creates a second collection variable, colVar_2, that references the value of colVar_1, which is the first collection.

There is still only one underlying collection referenced. Any changes made to colVar_1 will be visible in colVar_2, and if colVar1_1 is changed, then colVar_2 continues to reference the same underlying collection.

Tcl Return: A new variable reference to the collection.

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Example 2: % set colVar_2 [collection copy $colVar_1]

Description: In this example, the set command creates the collection variable

colVar_2. The nested collection copy command makes a duplicate of the colVar_1 collection and assigns it to the colVar2 collection variable, making it a completely separate collection.

Tcl Return: A new collection.

equal (compare two collections)

The collection equal command compares the contents of two collections. Collections are considered equal when the objects in both collections are the same. If the same objects are in both collections, the result is 1. If the objects in the compared collections are different, then the result is 0. By default, the order of the objects does not matter. Optionally, the order_dependent command can be specified for the order of the objects to be considered.

% collection equal <colVar_1> <colVar_2> [-order_dependent]

collection is the name of the Xilinx Tcl command.

equal is the name of the collection subcommand.

colVar_1 specifies the base collection for the comparison.

colVar_2 specifies the collection to compare with the base collection.

order_dependent optionally specifies that the collections are considered different when the

order of the objects in both collections are not the same.

Note:

When two empty collections are compared, they are considered identical and the result is 1.

Example: % set colVar_1 [search * -type instance]

% set colVar_2 [search /top/T* -type instance]

% collection equal $colVar_1 $colVar_2

Description: In this example, the contents of two collections are compared. First,

the Tcl set command is used to assign a collection of instances to the collection variable colVar_1; then another collection of filtered instance names is assigned to the collection variable colVar_2.

The collection equal command is used to specify the two collections to compare. The dollar sign ($) syntax is used to obtain the values of the collection variables. In this case, the values of colVar_1 and colVar_2 to determine if they are equal.

Tcl Return: 0 if the collections are not the same, 1 if the collections are the same.

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foreach (iterate over elements in a collection)

The collection foreach command iterates over each object in a collection through an iterator variable. The iterator variable specifies the collection to interate over and the set of commands or script to apply at each iteration.

% collection foreach <iterator_variable> <collection_variable> {body}

collection is the name of the Xilinx Tcl command.

foreach is the name of the collection subcommand.

iterator_variable specifies the name of the iterator variable.

collection_variable specifies the name of the collection to iterate through.

body specifies a set of commands or script to execute at each iteration.

Example: % set colVar [search * -type instance]

% collection foreach itr $colVar { puts [object name $itr]}

Description: In this example, the set command is used in the first line to assign a

collection of instances to the colVar collection variable.

In the second line, the collection foreach command is used to iterate over each object in the colVar collection.

itr is the name of the iterator variable.

Curly braces { } enclose the body, which is the script that executes at each iteration. Note that the object name command is nested in the body to return the value of the iterator variable, which is an instance in this case.

Tcl Commands for Advanced Scripting

Tcl Return: An integer return of the number of times the script was executed.

Caution!

collections. You must use the Xilinx-specific collection foreach command. Using the Tcl-supplied foreach command may cause the collection to be deleted.

You cannot use the standard Tcl-supplied foreach command to iterate over

get (get collection property)

The collection get command returns the value of the specified collection property. Collection properties and values are assigned with the collection set command.

collection get <property_name>

collection is the name of the Xilinx Tcl command.

get is the name of the collection subcommand.

property_name specifies the name of the property you wish to get the value of. Valid

property names for the collection get command are display_line_limit and display_type.

Example: % collection get display_type

Description: In this example, the collection get command is used to get the current

setting of the display_type property.

Tcl Return: The set value of the specified property.

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Note: See also the collection set command for more information on property values for the

collection command.

index (extract a collection object)

Given a collection and an index into it, the collection index command extracts the object at the specified index and returns the object, if the index is in range. The base collection is unchanged.

The range for an index is zero (0) to one less (-1) the size of the collection obtained with the collection sizeof command. See “sizeof (show the number of objects in a collection).”

collection index <collection_variable> <index>

collection is the name of the Xilinx Tcl command.

index is the name of the collection subcommand.

collection_variable specifies the name of the collection for index.

index specifies the index into the collection. Index values are 0 to -1, unless the size of the

collection was defined with the collection sizeof command.

Example: % set colVar [search * -type instance]

% set item [collection index $colVar 2]

% object name $item

Description: In this example, the collection index command extracts the third object

in the collection of instances.

In the first line, the set command is used to create a collection variable named colVar. The nested search command defines the value of the collection for colVar, which in this case is all of the instances in the current design.

In the second line, the set command is used to create a variable named item. The nested collection index command obtains the third object (starting with index 0, 1, 2 . . .) in the given collection.

The last line of this example uses the object name command to return the value of the item variable, which is the specified value of index.

Tcl Return: The object at the specified index.

Note:

on the collection, but they do generate the objects in the same, predictable order each time. Applications that support sorting collections, can impose a specific order on a collection.

Xilinx-specific Tcl commands that create a collection of objects do not impose a specific order

properties (list available collection properties)

The collection properties command displays a list of the supported properties for all collections in the current ISE project. You can set the value of any property with the collection set command.

% collection properties

collection is the name of the Xilinx Tcl command.

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Tcl Commands for Advanced Scripting

properties is the name of the collection subcommand. There are two collection properties: display_line_limit and display_type. These properties are supported with the collection get and collection set commands.

Example: % collection properties

Description: In this example, the collection properties command is used to display a

list of available collection properties.

Tcl Return: A list of available collection properties. In this example,

display_line_limit and display_type.

Note:

See the collection get command for a list of available properties.

remove_from (remove objects from a collection)

The collection remove_from command removes objects from a specified collection, modifying the collection in place. If you do not wish to modify the existing collection, first use the collection copy command to create a duplicate of the collection.

% collection remove_from <collection_variable> <objects_to_remove>

collection is the name of the Xilinx TCL command.

remove_from is the name of the collection subcommand.

collection_variable specifies the name of the collection variable.

objects_to_remove specifies a collection of objects, or the name of an object that you wish to

remove from the collection.

Example:

Description: In this example, the set command is first used to create the collection

% set colVar_1 [search * -type instance]

% set colVar_2 [search /stopwatch/s* -type instance]

% set colVar_3 [collection remove_from colVar_1 $colVar_2]

variables colVar_1 and colVar_2. Assume that the values of these two variables are different.

The last line of this example, creates a third collection variable, colVar_3 that contains all of the instances in colVar_1, but no instances in colVar_2.

Tcl Return: The original collection modified by removed elements. In this

example, the objects in colVar_2 are removed from colVar_1.

set (set the property for all collections)

The collection set command sets the specified property for all collection variables in the current ISE project.

% collection set <property_name> <property_value>

collection is the name of the Xilinx Tcl command.

set is the name of the collection subcommand.

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property_name and property_value specify the property name and value for all of the collection variables in the current ISE project. There are two available property settings for the collection set command, they are:

display_line_limit–specifies the number of lines that can be displayed by a collection variable. This property setting is useful for very large collections, which may have thousands, if not millions of objects. The default value for this property is 100. The minimum value is 0. There is no maximum value limit for this property.

display_type–instructs Tcl to include the object type in the display of objects from any specified collection variable. Values for this property are true and false. By default, this option is set to false, which means object types are not displayed. See the example below.

Example: % collection set display_type true

Description: In this example, the collection set command is used to set the property

name and value for all collection variables in the project.

display_type is the name of the property setting.

true specifies the value for the property.

Tcl Return: The previous value of the property.

sizeof (show the number of objects in a collection)

The collection sizeof command returns the number of objects in the specified collection.

% collection sizeof <collection_variable>

collection is the name of the Xilinx Tcl command.

sizeof is the name of the collection subcommand.

collection variable specifies the name of the collection for Tcl to return the size of.

Example: % collection sizeof $colVar

Description: In this example, the collection sizeof command is used to return the

size of the collection, which is referenced by the colVar collection variable.

Tcl Return: An integer return of the number of items in the specified collection.

object (get object information)

The object command returns the name, type, or property information of any Xilinx Tcl object in the current ISE project. You can specify a single object or an object from a collection of objects.

% object <subcommand>

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get (get object properties)

The object get command returns the value of the specified property.

% object get <object_name> <property_name>

object is the name of the Xilinx Tcl command.

name is the name of the object subcommand.

object_name specifies the object to get the property of. The object name will always be a Tcl

variable. The set command is used to create a Tcl variable, as shown in the following example.

property_name specifies the name of one of the properties of an object. The properties of an object vary depending on the type of object. Use the object properties command to get a list of valid properties for a specific object.

Example: % set colVar [search * -type instance]

Tcl Commands for Advanced Scripting

% collection foreach obj $colVar {set objProps [object properties $obj] foreach prop $objProps {puts [object get $obj $prop]}}

Description: This example first runs a search to create a collection of all instances

in the project. The second statement iterates through the objects in the collection. For each object, the list of available properties on the object are obtained by the object properties command. Then, the value of each property for each of the objects is returned.

Tcl Return: The value of the specified property.

name (name of the object)

The object name command returns the name of any Xilinx object. This command is useful when manipulating a collection of objects, which may have been returned from a search. The object name command can be used to narrow the collection.

% object name <object_name>

object is the name of the Xilinx Tcl command.

name is the name of the object subcommand.

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object_name specifies the object to return the name of. The object name will always be a string. The set command can be used to create a Tcl variable, as shown in the following example.

Example: % set colVar [search * -type instance]

% object name [collection index $colVar 1]

Description: In this example, the set command is first used to create the colVar

collection variable. The nested search command defines the value of the collection variable to be all instances in the current ISE project.

In the second line, the object name command is used to get the name of the second object in the collection. The collection index command defines which object to get, where:

$colvar specifies the collection to get the object from.

1 specifies the index into the collection. In this case, the second object

in the collection is returned because index values start at 0. See the collection index command for more information.

Tcl Return: The name of the object as a text string.

properties (list object properties)

The object properties command lists the available properties for the specified object.

% object properties <object_name>

object is the name of the Xilinx Tcl command.

name is the name of the object subcommand.

object_name specifies the object to list the properties of. The object name will always be a Tcl

variable created with the Tcl set command.

Example: % set colVar [search * -type partition]

% collection foreach obj $colVar {set objProps [object properties $obj] foreach prop $objProps {puts [object get $obj $prop]}}

Description: This example first runs a search to create a collection of objects. The

second statement iterates through the objects in the collection. For each object, a list of available properties for the object are obtained with the object properties command. Then, the value of each property is returned for each object.

Tcl Return: The available object properties as a text string.

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type (type of object)

The object type command returns the type of any Xilinx object.

% object type <object_name>

object is the name of the Xilinx Tcl command.

name is the name of the object subcommand.

object_name specifies the object to return the type of. The object name will always be a Tcl

variable. The set command is used to create a Tcl variable, as shown in the following example.

Example: % set colVar [search * -type instance]

Description: In this example, the set command is first used to create the colVar

Tcl Commands for Advanced Scripting

% object type [collection index $colVar 1]

collection variable. The nested search command defines the value of the collection variable.

In the second line, the object type command is used to get the type information for the object in the collection. The collection index command defines which object to get, where:

$colvar specifies the collection to get the object from.

1 specifies the index into the collection. In this case, the second object

in the collection is returned because index values start at 0. See the collection index command for more information.

Tcl Return: The type of the object as a text string.

search (search and return matching objects)

The search command is used to search for specific design objects that match a specified pattern.

search <pattern_string> [-exactmatch][-matchcase][-regexp][-type <object_type>]

search is the name of the Xilinx Tcl command.

pattern_string specifies a string to be used for the search. In Tcl, a string is distinguished on

the command line with double quotes (“). This string may contain regular expressions.

-exactmatch specifies that any matches found by the search, should match the pattern string

exactly.

-matchcase specifies that the search is case-sensitive.

-regexp specifies that the pattern string uses regular expressions. If not specified, the

matching is simple matching.

-type <object_type> specifies what type of design objects to search for. Supported search

types are partition and instance.

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Example: % search “/stopwatch” -type instance

Description: In this example, the search command is used to find all instances in

the design.

Tcl Return: A collection of objects that match the search criteria. If no matches

are found, an empty collection is returned.

Note: Use the collection foreach command to list or get access to each object in a collection. See

foreach (iterate over elements in a collection) for more information.

Project Properties and Options

This following tables list all of the available project properties and batch tool options. The first table lists all of the project properties. The remaining tables list all of the supported batch tool options, by Xilinx synthesis or implementation tool.

Batch tool options are listed as text strings, which are distinguished by double quotes (“) on the command line. The exact string representation, as shown in Project Navigator, is required.

Table 3-6: Project Properties

Property Name Description

device The device to use for the project.

family The device family to use for the project.

generated_simulation_language The language of the generated simulation netlist.

name Name of the project.

package The device package to use for the project.

speed The device speed grade to use for the project.

synthesis_tool The synthesis tool to use for this project. The default

tool to use is XST.

top The top-level design module or entity.

top_level_module_type The module type of the top-level source.

Table 3-7: XST Options

Option Name Synthesis Tool

“Add I/O Buffers” XST

“Bus Delimiter” XST

“Case Implementation Style” XST

“Case” CST

“Constrain Placement” XST

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Table 3-7: XST Options

Option Name Synthesis Tool

“Cores Search Directories” XST

“Cross Clock Analysis” XST

“Custom Compile File List” XST

“Decoder Extraction” XST

“Equivalent Register Removal” XST

“FSM Encoding Algorithm” XST

“FSM Style” XST

“Generate RTL Schematic” XST

“Global Optimization Goal” XST

“HDL INI File” XST

“Hierarchy Separator” XST

“Keep Hierarchy” XST

“Library Search Order” XST

“Logical Shifter Extraction” XST

“Max Fanout” XST

“Move First Flip-Flop Stage” XST

“Move Last Flip-Flop Stage” XST

“Mux Extraction” XST

“Mux Style” XST

“Number of Global Clock Buffers” XST

“Number of Regional Clock Buffers” XST

“Optimization Effort” XST

“Optimization Goal” XST

“Optimize Instantiated Primitives” XST

“Other XST Command Line Options” XST

“Pack I/O Registers into IOBs” XST

“Priority Encoder Extraction” XST

“RAM Extraction” XST

“RAM Style” XST

“Read Cores” XST

“Register Balancing” XST

“Register Duplication” XST

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Table 3-7: XST Options

Option Name Synthesis Tool

“Resource Sharing” XST

“ROM Extraction” XST

“ROM Style” XST

“Safe Implementation” XST

“Shift Register Extraction” XST

“Slice Packing” XST

“Slice Utilization Ration” XST

“Synthesis Constraints File” XST

“Use Clock Enable” XST

“Use DSP48” XST

“Use Synchronous Reset” XST

“Use Synchronous Set” XST

“Use Synthesis Constraints File” XST

“Verilog 2001” XST

“Verilog Include Directories” XST

“Work Directory” XST

“Write Timing Constraints” XST

“XOR Collapsing” XST

Table 3-8: NGDBuild Options

Option Name Implementation Tool

“Allow Unexpanded Blocks” NGDBuild

“Allow Unmatched LOC Constraints” NGDBuild

“Create I/O Pads from Ports” NGDBuild

“Macro Search Path” NGDBuild

“Netlist Translation Type” NGDBuild

“Other NGDBuild Command Line Options” NGDBuild

“Preserve Hierarchy on SubModule” NGDBuild

“Use LOC Constraints” NGDBuild

“Use Rules File for Netlister Launcher” NGDBuild

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Project Properties and Options

Table 3-9: MAP Options

Option Name Implementation Tool

“Allow Logic Optimization Across Hierarchy” MAP

“CLB Pack Factor Percentage” MAP

“Disable Register Ordering” MAP

“Equivalent Register Removal” MAP

“Extra Effort” MAP

“Generate Detailed MAP Report” MAP

“Global Optimization” MAP

“Map Effort Level” MAP

“Map Guide Design File (.ncd)” MAP

“Map Guide Mode” MAP

“Map Slice Logic into Unused Block RAMs” MAP

“Map to Input Functions” MAP

“Optimization Strategy (Cover Mode)” MAP

“Other Map Command Line Options” MAP

“Pack I/O Registers/Latches into IOBs” MAP

“Perform Timing-Driven Packing and Placement” MAP

“Register Duplication” MAP

“Replicate Logic to Allow Logic Level Reduction” MAP

“Retiming” MAP

“Starting Placer Cost Table (1-100)” MAP

“Trim Unconnected Signals” MAP

“Use RLOC Constraints” MAP

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Table 3-10: PAR Options

Option Name Implementation Tool

“Extra Effort (Highest PAR level only)” PAR

“Generate Asynchronous Delay Report” PAR

“Generate Clock Region Report” PAR

“Generate Post-Place & Route Simulation Model” PAR

“Generate Post-Place & Route Static Timing Report” PAR

“Nodelist File (Unix Only)” PAR

“Number of PAR Iterations (1-100)” PAR

“Number of Results to Save (0-100)” PAR

“Other Place & Route Command Line Options” PAR

“PAR Guide Design File (.ncd)” PAR

“PAR Guide Mode” PAR

“Place & Route Effort Level (Overall)” PAR

“Place and Route Mode” PAR

“Place Effort Level (Overrides Overall Level)” PAR

“Power Reduction” PAR

“Router Effort Level (Overrides Overall Level)” PAR

“Save Results in Directory (.dir will be appended)” PAR

“Starting Placer Cost Table (1-100)” PAR

“Use Bonded I/Os” PAR

“Using Timing Constraints” PAR

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Example Tcl Scripts

This section provides two example Tcl scripts. The first example is a “Sample Tcl Script for

General Usage”. The second example is a “Sample Tcl Script for Advanced Scripting”.

You can run these example Tcl scripts the following ways:

• Enter each statement interactively at the xtclsh prompt (%).

You can access the xtclsh prompt (%) from the command line by typing xtclsh, or from the Tcl Console tab in Project Navigator.

• Save the statements in a script file with a .tcl extension. To run the Tcl script, type the following from the xtclsh prompt (%):

% source <script_name>.tcl

Sample Tcl Script for General Usage

# open the project and set project-level properties

project new watchvhd.ise

project set family Virtex2P

project set device xc2vp2

project set package fg256

project set speed -7

Example Tcl Scripts

# add all the source HDLs and ucf

xfile add stopwatch.vhd statmatch.vhd cnt60.vhd dcm1.vhd decode.vhd

xfile add tenths.vhd hex2led

xfile add watchvhd.ucf

# define all partitions

partition new /stopwatch/MACHINE

partition new /stopwatch/Inst_dcm1

partition new /stopwatch/XCOUNTER

partition new /stopwatch/decoder

partition new /stopwatch/sixty

partition new /stopwatch/lsbled

partition new /stopwatch/msbled

# get partition properties

set props [partition properties]

puts "Partition Properties : $props"

# get top

set top [project get top]

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# get project properties available

set props2 [project properties]

puts "Project Properties for top-level module $top" $props2

# inspect the current value for the following batch application options

set map_guide_mode [project get "MAP Guide Mode"]

puts "MAP Guide Mode = $map_guide_mode"

set par_guide_mode [project get "PAR Guide Mode"]

puts "PAR Guide Mode = $par_guide_mode"

# set batch application options :

# 1. set synthesis optimization goal to speed

# 2. ignore any LOCs in ngdbuild

# 3. perform timing-driven packing

# 4. use the highest par effort level

# 5. set the par extra effort level

# 6. pass "-instyle xflow" to the par command-line

# 7. generate a verbose report from trce

# 8. create the IEEE 1532 file during bitgen

project set "Optimization Goal" Speed

project set "Use LOC Constraints" false

project set "Perform Timing-Driven Packing and Placement" TRUE

project set "Place & Route Effort Level (Overall)" High

project set "Extra Effort (Highest (PAR level only)" "Continue on Impossible"

project set "Other Place & Route Command Line Options" "-intsyle xflow"

project set "Report Type" "Verbose Report"

project set "Create IEEE 1532 Configuration File" TRUE

# run the entire xst-to-trce flow

process run "Implement Design"

# close project

project close

# open project again

project open

# alter some partition properties

partition rerun /stopwatch/sixty implementation

partition rerun /stopwatch/lsbled synthesis

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# rerun with only out-of-date partitions re-implemented

process run "Implement Design"

# close project

project close

Sample Tcl Script for Advanced Scripting

# create a new project and set device properties

project new watchvhd.ise

project set family virtex2p

project set device xc2VP2

project set package fG25

project get package

project set speed -7

Example Tcl Scripts

# add the watch vhd files

xfile add dve_ccir_top.v

xfile add stopwatch.vhd statmatch.vhd cnt60.vhd dcm1.vhd decode.vhd

xfile add tenths.vhd hex2led.vhd watchvhd.ucf

# check that no partitions are present yet

set dus [search * -type partition]

# search for all design instances

set dus [search * -type instance]

# display all design instances

collection foreach du $dus {

puts "Name [object name $du], Type [object type $du]"

}

# confine search to the top-level instances only

set dus [search {/[^/]+/[^/]+} -type instance -regexp -exactmatch]

# define partitions for all the toplevel instances in the design (note that the last partition created is returned)

partition new [search {/[^/]+/[^/]+} -type instance -regexp exactmatch]

# check that we created something

search * -type partition

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# run with default values

process run "Implement Design"

# close project

project close

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Xilinx Development System User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Development System Reference Guide

About This Guide

Guide Contents

Additional Resources

Conventions

Typographical

Online Document

Table of Contents

Introduction

Command Line Program Overview

Command Line Syntax

Command Line Options

–f (Execute Commands File)

–h (Help)

–intstyle (Integration Style)

–p (Part Number)

Invoking Command Line Programs

Design Flow

Design Flow Overview

Design Entry and Synthesis

Hierarchical Design

Schematic Entry Overview

Library Elements

CORE Generator Tool (FPGAs Only)

HDL Entry and Synthesis

Functional Simulation

Constraints

Mapping Constraints (FPGAs Only)

Block Placement

Timing Specifications

Netlist Translation Programs

Design Implementation

Mapping (FPGAs Only)

Placing and Routing (FPGAs Only)

Bitstream Generation (FPGAs Only)

Design Verification

Simulation

Back-Annotation

NetGen

Schematic-Based Simulation

HDL-Based Simulation

Static Timing Analysis (FPGAs Only)

In-Circuit Verification

Design Rule Checker (FPGAs Only)

Xilinx Design Download Cables

Probe

ChipScope ILA and ChipScope PRO

FPGA Design Tips

Design Size and Performance

Global Clock Distribution

Data Feedback and Clock Enable

Counters

Other Synchronous Design Considerations

Tcl

Tcl Overview

Xilinx Tcl Shell

Accessing Help

Tcl Fundamentals

Xilinx Namespace

Xilinx Tcl Commands

Tcl Commands for General Usage

partition (support design preservation)

delete (delete a partition)

get (get partition properties)

new (create a new partition)

properties (list available partition properties)

rerun (force partition synthesis and implementation)

set (set partition preserve property)

process (run and manage project processes)

run (run process task)

project (create and manage projects)

clean (remove system-generated project files)

close (close the ISE project)

get (get project properties)

get_processes (get project processes)

new (create a new ISE project)