XILINX Command Line Tools User Guide

CommandLineToolsUser Guide

(FormerlytheDevelopmentSystemReferenceGuide)

UG628(v13.1)March2,2011

Xilinxisdisclosingthisuserguide,manual,releasenote,and/orspecication(the“Documentation”)toyou solelyforuseinthedevelopmentofdesignstooperatewithXilinxhardwaredevices.Youmaynotreproduce, distribute,republish,download,display,post,ortransmittheDocumentationinanyformorbyanymeans including,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withouttheprior writtenconsentofXilinx.XilinxexpresslydisclaimsanyliabilityarisingoutofyouruseoftheDocumentation. Xilinxreservestheright,atitssolediscretion,tochangetheDocumentationwithoutnoticeatanytime.Xilinx assumesnoobligationtocorrectanyerrorscontainedintheDocumentation,ortoadviseyouofanycorrections orupdates.Xilinxexpresslydisclaimsanyliabilityinconnectionwithtechnicalsupportorassistancethatmaybe providedtoyouinconnectionwiththeInformation.

THEDOCUMENTATIONISDISCLOSEDTOYOU“ AS-IS”WITHNOWARRANTYOFANYKIND.XILINX MAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDING THEDOCUMENTA TION,INCLUDINGANYW ARRANTIESOFMERCHANTABILITY,FITNESSFORA PARTICULARPURPOSE,ORNONINFRINGEMENTOFTHIRD-PARTYRIGHTS.INNOEVENTWILL XILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY ,SPECIAL,ORINCIDENTAL DAMAGES,INCLUDINGANYLOSSOFDATAORLOSTPROFITS,ARISINGFROMYOURUSEOFTHE DOCUMENTA TION.

©Copyright2002-2011XilinxInc.AllRightsReserved.XILINX,theXilinxlogo,theBrandWindowandother designatedbrandsincludedhereinaretrademarksofXilinx,Inc.Allothertrademarksarethepropertyoftheir respectiveowners.ThePowerPCnameandlogoareregisteredtrademarksofIBMCorp.,andusedunderlicense. Allothertrademarksarethepropertyoftheirrespectiveowners.

RevisionHistory

Thefollowingtableshowstherevisionhistoryforthisdocument.

Date

03/01/2011

03/02/2011

Version

13.1downloadAddinginformationforXilinx®7seriesFPGAdevices.

13.1WebreleaseAdditionalupdatesforXilinx7seriesFPGAdevices.

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CommandLineToolsUserGuide

Youcanruntheseprogramsinthestandarddesignoworusespecialoptionstorunthe programsfordesignpreservation.Eachcommandlineprogramhasmultipleoptions, whichallowyoutocontrolhowaprogramexecutes.Forexample,youcansetoptionsto changeoutputlenames,tosetapartnumberforyourdesign,ortospecifylestoread inwhenexecutingtheprogram.Youcanalsouseoptionstocreateguidelesandrun guidemodetomaintaintheperformanceofapreviouslyimplementeddesign.

Someofthecommandlineprogramsdescribedinthisguideunderliemanyofthe XilinxGraphicalUserInterfaces(GUIs).TheGUIscanbeusedwiththecommand lineprogramsoralone.ForinformationontheGUIs,seetheonlineHelpprovided witheachXilinxtool.

MAP NoteMAPusesspeciedoptionstoenable

timing-drivenplacementandrouting (-timing),andre-synthesisandphysical synthesisoptimizationsthatcantransforma designtomeettimingrequirements.

NetGen

TRACE

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Chapter1:Introduction

CommandLineSyntax

Commandlinesyntaxalwaysbeginswiththecommandlineprogramname.The programnameisfollowedbyanyoptionsandthenbylenames.Usethefollowing ruleswhenspecifyingcommandlineoptions:

•Enteroptionsinanyorder,precededthemwithadash(minussignonthekeyboard) andseparatethemwithspaces.

•Beconsistentwithuppercaseandlowercase.

•Whenanoptionrequiresaparameter,separatetheparameterfromtheoptionby spacesortabs.Forexample,thefollowingshowsthecommandlinesyntaxfor runningPARwiththeeffortlevelsettohigh:

–Correct:par-olhigh –Incorrect:par-olhigh

•Whenusingoptionsthatcanbespeciedmultipletimes,precedeeachparameter withtheoptionletter.Inthisexample,the-loptionshowsthelistoflibrariesto search:

–Correct:-lxilinxun-lsynopsys –Incorrect:-lxilinxunsynopsys

•Enterparametersthatareboundtoanoptionaftertheoption. –Correct:-fcommand_file –Incorrect:command_file-f

CommandLineOptions

-f(ExecuteCommandsFile)

Usethefollowingruleswhenspecifyinglenames:

•Enterlenamesintheorderspeciedinthechapterthatdescribesthecommand lineprogram.Inthisexamplethecorrectorderisprogram,inputle,outputle, andthenphysicalconstraintsle.

–Correct:parinput.ncdoutput.ncdfreq.pcf –Incorrect:parinput.ncdfreq.pcfoutput.ncd

•Uselowercaseforallleextensions(forexample,.ncd).

Thefollowingoptionsarecommontomanyofthecommandlineprogramsprovided withtheISE®DesignSuite.

•-f(ExecuteCommandsFile)

•-h(Help)

•-intstyle(IntegrationStyle)

•-p(PartNumber)

WithanyXilinx®commandlineprogramforusewithFPGAdesigns,youcanstore commandlineprogramoptionsandlenamesinacommandle.Youcanthenexecute theargumentsbyenteringtheprogramnamewiththe-foptionfollowedbythename ofthecommandle.Thisisusefulifyoufrequentlyexecutethesameargumentseach timeyouexecuteaprogramorifthecommandlinecommandbecomestoolong.

Syntax

-fcommand_file

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Chapter1:Introduction

Youcanusetheleinthefollowingways:

•Tosupplyallofthecommandoptionsandlenamesfortheprogram,asinthe followingexample:

par-fcommand_le

command_leisthenameofthelethatcontainsthecommandoptionsandle

names.

•Toinsertcertaincommandoptionsandlenameswithinthecommandline,asin thefollowingexample:

par-fplaceoptions-frouteoptionsdesign_i.ncddesign_o.ncd

–placeoptionsisthenameofalecontainingplacementcommandparameters.

–routeoptionsisthenameofalecontainingroutingcommandparameters.

YoucreatethecommandleinASCIIformat.Usethefollowingruleswhencreating thecommandle:

•Separateprogramoptionsandlenameswithspaces.

•Precedecommentswiththepoundsign(#).

•PutnewlinesortabsanywherewhitespaceisallowedontheLinuxorDOS commandline.

•Putallargumentsonthesameline,oneargumentperline,oracombinationofthese.

•Allcarriagereturnsandothernon-printablecharactersaretreatedasspacesand ignored.

•Nolinelengthlimitationexistswithinthele.

Example

Followingisanexampleofacommandle:

#commandlineoptionsforparfordesignmine.ncd

-w

0l5 /home/yourname/designs/xilinx/mine.ncd #directoryforoutputdesigns /home/yourname/designs/xilinx/output.dir #usetimingconstraintsfile /home/yourname/designs/xilinx/mine.pcf

-h(Help)

Whenyouentertheprogramnamefollowedbythisoption,youwillgetamessage listingalloptionsfortheprogramandtheirparameters,aswellastheletypesusedby theprogram.Themessagealsoexplainseachoftheoptions.

Syntax

-h

-help

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Chapter1:Introduction

SymbolDescription

[]

{}

italicsIndicatesavariablenameornumberforwhich

()

Enclosesitemsthatareoptional.

Enclosesitemsthatmayberepeated.

youmustsubstituteinformation.

Showsarangeforanintegervariable.

Showsthestartofanoptionname.

Bindsavariablenametoarange.

LogicalORtoshowachoiceofoneoutof manyitems.TheORoperatormayonly separatelogicalgroupsorliteralkeywords.

Enclosesalogicalgroupingforachoice betweensub-formats.

Example

Followingareexamplesofsyntaxusedforlenames:

•inle[.ncd]showsthattypingthe.ncdextensionisoptionalbutthattheextension mustbe.ncd.

•inle.ednshowsthatthe.ednextensionisoptionalandisappendedonlyifthere isnootherextensioninthelename.

Forarchitecture-specicprograms,suchasBitGen,youcanenterthefollowingtogeta verbosehelpmessageforthespeciedarchitecture:

program_name-harchitecture_name

Youcanredirectthehelpmessagetoaletoreadlaterortoprintoutbyenteringthe following:

program_name-h>lename

OntheLinuxcommandline,enterthefollowingtoredirectthehelpmessagetoale andreturntothecommandprompt.

program_name-h>&lename

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

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Chapter1:Introduction

-p(PartNumber)

Thisoptionspeciesthepartintowhichyourdesignisimplemented.

Syntax

-ppart_number

Thisoptioncanspecifyanarchitectureonly,acompletepartspecication(device, package,andspeed),orapartialspecication(forexample,deviceandpackageonly). Thepartnumberordevicenamemustbefromadevicelibraryyouhaveinstalledon yoursystem.

AcompleteXilinx®partnumberconsistsofthefollowingelements:

•Architecture(forexample,spartan3e)

•Device(forexample,xc3s100e)

•Package(forexample,vq100)

•Speed(forexample,-4)

NoteTheSpeedprintprogramlistsblockdelaysfordevicespeedgrades.The-soption

letsyouspecifyaspeedgrade.Ifyoudonotspecifyaspeedgrade,Speedprintreports thedefaultspeedgradeforthedeviceyouaretargeting.

SpecifyingPartNumbers

Youcanspecifyapartnumberatvariouspointsinthedesignow,notallofwhich requirethe-poption.

•Intheinputnetlist(doesnotrequirethe-poption)

•InaNetlistConstraintsFile(NCF)(doesnotrequirethe-poption)

•Withthe-poptionwhenyourunanetlistreader(EDIF2NGD)

•IntheUserConstraintsFile(UCF)(doesnotrequirethe-poption)

•Withthe-poptionwhenyourunNGDBuild

BythetimeyourunNGDBuild,youmusthavealreadyspeciedadevice architecture.

•Withthe-poptionwhenyourunMAP

WhenyourunMAPyoumustspecifyanarchitecture,device,andpackage,either ontheMAPcommandlineorearlierinthedesignow.Ifyoudonotspecifya speed,MAPselectsadefaultspeed.YoucanonlyrunMAPusingapartnumber fromthearchitectureyouspeciedwhenyouranNGCBuild.

•Withthe-poptionwhenyourunSmartXplorer(FPGAdesignsonly)

•Withthe-poptionwhenyourunCPLDFit(CPLDdesignsonly)

NotePartnumbersspeciedinalaterstepofthedesignowoverrideapartnumber

speciedinanearlierstep.Forexample,apartspeciedwhenyourunMAPoverridesa partspeciedintheinputnetlist.

Examples

Thefollowingexamplesshowhowtospecifypartsonthecommandline.

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Chapter1:Introduction

SpeciﬁcationExamples

Architectureonly

Deviceonlyxc4vfx12

DevicePackagexc4fx12sf363

Device-Packagexc4vfx12-sf363

DeviceSpeed-Packagexc4vfx1210-sf363

DevicePackage-Speedxc4fx12sf363-10

Device-Speed-Packagexc4vfx12-10-sf363

Device-SpeedPackagexc4vfx12-10sf363

virtex4 virtex5 spartan3 spartan3a xc9500 xpla3(CoolRunner™XPLA3devices)

xc3s100e

xc3s100evq100

xc3s100e-vq100

xc3s100e4-vq100

xc3s100evq100-4

xc3s100e-4-vq100

xc3s100e-4vq100

InvokingCommandLinePrograms

YoustartXilinx®commandlineprogramsbyenteringacommandattheLinuxorDOS commandline.Seetheprogram-specicchaptersinthisbookfortheappropriatesyntax

XilinxalsoofferstheXFLOWprogram,whichletsyouautomatetherunningofseveral programsatonetime.SeetheXFLOWchapterformoreinformation.

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DesignFlow

Thischapterdescribestheprocessforcreating,implementing,verifying,and downloadingdesignsforXilinx®FPGAandCPLDdevices.Foracomplete descriptionofXilinxFPGAandCPLDsdevices,refertotheXilinxDataSheetsat:

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DesignFlowOverview

Thestandarddesignowcomprisesthefollowingsteps:

1.DesignEntryandSynthesis-CreateyourdesignusingaXilinx®-supported schematiceditor,aHardwareDescriptionLanguage(HDL)fortext-basedentry ,or both.IfyouuseanHDLfortext-basedentry ,youmustsynthesizetheHDLleinto anEDIFleor,ifyouareusingtheXilinxSynthesisTechnology(XST)GUI,you mustsynthesizetheHDLleintoanNGCle.

2.DesignImplementation-Convertthelogicaldesignleformat,suchasEDIF ,that youcreatedinthedesignentryandsynthesisstageintoaphysicalleformatby implementingtoaspecicXilinxarchitecture.Thephysicalinformationiscontained intheNativeCircuitDescription(NCD)leforFPGAsandtheVM6leforCPLDs. ThencreateabitstreamlefromtheselesandoptionallyprogramaPROMor EPROMforsubsequentprogrammingofyourXilinxdevice.

3.DesignV erication-Usingagate-levelsimulatororcable,ensurethatyourdesign meetstimingrequirementsandfunctionsproperly .SeetheiMPACTonlinehelpfor informationaboutXilinxdownloadcablesanddemonstrationboards.

Chapter2

Thefulldesignowisaniterativeprocessofentering,implementing,andverifying yourdesignuntilitiscorrectandcomplete.Thecommandlinetoolsprovidedwiththe ISE®DesignSuiteallowquickdesigniterationsthroughthedesignowcycle.Xilinx devicespermitunlimitedreprogramming.Youdonotneedtodiscarddeviceswhen debuggingyourdesignincircuit.

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Chapter2:DesignFlow

XilinxDesignFlow

ThisgureshowsthestandardXilinxdesignow.

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XilinxSoftwareDesignFlow(FPGAs)

ThisgureshowstheXilinxsoftwareowchartforFPGAdesigns.

Chapter2:DesignFlow

XilinxSoftwareDesignFlow(CPLDs)

ThisgureshowstheXilinxsoftwareowchartforCPLDdesigns.

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Chapter2:DesignFlow

DesignEntryandSynthesis

Youcanenteradesignwithaschematiceditororatext-basedtool.Designentrybegins withadesignconcept,expressedasadrawingorfunctionaldescription.Fromthe originaldesign,anetlistiscreated,thensynthesizedandtranslatedintoanativegeneric object(NGO)le.ThisleisfedintotheXilinx®softwareprogramcalledNGDBuild, whichproducesalogicalNativeGenericDatabase(NGD)le.

Thefollowinggureshowsthedesignentryandsynthesisprocess.

DesignEntryFlow

HierarchicalDesign

DesignhierarchyisimportantinbothschematicandHDLentryforthefollowing reasons:

•Helpsyouconceptualizeyourdesign

•Addsstructuretoyourdesign

•Promoteseasierdesigndebugging

•Makesiteasiertocombinedifferentdesignentrymethods(schematic,HDL,orstate editor)fordifferentpartsofyourdesign

•Makesiteasiertodesignincrementally ,whichconsistsofdesigning,implementing, andverifyingindividualpartsofadesigninstages

•Reducesoptimizationtime

•Facilitatesconcurrentdesign,whichistheprocessofdividingadesignamonga numberofpeoplewhodevelopdifferentpartsofthedesigninparallel.

Inhierarchicaldesigning,aspecichierarchicalnameidentieseachlibraryelement, uniqueblock,andinstanceyoucreate.Thefollowingexampleshowsahierarchical namewitha2-inputORgateintherstinstanceofamultiplexerina4-bitcounter:

/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2

Xilinx®stronglyrecommendsthatyounamethecomponentsandnetsinyourdesign. ThesenamesarepreservedandusedbyFPGAEditor.Thesenamesarealsousedfor back-annotationandappearinthedebugandanalysistools.Ifyoudonotnameyour componentsandnets,theSchematicEditorautomaticallygeneratesthenames.For example,ifleftunnamed,thesoftwaremightnamethepreviousexample,asfollows:

/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57

NoteItisdifculttoanalyzecircuitswithautomaticallygeneratednames,becausethe

namesonlyhavemeaningforXilinxsoftware.

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Chapter2:DesignFlow

Partitions

Inhierarchicaldesignows,suchasDesignPreservationandPartialReconguration, partitionsareusedtodenehierarchicalboundariessothatacomplexdesigncanbe brokenupintosmallerblocks.Partitionscreateaboundaryorinsulationaroundthe hierarchicalmodule,whichisolatesthemodulefromotherpartsofthedesign.A partitionthathasbeenimplementedandexportedcanbere-insertedintothedesign usingasimplecut-and-pastetypefunction,whichpreservestheplacementandrouting resultsfortheisolatedmodule.Allofthepartitiondenitionsandcontrolsaredoneina lecalledxpartition.pxml.Formoreinformationonusinghierarchicaldesignows andimplementingpartitions,seetheHierarchicalDesignMethodologyGuide(UG748).

PXMLFile

Partitiondenitionsarecontainedinthexpartition.pxmlle.ThePXMLlename iscase-sensitive,andmustbenamedxpartition.pxml.Thetoplevelmodule ofthedesignmustbedenedasapartitioninadditiontoanyoptionallowerlevel partitions.ThePXMLlecanbecreatedbyhand,fromscripts,orfromatoolsuchas thePlanAhead™software.ThePXMLwillbepickedupautomaticallybytheISE® DesignSuiteimplementationtoolswhenlocatedinthecurrentworkingdirectory. Formoreinformationaboutusingthexpartition.pxmlle,seetheHierarchical

DesignMethodologyGuide(UG748).Anexamplexpartition.pxmlleisavailable

at%XILINX%/PlanAhead/testcases/templates(where%XILINX%isyour installationdirectory)ifyouwishtocreateaPXMLlebyhand.

NoteAllpathsinthePXMLlemustbeabsolutepaths.

<?xmlversion="1.0"encoding="UTF-8"?>

<ProjectFileVersion="1.2"Name="Example"ProjectVersion="2.0">

<PartitionName="/top"State="implement"ImportLocation="NONE">

<PartitionName="/top/module_A"State="import"ImportLocation="/home/user/Example/import"Preserve="routing"> </Partition> <PartitionName="/top/module_B"State="import"ImportLocation="/home/user/Example/import"Preserve="routing"> </Partition> <PartitionName="/top/module_C"State="implement"ImportLocation="/home/user/Example/import"Preserve="placement"> </Partition>

</Partition>

</Project>

PXMLattributesforProjectdeﬁnition

Attributename

FileVersion

Name

ProjectVersion2.0

Value

1.2

Project_Name

Description

Usedforinternalpurposes.Donotchangethis value.

Project_Nameisuserdened.

Usedforinternalpurposes.Donotchangethis value.

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Chapter2:DesignFlow

PXMLattributesforPartitiondeﬁnition

Attributename

Name

State

ImportLocation

ImportTag

Preserve

BoundaryOpt

Value

Partition_Name

“implement”Partitionisimplementedfromscratch.

“import”

pathIgnoredifStatedoesnotequal“import.”

Partition_Name

“routing”

“placement”Placementispreservedbutroutingcanbe

“synthesis”Placementandroutingcanbemodied.

“inherit”Inheritvaluefromtheparentpartition.Thisis

“all”Enablestheimplementationtoolstodo

“none”

Description

Hierarchicalinstancenameofmoduleinwhich thepartitionshouldbeapplied.

Partitionisimportedandpreservedaccording tothelevelsetbyPreserve.

Thepathcanberelativeorabsolute,butthe locationspeciedmustcontainavalid"export" directorywhenState=import.“NONE”isa predenedkeywordfornoimportdirectory .

Allowsapartitiontobeimportedintoa differentlevelofhierarchythanitwasinitially implementedin.Setthevaluetothehierarchical instancenameofthepartitionwhereitwas implemented.

100%placementandroutingispreserved.This isthedefaultforthetoplevelPartition.

modied.

thedefaultforallpartitionsexceptthetoplevel partition.

optimizationonpartitionportsconnectedto constraintsaswellasunusedpartitionports.

Normalpartitionoptimizationrulesapply . Optimizationisallowedonlywithinpartition boundaries.Thisisthedefaultvalue.

SchematicEntryOverview

Schematictoolsprovideagraphicinterfacefordesignentry.Youcanusethesetoolsto connectsymbolsrepresentingthelogiccomponentsinyourdesign.Youcanbuildyour designwithindividualgates,oryoucancombinegatestocreatefunctionalblocks. Thissectionfocusesonwaystoenterfunctionalblocksusinglibraryelementsandthe COREGenerator™tool.

LibraryElements

Primitivesandmacrosarethe“buildingblocks”ofcomponentlibraries.Xilinx® librariesprovideprimitives,aswellascommonhigh-levelmacrofunctions.Primitives arebasiccircuitelements,suchasANDandORgates.Eachprimitivehasaunique libraryname,symbol,anddescription.Macroscontainmultiplelibraryelements,which canincludeprimitivesandothermacros.

YoucanusethefollowingtypesofmacroswithXilinxFPGAs:

•Softmacroshavepre-denedfunctionalitybuthaveexiblemapping,placement, androuting.SoftmacrosareavailableforallFPGAs.

•Relationallyplacedmacros(RPMs)havexedmappingandrelativeplacement. RPMsareavailableforalldevicefamilies,excepttheXC9500family .

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HDLEntryandSynthesis

Macrosarenotavailableforsynthesisbecausesynthesistoolshavetheirownmodule generatorsanddonotrequireRPMs.Ifyouwishtooverridethemodulegeneration,you caninstantiatemodulescreatedusingCOREGenerator.Formostleading-edgesynthesis tools,thisdoesnotofferanadvantageunlessitisforamodulethatcannotbeinferred.

COREGeneratorTool(FPGAsOnly)

TheXilinxCOREGeneratortooldeliversparameterizablecoresthatareoptimized forXilinxFPGAs.Thelibraryincludescoresrangingfromsimpledelayelementsto complexDSP(DigitalSignalProcessing)ltersandmultiplexers.Fordetails,refertothe COREGeneratorHelp(partofISEHelp).Y oucanalsorefertotheXilinxIP(Intellectual Property)CenterWebsiteath solutions.Thesesolutionsincludedesignreusetools,freereferencedesigns,Digital SignalProcessing(DSP),PCI™solutions,IPimplementationtools,cores,specialized systemlevelservices,andverticalapplicationIPsolutions.

AtypicalHardwareDescriptionLanguage(HDL)supportsamixed-leveldescriptionin whichgateandnetlistconstructsareusedwithfunctionaldescriptions.Thismixed-level capabilityletsyoudescribesystemarchitecturesatahighlevelofabstractionandthen incrementallyrenethedetailedgate-levelimplementationofadesign.

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Chapter2:DesignFlow

FunctionalSimulation

HDLdescriptionsofferthefollowingadvantages:

•Youcanverifydesignfunctionalityearlyinthedesignprocess.Adesignwrittenas anHDLdescriptioncanbesimulatedimmediately .Designsimulationatthishigh level,atthegate-levelbeforeimplementation,allowsyoutoevaluatearchitectural anddesigndecisions.

•AnHDLdescriptionismoreeasilyreadandunderstoodthananetlistorschematic description.HDLdescriptionsprovidetechnology-independentdocumentation ofadesignanditsfunctionality.BecausetheinitialHDLdesigndescriptionis technologyindependent,youcanuseitagaintogeneratethedesigninadifferent technology,withouthavingtotranslateitfromtheoriginaltechnology .

•LargedesignsareeasiertohandlewithHDLtoolsthanschematictools.

AfteryoucreateyourHDLdesign,youmustsynthesizeit.Duringsynthesis,behavioral informationintheHDLleistranslatedintoastructuralnetlist,andthedesignis optimizedforaXilinx®device.XilinxsupportsHDLsynthesistoolsforseveral third-partysynthesisvendors.Inaddition,Xilinxoffersitsownsynthesistool,Xilinx SynthesisTechnology(XST).Formoreinformation,seetheXSTUserGuideforVirtex-4,

Virtex-5,Spartan-3,andNewerCPLDDevices(UG627)ortheXSTUserGuideforVirtex-6, Spartan-6,and7SeriesDevices(UG687).Fordetailedinformationonsynthesis,seethe SynthesisandSimulationDesignGuide(UG626).

Afteryoucreateyourdesign,youcansimulateit.Functionalsimulationteststhe logicinyourdesigntodetermineifitworksproperly .Youcansavetimeduring subsequentdesignstepsifyouperformfunctionalsimulationearlyinthedesignow. SeeSimulationformoreinformation.

Constraints

Youmaywanttoconstrainyourdesignwithincertaintimingorplacementparameters. Youcanspecifymapping,blockplacement,andtimingspecications.

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Chapter2:DesignFlow

MappingConstraints(FPGAsOnly)

BlockPlacement

YoucanenterconstraintsmanuallyorusetheConstraintsEditororFPGAEditor,which aregraphicaluserinterface(GUI)toolsprovidedbyXilinx®.YoucanusetheTiming AnalyzerGUIorTRACEcommandlineprogramtoevaluatethecircuitagainstthese constraintsbygeneratingastatictiminganalysisofyourdesign.SeetheTRACEchapter andtheonlineHelpprovidedwiththeISE®DesignSuiteformoreinformation.For moreinformationonconstraints,seetheConstraintsGuide(UG625).

YoucanspecifyhowablockoflogicismappedintoCLBsusinganFMAPforall Spartan®andVirtex®FPGAarchitectures.Thesemappingsymbolscanbeusedin yourschematic.However,ifyouoverusethesespecications,itmaybedifcultto routeyourdesign.

Blockplacementcanbeconstrainedtoaspeciclocation,tooneofmultiplelocations,or toalocationrange.Locationscanbespeciedintheschematic,withsynthesistools, orintheUserConstraintsFile(UCF).Poorblockplacementcanadverselyaffectboth theplacementandtheroutingofadesign.OnlyI/Oblocksrequireplacementtomeet externalpinrequirements.

TimingSpeciﬁcations

Youcanspecifytimingrequirementsforpathsinyourdesign.PARusesthesetiming specicationstoachieveoptimumperformancewhenplacingandroutingyourdesign.

NetlistTranslationPrograms

NetlisttranslationprogramsletyoureadnetlistsintotheXilinx®softwaretools. EDIF2NGDletsyoureadanElectronicDataInterchangeFormat(EDIF)200le.The NGDBuildprogramautomaticallyinvokestheseprogramsasneededtoconvertyour EDIFletoanNGDle,therequiredformatfortheXilinxsoftwaretools.NGCles outputfromtheXilinxXSTsynthesistoolarereadinbyNGDBuilddirectly .

YoucannddetaileddescriptionsoftheEDIF2NGD,andNGDBuildprogramsinthe

NGDBuildchapterandtheEDIF2NGDandNGDBuildAppendix.

DesignImplementation

DesignImplementationbeginswiththemappingorttingofalogicaldesignletoa specicdeviceandiscompletewhenthephysicaldesignissuccessfullyroutedanda bitstreamisgenerated.Youcanalterconstraintsduringimplementationjustasyoudid duringtheDesignEntrystep.SeeConstraintsforinformation.

ThefollowinggureshowsthedesignimplementationprocessforFPGAdesigns:

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DesignImplementationFlow(FPGAs)

Chapter2:DesignFlow

ThefollowinggureshowsthedesignimplementationprocessforCPLDdesigns:

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Chapter2:DesignFlow

DesignImplementationFlow(CPLDs)

Mapping(FPGAsOnly)

ForFPGAs,theMAPcommandlineprogrammapsalogicaldesigntoaXilinx®FPGA. TheinputtoMAPisanNGDle,whichcontainsalogicaldescriptionofthedesignin termsofboththehierarchicalcomponentsusedtodevelopthedesignandthelower-level Xilinxprimitives,andanynumberofNMC(hardplaced-and-routedmacro)les,each ofwhichcontainsthedenitionofaphysicalmacro.MAPthenmapsthelogictothe components(logiccells,I/Ocells,andothercomponents)inthetargetXilinxFPGA.

TheoutputdesignfromMAPisanNCDle,whichisaphysicalrepresentationof thedesignmappedtothecomponentsintheXilinxFPGA.TheNCDlecanthenbe placedandrouted,usingthePARcommandlineprogram.SeetheMAPchapterfor detailedinformation.

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NoteMAPprovidesoptionsthatenableadvancedoptimizationsthatarecapable

ofimprovingtimingresultsbeyondstandardimplementations.Theseadvanced optimizationscantransformadesignpriortoorafterplacement.Optimizationscan beappliedattwodifferentstagesintheXilinxdesignow.Therststagehappens rightaftertheinitialmappingofthelogictothearchitectureslices;thesecondstageif afterplacement.SeeRe-SynthesisandPhysicalSynthesisOptimizationsintheMAP chapterformoreinformation.

PlacingandRouting(FPGAsOnly)

ForFPGAs,thePARcommandlineprogramtakesamappedNCDleasinput,places androutesthedesign,andoutputsaplacedandroutedNativeCircuitDescription (NCD)le,whichisusedbythebitstreamgenerator,BitGen.TheoutputNCDlecan alsoactasaguidelewhenyoureiterateplacementandroutingforadesigntowhich minorchangeshavebeenmadeafterthepreviousiteration.SeethePARchapterfor detailedinformation.

YoucanalsouseFPGAEditortodothefollowing:

•Placeandroutecriticalcomponentsbeforerunningautomaticplaceandroutetools onanentiredesign.

•Modifyplacementandroutingmanually.Theeditorallowsbothautomaticand manualcomponentplacementandrouting.

Chapter2:DesignFlow

NoteFormoreinformation,seetheonlineHelpprovidedwithFPGAEditor.

BitstreamGeneration(FPGAsOnly)

ForFPGAs,theBitGencommandlineprogramproducesabitstreamforXilinx® deviceconguration.BitGentakesafullyroutedNCDleasitsinputandproduces acongurationbitstream,whichisabinarylewitha.bitextension.TheBITle containsallofthecongurationinformationfromtheNCDledeningtheinternal logicandinterconnectionsoftheFPGA,plusdevice-specicinformationfromotherles associatedwiththetargetdevice.SeetheBitGenchapterfordetailedinformation.

AfteryougenerateyourBITle,youcandownloadittoadeviceusingtheiMPACTGUI. YoucanalsoformattheBITleintoaPROMleusingthePROMGencommandline programandthendownloadittoadeviceusingtheiMPACTGUI.SeethePROMGen

chapterofthisguideortheiMPACTonlinehelpformoreinformation.

DesignVeriﬁcation

Designvericationistestingthefunctionalityandperformanceofyourdesign.Y oucan verifyXilinx®designsinthefollowingways:

•Simulation(functionalandtiming)

•Statictiminganalysis

•In-circuitverication

Thefollowingtableliststhedifferentdesigntoolsusedforeachvericationtype.

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Chapter2:DesignFlow

VeriﬁcationTools

VeriﬁcationTypeTools

SimulationThird-partysimulators(integratedand

non-integrated)

StaticTimingAnalysisTRACE(commandlineprogram)

TimingAnalyzer(GUI)

MentorGraphicsTAUandInnovedaBLAST softwareforusewiththeSTAMPleformat (forI/Otimingvericationonly)

In-CircuitVericationDesignRuleChecker(commandlineprogram)

Downloadcable

Designvericationproceduresshouldoccurthroughoutyourdesignprocess,asshown inthefollowinggures.

ThreeVeriﬁcationMethodsoftheDesignFlow(FPGAs)

ThefollowinggureshowsthevericationmethodsofthedesignowforCPLDs.

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ThreeVeriﬁcationMethodsoftheDesignFlow(CPLDs)

Chapter2:DesignFlow

Simulation

Youcanrunfunctionalortimingsimulationtoverifyyourdesign.Thissectiondescribes theback-annotationprocessthatmustoccurpriortotimingsimulation.Italsodescribes thefunctionalandtimingsimulationmethodsforbothschematicandHDL-based designs.

Back-Annotation

Beforetimingsimulationcanoccur,thephysicaldesigninformationmustbetranslated anddistributedbacktothelogicaldesign.ForFPGAs,thisback-annotationprocessis donewithaprogramcalledNetGen.ForCPLDs,back-annotationisperformedwith theTSimTimingSimulator.Theseprogramscreateadatabase,whichtranslatesthe back-annotatedinformationintoanetlistformatthatcanbeusedfortimingsimulation.

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Chapter2:DesignFlow

Back-AnnotationFlowforFPGAs

Back-Annotation(CPLDs)

NetGen

NetGenisacommandlineprogramthatdistributesinformationaboutdelays,setup andholdtimes,clocktoout,andpulsewidthsfoundinthephysicalNativeCircuit Description(NCD)designlebacktothelogicalNativeGenericDatabase(NGD)le andgeneratesaVerilogorVHDLnetlistforusewithsupportedtimingsimulation, equivalencechecking,andstatictiminganalysistools.

NetGenreadsanNCDasinput.TheNCDlecanbeamapped-onlydesign,ora partiallyorfullyplacedandrouteddesign.AnNGMle,createdbyMAP ,isanoptional sourceofinput.NetGenmergesmappinginformationfromtheoptionalNGMlewith placement,routing,andtiminginformationfromtheNCDle.

NoteNetGenreadsanNGAleasinputtogenerateatimingsimulationnetlistfor

CPLDdesigns.

SeetheNetGenchapterfordetailedinformation.

FunctionalSimulation

Functionalsimulationdeterminesifthelogicinyourdesigniscorrectbeforeyou implementitinadevice.Functionalsimulationcantakeplaceattheearlieststagesof thedesignow .Becausetiminginformationfortheimplementeddesignisnotavailable atthisstage,thesimulatorteststhelogicinthedesignusingunitdelays.

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NoteItisusuallyfasterandeasiertocorrectdesignerrorsifyouperformfunctional

simulationearlyinthedesignow.

TimingSimulation

Timingsimulationveriesthatyourdesignrunsatthedesiredspeedforyourdevice underworst-caseconditions.Thisprocessisperformedafteryourdesignismapped, placed,androutedforFPGAsorttedforCPLDs.Atthistime,alldesigndelaysare known.

Timingsimulationisvaluablebecauseitcanverifytimingrelationshipsanddetermine thecriticalpathsforthedesignunderworst-caseconditions.Itcanalsodetermine whetherornotthedesigncontainsset-uporholdviolations.

Beforeyoucansimulateyourdesign,youmustgothroughtheback-annotationprocess, above.Duringthisprocess,NetGencreatessuitableformatsforvarioussimulators.

HDL-BasedSimulation

Xilinx®supportsfunctionalandtimingsimulationofHDLdesignsatthefollowing points:

•RegisterTransferLevel(RTL)simulation,whichmayincludethefollowing:

•Post-synthesisfunctionalsimulationwithoneofthefollowing:

•Post-implementationback-annotatedtimingsimulationwiththefollowing:

Chapter2:DesignFlow

–InstantiatedUNISIMlibrarycomponents

–COREGenerator™models

–HardIP(SecureIP)

–Gate-levelUNISIMlibrarycomponents

–COREGeneratormodels

–HardIP(SecureIP)

–SIMPRIMlibrarycomponents

–HardIP(SecureIP)

–StandardDelayFormat(SDF)le

Thefollowinggureshowswhenyoucanperformfunctionalandtimingsimulation:

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Chapter2:DesignFlow

SimulationPointsforHDLDesigns

Thethreeprimarysimulationpointscanbeexpandedtoallowfortwopost-synthesis simulations.ThesepointscanbeusedifthesynthesistoolcannotwriteVHDLor Verilog,orifthenetlistisnotintermsofUNISIMcomponents.Thefollowingtablelists allthesimulationpointsavailableintheHDLdesignow .

FiveSimulationPointsinHDLDesignFlow

SimulationUNISIMSIMPRIMSDF

RTL

Post-Synthesis

Functional Post-NGDBuild (Optional)

FunctionalPost-MAP (Optional)

Post-RouteTiming

Thesesimulationpointsaredescribedinthe“SimulationPoints”sectionoftheSynthesis

andSimulationDesignGuide(UG626).

Thelibrariesrequiredtosupportthesimulationowsaredescribedindetailin the“VHDL/VerilogLibrariesandModels”sectionoftheSynthesisandSimulation

DesignGuide(UG626).Theowsandlibrariessupportclosefunctionalequivalenceof

initializationbehaviorbetweenfunctionalandtimingsimulations.Thisisduetothe additionofmethodologiesandlibrarycellstosimulateGlobalSet/Reset(GSR)and Global3-State(GTS)behavior.

XilinxVHDLsimulationsupportstheVITALstandard.Thisstandardallowsyou tosimulatewithanyVITAL-compliantsimulator.Built-inVerilogsupportallows youtosimulatewiththeCadenceVerilog-XLandcompatiblesimulators.XilinxHDL simulationsupportsallcurrentXilinxFPGAandCPLDdevices.RefertotheSynthesis

andSimulationDesignGuide(UG626)forthelistofsupportedVHDLandV erilog

standards.

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+ 381 hidden pages

XILINX Command Line Tools User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

CommandLineToolsUser Guide

RevisionHistory

TableofContents

CommandLineProgramOverview

CommandLineSyntax

CommandLineOptions

-f(ExecuteCommandsFile)

Syntax

-h(Help)

Syntax

-intstyle(IntegrationStyle)

Syntax

-p(PartNumber)

Syntax

SpecifyingPartNumbers

InvokingCommandLinePrograms

DesignFlowOverview

DesignEntryandSynthesis

HierarchicalDesign

Partitions

PXMLFile

SchematicEntryOverview

LibraryElements

HDLEntryandSynthesis

COREGeneratorTool(FPGAsOnly)

FunctionalSimulation

Constraints

MappingConstraints(FPGAsOnly)

BlockPlacement

NetlistTranslationPrograms

DesignImplementation

Mapping(FPGAsOnly)

PlacingandRouting(FPGAsOnly)

BitstreamGeneration(FPGAsOnly)

Simulation

Back-Annotation

NetGen

FunctionalSimulation

TimingSimulation

HDL-BasedSimulation