XILINX Command Line Tools User Guide

CommandLineToolsUser Guide

(FormerlytheDevelopmentSystemReferenceGuide)

UG628(v13.1)March2,2011

Xilinxisdisclosingthisuserguide,manual,releasenote,and/orspecication(the“Documentation”)toyou solelyforuseinthedevelopmentofdesignstooperatewithXilinxhardwaredevices.Youmaynotreproduce, distribute,republish,download,display,post,ortransmittheDocumentationinanyformorbyanymeans including,butnotlimitedto,electronic,mechanical,photocopying,recording,orotherwise,withouttheprior writtenconsentofXilinx.XilinxexpresslydisclaimsanyliabilityarisingoutofyouruseoftheDocumentation. Xilinxreservestheright,atitssolediscretion,tochangetheDocumentationwithoutnoticeatanytime.Xilinx assumesnoobligationtocorrectanyerrorscontainedintheDocumentation,ortoadviseyouofanycorrections orupdates.Xilinxexpresslydisclaimsanyliabilityinconnectionwithtechnicalsupportorassistancethatmaybe providedtoyouinconnectionwiththeInformation.

THEDOCUMENTATIONISDISCLOSEDTOYOU“ AS-IS”WITHNOWARRANTYOFANYKIND.XILINX MAKESNOOTHERWARRANTIES,WHETHEREXPRESS,IMPLIED,ORSTATUTORY,REGARDING THEDOCUMENTA TION,INCLUDINGANYW ARRANTIESOFMERCHANTABILITY,FITNESSFORA PARTICULARPURPOSE,ORNONINFRINGEMENTOFTHIRD-PARTYRIGHTS.INNOEVENTWILL XILINXBELIABLEFORANYCONSEQUENTIAL,INDIRECT,EXEMPLARY ,SPECIAL,ORINCIDENTAL DAMAGES,INCLUDINGANYLOSSOFDATAORLOSTPROFITS,ARISINGFROMYOURUSEOFTHE DOCUMENTA TION.

©Copyright2002-2011XilinxInc.AllRightsReserved.XILINX,theXilinxlogo,theBrandWindowandother designatedbrandsincludedhereinaretrademarksofXilinx,Inc.Allothertrademarksarethepropertyoftheir respectiveowners.ThePowerPCnameandlogoareregisteredtrademarksofIBMCorp.,andusedunderlicense. Allothertrademarksarethepropertyoftheirrespectiveowners.

RevisionHistory

Thefollowingtableshowstherevisionhistoryforthisdocument.

Date

03/01/2011

03/02/2011

Version

13.1downloadAddinginformationforXilinx®7seriesFPGAdevices.

13.1WebreleaseAdditionalupdatesforXilinx7seriesFPGAdevices.

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CommandLineToolsUserGuide

Youcanruntheseprogramsinthestandarddesignoworusespecialoptionstorunthe programsfordesignpreservation.Eachcommandlineprogramhasmultipleoptions, whichallowyoutocontrolhowaprogramexecutes.Forexample,youcansetoptionsto changeoutputlenames,tosetapartnumberforyourdesign,ortospecifylestoread inwhenexecutingtheprogram.Youcanalsouseoptionstocreateguidelesandrun guidemodetomaintaintheperformanceofapreviouslyimplementeddesign.

Someofthecommandlineprogramsdescribedinthisguideunderliemanyofthe XilinxGraphicalUserInterfaces(GUIs).TheGUIscanbeusedwiththecommand lineprogramsoralone.ForinformationontheGUIs,seetheonlineHelpprovided witheachXilinxtool.

MAP NoteMAPusesspeciedoptionstoenable

timing-drivenplacementandrouting (-timing),andre-synthesisandphysical synthesisoptimizationsthatcantransforma designtomeettimingrequirements.

NetGen

TRACE

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Chapter1:Introduction

CommandLineSyntax

Commandlinesyntaxalwaysbeginswiththecommandlineprogramname.The programnameisfollowedbyanyoptionsandthenbylenames.Usethefollowing ruleswhenspecifyingcommandlineoptions:

•Enteroptionsinanyorder,precededthemwithadash(minussignonthekeyboard) andseparatethemwithspaces.

•Beconsistentwithuppercaseandlowercase.

•Whenanoptionrequiresaparameter,separatetheparameterfromtheoptionby spacesortabs.Forexample,thefollowingshowsthecommandlinesyntaxfor runningPARwiththeeffortlevelsettohigh:

–Correct:par-olhigh –Incorrect:par-olhigh

•Whenusingoptionsthatcanbespeciedmultipletimes,precedeeachparameter withtheoptionletter.Inthisexample,the-loptionshowsthelistoflibrariesto search:

–Correct:-lxilinxun-lsynopsys –Incorrect:-lxilinxunsynopsys

•Enterparametersthatareboundtoanoptionaftertheoption. –Correct:-fcommand_file –Incorrect:command_file-f

CommandLineOptions

-f(ExecuteCommandsFile)

Usethefollowingruleswhenspecifyinglenames:

•Enterlenamesintheorderspeciedinthechapterthatdescribesthecommand lineprogram.Inthisexamplethecorrectorderisprogram,inputle,outputle, andthenphysicalconstraintsle.

–Correct:parinput.ncdoutput.ncdfreq.pcf –Incorrect:parinput.ncdfreq.pcfoutput.ncd

•Uselowercaseforallleextensions(forexample,.ncd).

Thefollowingoptionsarecommontomanyofthecommandlineprogramsprovided withtheISE®DesignSuite.

•-f(ExecuteCommandsFile)

•-h(Help)

•-intstyle(IntegrationStyle)

•-p(PartNumber)

WithanyXilinx®commandlineprogramforusewithFPGAdesigns,youcanstore commandlineprogramoptionsandlenamesinacommandle.Youcanthenexecute theargumentsbyenteringtheprogramnamewiththe-foptionfollowedbythename ofthecommandle.Thisisusefulifyoufrequentlyexecutethesameargumentseach timeyouexecuteaprogramorifthecommandlinecommandbecomestoolong.

Syntax

-fcommand_file

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Chapter1:Introduction

Youcanusetheleinthefollowingways:

•Tosupplyallofthecommandoptionsandlenamesfortheprogram,asinthe followingexample:

par-fcommand_le

command_leisthenameofthelethatcontainsthecommandoptionsandle

names.

•Toinsertcertaincommandoptionsandlenameswithinthecommandline,asin thefollowingexample:

par-fplaceoptions-frouteoptionsdesign_i.ncddesign_o.ncd

–placeoptionsisthenameofalecontainingplacementcommandparameters.

–routeoptionsisthenameofalecontainingroutingcommandparameters.

YoucreatethecommandleinASCIIformat.Usethefollowingruleswhencreating thecommandle:

•Separateprogramoptionsandlenameswithspaces.

•Precedecommentswiththepoundsign(#).

•PutnewlinesortabsanywherewhitespaceisallowedontheLinuxorDOS commandline.

•Putallargumentsonthesameline,oneargumentperline,oracombinationofthese.

•Allcarriagereturnsandothernon-printablecharactersaretreatedasspacesand ignored.

•Nolinelengthlimitationexistswithinthele.

Example

Followingisanexampleofacommandle:

#commandlineoptionsforparfordesignmine.ncd

-w

0l5 /home/yourname/designs/xilinx/mine.ncd #directoryforoutputdesigns /home/yourname/designs/xilinx/output.dir #usetimingconstraintsfile /home/yourname/designs/xilinx/mine.pcf

-h(Help)

Whenyouentertheprogramnamefollowedbythisoption,youwillgetamessage listingalloptionsfortheprogramandtheirparameters,aswellastheletypesusedby theprogram.Themessagealsoexplainseachoftheoptions.

Syntax

-h

-help

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Chapter1:Introduction

SymbolDescription

[]

{}

italicsIndicatesavariablenameornumberforwhich

()

Enclosesitemsthatareoptional.

Enclosesitemsthatmayberepeated.

youmustsubstituteinformation.

Showsarangeforanintegervariable.

Showsthestartofanoptionname.

Bindsavariablenametoarange.

LogicalORtoshowachoiceofoneoutof manyitems.TheORoperatormayonly separatelogicalgroupsorliteralkeywords.

Enclosesalogicalgroupingforachoice betweensub-formats.

Example

Followingareexamplesofsyntaxusedforlenames:

•inle[.ncd]showsthattypingthe.ncdextensionisoptionalbutthattheextension mustbe.ncd.

•inle.ednshowsthatthe.ednextensionisoptionalandisappendedonlyifthere isnootherextensioninthelename.

Forarchitecture-specicprograms,suchasBitGen,youcanenterthefollowingtogeta verbosehelpmessageforthespeciedarchitecture:

program_name-harchitecture_name

Youcanredirectthehelpmessagetoaletoreadlaterortoprintoutbyenteringthe following:

program_name-h>lename

OntheLinuxcommandline,enterthefollowingtoredirectthehelpmessagetoale andreturntothecommandprompt.

program_name-h>&lename

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

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Chapter1:Introduction

-p(PartNumber)

Thisoptionspeciesthepartintowhichyourdesignisimplemented.

Syntax

-ppart_number

Thisoptioncanspecifyanarchitectureonly,acompletepartspecication(device, package,andspeed),orapartialspecication(forexample,deviceandpackageonly). Thepartnumberordevicenamemustbefromadevicelibraryyouhaveinstalledon yoursystem.

AcompleteXilinx®partnumberconsistsofthefollowingelements:

•Architecture(forexample,spartan3e)

•Device(forexample,xc3s100e)

•Package(forexample,vq100)

•Speed(forexample,-4)

NoteTheSpeedprintprogramlistsblockdelaysfordevicespeedgrades.The-soption

letsyouspecifyaspeedgrade.Ifyoudonotspecifyaspeedgrade,Speedprintreports thedefaultspeedgradeforthedeviceyouaretargeting.

SpecifyingPartNumbers

Youcanspecifyapartnumberatvariouspointsinthedesignow,notallofwhich requirethe-poption.

•Intheinputnetlist(doesnotrequirethe-poption)

•InaNetlistConstraintsFile(NCF)(doesnotrequirethe-poption)

•Withthe-poptionwhenyourunanetlistreader(EDIF2NGD)

•IntheUserConstraintsFile(UCF)(doesnotrequirethe-poption)

•Withthe-poptionwhenyourunNGDBuild

BythetimeyourunNGDBuild,youmusthavealreadyspeciedadevice architecture.

•Withthe-poptionwhenyourunMAP

WhenyourunMAPyoumustspecifyanarchitecture,device,andpackage,either ontheMAPcommandlineorearlierinthedesignow.Ifyoudonotspecifya speed,MAPselectsadefaultspeed.YoucanonlyrunMAPusingapartnumber fromthearchitectureyouspeciedwhenyouranNGCBuild.

•Withthe-poptionwhenyourunSmartXplorer(FPGAdesignsonly)

•Withthe-poptionwhenyourunCPLDFit(CPLDdesignsonly)

NotePartnumbersspeciedinalaterstepofthedesignowoverrideapartnumber

speciedinanearlierstep.Forexample,apartspeciedwhenyourunMAPoverridesa partspeciedintheinputnetlist.

Examples

Thefollowingexamplesshowhowtospecifypartsonthecommandline.

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Chapter1:Introduction

SpeciﬁcationExamples

Architectureonly

Deviceonlyxc4vfx12

DevicePackagexc4fx12sf363

Device-Packagexc4vfx12-sf363

DeviceSpeed-Packagexc4vfx1210-sf363

DevicePackage-Speedxc4fx12sf363-10

Device-Speed-Packagexc4vfx12-10-sf363

Device-SpeedPackagexc4vfx12-10sf363

virtex4 virtex5 spartan3 spartan3a xc9500 xpla3(CoolRunner™XPLA3devices)

xc3s100e

xc3s100evq100

xc3s100e-vq100

xc3s100e4-vq100

xc3s100evq100-4

xc3s100e-4-vq100

xc3s100e-4vq100

InvokingCommandLinePrograms

YoustartXilinx®commandlineprogramsbyenteringacommandattheLinuxorDOS commandline.Seetheprogram-specicchaptersinthisbookfortheappropriatesyntax

XilinxalsoofferstheXFLOWprogram,whichletsyouautomatetherunningofseveral programsatonetime.SeetheXFLOWchapterformoreinformation.

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DesignFlow

Thischapterdescribestheprocessforcreating,implementing,verifying,and downloadingdesignsforXilinx®FPGAandCPLDdevices.Foracomplete descriptionofXilinxFPGAandCPLDsdevices,refertotheXilinxDataSheetsat:

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DesignFlowOverview

Thestandarddesignowcomprisesthefollowingsteps:

1.DesignEntryandSynthesis-CreateyourdesignusingaXilinx®-supported schematiceditor,aHardwareDescriptionLanguage(HDL)fortext-basedentry ,or both.IfyouuseanHDLfortext-basedentry ,youmustsynthesizetheHDLleinto anEDIFleor,ifyouareusingtheXilinxSynthesisTechnology(XST)GUI,you mustsynthesizetheHDLleintoanNGCle.

2.DesignImplementation-Convertthelogicaldesignleformat,suchasEDIF ,that youcreatedinthedesignentryandsynthesisstageintoaphysicalleformatby implementingtoaspecicXilinxarchitecture.Thephysicalinformationiscontained intheNativeCircuitDescription(NCD)leforFPGAsandtheVM6leforCPLDs. ThencreateabitstreamlefromtheselesandoptionallyprogramaPROMor EPROMforsubsequentprogrammingofyourXilinxdevice.

3.DesignV erication-Usingagate-levelsimulatororcable,ensurethatyourdesign meetstimingrequirementsandfunctionsproperly .SeetheiMPACTonlinehelpfor informationaboutXilinxdownloadcablesanddemonstrationboards.

Chapter2

Thefulldesignowisaniterativeprocessofentering,implementing,andverifying yourdesignuntilitiscorrectandcomplete.Thecommandlinetoolsprovidedwiththe ISE®DesignSuiteallowquickdesigniterationsthroughthedesignowcycle.Xilinx devicespermitunlimitedreprogramming.Youdonotneedtodiscarddeviceswhen debuggingyourdesignincircuit.

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Chapter2:DesignFlow

XilinxDesignFlow

ThisgureshowsthestandardXilinxdesignow.

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XilinxSoftwareDesignFlow(FPGAs)

ThisgureshowstheXilinxsoftwareowchartforFPGAdesigns.

Chapter2:DesignFlow

XilinxSoftwareDesignFlow(CPLDs)

ThisgureshowstheXilinxsoftwareowchartforCPLDdesigns.

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Chapter2:DesignFlow

DesignEntryandSynthesis

Youcanenteradesignwithaschematiceditororatext-basedtool.Designentrybegins withadesignconcept,expressedasadrawingorfunctionaldescription.Fromthe originaldesign,anetlistiscreated,thensynthesizedandtranslatedintoanativegeneric object(NGO)le.ThisleisfedintotheXilinx®softwareprogramcalledNGDBuild, whichproducesalogicalNativeGenericDatabase(NGD)le.

Thefollowinggureshowsthedesignentryandsynthesisprocess.

DesignEntryFlow

HierarchicalDesign

DesignhierarchyisimportantinbothschematicandHDLentryforthefollowing reasons:

•Helpsyouconceptualizeyourdesign

•Addsstructuretoyourdesign

•Promoteseasierdesigndebugging

•Makesiteasiertocombinedifferentdesignentrymethods(schematic,HDL,orstate editor)fordifferentpartsofyourdesign

•Makesiteasiertodesignincrementally ,whichconsistsofdesigning,implementing, andverifyingindividualpartsofadesigninstages

•Reducesoptimizationtime

•Facilitatesconcurrentdesign,whichistheprocessofdividingadesignamonga numberofpeoplewhodevelopdifferentpartsofthedesigninparallel.

Inhierarchicaldesigning,aspecichierarchicalnameidentieseachlibraryelement, uniqueblock,andinstanceyoucreate.Thefollowingexampleshowsahierarchical namewitha2-inputORgateintherstinstanceofamultiplexerina4-bitcounter:

/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2

Xilinx®stronglyrecommendsthatyounamethecomponentsandnetsinyourdesign. ThesenamesarepreservedandusedbyFPGAEditor.Thesenamesarealsousedfor back-annotationandappearinthedebugandanalysistools.Ifyoudonotnameyour componentsandnets,theSchematicEditorautomaticallygeneratesthenames.For example,ifleftunnamed,thesoftwaremightnamethepreviousexample,asfollows:

/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57

NoteItisdifculttoanalyzecircuitswithautomaticallygeneratednames,becausethe

namesonlyhavemeaningforXilinxsoftware.

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Chapter2:DesignFlow

Partitions

Inhierarchicaldesignows,suchasDesignPreservationandPartialReconguration, partitionsareusedtodenehierarchicalboundariessothatacomplexdesigncanbe brokenupintosmallerblocks.Partitionscreateaboundaryorinsulationaroundthe hierarchicalmodule,whichisolatesthemodulefromotherpartsofthedesign.A partitionthathasbeenimplementedandexportedcanbere-insertedintothedesign usingasimplecut-and-pastetypefunction,whichpreservestheplacementandrouting resultsfortheisolatedmodule.Allofthepartitiondenitionsandcontrolsaredoneina lecalledxpartition.pxml.Formoreinformationonusinghierarchicaldesignows andimplementingpartitions,seetheHierarchicalDesignMethodologyGuide(UG748).

PXMLFile

Partitiondenitionsarecontainedinthexpartition.pxmlle.ThePXMLlename iscase-sensitive,andmustbenamedxpartition.pxml.Thetoplevelmodule ofthedesignmustbedenedasapartitioninadditiontoanyoptionallowerlevel partitions.ThePXMLlecanbecreatedbyhand,fromscripts,orfromatoolsuchas thePlanAhead™software.ThePXMLwillbepickedupautomaticallybytheISE® DesignSuiteimplementationtoolswhenlocatedinthecurrentworkingdirectory. Formoreinformationaboutusingthexpartition.pxmlle,seetheHierarchical

DesignMethodologyGuide(UG748).Anexamplexpartition.pxmlleisavailable

at%XILINX%/PlanAhead/testcases/templates(where%XILINX%isyour installationdirectory)ifyouwishtocreateaPXMLlebyhand.

NoteAllpathsinthePXMLlemustbeabsolutepaths.

<?xmlversion="1.0"encoding="UTF-8"?>

<ProjectFileVersion="1.2"Name="Example"ProjectVersion="2.0">

<PartitionName="/top"State="implement"ImportLocation="NONE">

<PartitionName="/top/module_A"State="import"ImportLocation="/home/user/Example/import"Preserve="routing"> </Partition> <PartitionName="/top/module_B"State="import"ImportLocation="/home/user/Example/import"Preserve="routing"> </Partition> <PartitionName="/top/module_C"State="implement"ImportLocation="/home/user/Example/import"Preserve="placement"> </Partition>

</Partition>

</Project>

PXMLattributesforProjectdeﬁnition

Attributename

FileVersion

Name

ProjectVersion2.0

Value

1.2

Project_Name

Description

Usedforinternalpurposes.Donotchangethis value.

Project_Nameisuserdened.

Usedforinternalpurposes.Donotchangethis value.

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Chapter2:DesignFlow

PXMLattributesforPartitiondeﬁnition

Attributename

Name

State

ImportLocation

ImportTag

Preserve

BoundaryOpt

Value

Partition_Name

“implement”Partitionisimplementedfromscratch.

“import”

pathIgnoredifStatedoesnotequal“import.”

Partition_Name

“routing”

“placement”Placementispreservedbutroutingcanbe

“synthesis”Placementandroutingcanbemodied.

“inherit”Inheritvaluefromtheparentpartition.Thisis

“all”Enablestheimplementationtoolstodo

“none”

Description

Hierarchicalinstancenameofmoduleinwhich thepartitionshouldbeapplied.

Partitionisimportedandpreservedaccording tothelevelsetbyPreserve.

Thepathcanberelativeorabsolute,butthe locationspeciedmustcontainavalid"export" directorywhenState=import.“NONE”isa predenedkeywordfornoimportdirectory .

Allowsapartitiontobeimportedintoa differentlevelofhierarchythanitwasinitially implementedin.Setthevaluetothehierarchical instancenameofthepartitionwhereitwas implemented.

100%placementandroutingispreserved.This isthedefaultforthetoplevelPartition.

modied.

thedefaultforallpartitionsexceptthetoplevel partition.

optimizationonpartitionportsconnectedto constraintsaswellasunusedpartitionports.

Normalpartitionoptimizationrulesapply . Optimizationisallowedonlywithinpartition boundaries.Thisisthedefaultvalue.

SchematicEntryOverview

Schematictoolsprovideagraphicinterfacefordesignentry.Youcanusethesetoolsto connectsymbolsrepresentingthelogiccomponentsinyourdesign.Youcanbuildyour designwithindividualgates,oryoucancombinegatestocreatefunctionalblocks. Thissectionfocusesonwaystoenterfunctionalblocksusinglibraryelementsandthe COREGenerator™tool.

LibraryElements

Primitivesandmacrosarethe“buildingblocks”ofcomponentlibraries.Xilinx® librariesprovideprimitives,aswellascommonhigh-levelmacrofunctions.Primitives arebasiccircuitelements,suchasANDandORgates.Eachprimitivehasaunique libraryname,symbol,anddescription.Macroscontainmultiplelibraryelements,which canincludeprimitivesandothermacros.

YoucanusethefollowingtypesofmacroswithXilinxFPGAs:

•Softmacroshavepre-denedfunctionalitybuthaveexiblemapping,placement, androuting.SoftmacrosareavailableforallFPGAs.

•Relationallyplacedmacros(RPMs)havexedmappingandrelativeplacement. RPMsareavailableforalldevicefamilies,excepttheXC9500family .

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HDLEntryandSynthesis

Macrosarenotavailableforsynthesisbecausesynthesistoolshavetheirownmodule generatorsanddonotrequireRPMs.Ifyouwishtooverridethemodulegeneration,you caninstantiatemodulescreatedusingCOREGenerator.Formostleading-edgesynthesis tools,thisdoesnotofferanadvantageunlessitisforamodulethatcannotbeinferred.

COREGeneratorTool(FPGAsOnly)

TheXilinxCOREGeneratortooldeliversparameterizablecoresthatareoptimized forXilinxFPGAs.Thelibraryincludescoresrangingfromsimpledelayelementsto complexDSP(DigitalSignalProcessing)ltersandmultiplexers.Fordetails,refertothe COREGeneratorHelp(partofISEHelp).Y oucanalsorefertotheXilinxIP(Intellectual Property)CenterWebsiteath solutions.Thesesolutionsincludedesignreusetools,freereferencedesigns,Digital SignalProcessing(DSP),PCI™solutions,IPimplementationtools,cores,specialized systemlevelservices,andverticalapplicationIPsolutions.

AtypicalHardwareDescriptionLanguage(HDL)supportsamixed-leveldescriptionin whichgateandnetlistconstructsareusedwithfunctionaldescriptions.Thismixed-level capabilityletsyoudescribesystemarchitecturesatahighlevelofabstractionandthen incrementallyrenethedetailedgate-levelimplementationofadesign.

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Chapter2:DesignFlow

FunctionalSimulation

HDLdescriptionsofferthefollowingadvantages:

•Youcanverifydesignfunctionalityearlyinthedesignprocess.Adesignwrittenas anHDLdescriptioncanbesimulatedimmediately .Designsimulationatthishigh level,atthegate-levelbeforeimplementation,allowsyoutoevaluatearchitectural anddesigndecisions.

•AnHDLdescriptionismoreeasilyreadandunderstoodthananetlistorschematic description.HDLdescriptionsprovidetechnology-independentdocumentation ofadesignanditsfunctionality.BecausetheinitialHDLdesigndescriptionis technologyindependent,youcanuseitagaintogeneratethedesigninadifferent technology,withouthavingtotranslateitfromtheoriginaltechnology .

•LargedesignsareeasiertohandlewithHDLtoolsthanschematictools.

AfteryoucreateyourHDLdesign,youmustsynthesizeit.Duringsynthesis,behavioral informationintheHDLleistranslatedintoastructuralnetlist,andthedesignis optimizedforaXilinx®device.XilinxsupportsHDLsynthesistoolsforseveral third-partysynthesisvendors.Inaddition,Xilinxoffersitsownsynthesistool,Xilinx SynthesisTechnology(XST).Formoreinformation,seetheXSTUserGuideforVirtex-4,

Virtex-5,Spartan-3,andNewerCPLDDevices(UG627)ortheXSTUserGuideforVirtex-6, Spartan-6,and7SeriesDevices(UG687).Fordetailedinformationonsynthesis,seethe SynthesisandSimulationDesignGuide(UG626).

Afteryoucreateyourdesign,youcansimulateit.Functionalsimulationteststhe logicinyourdesigntodetermineifitworksproperly .Youcansavetimeduring subsequentdesignstepsifyouperformfunctionalsimulationearlyinthedesignow. SeeSimulationformoreinformation.

Constraints

Youmaywanttoconstrainyourdesignwithincertaintimingorplacementparameters. Youcanspecifymapping,blockplacement,andtimingspecications.

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Chapter2:DesignFlow

MappingConstraints(FPGAsOnly)

BlockPlacement

YoucanenterconstraintsmanuallyorusetheConstraintsEditororFPGAEditor,which aregraphicaluserinterface(GUI)toolsprovidedbyXilinx®.YoucanusetheTiming AnalyzerGUIorTRACEcommandlineprogramtoevaluatethecircuitagainstthese constraintsbygeneratingastatictiminganalysisofyourdesign.SeetheTRACEchapter andtheonlineHelpprovidedwiththeISE®DesignSuiteformoreinformation.For moreinformationonconstraints,seetheConstraintsGuide(UG625).

YoucanspecifyhowablockoflogicismappedintoCLBsusinganFMAPforall Spartan®andVirtex®FPGAarchitectures.Thesemappingsymbolscanbeusedin yourschematic.However,ifyouoverusethesespecications,itmaybedifcultto routeyourdesign.

Blockplacementcanbeconstrainedtoaspeciclocation,tooneofmultiplelocations,or toalocationrange.Locationscanbespeciedintheschematic,withsynthesistools, orintheUserConstraintsFile(UCF).Poorblockplacementcanadverselyaffectboth theplacementandtheroutingofadesign.OnlyI/Oblocksrequireplacementtomeet externalpinrequirements.

TimingSpeciﬁcations

Youcanspecifytimingrequirementsforpathsinyourdesign.PARusesthesetiming specicationstoachieveoptimumperformancewhenplacingandroutingyourdesign.

NetlistTranslationPrograms

NetlisttranslationprogramsletyoureadnetlistsintotheXilinx®softwaretools. EDIF2NGDletsyoureadanElectronicDataInterchangeFormat(EDIF)200le.The NGDBuildprogramautomaticallyinvokestheseprogramsasneededtoconvertyour EDIFletoanNGDle,therequiredformatfortheXilinxsoftwaretools.NGCles outputfromtheXilinxXSTsynthesistoolarereadinbyNGDBuilddirectly .

YoucannddetaileddescriptionsoftheEDIF2NGD,andNGDBuildprogramsinthe

NGDBuildchapterandtheEDIF2NGDandNGDBuildAppendix.

DesignImplementation

DesignImplementationbeginswiththemappingorttingofalogicaldesignletoa specicdeviceandiscompletewhenthephysicaldesignissuccessfullyroutedanda bitstreamisgenerated.Youcanalterconstraintsduringimplementationjustasyoudid duringtheDesignEntrystep.SeeConstraintsforinformation.

ThefollowinggureshowsthedesignimplementationprocessforFPGAdesigns:

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DesignImplementationFlow(FPGAs)

Chapter2:DesignFlow

ThefollowinggureshowsthedesignimplementationprocessforCPLDdesigns:

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Chapter2:DesignFlow

DesignImplementationFlow(CPLDs)

Mapping(FPGAsOnly)

ForFPGAs,theMAPcommandlineprogrammapsalogicaldesigntoaXilinx®FPGA. TheinputtoMAPisanNGDle,whichcontainsalogicaldescriptionofthedesignin termsofboththehierarchicalcomponentsusedtodevelopthedesignandthelower-level Xilinxprimitives,andanynumberofNMC(hardplaced-and-routedmacro)les,each ofwhichcontainsthedenitionofaphysicalmacro.MAPthenmapsthelogictothe components(logiccells,I/Ocells,andothercomponents)inthetargetXilinxFPGA.

TheoutputdesignfromMAPisanNCDle,whichisaphysicalrepresentationof thedesignmappedtothecomponentsintheXilinxFPGA.TheNCDlecanthenbe placedandrouted,usingthePARcommandlineprogram.SeetheMAPchapterfor detailedinformation.

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NoteMAPprovidesoptionsthatenableadvancedoptimizationsthatarecapable

ofimprovingtimingresultsbeyondstandardimplementations.Theseadvanced optimizationscantransformadesignpriortoorafterplacement.Optimizationscan beappliedattwodifferentstagesintheXilinxdesignow.Therststagehappens rightaftertheinitialmappingofthelogictothearchitectureslices;thesecondstageif afterplacement.SeeRe-SynthesisandPhysicalSynthesisOptimizationsintheMAP chapterformoreinformation.

PlacingandRouting(FPGAsOnly)

ForFPGAs,thePARcommandlineprogramtakesamappedNCDleasinput,places androutesthedesign,andoutputsaplacedandroutedNativeCircuitDescription (NCD)le,whichisusedbythebitstreamgenerator,BitGen.TheoutputNCDlecan alsoactasaguidelewhenyoureiterateplacementandroutingforadesigntowhich minorchangeshavebeenmadeafterthepreviousiteration.SeethePARchapterfor detailedinformation.

YoucanalsouseFPGAEditortodothefollowing:

•Placeandroutecriticalcomponentsbeforerunningautomaticplaceandroutetools onanentiredesign.

•Modifyplacementandroutingmanually.Theeditorallowsbothautomaticand manualcomponentplacementandrouting.

Chapter2:DesignFlow

NoteFormoreinformation,seetheonlineHelpprovidedwithFPGAEditor.

BitstreamGeneration(FPGAsOnly)

ForFPGAs,theBitGencommandlineprogramproducesabitstreamforXilinx® deviceconguration.BitGentakesafullyroutedNCDleasitsinputandproduces acongurationbitstream,whichisabinarylewitha.bitextension.TheBITle containsallofthecongurationinformationfromtheNCDledeningtheinternal logicandinterconnectionsoftheFPGA,plusdevice-specicinformationfromotherles associatedwiththetargetdevice.SeetheBitGenchapterfordetailedinformation.

AfteryougenerateyourBITle,youcandownloadittoadeviceusingtheiMPACTGUI. YoucanalsoformattheBITleintoaPROMleusingthePROMGencommandline programandthendownloadittoadeviceusingtheiMPACTGUI.SeethePROMGen

chapterofthisguideortheiMPACTonlinehelpformoreinformation.

DesignVeriﬁcation

Designvericationistestingthefunctionalityandperformanceofyourdesign.Y oucan verifyXilinx®designsinthefollowingways:

•Simulation(functionalandtiming)

•Statictiminganalysis

•In-circuitverication

Thefollowingtableliststhedifferentdesigntoolsusedforeachvericationtype.

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Chapter2:DesignFlow

VeriﬁcationTools

VeriﬁcationTypeTools

SimulationThird-partysimulators(integratedand

non-integrated)

StaticTimingAnalysisTRACE(commandlineprogram)

TimingAnalyzer(GUI)

MentorGraphicsTAUandInnovedaBLAST softwareforusewiththeSTAMPleformat (forI/Otimingvericationonly)

In-CircuitVericationDesignRuleChecker(commandlineprogram)

Downloadcable

Designvericationproceduresshouldoccurthroughoutyourdesignprocess,asshown inthefollowinggures.

ThreeVeriﬁcationMethodsoftheDesignFlow(FPGAs)

ThefollowinggureshowsthevericationmethodsofthedesignowforCPLDs.

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ThreeVeriﬁcationMethodsoftheDesignFlow(CPLDs)

Chapter2:DesignFlow

Simulation

Youcanrunfunctionalortimingsimulationtoverifyyourdesign.Thissectiondescribes theback-annotationprocessthatmustoccurpriortotimingsimulation.Italsodescribes thefunctionalandtimingsimulationmethodsforbothschematicandHDL-based designs.

Back-Annotation

Beforetimingsimulationcanoccur,thephysicaldesigninformationmustbetranslated anddistributedbacktothelogicaldesign.ForFPGAs,thisback-annotationprocessis donewithaprogramcalledNetGen.ForCPLDs,back-annotationisperformedwith theTSimTimingSimulator.Theseprogramscreateadatabase,whichtranslatesthe back-annotatedinformationintoanetlistformatthatcanbeusedfortimingsimulation.

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Chapter2:DesignFlow

Back-AnnotationFlowforFPGAs

Back-Annotation(CPLDs)

NetGen

NetGenisacommandlineprogramthatdistributesinformationaboutdelays,setup andholdtimes,clocktoout,andpulsewidthsfoundinthephysicalNativeCircuit Description(NCD)designlebacktothelogicalNativeGenericDatabase(NGD)le andgeneratesaVerilogorVHDLnetlistforusewithsupportedtimingsimulation, equivalencechecking,andstatictiminganalysistools.

NetGenreadsanNCDasinput.TheNCDlecanbeamapped-onlydesign,ora partiallyorfullyplacedandrouteddesign.AnNGMle,createdbyMAP ,isanoptional sourceofinput.NetGenmergesmappinginformationfromtheoptionalNGMlewith placement,routing,andtiminginformationfromtheNCDle.

NoteNetGenreadsanNGAleasinputtogenerateatimingsimulationnetlistfor

CPLDdesigns.

SeetheNetGenchapterfordetailedinformation.

FunctionalSimulation

Functionalsimulationdeterminesifthelogicinyourdesigniscorrectbeforeyou implementitinadevice.Functionalsimulationcantakeplaceattheearlieststagesof thedesignow .Becausetiminginformationfortheimplementeddesignisnotavailable atthisstage,thesimulatorteststhelogicinthedesignusingunitdelays.

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NoteItisusuallyfasterandeasiertocorrectdesignerrorsifyouperformfunctional

simulationearlyinthedesignow.

TimingSimulation

Timingsimulationveriesthatyourdesignrunsatthedesiredspeedforyourdevice underworst-caseconditions.Thisprocessisperformedafteryourdesignismapped, placed,androutedforFPGAsorttedforCPLDs.Atthistime,alldesigndelaysare known.

Timingsimulationisvaluablebecauseitcanverifytimingrelationshipsanddetermine thecriticalpathsforthedesignunderworst-caseconditions.Itcanalsodetermine whetherornotthedesigncontainsset-uporholdviolations.

Beforeyoucansimulateyourdesign,youmustgothroughtheback-annotationprocess, above.Duringthisprocess,NetGencreatessuitableformatsforvarioussimulators.

HDL-BasedSimulation

Xilinx®supportsfunctionalandtimingsimulationofHDLdesignsatthefollowing points:

•RegisterTransferLevel(RTL)simulation,whichmayincludethefollowing:

•Post-synthesisfunctionalsimulationwithoneofthefollowing:

•Post-implementationback-annotatedtimingsimulationwiththefollowing:

Chapter2:DesignFlow

–InstantiatedUNISIMlibrarycomponents

–COREGenerator™models

–HardIP(SecureIP)

–Gate-levelUNISIMlibrarycomponents

–COREGeneratormodels

–HardIP(SecureIP)

–SIMPRIMlibrarycomponents

–HardIP(SecureIP)

–StandardDelayFormat(SDF)le

Thefollowinggureshowswhenyoucanperformfunctionalandtimingsimulation:

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Chapter2:DesignFlow

SimulationPointsforHDLDesigns

Thethreeprimarysimulationpointscanbeexpandedtoallowfortwopost-synthesis simulations.ThesepointscanbeusedifthesynthesistoolcannotwriteVHDLor Verilog,orifthenetlistisnotintermsofUNISIMcomponents.Thefollowingtablelists allthesimulationpointsavailableintheHDLdesignow .

FiveSimulationPointsinHDLDesignFlow

SimulationUNISIMSIMPRIMSDF

RTL

Post-Synthesis

Functional Post-NGDBuild (Optional)

FunctionalPost-MAP (Optional)

Post-RouteTiming

Thesesimulationpointsaredescribedinthe“SimulationPoints”sectionoftheSynthesis

andSimulationDesignGuide(UG626).

Thelibrariesrequiredtosupportthesimulationowsaredescribedindetailin the“VHDL/VerilogLibrariesandModels”sectionoftheSynthesisandSimulation

DesignGuide(UG626).Theowsandlibrariessupportclosefunctionalequivalenceof

initializationbehaviorbetweenfunctionalandtimingsimulations.Thisisduetothe additionofmethodologiesandlibrarycellstosimulateGlobalSet/Reset(GSR)and Global3-State(GTS)behavior.

XilinxVHDLsimulationsupportstheVITALstandard.Thisstandardallowsyou tosimulatewithanyVITAL-compliantsimulator.Built-inVerilogsupportallows youtosimulatewiththeCadenceVerilog-XLandcompatiblesimulators.XilinxHDL simulationsupportsallcurrentXilinxFPGAandCPLDdevices.RefertotheSynthesis

andSimulationDesignGuide(UG626)forthelistofsupportedVHDLandV erilog

standards.

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StaticTimingAnalysis(FPGAsOnly)

Statictimingallowsyoutodeterminepathdelaysinyourdesign.Followingarethe twomajorgoalsofstatictiminganalysis:

•Timingverication

Thisisverifyingthatthedesignmeetsyourtimingconstraints.

•Reporting

Thisisenumeratinginputconstraintviolationsandplacingthemintoanaccessible le.Youcananalyzepartiallyorcompletelyplacedandrouteddesigns.Thetiming informationdependsontheplacementandroutingoftheinputdesign.

YoucanrunstatictiminganalysisusingtheTimingReporterAndCircuitEvaluator (TRACE)commandlineprogram.SeetheTRACEchapterfordetailedinformation.Y ou canalsousetheTimingAnalyzertoperformthisfunction.SeetheHelpthatcomeswith TimingAnalyzerforadditionalinformation.Useeithertooltoevaluatehowwellthe placeandroutetoolsmettheinputtimingconstraints.

In-CircuitVeriﬁcation

Asanaltest,youcanverifyhowyourdesignperformsinthetargetapplication. In-circuitvericationteststhecircuitundertypicaloperatingconditions.Becauseyou canprogramyourFPGAdevicesrepeatedly ,youcaneasilyloaddifferentiterationsof yourdesignintoyourdeviceandtestitin-circuit.Toverifyyourdesignin-circuit, downloadyourdesignbitstreamintoadevicewiththeappropriateXilinx®cable.

Chapter2:DesignFlow

NoteForinformationaboutXilinxcablesandhardware,seetheiMPACTonlinehelp.

DesignRuleChecker(FPGAsOnly)

Beforegeneratingthenalbitstream,itisimportanttousetheDRCoptioninBitGen toevaluatetheNCDleforproblemsthatcouldpreventthedesignfromfunctioning properly.DRCisinvokedautomaticallyunlessyouusethe-doption.SeethePhysical

DesignRuleCheckchapterandtheBitGenchapterfordetailedinformation.

Probe

TheXilinxPROBEfunctioninFPGAEditorprovidesreal-timedebugcapabilitygood foranalyzingafewsignalsatatime.UsingPROBEadesignercanquicklyidentifyand routeanyinternalsignalstoavailableI/Opinswithouthavingtoreplaceandroutethe design.Thereal-timeactivityofthesignalcanthenbemonitoredusingnormallabtest equipmentsuchaslogic/stateanalyzersandoscilloscopes.

ChipScope™ILAandChipScopePro

TheChipScopetoolsetwasdevelopedtoassistengineersworkingatthePCBlevel. ChipScopeILAactuallyembedslogicanalyzercoresintoyourdesign.Theselogiccores allowtheusertoviewalltheinternalsignalsandnodeswithinanFPGA.Triggersare changeableinreal-timewithoutaffectingtheuserlogicorrequiringrecompilation oftheuserdesign.

FPGADesignTips

TheXilinx®FPGAarchitectureisbestsuitedforsynchronousdesign.Strictsynchronous designensuresthatallregistersaredrivenfromthesametimebasewithnoclockskew. Thissectiondescribesseveraltipsforproducinghigh-performancesynchronousdesigns.

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Chapter2:DesignFlow

DesignSizeandPerformance

Informationaboutdesignsizeandperformancecanhelpyoutooptimizeyourdesign. Whenyouplaceandrouteyourdesign,theresultingreportleslistthenumberof CLBs,IOBs,andotherdeviceresourcesavailable.Arstpassestimatecanbeobtained byprocessingthedesignthroughtheMAPprogram.

Ifyouwanttodeterminethedesignsizeandperformancewithoutrunningautomatic implementationsoftware,youcanquicklyobtainanestimatefromaroughcalculation basedontheXilinxFPGAarchitecture.

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PARTGen

ThischapterdescribesPARTGen.

PARTGenOverview

PARTGenisaXilinx®commandlinetoolthatdisplaysarchitecturaldetailsabout supportedXilinxdevices.

DeviceSupport

Thisprogramiscompatiblewiththefollowingdevicefamilies:

•7series

•Spartan®-3,Spartan-3A,Spartan-3E,andSpartan-6

•Virtex®-4,Virtex-5,andVirtex-6

•CoolRunner™XPLA3andCoolRunner-II

•XC9500andXC9500XL

Chapter3

PARTGenInputFiles

PARTGendoesnothaveanyuserinputles.

PARTGenOutputFiles

PARTGenoutputstwoletypes:

•PARTGenPartlistFiles(ASCIIandXML)

•PARTGenPackageFiles(ASCII)

PARTGenPartlistFiles

PARTGenpartlistlescontaindetailedinformationaboutarchitecturesanddevices, includingsupportedsynthesistools.PartlistlesaregeneratedinbothASCII(.xct) andXML(.xml)formats.

ThepartlistleisautomaticallygeneratedinXMLformatwheneverapartlistleis createdwiththePARTGen-p(GeneratePartlistandPackageFiles)orPARTGen-v

(GeneratePartlistandPackageFiles)options.Noseparatecommandlineoptionis

required.

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Chapter3:PARTGen

Thepartlistleisaseriesofpartentries.Thereisoneentryforeverypartsupported intheinstalledsoftware.Thefollowingsectionsdescribetheinformationcontained inthepartlistle.

•PARTGenPartlistFileHeader

•PARTGenPartlistFileDeviceAttributesforBoth-pand-vOptions

•PARTGenPartlistFileDeviceAttributesfor-vOptionOnly

PARTGenPartlistFileHeader

TherstpartofaP ARTGenpartlistleisaheaderfortheentry .

partarchitecturefamilypartnamedienamepackagefilename

PARTGenPartlistFileHeaderExampleforXC6VLX550TFF1759Device

partVIRTEXXC6VLX550Tff1759NA.diexc6vlx550tff1759.pkg

PARTGenPartlistFileDeviceAttributesforboth-pand-vOptions

ThefollowingPARTGenpartlistledeviceattributesdisplayforboththe-pand-v commandlineoptions.

•CLBrowandcolumnsizes

NCLBROWS=#NCLBCOLS=#

•Sub-familydesignation

STYLE=sub_family(Forexample,STYLE=Virtex6)

•Inputregisters

IN_FF_PER_IOB=#

•Outputregisters

OUT_FF_PER_IOB=#

•Numberofpadsperrowandpercolumn

NPADS_PER_ROW=#NP ADS_PER_COL=#

•Bitstreaminformation

–Numberofframes:NFRAMES=#

–Numberbits/frame:NBITSPERFRAME=#

•Steppinglevelssupported:STEP=#

•I/OStandards

ForeachI/Ostandard,PARTGennowreportsallpropertiesinaparsableformat. ThisallowsthirdpartytoolstoperformcompleteI/Obankingdesignruleschecking (DRC).

Thefollowinginformationhasbeenaddedtothepartlist.xctand

partlist.xmloutputforeachavailableI/Ostandard: IOSTD_NAME:LVTTL\

IOSTD_DRIVE:1224681624\ IOSTD_SLEW:SLOWFAST\ IOSTD_DIRECTION:INPUT=1OUTPUT=1BIDIR=1\ IOSTD_INPUTTERM:NONE\ IOSTD_OUTPUTTERM:NONE\ IOSTD_VCCO:3.300000\ IOSTD_VREF:100.000000\ IOSTD_VRREQUIRED:0\ IOSTD_DIFFTERMREQUIRED:0\

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Chapter3:PARTGen

ForIOSTD_DRIVEandIOSTD_SLEW,thedefaultvaluesarereportedrstinthe list.Fortrue/falsevalues:

–1indicatestrue –0indicatesfalse

Avalueof100.000000forIOSTD_VREFindicatesthatthiskeywordisundened forthisstandard.

•SOandWASSOCalculations

PARTGennowexportsI/Ostandardanddevicepropertiesinamachinereadable format.ThisallowsthirdpartytoolstoperformSSOandW ASSOcalculations.

SSOdataconsistsoftwoparts:

–ThemaximumnumberofSSOsallowedperpower/groundpair

–Thenumberofpower/groundpairsforagivenbank. Thisdatahasbeenaddedtothepartlist.xctandpartlist.xmloutputfor

eachdevice/packagecombination.Thenumberofpower/groundpairsislisted bybanknumber:

PER_BANK_PWRGND_PAIRS\

BANK_SSONAME=0TYPE=INT1\ BANK_SSONAME=1TYPE=INT1\ BANK_SSONAME=2TYPE=INT1\ BANK_SSONAME=3TYPE=INT1\ BANK_SSONAME=4TYPE=INT1\ BANK_SSONAME=5TYPE=INT5\ BANK_SSONAME=6TYPE=INT5\ BANK_SSONAME=7TYPE=INT3\ BANK_SSONAME=8TYPE=INT3\

ThemaximumnumberofSSOsallowedperpower/groundpairisreportedusing theSSO_PER_IOSTDkeyword.EachentryreectsthemaximumnumberofSSOs (column6)fortheI/Ostandard(column3),drivestrength(column2),andslew rate(column4)shown.

Forexample,L VTTL,withdrivestrength12andslewrateSLOW ,hasamaximumof 15SSOsperpower/groundpair.

MAX_SSO_PER_IOSTD_PER_BANK\

IOSTD_SSODRIVE=12NAME=LVTTLSLEW=SLOWTYPE=INT15\ IOSTD_SSODRIVE=12NAME=LVTTLSLEW=FASTTYPE=INT10\ IOSTD_SSODRIVE=2NAME=LVTTLSLEW=SLOWTYPE=INT68\ IOSTD_SSODRIVE=2NAME=LVTTLSLEW=FASTTYPE=INT40\ IOSTD_SSODRIVE=4NAME=LVTTLSLEW=SLOWTYPE=INT41\ IOSTD_SSODRIVE=4NAME=LVTTLSLEW=FASTTYPE=INT24\ IOSTD_SSODRIVE=6NAME=LVTTLSLEW=SLOWTYPE=INT29\ IOSTD_SSODRIVE=6NAME=LVTTLSLEW=FASTTYPE=INT17\ IOSTD_SSODRIVE=8NAME=LVTTLSLEW=SLOWTYPE=INT22\ IOSTD_SSODRIVE=8NAME=LVTTLSLEW=FASTTYPE=INT13\ IOSTD_SSODRIVE=16NAME=LVTTLSLEW=SLOWTYPE=INT11\ IOSTD_SSODRIVE=16NAME=LVTTLSLEW=FASTTYPE=INT8\ IOSTD_SSODRIVE=24NAME=LVTTLSLEW=SLOWTYPE=INT7\ IOSTD_SSODRIVE=24NAME=LVTTLSLEW=FASTTYPE=INT5\

•Deviceglobal,localandregionalclockingproperties

Foreachtypeofclockavailableonthedevice,PARTGennowreports:

–Whichpinnumbercanbehaveaswhichclocktype

–WhichI/Ocanbedrivenbythisclockpin

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Chapter3:PARTGen

ThisallowsthirdpartytoolstoassignpinsonXilinx®packageswithoutviolating clockingrules.

Thefollowinginformationhasbeenaddedtothepartlist.xctand

partlist.xmloutputforeachclockregionofadevice:

DEVICE_CLKRGN\

NUM_CLKRGNTYPE=INT8\ NUM_CLKRGN_ROWTYPE=INT4\ NUM_CLKRGN_COLTYPE=INT2\

CLKRGNTYPE=STRINGX0Y0\

CLK_CAPABLE_SCOPE\

UNASSOCIATED_PINS\ NUM_UNBONDED_PINSTYPE=INT2\ UNBONDED_PIN_LISTTYPE=STRINGLISTT17R17\ UNBONDED_IOB_LISTTYPE=STRINGLISTIOB_X0Y15IOB_X0Y17\ ASSOCIATED_BUFIO\ NUM_BUFIOTYPE=INT4\ BUFIO_SITESTYPE=STRINGLISTBUFIO_X0Y0BUFIO_X0Y1BUFIO_X1Y0BUFIO_X1Y1\ ASSOCIATED_BUFR\ NUM_BUFRTYPE=INT2\ BUFR_SITESTYPE=STRINGLISTBUFR_X0Y0BUFR_X0Y1\ ASSOCIATED_PINS\ NUM_BONDED_PINSTYPE=INT39\ BONDED_PIN_LISTTYPE=STRINGLISTV18V17W17Y17W19W18U17U16V20V19U15T15U19U18T18\

T17R18R17T20T19R16R15R20R19W8W9Y9Y10W7Y7W10W11W6Y6Y11Y12W5Y5W12\

BONDED_IOB_LISTTYPE=STRINGLISTIOB_X0Y0IOB_X0Y1IOB_X0Y2IOB_X0Y3IOB_X0Y4IOB_X0Y5IOB_\

X0Y6IOB_X0Y7IOB_X0Y8IOB_X0Y9IOB_X0Y10IOB_X0Y11IOB_X0Y12IOB_X0Y13IOB_X0Y14IOB_\ X0Y15IOB_X0Y16IOB_X0Y17IOB_X0Y18IOB_X0Y19IOB_X0Y22IOB_X0Y23IOB_X0Y24IOB_X0Y25IOB_\ X1Y16IOB_X1Y17IOB_X1Y18IOB_X1Y19IOB_X1Y20IOB_X1Y21IOB_X1Y22IOB_X1Y23IOB_X1Y24IOB_\ X1Y25IOB_X1Y26IOB_X1Y27IOB_X1Y28IOB_X1Y29IOB_X1Y30\

PARTGenPartlistFileDeviceAttributesforpartgen-vOptionOnly

ThefollowingPARTGenpartlistledeviceattributesdisplayforthe-vcommand lineoptiononly.

•NumberofIOBSindevice

NIOBS=#

•NumberofbondedIOBS

NBIOBS=#

•SlicesperCLB:SLICES_PER_CLB=#

Forslice-basedarchitectures.Fornon-slicebasedarchitectures,assumeoneslice perCLB.

•Flip-opsforeachslice

FFS_PER_SLICE=#

•Latchesforeachslice

CANBELATCHES={TRUE|FALSE}

•NumberofDCMs,PLLsand/orMMCMs

•LUTsinaslice:LUT_NAME=nameLUT_SIZE=#

•Numberofglobalbuffers:NUM_GLOBAL_BUFFERS=#

(Thenumberofplaceswhereabuffercandriveaglobalclockcombination)

•BlockRAM

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NUM_BLK_RAMS=#BLK_RAM_COLS=#BLK_RAM_COL0=#BLK_RAMCOL1=# BLK_RAM_COL2=#BLK_RAM_COL_3=#BLK_RAM_SIZE=4096x1 BLK_RAM_SIZE=2048x2BLK_RAM_SIZE=512x8BLK_RAM_SIZE=256x16

BlockRAMlocationsaregivenwithreferencetoCLBcolumns.Inthefollowing example,BlockRAM5ispositionedinCLBcolumn32.

NUM_BLK_RAMS=10BLK_RAM_COL_5=32BLK_RAM_SIZE=4096X1

•SelectRAM

NUM_SEL_RAMS=#SEL_RAM_SIZE=#X#

•SelectDualPortRAM

SEL_DP_RAM={TRUE|FALSE}

ThiseldindicateswhethertheselectRAMcanbeusedasadualportram.The assumptionisthatthenumberofaddressableelementsisreducedbyhalf,thatis,the sizeoftheselectRAMinDualPortModeishalfthatindicatedbySEL_RAM_SIZE.

•Speedgradeinformation:SPEEDGRADE=#

DelaysinformationnolongerappearsintheXCTandXMLpartlistles.Delay informationcanbeobtainedusingSpeedprint.Formoreinformation,seethe

Speedprintchapterinthisdocument.

•MaximumLUTconstructedinaslice MAX_LUT_PER_SLICE=#(FromalltheLUTsintheslice)

•MaxLUTconstructedinaCLB:MAX_LUT_PER_CLB=#

ThiselddescribeshowwideaLUTcanbeconstructedintheCLBfromthe availableLUTsintheslice.

•Numberofinternaltristatebuffersinadevice

NUM_TBUFSPERROW=#

•Ifavailableonaparticulardeviceorpackage,PartGenreports:

PARTGenPackageFiles

PARTGenpackagelesareASCIIformattedlesthatcorrelateIOBswithoutput pinnames.PackagelesareinXACTpackageformat,whichisasetofcolumnsof informationaboutthepinsofaparticularpackage.The-p(terse)commandlineoption generatesathreecolumnentrydescribingthepins.The-v(verbose)commandline optionaddssixmorecolumnsdescribingthepins.Thefollowingsectionsdescribethe informationcontainedinthepackageles.

•PARTGenPackageFilesWiththe-pOption

•PARTGenPackageFilesWiththe-vOption

PARTGenPackageFilesUsingthe-pOption

Thepartgen-pcommandlineoptiongeneratespackagelesanddisplaysa three-columnentrydescribingthepins.Seethefollowingtable.

NUM_PPC=# NUM_GT=# NUM_MONITOR=# NUM_DPM=# NUM_PMCD=# NUM_DSP=# NUM_FIFO=# NUM_EMAC=# NUM_MULT=#

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Chapter3:PARTGen

PackageFilesColumnDescriptions

ColumnContentsDescription

Forexample,thecommandpartgen-pxc6vlx75tgeneratesthefollowingpackage les:

•xc6vlx75tff484.pkg

•xc6vlx75tff784.pkg

PackageFileExampleUsingthe-pOption

Followingisanexampleofaportionofthepackageleforanxc6vlx75tff484package:

pin(useraccessiblepin)orpkgpin (dedicatedpin)

pinname

packagepinSpeciesthepackagepin

Containseitherpin(useraccessiblepin) orpkgpin(dedicatedpin)

Foruseraccessiblepins,thenameofthe pinisthebondedpadnameassociated withanIOBonthedevice,orthename ofamulti-purposepin.Fordedicated pins,thenameiseitherthefunctional nameofthepin,ornoconnection(N.C.

packagexc6vlx75tff484 pinIPAD_X1Y25G3 pinIPAD_X0Y31M11 pinIOB_X0Y39M18 . . .

PARTGenPackageFilesUsingthe-vOption

Thepartgen-vcommandlineoptiongeneratespackagelesanddisplaysa nine-columnentrydescribingthepins.Seethefollowingtable.

PackageFilesColumnDescriptions

ColumnContentsDescription

pin(useraccessiblepin)orpkgpin (dedicatedpin)

pinname

packagepinSpeciesthepackagepin

VREFBANK

VCCOBANK

functionnameConsistsofastringindicatinghowthe

Containseitherpin(useraccessiblepin) orpkgpin(dedicatedpin)

Foruseraccessiblepins,thenameofthe pinisthebondedpadnameassociated withanIOBonthedevice,orthename ofamulti-purposepin.Fordedicated pins,thenameiseitherthefunctional nameofthepin,ornoconnection(N.C.

Apositiveintegerassociatedwith therelativebank,or1fornobank association

pinisused.Ifthepinisdedicated, thenthestringwillindicateaspecic function.Ifthepinisagenericuser

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ColumnContentsDescription

CLB

LVDSIOB

ight-timedataFlight-timedatainunitsofmicrons.

PARTGenVerbosePinDescriptorsExample

FollowingareexamplesoftheverbosepindescriptorsinPARTGen.

Chapter3:PARTGen

pin,thestringis“IO”.Ifthepinis multipurpose,anunderscore-separated setofcharacterswillmakeupthestring

ClosestCLBroworcolumntothepin, andappearsintheform

R[0-9]C[0-9]orx[0-9]y[0-9]

Astringforeachpinassociatedwitha LVDSIOB.Thestringconsistsofand indexandtheletterMorS.Indexvalues willgofrom0tothenumberofL VDS pairs.Thevalueforanon-L VDSpin defaultstoN.A.

Ifnoight-timedataisavailable,this columncontainsN/A.

packagexc6vlx75tff484 #PartGenL.44 #padpinvrefvccofunctionnearestdiff.tracelength #namenamebankbanknameCLBpair(um) pinIPAD_X1Y25G3-1-1MGTRXP0_115N.A.N.A.8594 pinIPAD_X0Y31M1100VN_0N.A.N.A.1915 pinIOB_X0Y39M181414IO_L0P_14X0Y380M4111 pinIOB_X0Y38N181414IO_L0N_14X0Y380S3390

PARTGenSyntax

ThePARTGencommandlinesyntaxis:

partgenoptions

optionscanbeanynumberoftheoptionslistedinP ARTGenCommandLineOptions. Enteroptionsinanyorder,precededthemwithadash(minussignonthekeyboard) andseparatethemwithspaces.

Bothpackageandpartlistlescanbegeneratedusingthepartgen-p(terse)and partgen-v(verbose)options.

•partgen-pgeneratesathreecolumnentrydescribingthepins.

•partgen-vaddssixmorecolumnsdescribingthepins.

PARTGenCommandLineOptions

ThissectiondescribesthePARTGencommandlineoptions.

•PARTGen–arch(OutputInformationforSpeciedArchitecture)

•PARTGen–i(OutputListofDevices,Packages,andSpeeds)

•PARTGen–intstyle(SpecifyIntegrationStyle)

•PARTGen–nopkgle(GenerateNoPackageFile)

•PARTGen–p(GeneratePartlistandPackageFiles)

•PARTGen–v(GeneratePartlistandPackageFiles)

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-arch(OutputInformationforSpeciﬁedArchitecture)

Thisoptionoutputsalistofdevices,packages,andspeedsforaspeciedarchitecture.

Syntax

-archarchitecture_name

Allowedvaluesforarchitecture_nameare:

•acr2(forAutomotiveCoolRunner™-II)

•aspartan3(forAutomotiveSpartan®-3)

•aspartan3a(forAutomotiveSpartan-3A)

•aspartan3adsp(forAutomotiveSpartan-3ADSP)

•aspartan3e(forAutomotiveSpartan-3E)

•aspartan6(forAutomotiveSpartan-6)

•kintex7(forKintex™-7)

•kintex7l(forKintex-7LowerPower)

•qrvirtex4(forQPro™Virtex®-4RadTolerant)

•qvirtex4(forQProVirtex-4Hi-Rel)

•qvirtex5(forQProVirtex-5Hi-Rel)

•qspartan6(forQProSpartan-6Hi-Rel)

•qvirtex6(forQProVirtex-6Hi-Rel)

•spartan3(forSpartan-3)

•spartan3a(forSpartan-3A)

•spartan3adsp(forSpartan-3ADSP)

•spartan3e(forSpartan-3E)

•spartan6(forSpartan-6)

•virtex4(forVirtex-4)

•virtex5(forVirtex-5)

•virtex6(forVirtex-6)

•virtex6l(forVirtex-6LowerPower)

•virtex7(forVirtex-7)

•virtex7l(forVirtex-7LowerPower)

•xa9500xl(forAutomotiveXC9500XL)

•xbr(forCoolRunner-II)

•xc9500(forXC9500)

•xc9500xl(forXC9500XL)

•xpla3(forCoolRunnerXPLA3)

-i(OutputListofDevices,Packages,andSpeeds)

Thisoptionoutputsalistofdevices,packages,andspeedsforeveryinstalleddevice.

Syntax

-i

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-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

-nopkgﬁle(GenerateNoPackageFile)

Chapter3:PARTGen

Thisoptioncancelstheproductionofthepackageleswhenthe-pand-voptionsare used.The-nopkgfileoptionallowsyoutobypasscreatingpackageles.

Syntax

-nopkgfile

-p(GeneratePartlistandPackageFiles)

Thiscommandlineoptiongenerates:

•PartlistlesinASCII(.xct)andXML(.xml)formats

•PackagelesinASCII(.pkg)format

Syntax

-pname

Validentriesfornameinclude:

•architectures

•devices

•parts

Alllesareplacedintheworkingdirectory.

Ifanarchitecture,device,orpartisnotspeciedwiththisoption,detailedinformation foreveryinstalleddeviceissubmittedtothepartlist.xctle.Formoreinformation, seePARTGenPartlistFiles.

The-poptiongeneratesmoredetailedinformationthanthe-archoption,butless informationthanthe-voption.The-pand-voptionsaremutuallyexclusive.Youcan specifyoneortheotherbutnotboth.Formoreinformationsee:

•PARTGenPackageFiles

•PARTGenPartlistFiles

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-v(GeneratePartlistandPackageFiles)

ExamplesofValidCommandLineEntries

NameExampleCommandLineEntry

architecture

device

part

-pvirtex5

-pxc5vlx110t

-pxc5vlx110tff1136

Thiscommandlineoptiongenerates:

•PartlistlesinASCII(.xct)andXML(.xml)formats

•PackagelesinASCII(.pkg)format

Syntax

-vname

Validentriesfornameinclude:

•architectures

•devices

•parts

Ifnoarchitecture,device,orpartisspeciedwiththe-voption,informationforevery installeddeviceissubmittedtothepartlistle.Formoreinformation,seePARTGen

PartlistFiles.

The-voptiongeneratesmoredetailedinformationthanthe-poption.The-pand-v optionsaremutuallyexclusive.Youcanspecifyoneortheotherbutnotboth.For moreinformation,see:

•PARTGenPackageFiles

•PARTGenPartlistFiles

ExamplesofCommandLineEntriesforthe-vOption

NameExampleCommandLineEntry

architecture

device

part

partgen-vvirtex6 partgen-vxc5vlx110t partgen-vxc5vlx110tff1136

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NetGen

NetGenOverview

Chapter4

ThischapterdescribestheNetGenprogram,whichgeneratesnetlistsforusewith third-partytools.

NetGenisacommandlineexecutablethatreadsXilinx®designlesasinput,extracts datafromthedesignles,andgeneratesnetliststhatareusedwithsupported third-partysimulation,equivalencechecking,andstatictiminganalysistools.

NetGencantakeanimplementeddesignleandwriteoutasinglenetlistforthe entiredesign,ormultiplenetlistsforeachmoduleofahierarchicaldesign.Individual modulesofadesigncanbesimulatedontheirown,ortogetheratthetop-level. ModulesidentiedwiththeKEEP_HIERARCHYattributearewrittenasuser-specied Verilog,VHDL,andSDFnetlistswiththe-mhf(MultipleHierarchicalFiles)option.See

PreservingandWritingHierarchyFilesforadditionalinformation.

NetGenFlows

NetGencanbedescribedashavingthreefundamentalows:simulation,equivalency checking,andthird-partystatictiminganalysis.Thischaptercontainsow-specic sectionsthatdetailtheuseandfeaturesofNetGensupportowsanddescribeany sub-ows.Forexample,thesimulationowincludestwoowstypes:functional simulationandtimingsimulation.

Eachow-specicsectionincludescommandlinesyntax,inputles,outputles,and availablecommandlineoptionsforeachNetGenow.

NetGensyntaxisbasedonthetypeofNetGenowyouarerunning.Fordetailson NetGenowsandsyntax,refertotheow-specicsectionsthatfollow.

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Validnetlistowsare:

•-sim(Simulation)-generatesasimulationnetlistforfunctionalsimulationortiming simulation.Forthisnetlisttype,youmustspecifytheoutputletypeasVerilogor VHDLwiththe-ofmtoption.

netgen-sim[options]

•-ecn(Equivalence)-generatesaVerilog-basedequivalencecheckingnetlist.Forthis netlisttype,youmustspecifyatoolnameafterthe-ecnoption.Possibletoolnames forthisnetlisttypeareconformalorformality.

netgen-ecnconformal|formality[options]

•-sta(StaticTimingAnalysis)-generatesaVerilognetlistforstatictiminganalysis.

netgen-sta[options]

NetGensupportsthefollowingowtypes:

•FunctionalSimulationforFPGAandCPLDdesigns

•TimingSimulationforFPGAandCPLDdesigns

•EquivalenceCheckingforFPGAdesigns

•StaticTimingAnalysisforFPGAdesigns

TheowtypethatNetGenrunsisbasedontheinputdesignle(NGC,NGD,orNCD). Thefollowingtableshowstheoutputletypes,basedontheinputdesignles:

InputDesignFileOutputFileType

NGC

NGD

NGAfromCPLDSIMPRIM-basednetlist,alongwithafull

NCDfromMAPSIMPRIM-basednetlist,alongwithapartial

NCDfromPARSIMPRIM-basednetlist,alongwithafull

NetGenDeviceSupport

Thisprogramiscompatiblewiththefollowingdevicefamilies:

•7series

•Spartan®-3,Spartan-3A,Spartan-3E,andSpartan-6

•Virtex®-4,Virtex-5,andVirtex-6

•CoolRunner™XPLA3andCoolRunner-II

•XC9500andXC9500XL

NetGenOutputFiles

UNISIM-basedfunctionalsimulationnetlist

SIMPRIM-basedfunctionalnetlist

timingSDFle.

timingSDFle

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NetGenSimulationFlow

WithintheNetGenSimulationow ,therearetwosub-ows:functionalsimulationand timingsimulation.ThefunctionalsimulationowmaybeusedforUNISIM-basedor SIMPRIM-basednetlists,basedontheinputle.AninputNGClewillgeneratea UNISIM-basednetlistforfunctionalsimulation.AninputNGDlewillgeneratea SIMPRIM-basednetlistforfunctionalsimulation.Similarly ,timingsimulationcanbe brokendownfurthertopost-maptimingsimulationandpost-partimingsimulation, bothofwhichuseSIMPRIM-basednetlists.

NoteNetGendoesnotlistLOCparameterswhenanNGDleisusedasinput.Inthis

case,UNPLACEDisreportedasthedefaultvalueforLOCparameters.

OptionsfortheNetGenSimulationow(andsub-ows)canbeviewedbyrunning netgen-hsimfromthecommandline.

NetGenFunctionalSimulationFlow

Thissectiondescribesthefunctionalsimulationow ,whichisusedtotranslateNGC andNGDlesintoVerilogorVHDLnetlists.

WhenyouenteranNGCleasinputontheNetGencommandline,NetGeninvokes thefunctionalsimulationowtoproduceaUNISIM-basednetlist.Similarly,whenyou enteranNGDleasinputontheNetGencommandline,NetGeninvokesthefunctional simulationowtoproduceaSIMPRIM-basednetlist.Youmustalsospecifythetypeof netlistyouwanttocreate:VerilogorVHDL.

Chapter4:NetGen

TheFunctionalSimulationowusesthefollowinglesasinput:

•NGC-ThisleoutputbyXSTisusedtocreateaUNISIM-basednetlistsuitablefor usingwithIPCoresandperformingpost-synthesisfunctionalsimulation.

•NGD-ThisleoutputbyNGDBuildcontainsalogicaldescriptionofthedesign andisusedtocreateaSIMPRIM-basednetlist.

FunctionalSimulationforUNISIM-basedNetlists

ForXSTusers,theoutputNGClecanbeenteredonthecommandline.Forthird-party synthesistoolusers,youmustrstusethengcbuildcommandtoconvertallofthe designnetliststoasingleNGCle,whichNetGentakesasinput.

Thefollowingcommandreadsthetop-levelEDIFnetlistandconvertsittoanNGCle:

ngcbuild[options]top_level_netlist_fileoutput_ngc_file

OutputﬁlesforNetGenFunctionalSimulation

•Vle-AIEEE1364-2001compliantVerilogHDLlethatcontainsnetlist informationobtainedfromtheinputdesignles.Thisleisasimulationmodel.It cannotbesynthesized,andcanonlybeusedforsimulation.

•VHDle-AVHDLIEEE1076.4VITAL-2000compliantVHDLlethatcontains netlistinformationobtainedfromtheinputdesignles.Thisleisasimulation model.Itcannotbesynthesized,andcanonlybeusedforsimulation.

SyntaxforNetGenFunctionalSimulation

ThefollowingcommandrunstheNetGenFunctionalSimulationow:

netgen-ofmt[verilog|vhdl][options]input_file[.ngd|.ngc]

-ofmtspeciestheoutputnetlistformat(verilogorvhdl).

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optionsisoneormoreoftheoptionslistedintheOptionsforNetGenSimulation

Flowsection.Inadditiontocommonoptions,thissectionalsocontainsVerilogand

VHDL-specicoptions. input_leistheinputlename.IfanNGDleisused,the.ngdextensionmustbe

specied.

NetGenTimingSimulationFlow

ThissectiondescribestheNetGenTimingSimulationow,whichisusedfortiming vericationonFPGAandCPLDdesigns.ForFPGAdesigns,timingsimulationisdone afterPAR,butmayalsobedoneafterMAPifonlycomponentdelayandnoroute delayinformationisneeded.Whenperformingtimingsimulation,youmustspecify thetypeofnetlistyouwanttocreate:V erilogorVHDL.Inadditiontothespecied netlist,NetGenalsocreatesanSDFleasoutput.TheoutputVerilogandVHDLnetlists containthefunctionalityofthedesignandtheSDFlecontainsthetiminginformation forthedesign.

InputletypesdependonwhetheryouareusinganFPGAorCPLDdesign.Pleaserefer toFPGATimingSimulationandCPLDTimingSimulationbelowfordesign-specic information,includinginputletypes.

FPGATimingSimulation

YoucanverifythetimingofanFPGAdesignusingtheNetGenTimingSimulationow togenerateaVerilogorVHDLnetlistandanSDFle.Thegurebelowillustratesthe NetGenTimingSimulationowusinganFPGAdesign.

TheFPGATimingSimulationowusesthefollowinglesasinput:

•NCD-Thisphysicaldesignlemaybemappedonly ,partiallyorfullyplaced,or partiallyorfullyrouted.

•PCF(optional)-Thisisaphysicalconstraintsle.Ifproratedvoltageortemperature isappliedtothedesign,thePCFmustbeincludedtopassthisinformationto NetGen.See-pcf(PCFFile)formoreinformation.

•ELF(MEM)(optional)-ThislepopulatestheBlockRAMsspeciedinthe.bmm le.See-bd(BlockRAMDataFile)formoreinformation.

TheFPGATimingSimulationowcreatesthefollowingoutputles:

•SDFle-ThisSDF3.0compliantstandarddelayformatlecontainsdelays obtainedfromtheinputdesignles.

•Vle-ThisisaIEEE1364-2001compliantVerilogHDLlethatcontainsthenetlist informationobtainedfromtheinputdesignles.Thisleisasimulationmodel.It cannotbesynthesized,andcanonlybeusedforsimulation.

•VHDle-ThisVHDLIEEE1076.4VITAL-2000compliantVHDLlecontainsthe netlistinformationobtainedfromtheinputdesignles.Thisleisasimulation model.Itcannotbesynthesized,andcanonlybeusedforsimulation.

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CPLDTimingSimulation

YoucanusetheNetGenTimingSimulationowtoverifythetimingofaCPLDdesign afteritisimplementedusingCPLDFitandthedelaysareannotatedusingthe-tsim option.TheinputleistheannotatedNGAlefromtheTSIMprogram.

NoteSeetheCPLDFitchapterandtheTSIMchapterforadditionalinformation.

TheCPLDTimingSimulationowusesthefollowinglesasinput:

NGAle-ThisnativegenericannotatedleisalogicaldesignlefromTSIMthat containsXilinx®primitives.SeetheTSIMchapterforadditionalinformation.

Chapter4:NetGen

TheNetGenSimulationFlowcreatesthefollowingoutputles:

•SDFle-Astandarddelayformatlethatcontainsdelaysobtainedfromtheinput NGAle.

•Vle-AnIEEE1364-2001compliantV erilogHDLlethatcontainsnetlist informationobtainedfromtheinputNGAle.Thisleisasimulationmodel.It cannotbesynthesized,andcanonlybeusedforsimulation.

•VHDle-AVHDLIEEE1076.4VITAL-2000compliantVHDLlethatcontains netlistinformationobtainedfromtheinputNGAle.Thisleisasimulationmodel. Itcannotbesynthesized,andcanonlybeusedforsimulation.

SyntaxforNetGenTimingSimulationFlow

ThefollowingcommandrunstheNetGenTimingSimulationow:

netgen-sim-ofmt[verilog|vhdl][options]input_file[.ncd] verilogorvhdlistheoutputnetlistformatthatyouspecifywiththerequired-ofmt

option.

optionsisoneormoreoftheoptionslistedintheOptionsforNetGenSimulationFlow section.Inadditiontocommonoptions,thissectionalsocontainsVerilogandVHDLspecicoptions.

input_leistheinputlename.

TogethelponthecommandlineforNetGenTimingSimulationcommands,type netgen-hsim.

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OptionsforNetGenSimulationFlow

ThissectiondescribesthesupportedNetGencommandlineoptionsfortiming simulation.

•-aka(WriteAlso-Known-AsNamesasComments)

•-bd(BlockRAMDataFile)

•-bx(BlockRAMInitFilesDirectory)

•-dir(DirectoryName)

•-fn(ControlFlatteningaNetlist)

•-gp(BringOutGlobalResetNetasPort)

•-insert_pp_buffers(InsertPathPulseBuffers)

•-intstyle(IntegrationStyle)

•-mhf(MultipleHierarchicalFiles)

•-ofmt(OutputFormat)

•-pcf(PCFFile)

•-s(Speed)

•-sim(GenerateSimulationNetlist)

•-tb(GenerateTestbenchT emplateFile)

•-ti(TopInstanceName)

•-tp(BringOutGlobal3-StateNetasPort)

•-w(OverwriteExistingFiles)

-aka(WriteAlso-Known-AsNamesasComments)

Thisoptionincludesoriginaluser-denedidentiersascommentsinthenetlist.This optionisusefulifuser-denedidentiersarechangedbecauseofnamelegalization processesinNetGen.

Syntax

-aka

-bd(BlockRAMDataFile)

ThisoptionspeciesthepathandlenameoftheleusedtopopulatetheBlockRAM instancesspeciedinthe.bmmle.Data2MEMcandeterminetheADDRESS_BLOCKin whichtoplacethedatafromaddressanddatainformationinthe.elf(fromEDK)or .memle.Youcanincludemorethanoneinstanceof-bd.

Optionally,youcanspecifytagtagname,inwhichcaseonlytheaddressspaceswith thesamenameinthe.bmmleareusedfortranslation,anddataoutsideofthetagname addressspacesareignored.

Syntax

-bdfilename[.elf|.mem][tagtagname]

NoteWhenusingthisoption,youmustalsouse-bx(BlockRAMInitFilesDirectory)to

specifythedirectoryintowhichtheBlockRAMInitializationleswillbewritten.

-bx(BlockRAMInitFilesDirectory)

ThisoptionspeciesthedirectoryintowhichtheBlockRAMInitializationleswill bewritten.

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Syntax

-bxbram_output_dir

-dir(DirectoryName)

Thisoptionspeciesthedirectoryfortheoutputles.

Syntax

-dirdirectory_name

-fn(ControlFlatteningaNetlist)

Thisoptionoutputsaattenednetlist.Aatnetlistdoesnotincludeanydesign hierarchy.

Syntax

-fn

-gp(BringOutGlobalResetNetasPort)

Chapter4:NetGen

ThisoptioncausesNetGentobringouttheglobalresetsignal(whichisconnectedtoall ip-opsandlatchesinthephysicaldesign)asaportonthetop-leveldesignmodule. Specifyingtheportnameallowsyoutomatchtheportnameyouusedinthefrontend.

Thisoptionisusedonlyiftheglobalresetnetisnotdriven.Forexample,ifyouinclude aSTARTUP_VIRTEX5componentinaVirtex®-5design,youshouldnotenterthe-gp optionbecausetheST ARTUP_VIRTEX5componentdrivestheglobalresetnet.

Syntax

-gpport_name

NoteDonotuseGR,GSR,PRLD,PRELOAD,orRESETasportnames,becausethese

arereservednamesintheXilinx®software.ThisoptionisignoredbyUNISIM-based ows,whichuseanNGCleasinput.

-insert_pp_buffers(InsertPathPulseBuffers)

Thisoptioncontrolswhetherpathpulsebuffersareinsertedintotheoutputnetlistto eliminatepulseswallowing.Pulseswallowingisseenonsignalsinback-annotated timingsimulationswhenthepulsewidthisshorterthanthedelayontheinputport ofthecomponent.Forexample,ifaclockofperiod5ns(2.5nshigh/2.5nslow)is propagatedthroughabuffer,butintheSDF,thePORTorIOPATHdelayfortheinput portofthatbufferisgreaterthan2.5ns,theoutputwillbeunchangedinthewaveform window(e.g.,iftheoutputwas"X"atthestartofsimulation,itwillremainat"X").

NoteThisoptionisavailablewhentheinputisanNCDle.

Syntax

-insert_pp_bufferstrue|false

Bydefaultthiscommandissettofalse.

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

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Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

-mhf(MultipleHierarchicalFiles)

Thisoptionisusedtowritemultiplehierarchicalles.Onehierarchicallewillbe writtenforeachmodulethathastheKEEP_HIERARCHYattribute.

NoteSeePreservingandW ritingHierarchyFilesforadditionalinformation.

Syntax

-ofmt(OutputFormat)

-pcf(PCFFile)

-s(ChangeSpeed)

-mhf

Thisisarequiredoptionthatspeciestheoutputformatfornetlists(eitherVerilog orVHDL).

Syntax

-ofmtverilog|vhdl

ThisoptionletsyouspecifyaPhysicalConstraintsFile(PCF)asinputtoNetGen.You onlyneedtospecifyaPCFleifyouuseproratingconstraints(temperatureand/or voltage).

TemperatureandvoltageconstraintsandprorateddelaysaredescribedintheConstraints

Guide(UG625).

Syntax

-pcfpcf_file.pcf

ThisoptioninstructsNetGentoannotatethedevicespeedgradeyouspecifytothe netlist.

Syntax

-sspeedgrade|min

speedgradecanbeenteredwithorwithouttheleadingdash.Forexample,both-s3 and-s-3areallowed.

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Somearchitecturessupportthe-sminoption,whichinstructsNetGentoannotate aprocessminimumdelay,ratherthanamaximumworst-casetothenetlist.Usethe SpeedprintorPARTGenutilityprogramsinthesoftwaretodeterminewhetherprocess minimumdelaysareavailableforyourtargetarchitecture.SeethePARTGenchapterfor additionalinformation.

SettingsmadewiththisoptionoverrideproratedtimingparametersinthePhysical ConstraintsFile(PCF).Ifyouuse-smin,alleldsintheresultingSDFle (MIN:TYP:MAX)aresettotheprocessminimumvalue.

-sim(GenerateSimulationNetlist)

Thisoptionwritesasimulationnetlist.ThisisthedefaultoptionforNetGen.

Syntax

-sim

-tb(GenerateTestbenchTemplateFile)

Thisoptiongeneratesatestbenchlewitha.tvextensionforverilog,and.tvhd extensionforvhd.Itisaready-to-useVerilogorVHDLtemplatele,basedontheinput NCDle.Thetypeoftemplatele(VerilogorVHDL)isspeciedwiththe-ofmtoption.

Chapter4:NetGen

Syntax

-tb

-ti(TopInstanceName)

Thisoptionspeciesauserinstancenameforthedesignundertestinthetestbench lecreatedwiththe-tboption.

Syntax

-titop_instance_name

-tp(BringOutGlobal3-StateNetasPort)

ThisoptioncausesNetGentobringouttheglobal3-statesignal(whichforcesallFPGA outputstothehigh-impedancestate)asaportonthetop-leveldesignmoduleor outputle.Specifyingtheportnameallowsyoutomatchtheportnameyouusedin thefront-end.

Thisoptionisonlyusediftheglobal3-statenetisnotdriven.

NoteDonotusethenameofanywireorportthatalreadyexistsinthedesign,because

thiscausesNetGentoissueanerror.ThisoptionisignoredinUNISIM-basedows, whichuseanNGCleasinput.

Syntax

-tpport_name

-w(OverwriteExistingFiles)

ThisoptioncausesNetGentooverwritethenetlist(.vhdor.v)leifitexists.By default,NetGendoesnotoverwritethenetlistle.

NoteAllotheroutputlesareautomaticallyoverwritten.

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Syntax

-w

Verilog-SpeciﬁcOptionsforFunctionalandTimingSimulation

ThissectiondescribestheVerilog-speciccommandlineoptionsfortimingsimulation.

•-insert_glbl(Insertglbl.vModule)

•-ism(IncludeSimPrimModulesinVerilogFile)

•-ne(NoNameEscaping)

•-pf(GeneratePINFile)

•-sdf_anno(Include$sdf_annotate)

•-sdf_path(FullPathtoSDFFile)

•-shm(Write$shmStatementsinTestFixtureFile)

•-ul(WriteuselibDirective)

•-vcd(Write$dumpStatementsInTestFixtureFile)

-insert_glbl(Insertglbl.vModule)

ThisoptiontellsNetGentoincludetheglbl.vmoduleintheoutputV erilogsimulation netlist.

Syntax

-insert_glbl[true|false]

Thedefaultvalueofthisoptionistrue. Ifyousetthisoptiontofalse,theoutputVerilognetlistwillnotcontaintheglbl.v

module.Formoreinformationonglbl.v,seetheSynthesisandSimulationDesignGuide

(UG626)

NoteIfthe-mhf(multiplehierarchicalles)optionisused,-insert_glblcannot

besettotrue.

-ism(IncludeSIMPRIMModulesinVerilogFile)

ThisoptionincludesSIMPRIMmodulesfromtheSIMPRIMlibraryintheoutputVerilog (.v)le.Thisoptionletsyouavoidspecifyingthelibrarypathduringsimulation,but increasesthesizeofyournetlistleandyourcompiletime.

Whenyouusethisoption,NetGenchecksthatyourlibrarypathissetupproperly . Followingisanexampleoftheappropriatepath:

$XILINX/verilog/src/simprim

Ifyouareusingcompiledlibraries,thisswitchoffersnoadvantage.Ifyouusethis switch,donotusethe-ulswitch.

NoteThe-ismoptionisvalidforpost-translate(NGD),post-map,andpost-placeand

routesimulationows.

Syntax

-ism

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-ne(NoNameEscaping)

Thisoptionreplacesinvalidcharacterswithunderscores,sothatnameescapingdoes notoccur.Forexample,thenetname“p1$40/empty”becomes“p1$40_empty”when youdonotusenameescaping.Theleadingbackslashdoesnotappearaspartofthe identier.TheresultingVeriloglecanbeusedifavendor’sVerilogsoftwarecannot interpretescapedidentierscorrectly.

Syntax

-ne

Bydefault(withoutthe-neoption),NetGen“escapes”illegalblockornetnamesinyour designbyplacingaleadingbackslash(\)beforethenameandappendingaspaceatthe endofthename.Forexample,thenetname“p1$40/empty”becomes“\p1$40/empty ”whennameescapingisused.IllegalVerilogcharactersarereservedVerilognames, suchas“input”and“output,”andanycharactersthatdonotconformtoVerilognaming standards.

-pf(GeneratePINFile)

ThisoptiontellsNetGentogenerateaPINle.

ThisoptionisavailableforFPGA/Cadenceonly .

Chapter4:NetGen

Syntax

-pf

-sdf_anno(Include$sdf_annotate)

Thisoptioncontrolstheinclusionofthe$sdf_annotateconstructinaVerilognetlist.The defaultforthisoptionistrue.T odisablethisoption,usefalse.

NoteThe-sdf_annooptionisvalidforthetimingsimulationow .

Syntax

-sdf_anno[true|false]

-sdf_path(FullPathtoSDFFile)

ThisoptionoutputstheSDFletothespeciedfullpath.Thisoptionwritesthe fullpathandtheSDFlenametothe$sdf_annotatestatement.Ifafullpathisnot specied,itwritesthefullpathofthecurrentworkdirectoryandtheSDFlename tothe$sdf_annotatestatement.

NoteThe-sdf_pathoptionisvalidforthetimingsimulationow .

Syntax

-sdf_path[path_name]

-shm(Write$shmStatementsinTestFixtureFile)

Thisoptionplaces$shmstatementsinthestructuralVeriloglecreatedbyNetGen. These$shmstatementsallowNC-Verilogtodisplaysimulationdataaswaveforms.This optionisforusewithCadenceNC-Veriloglesonly.

Syntax

-shm

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-ul(WriteuselibDirective)

ThisoptioncausesNetGentowritealibrarypathpointingtotheSimPrimlibraryinto theoutputVerilog(.v)le.Thepathiswrittenasshownbelow:

uselibdir=$XILINX/verilog/src/simprimslibext=.v

$XILINXisthelocationoftheXilinxsoftware. Ifyoudonotentera-uloption,the‘useliblineisnotwrittenintotheVerilogle.

NoteAblank‘uselibstatementisautomaticallyappendedtotheendoftheVerilogle

toclearoutthe‘uselibdata.Ifyouusethisoption,donotusethe-ismoption.

NoteThe-uloptionisvalidforSIMPRIM-basedfunctionalsimulationandtiming

simulationows;althoughnotallsimulatorssupportthe‘uselibdirective.Xilinx recommendsusingthisoptionwithcaution.

Syntax

-ul

-vcd(Write$dumpStatementsInTestFixtureFile)

Thisoptionwrites$dumple/$dumpvarsstatementsintestxture.Thisoptionisforuse withCadenceVeriloglesonly .

Syntax

-vcd

VHDL-SpeciﬁcOptionsforFunctionalandTimingSimulation

ThissectiondescribestheVHDL-speciccommandlineoptionsfortimingsimulation.

•-a(ArchitectureOnly)

•-ar(RenameArchitectureName)

•-extid(ExtendedIdentiers)

•-rpw(SpecifythePulseWidthforROC)

•-tpw(SpecifythePulseWidthforTOC)

-a(ArchitectureOnly)

Thisoptionsuppressesgenerationofentitiesintheoutput.Whenspecied,only architecturesappearintheoutput.Bydefault,NetGengeneratesbothentitiesand architecturesfortheinputdesign.

Syntax

-a

-ar(RenameArchitectureName)

ThisoptionletsyouchangethearchitecturenamegeneratedbyNetGen.Thedefault architecturenameforeachentityinthenetlistisSTRUCTURE.

Syntax

-ararchitecture_name

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-extid(ExtendedIdentiﬁers)

ThisoptioninstructsNetGentowriteVHDLextendedidentiers.Therearetwotypes ofidentiers:basicandextended.Bydefault,NetGenwritesbasicidentiersonly .

Syntax

-extid

-rpw(SpecifythePulseWidthforROC)

Thisoptionspeciesthepulsewidth,innanoseconds,fortheROCcomponent.You mustspecifyapositiveintegertosimulatethecomponent.Thisoptionisnotrequired. Bydefault,theROCpulsewidthissetto100ns.

Syntax

-rpwroc_pulse_width

-tpw(SpecifythePulseWidthforTOC)

Chapter4:NetGen

Thisoptionspeciesthepulsewidth,innanoseconds,fortheTOCcomponent.You mustspecifyapositiveintegertosimulatethecomponent.Thisoptionisrequiredwhen youinstantiatetheTOCcomponent(forexample,whentheglobalset/resetandglobal 3-Statenetsaresourcelessinthedesign).

Syntax

-tpwtoc_pulse_width

NetGenEquivalenceCheckingFlow

ThissectiondescribestheNetGenEquivalenceCheckingow,whichisusedforformal vericationofFPGAdesigns.ThisowcreatesaVerilognetlistandconformalor formalityassertionleforusewithsupportedequivalencecheckingtools.

Post-NGDBuildFlowforFPGAs

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Post-ImplementationFlowforFPGAs

InputﬁlesforNetGenEquivalenceChecking

TheNetGenEquivalenceCheckingowusesthefollowinglesasinput:

•NGDle-ThisleisalogicaldescriptionofanunmappedFPGAdesign.

•NCDle-Thisphysicaldesignlemaybemappedonly ,partiallyorfullyplaced, orpartiallyorfullyrouted.

•NGMle-ThismappeddesignleisgeneratedbyMAPandcontainsinformation onwhatwastrimmedandtransformedduringtheMAPprocess.See-ngm(Design

CorrelationFile)formoreinformation.

•ELF(MEM)(optional)-ThisleisusedtopopulatetheBlockRAMsspeciedinthe .bmmle.See-bd(BlockRAMDataFile)formoreinformation.

OutputﬁlesforNetGenEquivalenceChecking

TheNetGenEquivalenceCheckingowusesthefollowinglesasoutput:

•Verilog(.v)le-AnIEEE1364-2001compliantVerilogHDLlethatcontainsthe netlistinformationobtainedfromtheinputle.Thisleisanequivalencechecking modelandcannotbesynthesizedorusedinanyothermannerthanequivalence checking.

•Formality(.svf)le-AnassertionlewrittenfortheFormalityequivalence checkingtool.Thisleprovidesinformationaboutsomeofthetransformationsthat adesignwentthrough,afteritwasprocessedbyXilinximplementationtools.

•Conformal-LEC(.vxc)le-AnassertionlewrittenfortheConformal-LEC equivalencecheckingtool.Thisleprovidesinformationaboutsomeofthe transformationsthatadesignwentthrough,afteritwasprocessedbyXilinx implementationtools.

NoteForspecicinformationonConformal-LECandFormalitytools,pleasereferto

theSynthesisandSimulationDesignGuide(UG626).

SyntaxforNetGenEquivalenceChecking

ThefollowingcommandrunstheNetGenEquivalenceCheckingow:

netgen-ecn[tool_name][options]input_file[.ncd|.ngd]ngm_file

optionsisoneormoreoftheoptionslistedintheOptionsforNetGenEquivalence

CheckingFlowsection.

tool_nameisarequiredswitchthatgeneratesanetlistcompatiblewithequivalence checkingtools.Validtool_nameargumentsareconformalorformality.For additionalinformationonequivalencecheckingandformalvericationtools,please refertotheSynthesisandSimulationDesignGuide.

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input_leistheinputlename.IfanNGDleisused,the.ngdextensionmustbe specied.

ngm_le(optional,butrecommended)istheinputlename,whichisadesignle, producedbyMAP ,thatcontainsinformationaboutwhatwastrimmedandtransformed duringtheMAPprocess.

TogethelponthecommandlineforNetGenEquivalenceCheckingcommands,type netgen-hecn.

OptionsforNetGenEquivalenceCheckingFlow

ThissectiondescribesthesupportedNetGencommandlineoptionsforequivalence checking.

•-aka(WriteAlso-Known-AsNamesasComments)

•-bd(BlockRAMDataFile)

•-bx(BlockRAMInitFileDirectory)

•-dir(DirectoryName)

•-ecn(EquivalenceChecking)

•-fn(ControlFlatteningaNetlist)

•-intstyle(IntegrationStyle)

•-mhf(MultipleHierarchicalFiles)

•-ne(NoNameEscaping)

•-ngm(DesignCorrelationFile)

•-w(OverwriteExistingFiles)

Chapter4:NetGen

-aka(WriteAlso-Known-AsNamesasComments)

Thisoptionincludesoriginaluser-denedidentiersascommentsinthenetlist.This optionisusefulifuser-denedidentiersarechangedbecauseofnamelegalization processesinNetGen.

Syntax

-aka

-bd(BlockRAMDataFile)

Optionally,youcanspecifytagtagname,inwhichcaseonlytheaddressspaceswith thesamenameinthe.bmmleareusedfortranslation,anddataoutsideofthetagname addressspacesareignored.

Syntax

-bdfilename[.elf|.mem][tagtagname]

NoteWhenusingthisoption,youmustalsouse-bx(BlockRAMInitFilesDirectory)to

specifythedirectoryintowhichtheBlockRAMInitializationleswillbewritten.

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-bx(BlockRAMInitFilesDirectory)

ThisoptionspeciesthedirectoryintowhichtheBlockRAMInitializationleswill bewritten.

Syntax

-bxbram_output_dir

-dir(DirectoryName)

Thisoptionspeciesthedirectoryfortheoutputles.

Syntax

-dirdirectory_name

-ecn(EquivalenceChecking)

Thisoptiongeneratesanequivalencecheckingnetlisttouseinformalvericationofan FPGAdesign.

Foradditionalinformationonequivalencecheckingandformalvericationtools,please refertotheSynthesisandSimulationDesignGuide(UG626).

Syntax

netgen-ecntool_name

tool_nameisthenameofthetoolforwhichtooutputthenetlist.V alidtoolnamesare conformalandformality.

-fn(ControlFlatteningaNetlist)

Thisoptionoutputsaattenednetlist.Aatnetlistdoesnotincludeanydesign hierarchy.

Syntax

-fn

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

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-mhf(MultipleHierarchicalFiles)

Thisoptionisusedtowritemultiplehierarchicalles.Onehierarchicallewillbe writtenforeachmodulethathastheKEEP_HIERARCHYattribute.

NoteSeePreservingandW ritingHierarchyFilesforadditionalinformation.

Syntax

-mhf

-ne(NoNameEscaping)

Syntax

-ne

Chapter4:NetGen

-ngm(DesignCorrelationFile)

ThisoptionisusedtospecifyanNGMdesigncorrelationle.Thisoptionisusedfor equivalencecheckingows.

Syntax

-ngm[ngm_file]

-w(OverwriteExistingFiles)

ThisoptioncausesNetGentooverwritethenetlist(.vhdor.v)leifitexists.By default,NetGendoesnotoverwritethenetlistle.

NoteAllotheroutputlesareautomaticallyoverwritten.

Syntax

-w

NetGenStaticTimingAnalysisFlow

ThissectiondescribestheNetGenStaticTimingAnalysisow,whichisusedfor analyzingthetiming,includingminimumofmaximumdelayvalues,ofFPGAdesigns.

Minimumofmaximumdelaysareusedbystatictiminganalysistoolstocalculate skew,setupandholdvalues.Minimumofmaximumdelaysaretheminimumdelay valuesofadeviceunderaspeciedoperatingcondition(speedgrade,temperatureand voltage).Iftheoperatingtemperatureandvoltagearenotspecied,thentheworstcase temperatureandvoltagevaluesareused.Notethattheminimumofmaximumdelay valueisdifferentfromtheprocessminimumgeneratedbyusingthe-sminoption.

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Chapter4:NetGen

ThefollowingexampleshowsDELAYpropertiescontainingrelativeminimumand maximumdelays.

(DELAY) (ABSOLUTE) (PORTI(234:292:292)(234:292:292)) (IOPATHIO(392:489:489)(392:489:489))

NoteBoththeTYPandMAXeldscontainthemaximumdelay .

NetGenusestheStaticTimingAnalysisowtogenerateVerilogandSDFnetlists compatiblewithsupportedstatictiminganalysistools.

StaticTimingAnalysisFlowforFPGAs

InputﬁlesforStaticTimingAnalysis

TheStaticTimingAnalysisowusesthefollowinglesasinput:

•NCDle-Thisphysicaldesignlemaybemappedonly ,partiallyorfullyplaced, orpartiallyorfullyrouted.

•PCF(optional)-Thisisaphysicalconstraintsle.Ifproratedvoltageand temperatureisappliedtothedesign,thePCFlemustbeincludedtopassthis informationtoNetGen.See-pcf(PCFFile)formoreinformation.

OutputﬁlesforStaticTimingAnalysis

TheStaticTimingAnalysisowusesthefollowinglesasoutput:

•SDFle-ThisSDF3.0compliantstandarddelayformatlecontainsdelays obtainedfromtheinputle.

•Verilog(.v)le-AnIEEE1364-2001compliantVerilogHDLlethatcontainsnetlist informationobtainedfromtheinputle.Thisleisatimingsimulationmodel andcannotbesynthesizedorusedinanymannerotherthanforstatictiming analysis.Thisnetlistusessimulationprimitives,whichmaynotrepresentthe trueimplementationofthedevice.Thenetlistrepresentsafunctionalmodelof theimplementeddesign.

SyntaxforNetGenStaticTimingAnalysis

ThefollowingcommandrunstheNetGenStaticTimingAnalysisow:

netgen-stainput_file[.ncd]

input_leistheinputlename. Togethelponthecommandlineforstatictiminganalysis,typenetgen-hsta.

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OptionsforNetGenStaticTimingAnalysisFlow

ThissectiondescribesthesupportedNetGencommandlineoptionsforstatictiming analysis.

•-aka(WriteAlso-Known-AsNamesasComments)

•-bd(BlockRAMDataFile)

•-bx(BlockRAMInitFileDirectory)

•-dir(DirectoryName)

•-fn(ControlFlatteningaNetlist)

•-intstyle(IntegrationStyle)

•-mhf(MultipleHierarchicalFiles)

•-ne(NoNameEscaping)

•-pcf(PCFFile)

•-s(ChangeSpeed)

•-sta(GenerateStaticTimingAnalysisNetlist)

•-w(OverwriteExistingFiles)

-aka(WriteAlso-Known-AsNamesasComments)

Chapter4:NetGen

Thisoptionincludesoriginaluser-denedidentiersascommentsinthenetlist.This optionisusefulifuser-denedidentiersarechangedbecauseofnamelegalization processesinNetGen.

Syntax

-aka

-bd(BlockRAMDataFile)

Optionally,youcanspecifytagtagname,inwhichcaseonlytheaddressspaceswith thesamenameinthe.bmmleareusedfortranslation,anddataoutsideofthetagname addressspacesareignored.

Syntax

-bdfilename[.elf|.mem][tagtagname]

NoteWhenusingthisoption,youmustalsouse-bx(BlockRAMInitFilesDirectory)to

specifythedirectoryintowhichtheBlockRAMInitializationleswillbewritten.

-bx(BlockRAMInitFilesDirectory)

ThisoptionspeciesthedirectoryintowhichtheBlockRAMInitializationleswill bewritten.

Syntax

-bxbram_output_dir

-dir(DirectoryName)

Thisoptionspeciesthedirectoryfortheoutputles.

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Syntax

-dirdirectory_name

-fn(ControlFlatteningaNetlist)

Thisoptionoutputsaattenednetlist.Aatnetlistdoesnotincludeanydesign hierarchy.

Syntax

-fn

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

-mhf(MultipleHierarchicalFiles)

Thisoptionisusedtowritemultiplehierarchicalles.Onehierarchicallewillbe writtenforeachmodulethathastheKEEP_HIERARCHYattribute.

NoteSeePreservingandW ritingHierarchyFilesforadditionalinformation.

Syntax

-mhf

-ne(NoNameEscaping)

Syntax

-ne

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-pcf(PCFFile)

-s(ChangeSpeed)

Chapter4:NetGen

ThisoptionletsyouspecifyaPhysicalConstraintsFile(PCF)asinputtoNetGen.You onlyneedtospecifyaPCFleifyouuseproratingconstraints(temperatureand/or voltage).

TemperatureandvoltageconstraintsandprorateddelaysaredescribedintheConstraints

Guide(UG625).

Syntax

-pcfpcf_file.pcf

ThisoptioninstructsNetGentoannotatethedevicespeedgradeyouspecifytothe netlist.

Syntax

-sspeedgrade|min

speedgradecanbeenteredwithorwithouttheleadingdash.Forexample,both-s3 and-s-3areallowed.

SettingsmadewiththisoptionoverrideproratedtimingparametersinthePhysical ConstraintsFile(PCF).Ifyouuse-smin,alleldsintheresultingSDFle (MIN:TYP:MAX)aresettotheprocessminimumvalue.

-sta(GenerateStaticTimingAnalysisNetlist)

Thisoptionwritesastatictiminganalysisnetlist.

Syntax

-sta

-w(OverwriteExistingFiles)

ThisoptioncausesNetGentooverwritethenetlist(.vhdor.v)leifitexists.By default,NetGendoesnotoverwritethenetlistle.

NoteAllotheroutputlesareautomaticallyoverwritten.

Syntax

-w

PreservingandWritingHierarchyFiles

Whenhierarchyispreservedduringsynthesisandimplementationusingthe KEEP_HIERARCHYconstraint,theNetGen-mhfoptionwritesseparatenetlistsand SDFles(ifapplicable)foreachpieceofhierarchy .

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Chapter4:NetGen

ThehierarchyofSTARTUPandglbl(V erilogonly)modulesispreservedintheoutput netlist.Ifthe-mhfoptionisusedandthereisatleastonehierarchicalblockwiththe KEEP_HIERARCHYconstraintinthedesign,NetGenwritesoutaseparatenetlistle fortheSTARTUPandglblmodules.IfthereisnoblockwiththeKEEP_HIERARCHY constraint,the-mhfoptionisignoredevenifthereareSTARTUPandglblmodules inthedesign.

Thissectiondescribestheoutputletypesproducedwiththe-mhfoption.Thetypeof netlistoutputbyNetGendependsonwhetheryouarerunningtheNetGensimulation, equivalencechecking,orstatictiminganalysisow .Forsimulation,NetGenoutputsa VerilogorVHDLle.The-ofmtoptionmustbeusedtospecifytheoutputletypeyou wishtoproducewhenyouarerunningtheNetGensimulationow .

NoteWhenVerilogisspecied,the$sdf_annotateisincludedintheVerilognetlistfor

eachmodule.

Thefollowingtableliststhebasenamingconventionforhierarchyoutputles:

HierarchyFileContent

HierarchyFile ContentSimulation

FilewithTop-level Module

FilewithLowerLevel Module

The[module_name]isthenameofthehierarchicalmodulefromthefront-endthattheuser isalreadyfamiliarwith.Therearecaseswhenthe[module_name]coulddiffer,theyare:

•Ifmultipleinstancesofamoduleareusedinthedesign,theneachinstantiationof themoduleisuniquebecausethetimingforthemoduleisdifferent.Thenamesare madeuniquebyappendinganunderscorefollowedbyaINST_stringandacount value(e.g.,numgen,numgen_INST_1,numgen_INST_2).

•Ifanewlenameclasheswithanexistinglenamewithinthenamescope,thenthe newnamewillbe[module_name]_[instance_name].

TestbenchFile

Atestbenchleiscreatedforthetop-leveldesignwhenthe-tboptionisused.The basenameofthetestbenchleisthesameasthebasenameofthedesign,witha.tv extensionforVerilog,anda.tvhdextensionforVHDL.

HierarchyInformationFile

Equivalence Checking

[input_lename] (default),oruser speciedoutput lename

[module_name].sim[module_name].ecn[module_name].sta

[input_lename].ecn, oruserspecied outputlename

StaticTiming Analysis

[input_lename].sta,or

userspeciedoutput lename

Inadditiontowritingseparatenetlists,NetGenalsogeneratesaseparatetextle containinghierarchyinformation.Thefollowinginformationappearsinthehierarchy textle.NONEappearsifoneofthelesdoesnothaverelativeinformation.

//Module:Thenameofthehierarchicaldesignmodule. //Instance:Theinstancenameusedintheparentmodule. //DesignFile:Thenameofthefilethatcontainsthemodule. //SDFFile:TheSDFfileassociatedwiththemodule. //SubModule:Thesubmodule(s)containedwithinagivenmodule. //Module,Instance:Thesubmoduleandinstancenames.

NoteThehierarchyinformationleforatop-leveldesigndoesnotcontainanInstance

eld.

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Thebasenameofthehierarchyinformationleis:design_base_name_mhf_info.txt

TheSTARTUPblockisonlysupportedonthetop-leveldesignmodule.Theglobalset reset(GSR)andglobaltristatesignal(GTS)connectivityofthedesignismaintained asdescribedintheDedicatedGlobalSignalsinBack-AnnotationSimulationsection ofthischapter.

DedicatedGlobalSignalsinBack-AnnotationSimulation

Theglobalsetreset(GSR),PRLDforCPLDs,signalandglobaltristatesignal(GTS)are globalroutingnetspresentinthedesignthatprovideameansofsetting,resetting,or tristatingapplicablecomponentsinthedevice.Thesimulationbehaviorofthesesignals ismodeledinthelibrarycellsoftheXilinxSIMPRIMlibraryandthesimulationnetlist usingtheglblmoduleinVerilogandtheX_ROC/X_TOCcomponentsinVHDL.

ThefollowingsectionsexplaintheconnectivityforVerilogandVHDLnetlists.

GlobalSignalsinVerilogNetlist

ForVerilog,theglblmoduleisusedtomodelthedefaultbehaviorofGSRandGTS.The glbl.GSRandglbl.GTScanbedirectlyreferencedasglobalGSR/GTSsignalsanywhere inadesignorinanylibrarycells.

Chapter4:NetGen

NetGenwritesouttheglblmoduledenitionintheoutputVerilognetlist.Fora non-hierarchicaldesignorasingle-lehierarchicaldesign,thisglblmoduledenition iswrittenatthebottomofthenetlist.Forasingle-lehierarchicaldesign,theglbl moduleisdenedinsidethetop-mostmodule.Foramulti-lehierarchicaldesign(-mhf option),NetGenwritesoutglbl.vasahierarchicalmodule.

IftheGSRandGTSarebroughtouttothetop-leveldesignasportsusingthe-gpand

-tpoptions,thetop-mostmodulehasthefollowingconnectivity:

glbl.GSR=GSR_PORT glbl.GTS=GTS_PORT

TheGSR_PORTandGTS_PORTareportsonthetop-levelmodulecreatedwiththe

-gpand-tpoptions.IfyouuseaSTARTUPblockinthedesign,theSTARTUPblock

istranslatedtobuffersthatpreservetheintendedconnectivityoftheuser-controlled signalstotheglobalGSRandGTS(glbl.GSRandglbl.GTS).

WhenthereisaSTARTUPblockinthedesign,theSTARTUPblockhierarchicallevel isalwayspreservedintheoutputnetlist.TheoutputofSTARTUPisconnectedtothe globalGSR/GTSsignals(glbl.GSRandglbl.GTS).

Forallhierarchicaldesigns,theglblmodulemustbecompiledandreferencedalong withthedesign.ForinformationonsettingtheGSRandGTSforFPGAs,seethe

SynthesisandSimulationDesignGuide(UG626).

GlobalSignalsinVHDLNetlist

GlobalsignalsforVHDLnetlistsareGSRandGTS,whicharedeclaredinthelibrary packageSimprim_Vcomponents.vhd.TheGSRandGTScanbedirectlyreferenced anywhereinadesignorinanylibrarycells.

TheX_ROCandX_TOCcomponentsintheVHDLlibrarymodelthedefaultbehaviorof theGSRandGTS.Ifthe-gpand-tpoptionsarenotused,NetGeninstantiatesX_ROC andX_TOCintheoutputnetlist.EachdesignhasonlyoneinstanceofX_ROCand X_TOC.Forhierarchicaldesigns,X_ROCandX_TOCareinstantiatedinthetop-most modulenetlist.

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Chapter4:NetGen

X_ROCandX_TOCareinstantiatedasshownbelow:

X_ROC(O=>GSR); X_TOC(O=>GTS);.

IftheGSRandGTSarebroughtouttothetop-leveldesignusingthe-gpand-tp options,therewillbenoX_ROCorX_TOCinstantiationinthedesignnetlist.Instead, thetop-mostmodulehasthefollowingconnectivity:

GSR<=GSR_PORT GTS<=GTS_PORT

TheGSR_PORTandGTS_PORTareportsonthetop-levelmodulecreatedwiththe

-gpand-tpoptions.

WhenthereisaSTARTUPblockinthedesign,theSTARTUPblockhierarchicallevel ispreservedintheoutputnetlist.TheoutputofSTARTUPisconnectedtotheglobal GSRandGTSsignals.

ForinformationonsettingGSRandGTSforFPGAs,seetheSynthesisandSimulation

DesignGuide(UG626).

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LogicalDesignRuleCheck(DRC)

ThischapterdescribestheLogicalDesignRuleCheck(DRC).

LogicalDRCOverview

TheLogicalDesignRuleCheck(DRC),alsoknownastheNGDDRC,comprisesaseries ofteststoverifythelogicaldesignintheNativeGenericDatabase(NGD)le.The LogicalDRCperformsdevice-independentchecks.

TheLogicalDRCgeneratesmessagestoshowthestatusofthetestsperformed. Messagescanbeerrormessages(forconditionswherethelogicwillnotoperate correctly)orwarnings(forconditionswherethelogicisincomplete).

TheLogicalDRCrunsautomaticallyatthefollowingtimes:

•AttheendofNGDBuild,beforeNGDBuildwritesouttheNGDle

NGDBuildwritesouttheNGDleifDRCwarningsarediscovered,butdoesnot writeoutanNGDleifDRCerrorsarediscovered.

•AttheendofNetGen,beforewritingoutthenetlistle

Thenetlistwriter(NetGen)doesnotperformtheentireDRC.Itonlyperformsthe NetchecksandNamechecks.ThenetlistwriterwritesoutanetlistleevenifDRC warningsorerrorsarediscovered.

Chapter5

LogicalDRCDeviceSupport

Thisprogramiscompatiblewiththefollowingdevicefamilies:

•7series

•Spartan®-3,Spartan-3A,Spartan-3E,andSpartan-6

•Virtex®-4,Virtex-5,andVirtex-6

•CoolRunner™XPLA3andCoolRunner-II

•XC9500andXC9500XL

LogicalDRCChecks

TheLogicalDRCperformsthefollowingtypesofchecks:

•Blockcheck

•Netcheck

•Padcheck

•Clockbuffercheck

•Namecheck

•Primitivepincheck

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Chapter5:LogicalDesignRuleCheck(DRC)

BlockCheck

TheblockcheckveriesthateachterminalsymbolintheNGDhierarchy(thatis,each symbolthatisnotresolvedtoanylower-levelcomponents)isanNGDprimitive.A blockcheckfailureistreatedasanerror.Aspartoftheblockcheck,theDRCalso checksuser-denedpropertiesonsymbolsandthevaluesonthepropertiestomake suretheyarelegal.

NetCheck

ThenetcheckdeterminesthenumberofNGDprimitiveoutputpins(drivers),3-state pins(drivers),andinputpins(loads)oneachsignalinthedesign.Ifasignaldoes nothaveatleastonedriver(orone3-statedriver)andatleastoneload,awarningis generated.Anerrorisgeneratedifasignalhasmultiplenon-3-statedriversorany combinationof3-stateandnon-3-statedrivers.Aspartofthenetcheck,theDRCalso checksuser-denedpropertiesonsignalsandthevaluesonthepropertiestomake suretheyarelegal.

PadCheck

Thepadcheckveriesthateachsignalconnectedtopadprimitivesobeysthefollowing rules.

•IfthePADisaninputpad,thesignaltowhichitisconnectedcanonlybeconnected tothefollowingtypesofprimitives:

–Buffers

–Clockbuffers

–PULLUP

–PULLDOWN

–KEEPER

–BSCAN

Theinputsignalcanbeattachedtomultipleprimitives,butonlyoneofeachof theabovetypes.Forexample,thesignalcanbeconnectedtoabufferprimitive, aclockbufferprimitive,andaPULLUPprimitive,butitcannotbeconnected toabufferprimitiveandtwoclockbufferprimitives.Also,thesignalcannot beconnectedtobothaPULLUPprimitiveandaPULLDOWNprimitive.Any violationoftherulesaboveresultsinanerror,withtheexceptionofsignals attachedtomultiplepull-upsorpull-downs,whichproducesawarning.A signalthatisnotattachedtoanyoftheabovetypesofprimitivesalsoproducesa warning.

•IfthePADisanoutputpad,thesignalitisattachedtocanonlybeconnectedto oneofthefollowingprimitiveoutputs:

–Asinglebufferprimitiveoutput

–Asingle3-stateprimitiveoutput

–AsingleBSCANprimitive

Inaddition,thesignalcanalsobeconnectedtooneofthefollowingprimitives:

–AsinglePULLUPprimitive

–AsinglePULLDOWNprimitive

–AsingleKEEPERprimitive

Anyotherprimitiveoutputconnectionsonthesignalwillresultinanerror.

Iftheconditionaboveismet,theoutputP ADsignalmayalsobeconnectedto oneclockbufferprimitiveinput,onebufferprimitiveinput,orboth.

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•IfthePADisabidirectionalorunbondedpad,thesignalitisattachedtomustobey therulesstatedaboveforinputandoutputpads.Anyotherprimitiveconnections onthesignalresultsinanerror.Thesignalconnectedtothepadmustbecongured asbothaninputandanoutputsignal;ifitisnot,youreceiveawarning.

•Ifthesignalattachedtothepadhasaconnectiontoatop-levelsymbolofthedesign, thattop-levelsymbolpinmusthavethesametypeasthepadpin,exceptthatoutput padscanbeassociatedwith3-statetop-levelpins.Aviolationofthisruleresults inawarning.

•Ifasignalisconnectedtomultiplepads,anerrorisgenerated.Ifasignalis connectedtomultipletop-levelpins,awarningisgenerated.

ClockBufferCheck

Theclockbuffercongurationcheckveriesthattheoutputofeachclockbuffer primitiveisconnectedtoonlyinverter,ip-oporlatchprimitiveclockinputs,orother clockbufferinputs.Violationsaretreatedaswarnings.

NameCheck

Chapter5:LogicalDesignRuleCheck(DRC)

ThenamecheckveriestheuniquenessofnamesonNGDobjectsusingthefollowing criteria:

•Pinnamesmustbeuniquewithinasymbol.Aviolationresultsinanerror.

•Instancenamesmustbeuniquewithintheinstancespositioninthehierarchy(that is,asymbolcannothavetwosymbolswiththesamenameunderit).Aviolation resultsinawarning.

•Signalnamesmustbeuniquewithinthesignalshierarchicallevel(thatis,ifyou pushdownintoasymbol,youcannothavetwosignalswiththesamename).A violationresultsinawarning.

•Globalsignalnamesmustbeuniquewithinthedesign.Aviolationresultsina warning.

PrimitivePinCheck

Theprimitivepincheckveriesthatcertainpinsoncertainprimitivesareconnected tosignalsinthedesign.

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NGDBuild

ThischapterdescribestheNGDBuildprogram.

NGDBuildOverview

NGDBuildreadsinanetlistleinEDIForNGCformatandcreatesaXilinx®Native GenericDatabase(NGD)lethatcontainsalogicaldescriptionofthedesignintermsof logicelements,suchasANDgates,ORgates,LUTs,ip-ops,andRAMs.

TheNGDlecontainsbothalogicaldescriptionofthedesignreducedtoXilinx primitivesandadescriptionoftheoriginalhierarchyexpressedintheinputnetlist.The outputNGDlecanbemappedtothedesireddevicefamily .

ThefollowinggureshowsasimpliedversionoftheNGDBuilddesignow. NGDBuildinvokesotherprogramsthatarenotshowninthefollowinggure.

Chapter6

NGDBuildDesignFlow

NGDBuildDeviceSupport

Thisprogramiscompatiblewiththefollowingdevicefamilies:

•7series

•Spartan®-3,Spartan-3A,Spartan-3E,andSpartan-6

•Virtex®-4,Virtex-5,andVirtex-6

•CoolRunner™XPLA3andCoolRunner-II

•XC9500andXC9500XL

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Chapter6:NGDBuild

ConvertingaNetlisttoanNGDFile

NGDBuildperformsthefollowingstepstoconvertanetlisttoanNGDle:

1.Readsthesourcenetlist

NGDBuildinvokestheNetlistLauncher.TheNetlistLauncherdeterminestheinput netlisttypeandstartstheappropriatenetlistreaderprogram.Thenetlistreader incorporatesNCFlesassociatedwitheachnetlist.NCFlescontaintimingand layoutconstraintsforeachmodule.TheNetlistLauncherisdescribedindetailinthe

NetlistLauncher(Netlister)appendix.

2.ReducesallcomponentsinthedesigntoNGDprimitives

NGDBuildmergescomponentsthatreferenceotherles.NGDBuildalsonds theappropriatesystemlibrarycomponents,physicalmacros(NMCles),and behavioralmodels.

3.ChecksthedesignbyrunningaLogicalDesignRuleCheck(DRC)ontheconverted design

LogicalDRCisaseriesoftestsonalogicaldesign.ItisdescribedintheLogical

DesignRuleCheckchapter.

4.WritesanNGDleasoutput

NGDBuildInputFiles

NoteThisprocedure,theNetlistLauncher,andthenetlistreaderprogramsare

describedinmoredetailintheAppendix.

NGDBuildusesthefollowinglesasinput:

TheinputdesigncanbeanEDIF200orNGCnetlistle.Iftheinputnetlistisinanother formatrecognizedbytheNetlistLauncher,theNetlistLauncherinvokestheprogram necessarytoconvertthenetlisttoEDIFformatandtheninvokestheappropriatenetlist reader,EDIF2NGD.

WiththedefaultNetlistLauncheroptions,NGDBuildrecognizesandprocessesles withtheextensionsshowninthefollowingtable.NGDBuildsearchesthetop-level designnetlistdirectoryforanetlistlewithoneoftheextensions.Bydefault,NGDBuild searchesforanEDIFlerst.

FileTypeRecognizedExtensions

EDIF

NGC

.sedif,.edn,.edf,.edif .ngc

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Chapter6:NGDBuild

Removealloutofdatenetlistlesfromyourdirectory.Obsoletenetlistlesmaycause errorsinNGDBuild.

•UCFle-TheUserConstraintsFile(UCF)isanASCIIlethatyoucreate.Youcan createthislebyhandorbyusingtheConstraintsEditor.SeetheHelpprovided withtheConstraintsEditorformoreinformation.TheUCFlecontainstimingand layoutconstraintsthataffecthowthelogicaldesignisimplementedinthetarget device.TheconstraintsintheleareaddedtotheinformationintheoutputNGD le.Formoreinformationonconstraints,seetheConstraintsGuide(UG625).

Bydefault,NGDBuildreadstheconstraintsintheUCFleautomaticallyiftheUCF lehasthesamebasenameastheinputdesignleanda.ucfextension.Youcan overridethedefaultbehaviorandspecifyadifferentconstraintslewiththe-uc option.See-uc(UserConstraintsFile)formoreinformation.

•NCF-TheNetlistConstraintsFile(NCF)isproducedbyaCAEvendortoolset.This lecontainsconstraintsspeciedwithinthetoolset.Thenetlistreaderinvokedby NGDBuildreadstheconstraintsinthisleiftheNCFhasthesamenameasthe inputEDIForNGCnetlist.ItaddstheconstraintstotheintermediateNGOleand theoutputNativeGenericDatabase(NGD)le.NCFlesarereadinandannotated totheNGOleduringanedif2ngdconversion.ThisalsoimpliesthatunlikeUCF les,NCFconstraintsonlybindtoasinglenetlist;theydonotcrosslehierarchies.

NoteNGDBuildcheckstomakesuretheNGOleisup-to-dateandreruns

EDIF2NGDonlywhentheEDIFhasatimestampthatisnewerthantheNGOle. UpdatingtheNCFhasnoaffectonwhetherEDIF2NGDisrerun.Therefore,ifthe NGOisup-to-dateandyouonlyupdatetheNCFle(nottheEDIF),usethe-nton optiontoforcetheregenerationoftheNGOlefromtheunchangedEDIFandnew NCF.See-nt(NetlistTranslationType)formoreinformation.

•URFle-TheUserRulesFile(URF)isanASCIIlethatyoucreate.TheNetlist Launcherreadsthisletodeterminetheacceptablenetlistinputles,thenetlist readersthatreadtheseles,andthedefaultnetlistreaderoptions.Thislealso allowsyoutospecifythird-partytoolcommandsforprocessingdesigns.TheURF canaddtooroverridetherulesinthesystemrulesle.

YoucanspecifythelocationoftheURFwiththeNGDBuild-uroption.TheURF musthavea.urfextension.See-ur(ReadUserRulesFile)orUserRulesFile(URF) inAppendixBformoreinformation.

•NGCle-Thisbinarylecanbeusedasatop-leveldesignleorasamodulele:

Top-leveldesignle.

ThisleisoutputbytheXilinxSynthesisTechnology(XST)software.Seethe descriptionofdesignlesearlierinthissectionfordetails.

NoteThisisnotatruenetlistle.However,itisreferredtoasanetlistinthiscontext

todifferentiateitfromtheNGCmodulele.NGClesareequivalenttoNGOles createdbyEDIF2NGD,butarecreatedbyXSTandCOREGenerator™software.

•NMCles-Thesephysicalmacrosarebinarylesthatcontaintheimplementation ofaphysicalmacroinstantiatedinthedesign.NGDBuildreadstheNMCleto createafunctionalsimulationmodelforthemacro.

UnlessafullpathisprovidedtoNGDBuild,itsearchesfornetlist,NCF,NGC,NMC, andMEMlesinthefollowinglocations:

•TheworkingdirectoryfromwhichNGDBuildwasinvoked.

•Thepathspeciedforthetop-leveldesignnetlistontheNGDBuildcommandline.

•Anypathspeciedwiththe-sd(SearchSpeciedDirectory)ontheNGDBuild commandline.

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Chapter6:NGDBuild

NGDBuildIntermediateFiles

NGOles-Thesebinarylescontainalogicaldescriptionofthedesignintermsofits originalcomponentsandhierarchy .TheselesarecreatedwhenNGDBuildreadsthe inputEDIFnetlist.Iftheselesalreadyexist,NGDBuildreadstheexistingles.Ifthese lesdonotexistorareoutofdate,NGDBuildcreatesthem.

NGDBuildOutputFiles

NGDBuildcreatesthefollowinglesasoutput:

•NGDle-TheNativeGenericDatabase(NGD)leisabinarylecontaining alogicaldescriptionofthedesignintermsofbothitsoriginalcomponentsand hierarchyandtheprimitivestowhichthedesignisreduced.

•BLDle-ThisbuildreportlecontainsinformationabouttheNGDBuildrunand aboutthesubprocessesrunbyNGDBuild.SubprocessesincludeEDIF2NGD,and programsspeciedintheURF.TheBLDlehasthesamerootnameastheoutput NGDleanda.bldextension.Theleiswrittenintothesamedirectoryasthe outputNGDle.

NGDBuildSyntax

ngdbuild[options]design_name[ngd_file[.ngd]]

optionscanbeanynumberoftheNGDBuildcommandlineoptionslistedinNGDBuild

Options.Enteroptionsinanyorder,precededthemwithadash(minussignonthe

keyboard)andseparatethemwithspaces.

design_nameisthetop-levelnameofthedesignleyouwanttoprocess.Toensurethe designprocessescorrectly,specifyaleextensionfortheinputle,usingoneofthe legalleextensionsspeciedinOverviewsection.Usinganincorrectornonexistentle extensioncausesNGDBuildtofailwithoutcreatinganNGDle.Ifyouuseanincorrect leextension,NGDBuildmayissueanunexpandederror.

NoteIfyouareusinganNGCleasyourinputdesign,youshouldspecifythe.ngc

extension.IfNGDBuildndsanEDIFnetlistorNGOleintheprojectdirectory,it doesnotcheckforanNGCle.

ngd_leistheoutputleinNGDformat.Theoutputlename,itsextension,andits locationaredeterminedasfollows:

•Ifyoudonotspecifyanoutputlename,theoutputlehasthesamenameas theinputle,withan.ngdextension.

•Ifyouspecifyanoutputlenamewithnoextension,NGDBuildappendsthe.ngd extensiontothelename.

•Ifyouspecifyalenamewithanextensionotherthan.ngd,yougetanerror messageandNGDBuilddoesnotrun.

•Iftheoutputlealreadyexists,itisoverwrittenwiththenewle.

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NGDBuildOptions

Chapter6:NGDBuild

ThissectiondescribestheNGDBuildcommandlineoptions.

•-a(AddPADstoT op-LevelPortSignals)

•-aul(AllowUnmatchedLOCs)

•-aut(AllowUnmatchedTimegroups)

•-bm(SpecifyBMMFiles)

•-dd(DestinationDirectory)

•-f(ExecuteCommandsFile)

•-i(IgnoreUCFFile)

•-insert_keep_hierarchy(InsertKEEP_HIERARCHYconstraint)

•-intstyle(IntegrationStyle)

•-lter(FilterFile)

•-l(LibrariestoSearch)

•-nt(NetlistTranslationType)

•-p(PartNumber)

•-quiet(Quiet)

•-r(IgnoreLOCConstraints)

•-sd(SearchSpeciedDirectory)

•-u(AllowUnexpandedBlocks)

•-uc(UserConstraintsFile)

•-ur(ReadUserRulesFile)

•-verbose(ReportAllMessages)

-a(AddPADstoTop-LevelPortSignals)

Ifthetop-levelinputnetlistisinEDIFformat,thisoptioncausesNGDBuildtoadda PADsymboltoeverysignalthatisconnectedtoaportontheroot-levelcell.Thisoption hasnoeffectonlower-levelnetlists.

Syntax

-a

Usingthe-aoptiondependsonthebehaviorofyourthird-partyEDIFwriter.Ifyour EDIFwritertreatspadsasinstances(likeotherlibrarycomponents),donotuse-a.If yourEDIFwritertreatspadsashierarchicalports,use-atoinferactualpadsymbols.If youdonotuse-awherenecessary ,logicmaybeimproperlyremovedduringmapping. ForEDIFlesproducedbyMentorGraphicsandCadenceschematictools,the-aoption issetautomatically;youdonothavetoenter-aexplicitlyforthesevendors.

NoteTheNGDBuild-aoptioncorrespondstotheEDIF2NGD-aoption.Ifyourun

EDIF2NGDonthetop-levelEDIFnetlistseparately ,ratherthanallowingNGDBuildto runEDIF2NGD,youmustusethetwo-aoptionsconsistently .Ifyoupreviouslyran NGDBuildonyourdesignandNGOlesarepresent,youmustusethe-ntonoption thersttimeyouuse-a.ThisforcesarebuildoftheNGOles,allowingEDIF2NGDto runthe-aoption.

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Chapter6:NGDBuild

-aul(AllowUnmatchedLOCs)

Bydefaulttheprogramgeneratesanerroriftheconstraintsspeciedforpin,net,or instancenamesintheUCForNCFlecannotbefoundinthedesign,andanNGD leisnotwritten.UsethisoptiontogenerateawarninginsteadofanerrorforLOC constraintsandmakesureanNGDleiswritten.

Syntax

-aul

Youmaywanttorunthisprogramwiththe-auloptionifyourconstraintsleincludes locationconstraintsforpin,net,orinstancenamesthathavenotyetbeendenedinthe HDLorschematic.Thisallowsyoutomaintainoneversionofyourconstraintslesfor bothpartiallycompleteandnaldesigns.

NoteWhenusingthisoption,makesureyoudonothavemisspellednetorinstance

namesinyourdesign.Misspellednamesmaycauseinaccurateplacingandrouting.

-aut(AllowUnmatchedTimegroups)

BydefaulttheprogramgeneratesanerroriftimegroupsspeciedintheUCForNCF lecannotbefoundinthedesign,andanNGDleisnotwritten.Usethisoptionto generateawarninginsteadofanerrorfortimegroupconstraintsandmakesurean NGDleiswritten.

Syntax

-aut

Youmaywanttorunthisprogramwiththe-autoptionifyourconstraintsleincludes timegroupconstraintsthathavenotyetbeendenedintheHDLorschematic.This allowsyoutomaintainoneversionofyourconstraintslesforbothpartiallycomplete andnaldesigns.

NoteWhenusingthisoption,makesureyoudonothavemisspelledtimegroupnames

inyourdesign.Misspellednamesmaycauseinaccurateplacingandrouting.

-bm(SpecifyBMMFiles)

ThisoptionspeciesaswitchfortheBMMles.Iftheleextensionismissing,a.bmm leextensionisassumed.

Syntax

-bmfile_name[.bmm]

Ifthisoptionisunspecied,theELForMEMrootlenamewitha.bmmextension isassumed.Ifonlythisoptionisgiven,thenNGDBuildveriesthattheBMMleis syntacticallycorrectandmakessurethattheinstancesspeciedintheBMMleexistin thedesign.Onlyone-bmoptioncanbeused.

-dd(DestinationDirectory)

Thisoptionspeciesthedirectoryforintermediateles(designNGOlesandnetlist les).Ifthe-ddoptionisnotspecied,lesareplacedinthecurrentdirectory .

Syntax

-ddNGOoutput_directory

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-f(ExecuteCommandsFile)

Thisoptionexecutesthecommandlineargumentsinthespeciedcommand_le.

Syntax

-fcommand_file

Formoreinformationonthe-foption,see-f(ExecuteCommandsFile)inthe Introductionchapter.

-i(IgnoreUCFFile)

ThisoptiontellsNGDBuildtoignoretheUCFle.WithoutthisoptionNGDBuildreads theconstraintsintheUCFleautomaticallyiftheUCFleinthetop-leveldesignnetlist directoryhasthesamebasenameastheinputdesignleanda.ucfextension.

Syntax

-i

NoteIfyouusethisoption,donotusethe-ucoption.

Chapter6:NGDBuild

-insert_keep_hierarchy(InsertKEEP_HIERARCHYconstraint)

ThisoptionautomaticallyattachestheKEEP_HIERARCHYconstrainttoeachinput netlist.Itshouldonlybeusedwhenperformingabottom-upsynthesisow,where separatenetlistsarecreatedforeachpieceofhierarchy .Whenusingthisoptionyou shouldusegooddesignpracticesasdescribedintheSynthesisandSimulationDesign

Guide(UG626).

Syntax

-insert_keep_hierarchy

NoteCareshouldbetakenwhentryingtousethisoptionwithCores,astheymay

notbecodedformaintaininghierarchy.

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

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Chapter6:NGDBuild

-ﬁlter(FilterFile)

Thisoptionspeciesalterle,whichcontainssettingstocaptureandltermessages producedbytheprogramduringexecution.

Syntax

-filter[filter_file]

Bydefault,thelterlenameisfilter.filter.

-l(LibrariestoSearch)

Thisoptionletsyoulistthelibrariestosearchwhendeterminingwhatlibrary componentswereusedtobuildthedesign.Thisoptionispassedtotheappropriate netlistreader.TheinformationallowsNGDBuildtodeterminethesourceofthedesign componentssoitcanresolvethecomponentstoNGDprimitives.

Syntax

-l{libname}

Tospecifymultiplelibraries,includemultiple-llibnameentriesontheNGDBuild commandline.

Validentriesforlibnameare:

•xilinxun(Xilinx®Uniedlibrary)

•synopsys

NoteUsing-lxilinxunisoptional,sinceNGDBuildautomaticallyaccessesthese

libraries.IncaseswhereNGDBuildautomaticallydetectsSynopsysdesigns(for example,thenetlistextensionis.sedif),-lsynopsysisalsooptional.

-nt(NetlistTranslationType)

ThisoptiondetermineshowtimestampsaretreatedbytheNetlistLauncherwhenitis invokedbyNGDBuild.Atimestampisinformationinalethatindicatesthedateand timethelewascreated.

Syntax

-nttimestamp|on|off

timestamp(thedefault)instructstheNetlistLaunchertoperformthenormaltimestamp checkandupdateNGOlesaccordingtotheirtimestamps.

ontranslatesnetlistsregardlessoftimestamps(rebuildingallNGOles).

offdoesnotrebuildanexistingNGOle,regardlessofitstimestamp.

-p(PartNumber)

Thisoptionspeciesthepartintowhichyourdesignisimplemented.

Syntax

-ppart_number

NoteForsyntaxdetailsandexamples,see-p(PartNumber)intheIntroductionchapter.

Whenyouusethisoption,theNGDleproducedbyNGDBuildisoptimizedfor mappingintothatarchitecture.

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-quiet(Quiet)

-r(IgnoreLOCConstraints)

Chapter6:NGDBuild

YoudonotneedtospecifyapartifyourNGOlealreadycontainsinformationabout thedesiredvendorandfamily(forexample,ifyouplacedaPARTpropertyina schematicoraCONFIGPARTstatementinaUCFle).However,youcanoverridethe informationintheNGOlewiththe-poptionwhenyourunNGDBuild.

Thisoptiontellstheprogramtoonlyreporterrorandwarningmessages.

Syntax

-quiet

Thisoptioneliminatesalllocationconstraints(LOC=)foundintheinputnetlistorUCF le.Usethisoptionwhenyoumigratetoadifferentdeviceorarchitecture,because locationsinonearchitecturemaynotmatchlocationsinanother.

Syntax

-r

-sd(SearchSpeciﬁedDirectory)

Thisoptionaddsthespeciedsearch_pathtothelistofdirectoriestosearchwhen resolvinglereferences(thatis,lesspeciedintheschematicwithaFILE=lename property)andwhensearchingfornetlist,NGO,NGC,NMC,andMEMles.Youdo nothavetospecifyasearchpathforthetop-leveldesignnetlistdirectory,becauseit isautomaticallysearchedbyNGDBuild.

Syntax

-sd{search_path}

Thesearch_pathmustbeseparatedfromthe-sdoptionbyspacesortabs(forexample,

-sddesignsiscorrect,-sddesignsisnot).Y oucanspecifymultiplesearchpaths

onthecommandline.Eachmustbeprecededwiththe-sdoption;youcannotspecify morethanonesearch_pathwithasingle-sdoption.Forexample,thefollowingsyntaxis acceptableforspecifyingtwosearchpaths:

-sd/home/macros/counter-sd/home/designs/pal2

Thefollowingsyntaxisnotacceptable:

-sd/home/macros/counter/home/designs/pal2

-u(AllowUnexpandedBlocks)

InthedefaultbehaviorofNGDBuild(withoutthe-uoption),NGDBuildgeneratesan errorifablockinthedesigncannotbeexpandedtoNGDprimitives.Ifthiserroroccurs, anNGDleisnotwritten.Ifyouenterthisoption,NGDBuildgeneratesawarning insteadofanerrorifablockcannotbeexpanded,andwritesanNGDlecontaining theunexpandedblock.

Syntax

-u

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Chapter6:NGDBuild

YoumaywanttorunNGDBuildwiththe-uoptiontoperformpreliminarymapping, placementandrouting,timinganalysis,orsimulationonthedesigneventhoughthe designisnotcomplete.Toensuretheunexpandedblocksremaininthedesignwhenitis mapped,runtheMAPprogramwiththe-u(DoNotRemoveUnusedLogic)option,as describedintheMAPchapter.

-uc(UserConstraintsFile)

ThisoptionspeciesaUserConstraintsFile(UCF)fortheNetlistLaunchertoread. UCFlescontaintimingandlayoutconstraintsthataffectthewaythelogicaldesignis implementedinthetargetdevice.

Youcanincludemultipleinstancesofthe-ucoptiononthecommandline.MultipleUCF lesareprocessedintheordertheyappearonthecommandline,andasthoughthey aresimplyconcatenated.

NoteIfyouusethisoption,donotusethe-ioption.

Syntax

-ucucf_file[.ucf]

ucf_leisthenameoftheUCFle.Theuserconstraintslemusthavea.ucfextension. Ifyouspecifyauserconstraintslewithoutanextension,NGDBuildappendsthe.ucf extensiontothelename.Ifyouspecifyalenamewithanextensionotherthan.ucf, yougetanerrormessageandNGDBuilddoesnotrun.

Ifyoudonotentera-ucoptionandaUCFleexistswiththesamebasenameasthe inputdesignleanda.ucfextension,NGDBuildautomaticallyreadstheconstraintsin thisUCFle.

Formoreinformationonconstraints,seetheConstraintsGuide(UG625).

-ur(ReadUserRulesFile)

ThisoptionspeciesauserruleslefortheNetlistLaunchertoaccess.Thisle determinestheacceptablenetlistinputles,thenetlistreadersthatreadtheseles, andthedefaultnetlistreaderoptions.Thislealsoallowsyoutospecifythird-party toolcommandsforprocessingdesigns.

Syntax

-urrules_file[.urf]

Theuserruleslemusthavea.urfextension.Ifyouspecifyauserruleslewithno extension,NGDBuildappendsthe.urfextensiontothelename.Ifyouspecifyale namewithanextensionotherthan.urf,yougetanerrormessageandNGDBuild doesnotrun.

SeeUserRulesFile(URF)inAppendixBformoreinformation.

-verbose(ReportAllMessages)

Thisoptionenhancesscreenoutputtoincludeallmessagesoutputbythetoolsrun: NGDBuild,thenetlistlauncher,andthenetlistreader.Thisoptionisusefulifyouwant toreviewdetailsaboutthetoolsrun.

Syntax

-verbose

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MAP

MAPOverview

Chapter7

ThischapterdescribestheMAPprogram,whichisusedduringtheimplementation processtomapalogicaldesigntoaXilinx®FPGA.

TheMAPprogrammapsalogicaldesigntoaXilinx®FPGA.TheinputtoMAPisan NGDle,whichisgeneratedusingtheNGDBuildprogram.TheNGDlecontainsa logicaldescriptionofthedesignthatincludesboththehierarchicalcomponentsusedto developthedesignandthelowerlevelXilinxprimitives.TheNGDlealsocontainsany numberofNMC(macrolibrary)les,eachofwhichcontainsthedenitionofaphysical macro.Finally ,dependingontheoptionsused,MAPplacesthedesign.

MAPrstperformsalogicalDRC(DesignRuleCheck)onthedesignintheNGDle. MAPthenmapsthedesignlogictothecomponents(logiccells,I/Ocells,andother components)inthetargetXilinxFPGA.

TheoutputfromMAPisanNCD(NativeCircuitDescription)leaphysical representationofthedesignmappedtothecomponentsinthetargetedXilinxFPGA. ThemappedNCDlecanthenbeplacedandroutedusingthePARprogram.

ThefollowinggureshowstheMAPdesignow:

MAPDesignFlow

MAPDeviceSupport

Thisprogramiscompatiblewiththefollowingdevicefamilies:

•7series

•Spartan®-3,Spartan-3A,Spartan-3E,andSpartan-6

•Virtex®-4,Virtex-5,andVirtex-6

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MAPInputFiles

MAPusesthefollowinglesasinput:

•NGDle-NativeGenericDatabase(NGD)le.Thislecontainsalogical descriptionofthedesignexpressedbothintermsofthehierarchyusedwhenthe designwasrstcreatedandintermsoflower-levelXilinxprimitivestowhichthe hierarchyresolves.Thelealsocontainsalloftheconstraintsappliedtothedesign duringdesignentryorenteredinaUCF(UserConstraintsFile).TheNGDle iscreatedbytheNGDBuildprogram.

•NMCle-Macrolibraryle.AnNMClecontainsthedenitionofaphysical macro.WhentherearemacroinstancesintheNGDdesignle,NMClesare usedtodenethemacroinstances.ThereisoneNMCleforeachtypeofmacro inthedesignle.

•GuideNCDle-AnoptionalinputlegeneratedfromapreviousMAPrun.An NCDlecontainsaphysicaldescriptionofthedesignintermsofthecomponentsin thetargetXilinxdevice.AguideNCDleisanoutputNCDlefromaprevious MAPrunthatisusedasaninputtoguidealaterMAPrun.

•GuideNGMle-Anoptionalinputle,whichisabinarydesignlecontaining allofthedataintheinputNGDleaswellasinformationonthephysicaldesign producedbythemapping.SeeGuidedMappingfordetails.

•Activityles-Anoptionalinputle.MAPsupportstwoactivityleformats, .saifand.vcd.

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MAPOutputFiles

Chapter7:MAP

OutputfromMAPconsistsofthefollowingles:

•NCD(NativeCircuitDescription)le-Aphysicaldescriptionofthedesignin termsofthecomponentsinthetargetXilinxdevice.Foradiscussionoftheoutput NCDlenameanditslocation,see-o(OutputFileName).

•PCF(PhysicalConstraintsFile)-AnASCIItextlethatcontainsconstraints speciedduringdesignentryexpressedintermsofphysicalelements.Thephysical constraintsinthePCFareexpressedinXilinxconstraintlanguage.

MAPcreatesaPCFleifonedoesnotexistorrewritesanexistinglebyoverwriting theschematic-generatedsectionofthele(betweenthestatementsSCHEMATIC STARTandSCHEMATICEND).Foranexistingphysicalconstraintsle,MAPalso checkstheuser-generatedsectionforsyntaxerrorsandsignalserrorsbyhalting theoperation.Ifnoerrorsarefoundintheuser-generatedsection,thesection isunchanged.

•NGMle-AbinarydesignlethatcontainsallofthedataintheinputNGDleas wellasinformationonthephysicaldesignproducedbymapping.TheNGMleis usedtocorrelatetheback-annotateddesignnetlisttothestructureandnamingof thesourcedesign.ThisleisalsousedbySmartGuide™technology .

•MRP(MAPreport)-AlethatcontainsinformationabouttheMAPrun.The MRPlelistsanyerrorsandwarningsfoundinthedesign,listsdesignattributes specied,anddetailsonhowthedesignwasmapped(forexample,thelogicthat wasremovedoraddedandhowsignalsandsymbolsinthelogicaldesignwere mappedintosignalsandcomponentsinthephysicaldesign).Thelealsosupplies statisticsaboutcomponentusageinthemappeddesign.SeeMAPReport(MRP)

Fileformoredetails.

•MAP(MAPLog)le-AloglewhichisthelogasitisdumpedbyMapduring operation(asopposedtothereportle(MRP),whichisaformattedlecreated afterMapcompletes).

•PSR(PhysicalSynthesisReport)le-Aledetailstheoptimizationsthatweredone byanyoftheMAPphysicalsynthesisoptions.Theseoptionsinclude–global_opt,

-register_duplication,-retiming,-equivalent_register_removal,

-logic_opt,and–register_duplication.Thisreportwillonlygetgenerated

ifoneoftheseoptionsisenabled.

TheMRP ,MAP ,PCF,andNGMlesproducedbyaMAPrunallhavethesamenameas theoutputNCDle,withtheappropriateextension.IftheMRP ,MAP ,PCF,orNGM lesalreadyexist,theyareoverwrittenbythenewles.

MAPProcess

MAPperformsthefollowingstepswhenmappingadesign.

1.SelectsthetargetXilinx®device,package,andspeed.MAPselectsapartinone ofthefollowingways:

•UsesthepartspeciedontheMAPcommandline.

•Ifapartisnotspeciedonthecommandline,MAPselectsthepartspeciedin

theinputNGDle.IftheinformationintheinputNGDledoesnotspecifya completearchitecture,device,andpackage,MAPissuesanerrormessageand stops.Ifnecessary,MAPsuppliesadefaultspeed.

2.Readstheinformationintheinputdesignle.

3.PerformsaLogicalDRC(DesignRuleCheck)ontheinputdesign.IfanyDRC errorsaredetected,theMAPrunisaborted.IfanyDRCwarningsaredetected, thewarningsarereported,butMAPcontinuestorun.TheLogicalDesignRule

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Chapter7:MAP

Check(DRC)(alsocalledtheNGDDRC)isdescribedintheLogicalDesignRule

Check(DRC)chapter.

NoteStep3isskippediftheNGDBuildDRCwassuccessful.

4.Removesunusedlogic.Allunusedcomponentsandnetsareremoved,unlessthe followingconditionsexist:

•AXilinxSaveconstrainthasbeenplacedonanetduringdesignentry .Ifan

unusednethasanSconstraint,thenetandallusedlogicconnectedtothenet (asdriversorloads)isretained.Allunusedlogicconnectedtothenetisdeleted. ForamorecompletedescriptionoftheSconstraint,seetheConstraintsGuide

(UG625).

•The-uoptionwasspeciedontheMAPcommandline.Ifthisoptionis

specied,allunusedlogiciskeptinthedesign.

5.MapspadsandtheirassociatedlogicintoIOBs.

6.MapsthelogicintoXilinxcomponents(IOBs,Slices,etc.).Themappingisinuenced byvariousconstraints;theseconstraintsaredescribedintheConstraintsGuide

(UG625).

7.UpdatestheinformationreceivedfromtheinputNGDleandwritethisupdated informationintoanNGMle.ThisNGMlecontainsbothlogicalinformationabout thedesignandphysicalinformationabouthowthedesignwasmapped.TheNGM leisusedonlyforback-annotation.Formoreinformation,seeGuidedMapping.

8.Createsaphysicalconstraints(PCF)le.Thisisatextlethatcontainsany constraintsspeciedduringdesignentry .Ifnoconstraintswerespeciedduring designentry ,anemptyleiscreatedsothatyoucanenterconstraintsdirectlyinto theleusingatexteditororindirectlythroughFPGAEditor.

MAPeithercreatesaPCFleifnoneexistsorrewritesanexistinglebyoverwriting theschematic-generatedsectionofthele(betweenthestatementsSCHEMATIC STARTandSCHEMATICEND).Foranexistingconstraintsle,MAPalsochecks theuser-generatedsectionandmayeithercommentoutconstraintswitherrorsor halttheprogram.Ifnoerrorsarefoundintheuser-generatedsection,thesection remainsthesame.

9.AutomaticallyplacesthedesignforallarchitecturesotherthanSpartan®-3or Virtex®-4.ForMAPtorunplacementforSpartan-3orVirtex-4parts,the–timing optionmustbeenabled.

10.RunsaphysicalDesignRuleCheck(DRC)onthemappeddesign.IfDRCerrorsare found,MAPdoesnotwriteanNCDle.

11.CreatesanNCDle,whichrepresentsthephysicaldesign.TheNCDledescribes thedesignintermsofXilinxcomponentsCLBs,IOBs,etc.

12.WritesaMAPreport(MRP)le,whichlistsanyerrorsorwarningsfoundinthe design,detailshowthedesignwasmapped,andsuppliesstatisticsaboutcomponent usageinthemappeddesign.

MAPSyntax

Thefollowingsyntaxmapsyourlogicaldesign:

map[options]infile[.ngd][pcf_file.pcf]

optionscanbeanynumberoftheMAPcommandlineoptionslistedintheMAPOptions sectionofthischapter.Enteroptionsinanyorder,precededthemwithadash(minus signonthekeyboard)andseparatethemwithspaces.

inleistheinputNGDlename.Y oudonotneedtoenterthe.ngdextension,since maplooksforanNGDleasinput.

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Chapter7:MAP

pcf_leisthenameoftheoutputPhysicalConstraintsFile(PCF).Ifnotspecied,thePCF nameandlocationaredeterminedinthefollowingways:

•IfyoudonotspecifyaPCFonthecommandline,thePCFhasthesamenameasthe outputlebutwitha.pcfextension.Theleisplacedintheoutputlesdirectory .

•IfyouspecifyaPCFwithnopathspecier(forexample,cpu_1.pcfinsteadof /home/designs/cpu_1.pcf),thePCFisplacedinthecurrentworkingdirectory .

•Ifyouspecifyaphysicalconstraintslenamewithafullpathspecier(forexample, /home/designs/cpu_1.pcf),thePCFisplacedinthespecieddirectory .

•IfthePCFalreadyexists,MAPreadsthele,checksitforsyntaxerrors,and overwritestheschematic-generatedsectionofthele.MAPalsochecksthe user-generatedsectionforerrorsandcorrectserrorsbycommentingoutphysical constraintsintheleorbyhaltingtheoperation.Ifnoerrorsarefoundinthe user-generatedsection,thesectionisunchanged.

NoteForadiscussionoftheoutputlenameanditslocation,see-o(OutputFileName).

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MAPOptions

ThissectiondescribesMAPoptionsinmoredetail.Thelistingisinalphabeticalorder.

•-activity_le

•-bp(MapSliceLogic)

•-c(PackSlices)

•-cm(CoverMode)

•-detail(GenerateDetailedMAPReport)

•-equivalent_register_removal(RemoveRedundantRegisters)

•-f(ExecuteCommandsFile)

•-global_opt(GlobalOptimization)

•-ignore_keep_hierarchy(IgnoreKEEP_HIERARCHYProperties)

•-intstyle(IntegrationStyle)

•-ir(DoNotUseRLOCstoGenerateRPMs)

•-lter(FilterFile)

•-lc(LutCombining)

•-logic_opt(LogicOptimization)

•-mt(Multi-Threading)

•-ntd(NonTimingDriven)

•-o(OutputFileName)

•-ol(OverallEffortLevel)

•-p(PartNumber)

•-power(PowerOptimization)

•-pr(PackRegistersinI/O)

•-register_duplication(DuplicateRegisters)

•-r(RegisterOrdering)

•-retiming(RegisterRetimingDuringGlobalOptimization)

•-smartguide(SmartGuide)

•-t(PlacerCostTable)

•-timing(Timing-DrivenPackingandPlacement)

•-u(DoNotRemoveUnusedLogic)

•-w(OverwriteExistingFiles)

•-x(PerformanceEvaluationMode)

•-xe(ExtraEffortLevel)

•-xt(RoutingStrategy)

-activity_ﬁle(ActivityFile)

Thisoptionletsyouspecifyaswitchingactivitydataletoguidepoweroptimizations. Thisleistheoutputofasimulationrunonthedesign.Forpowerreduction,MAP usesthisletosetfrequenciesandactivityratessignalsthatarenotinputsoroutputs, butinternaltothedesign.

NoteThisoptionissupportedforallFPGAarchitectures.However,forSpartan®-6,

Virtex®-6,and7seriesdevices,intelligentclockgatingoptimizationisnotaffected bythepoweractivityle.

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Syntax

-bp(MapSliceLogic)

Chapter7:MAP

-activity_fileactivity_file.vhdl|.saif

activity_leisthenameofthe.vhdlor.saifletouseforpoweroptimization.

NoteThisoptionisonlyvalidifyoualsouse-poweron(See-power(Power

Optimization))intheMAPcommandline.

ThisoptionenablesblockRAMmapping.

WhenblockRAMmappingisenabled,MAPattemptstoplaceLUTsandFFsinto single-output,single-portblockRAMs.

Youcancreatealecontainingalistofregisteroutputnetsthatyouwantconverted intoblockRAMoutputs.ToinstructMAPtousethisle,settheenvironmentvariable XIL_MAP_BRAM_FILEtothelename.MAPlooksforthisenvironmentvariablewhen the-bpoptionisspecied.Onlythoseoutputnetslistedinthelearemadeintoblock RAMoutputs.BecauseblockRAMoutputsaresynchronousandcanonlybereset,the registerspackedintoablockRAMmustalsobesynchronousreset.

NoteAnyLUTwithanareagroupconstraintwillnotbeplacedinblockRAM.Any

logictobeconsideredforpackingintoblockRAMmustberemovedfromareagroups.

-c(PackSlices)

Syntax

-bp

Thisoptiondeterminesthedegreetowhichslicesutilizeunrelatedpackingwhenthe designismapped.

NoteSlicepackingandcompressionarenotavailableifyouuse-timing

(timing-drivenpackingandplacement).

Syntax

-c[packfactor]

Thedefaultvalueforpackfactor(novaluefor-c,or-cisnotspecied)is100.

•ForSpartan®-3,Spartan-3A,Spartan-3E,andVirtex®-4deviceswhen-timingis notspecied,packfactorcanbeanyintegerbetween0and100(inclusive).

•ForSpartan-3,Spartan-3A,Spartan-3E,andVirtex-4deviceswhen-timingis specied,packfactorcanonlybe0,1or100.

•ForSpartan-6,Virtex-5,Virtex-6,and7seriesdevices,timing-drivenpackingand placementisalwaysonandpackfactorcanonlybe1or100.

NoteForthesearchitectures,youcanalsotry-lc(LutCombining)toincrease

packingdensity.

Thepackfactor(fornon-zerovalues)isthetargetslicedensitypercentage.

•Apackfactorvalueof0speciesthatonlyrelatedlogic(logichavingsignalsin common)shouldbepackedintoasingleSlice,andyieldstheleastdenselypacked design.

•Apackfactorof1resultsinmaximumpackingdensityasthepackerisattempting 1%sliceutilization.

•Apackfactorof100meansthatonlyenoughunrelatedpackswilloccurtotthe devicewith100%utilization.Thisresultsinminimumpackingdensity.

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Forpackfactorvaluesfrom1to100,MAPmergesunrelatedlogicintothesamesliceonly ifthedesignrequiresdenserpackingtomeetthetargetsliceutilization.Ifthereisno unrelatedpackingrequiredtotthedevice,thenumberofslicesutilizedwhen-c100 isspeciedwillequalthenumberutilizedwhen-c0isspecied.

Althoughspecifyingalowerpackfactorresultsinadenserdesign,thedesignmaythen bemoredifcultplaceandroute.Unrelatedpackscancreatesliceswithconicting placementneedsandthedenserpackingcancreatelocalroutingcongestion.

NoteThe-c1settingshouldonlybeusedtodeterminethemaximumdensity

(minimumarea)towhichadesigncanbepacked.Xilinx®doesnotrecommend usingthisoptionintheactualimplementationofyourdesign.Designspackedtothis maximumdensitygenerallyhavelongerruntimes,severeroutingcongestionproblems inPAR,andpoordesignperformance.

Processingadesignwiththe-c0optionisagoodwaytogetarstestimateofthe numberofSlicesrequiredbyyourdesign.

-cm(CoverMode)

ThisoptionspeciesthecriteriausedduringthecoverphaseofMAP .

NoteThisoptionisnotavailableforSpartan®-6,Virtex®-6,and7seriesarchitectures.

Syntax

-cm[area|speed|balanced]

Inthisphase,MAPassignsthelogictoCLBfunctiongenerators(LUTs).Usethearea, speed,andbalancedsettingsasfollows:

area(thedefault)makesreducingthenumberofLUTs(andthereforethenumberof CLBs)thehighestpriority.

speedhasadifferenteffectdependingonwhetherornotthereareuserspeciedtiming constraints.Fordesignswithuser-speciedtimingconstraints,thespeedmodemakes achievingtimingconstraintsthehighestpriorityandreducingthenumberoflevelsof LUTS(thenumberofLUTsapathpassesthrough)thenextpriority .Fordesignswithno user-speciedtimingconstraints,thespeedmodemakesachievingmaximumsystem frequencythehighestpriorityandreducingthenumberlevelsofLUTsthenextpriority . Thissettingmakesiteasiesttoachievetimingconstraintsafterthedesignisplacedand routed.Formostdesigns,thereisasmallincreaseinthenumberofLUTs(comparedto theareasetting),butinsomecasestheincreasemaybelarge.

balancedtriestobalancethetwopriorities-achievingtimingrequirementsandreducing thenumberofLUTs.Itproducesresultssimilartothespeedsettingbutavoidsthe possibilityofalargeincreaseinthenumberofLUT s.Foradesignwithuser-specied timingconstraints,thebalancedmodemakesachievingtimingconstraintsthehighest priorityandreducingthenumberofLUTSthenextpriority .Forthedesignwithno user-speciedtimingconstraints,thebalancedmodemakesachievingmaximumsystem frequencythehighestpriorityandreducingthenumberofLUTsthenextpriority .

-detail(GenerateDetailedMAPReport)

ThisoptionenablesoptionalsectionsintheMapreport.

Syntax

-detail

Whenyouuse-detail,DCMandPLLcongurationdata(Section12)andinformation oncontrolsets(Section13,Virtex®-5only)areincludedintheMAPreport.

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-equivalent_register_removal(RemoveRedundantRegisters)

Thisoptionremovesredundantregisters.

NoteThisoptionisavailablefor7series,Spartan®-6,Virtex®-6,Virtex-5,andVirtex-4

devicesonly.

Syntax

-equivalent_register_removal{on|off}

Withthisoptionon,anyregisterswithredundantfunctionalityareexaminedtoseeif theirremovalwillincreaseclockfrequencies.Bydefault,thisoptionison.

NoteThisoptionisavailableonlywhenyouusethe-global_opt(GlobalOptimization).

-f(ExecuteCommandsFile)

Thisoptionexecutesthecommandlineargumentsinthespeciedcommand_le.

Syntax

Chapter7:MAP

-global_opt(GlobalOptimization)

-fcommand_file

Formoreinformationonthe-foption,see-f(ExecuteCommandsFile)inthe Introductionchapter.

ThisoptiondirectsMAPtoperformglobaloptimizationroutinesonthefullyassembled netlistbeforemappingthedesign.

NoteThisoptionisavailablefor7series,Spartan®-6,Virtex®-6,Virtex-5,andVirtex-4

devicesonly.

Syntax

-global_optoff|speed|area|power

off(thedefault)tellsMAPnottorunglobaloptimization.

speedoptimizesforspeed.

areaoptimizesforminimumarea(notavailableforVirtex-4devices).

poweroptimizesforminimumpower(notavailableforVirtex-4devices)

Globaloptimizationincludeslogicremappingandtrimming,logicandregister replicationandoptimization,andlogicreplacementof3–statebuffers.Theseroutines willextendtheruntimeofMAPbecauseextraprocessingoccurs.Bydefaultthisoption isoff.

NoteThe-global_optpoweroptioncanusetheactivitydatasuppliedviathe

-activityfileoption

Youcannotusethe-uoptionwith-global_opt.WhenSmartGuide™isenabled (-smartguide),guidepercentageswilldecrease.

NoteSeethe-equivalent_register_removal(RemoveRedundantRegisters)and

-retiming(RegisterRetimingDuringGlobalOptimization)optionsforusewith

-global_opt.SeealsotheRe-SynthesisandPhysicalSynthesisOptimizationssection

ofthischapter.

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-ignore_keep_hierarchy(IgnoreKEEP_HIERARCHYProperties)

ThisoptioncausesMAPtoignoreall"KEEP_HIERARCHY"propertiesonblocks.

Syntax

-ignore_keep_hierarchy

-intstyle(IntegrationStyle)

Thisoptionlimitsscreenoutput,basedontheintegrationstylethatyouarerunning,to warninganderrormessagesonly.

Syntax

-intstyleise|xflow|silent

Whenusing-intstyle,oneofthreemodesmustbespecied:

•-intstyleiseindicatestheprogramisbeingrunaspartofanintegrateddesign environment.

•-intstylexflowindicatestheprogramisbeingrunaspartofanintegrated batchow.

•-intstylesilentlimitsscreenoutputtowarninganderrormessagesonly.

Note-intstyleisautomaticallyinvokedwhenrunninginanintegratedenvironment

suchasProjectNavigatororXFLOW.

-ir(DoNotUseRLOCstoGenerateRPMs)

ThisoptioncontrolshowMAPprocessesRLOCstatements.

Syntax

-irall|off|place

alldisablesallRLOCprocessing.

offallowsallRLOCprocessing.

placetellsMAPtouseRLOCconstraintstogrouplogicwithinSlices,butnottogenerate RPMs(RelationallyPlacedMacros)controllingtherelativeplacementofSlices.

-ﬁlter(FilterFile)

Thisoptionspeciesalterle,whichcontainssettingstocaptureandltermessages producedbytheprogramduringexecution.

Syntax

-filter[filter_file]

Bydefault,thelterlenameisfilter.filter.

-lc(LutCombining)

ThisoptioninstructsMaptocombinetwoLUTcomponentsintoasingleLUT6site, utilizingthedualoutputpinsofthatsite.

NoteThisoptionisavailablefor7series,Spartan®-6,Virtex®-6,andVirtex-5devices

only.

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-logic_opt(LogicOptimization)

Chapter7:MAP

Syntax

-lc[off|auto|area]

off(thedefault)willdisabletheLUTCombiningfeature.

areaisthemoreaggressiveoption,combiningLUTswheneverpossible.

autowillattempttostrikeabalancebetweencompressionandperformance.

Thisoptioninvokespost-placementlogicrestructuringforimprovedtiminganddesign performance.

Syntax

-logic_opton|off

The-logic_optoptionworksonaplacednetlisttotryandoptimizetiming-critical connectionsthroughrestructuringandresynthesis,followedbyincrementalplacement andincrementaltiminganalysis.Afullyplaced,timingoptimizedNCDdesignleis produced.Notethatthisoptionrequirestiming-drivenmapping,whichisenabled withtheMAP-timingoption.WhenSmartGuide™isenabled(-smartguide),guide percentageswilldecrease.

-mt(Multi-Threading)

Syntax

-ntd(NonTimingDriven)

Syntax

NoteSeealsotheRe-SynthesisandPhysicalSynthesisOptimizationssectionofthis

chapter.

ThisoptionletsMAPusemorethanoneprocessor.Itprovidesmulti-threading capabilitiestothePlacer.

NoteThisoptionisavailablefor7series,Spartan®-6,Virtex®-6,andVirtex-5devices

only.

-mtoff|2

Thedefaultisoff.Whenoff,thesoftwareusesonlyoneprocessor.Whenthevalueis 2,thesoftwarewilluse2coresiftheyareavailable.

Thisoptionperformsnon-timingdrivenplacement.

-ntd

Whenthe-ntdswitchisenabled,alltimingconstraintsareignoredandthe implementationtoolsdonotuseanytiminginformationtoplaceandroutethedesign.

NoteToruntheentireowwithouttimingconstraints,the-ntdswitchneedstobe

speciedforbothMAPandPAR.

-o(OutputFileName)

ThisoptionspeciesthenameoftheoutputNCDleforthedesign.

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Syntax

-ooutfile[.ncd]

The.ncdextensionisoptional.Theoutputlenameanditslocationaredeterminedin thefollowingways:

•Ifyoudonotspecifyanoutputlenamewiththe-ooption,theoutputlehasthe samenameastheinputle,witha.ncdextension.Theleisplacedintheinput lesdirectory

•Ifyouspecifyanoutputlenamewithnopathspecier(forexample,cpu_dec.ncd insteadof/home/designs/cpu_dec.ncd),theNCDleisplacedinthecurrent workingdirectory.

•Ifyouspecifyanoutputlenamewithafullpathspecier(forexample, /home/designs/cpu_dec.ncd),theoutputleisplacedinthespecieddirectory .

•Iftheoutputlealreadyexists,itisoverwrittenwiththenewNCDle.Y oudonot receiveawarningwhentheleisoverwritten.

NoteSignalsconnectedtopadsortotheoutputsofip-ops,latches,andRAMSfound

intheinputlearepreservedforback-annotation.

-ol(OverallEffortLevel)

ThisoptionsetstheoverallMAPeffortlevel.Theeffortlevelcontrolstheamountoftime usedforpackingandplacementbyselectingamoreorlessCPU-intensivealgorithm forplacement.

Syntax

-olstd|high

•Usestdforloweffortlevel(fastestruntimeatexpenseofQOR)

•Usehighforhigheffortlevel(bestQORwithincreasedruntime)

Thedefaulteffortlevelishighforallarchitectures. The-oloptionisavailablewhenrunningtiming-drivenpackingandplacementwith

the-timingoption. NoteXilinx®recommendssettingtheMAPeffortleveltoequalorhigherthanthe

PAReffortlevel.

Example

map-timing-olstddesign.ncdoutput.ncddesign.pcf

ThisexamplesetstheoverallMAPeffortleveltostd(fastestruntimeatexpenseof QOR).

-p(PartNumber)

Thisoptionspeciesthepartintowhichyourdesignisimplemented.

Syntax

-ppart_number

NoteForsyntaxdetailsandexamples,see-p(PartNumber)intheIntroductionchapter.

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-power(PowerOptimization)

Chapter7:MAP

Ifyoudonotspecifyapartnumber,MAPselectsthepartspeciedintheinputNGD le.IftheinformationintheinputNGDledoesnotspecifyacompletedeviceand package,youmustenteradeviceandpackagespecicationusingthisoption.MAP suppliesadefaultspeedvalue,ifnecessary .

ThearchitectureyouspecifymustmatchthearchitecturespeciedintheinputNGDle. YoumayhavechosenthisarchitecturewhenyouranNGDBuildorduringanearlier stepinthedesignentryprocess(forexample,youmayhavespeciedthearchitecturein theISE®DesignSuiteorinyoursynthesistool).Ifthearchitecturedoesnotmatch,you mustrunNGDBuildagainandspecifythearchitecture.

Thisoptionspeciesthatplacementisoptimizedtoreducepower.ForSpartan®-6, Virtex®-6,and7seriesdevices,youcanusethehighandxeoptionstospecifytheuse ofintelligentclockgatingalgorithmstofurtherreducepower.

Syntax

-poweron|off|high|xe

offspeciesthatnopoweroptimizationwithanegativeeffectonruntime,memoryor

performancewillbeperformed.Thisisthedefaultoption. on(standard)speciestheuseofpoweroptimizationalgorithmsduringplacementto

decreasecapacitiveloadingondataandclockingnetstoreduceoveralldynamicpower. Themaintrade-offwiththisoptionisadditionalruntimeandmodiedplacement,which mayresultinslightlyreducedperformance.Thisoptionisavailableforallarchitectures.

highspeciestheuseofintelligentclockgatingalgorithmsthatreduceoverallswitching toreducedynamicpowerinthedesign.Themaintrade-offwiththisoptionisadditional runtime,minorareaincrease,increasedsystemmemoryrequirementsandadditional logicinthedataorcontrolpathsthatcanresultinreducedperformance.However,the powersavingsisgenerallymoresubstantialthansavingswhenyouuseon(standard). ThisoptionisavailableforSpartan-6andVirtex-6,and7seriesdevicesonly.

xe(extraeffort)speciestheuseofbothstandardandhighalgorithmsforthegreatest reductionindynamicpoweroptimization.However,thisselectiongenerallyhas thelargestimpactonruntime,area,memory,andperformance.Thisoptionisonly recommendedwhenyouhaveadequatetimingslackinthedesignandadditional runtimeandmemorycanbetolerated.ThisoptionisavailableforSpartan-6and Virtex-6,and7seriesdevicesonly.

Whenyouuse-poweron,youcanalsospecifyaswitchingactivityletofurther improvepoweroptimization.Formoreinformationsee-activity_le.

Youcanusethe-poweroptionwiththe-global_optpowerswitchforadditional poweroptimizationandimprovement.Formoreinformationsee-global_opt.

-pr(PackRegistersinI/O)

ThisoptionplacesregistersinI/O.

Syntax

-proff|i|o|b

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Bydefault(withoutthe-proption),MAPonlyplacesip-opsorlatcheswithinan I/OcomponentifanIOB=TRUEattributehasbeenappliedtotheregistereitherby thesynthesistoolorbytheUserConstraintsFile(.ucf).The-proptionspeciesthat ip-opsorlatchesmaybepackedintoinputregisters(iselection),outputregisters (oselection),orboth(bselection)evenifthecomponentshavenotbeenspeciedin thisway .Ifthisoptionisnotspecied,defaultstooff.AnIOBpropertyonaregister, whethersettoTRUEorFALSE,willoverridethe–proptionforthatspecicregister.

-register_duplication(DuplicateRegisters)

Thisoptionduplicatesregisters.

Syntax

-register_duplicationon|off

The-register_duplicationoptionisonlyavailablewhenrunningtiming-driven packingandplacementwiththe-timingoption.The-register_duplication optionduplicatesregisterstoimprovetimingwhenrunningtiming-drivenpacking.See

-timing(Timing-DrivenPackingandPlacement).

-retiming(RegisterRetimingDuringGlobalOptimization)

Syntax

-r(RegisterOrdering)

Syntax

Thisoptionregistersretimingduringglobaloptimization.

NoteThisoptionisavailablefor7series,Spartan®-6,Virtex®-6,Virtex-5,andVirtex-4

devicesonly.

-retimingon|off

Whenthisoptionison,registersaremovedforwardorbackwardsthroughthelogic tobalanceoutthedelaysinatimingpathtoincreasetheoverallclockfrequency .By default,thisoptionisoff.

Theoverallnumberofregistersmaybealteredduetotheprocessing.

NoteThisoptionisavailableonlywhen-global_opt(GlobalOptimization)isused.

Thisoptiongroupsregistersformingabusintoorderedsequencespackedinaslice.The registersaredeterminedtoformabusbasedontheirnames.

-r[4|off|8]

offdisablesregisterordering.

4(thedefault)uses4registerspersliceiftheyarenotsourcedbyaLUT(otherwise uses8registers).

8usesall8registersintheslice.

-smartguide(SmartGuide)

Thisoptioninstructstheprogramtouseresultsfromapreviousimplementationtoguide thecurrentimplementation,basedonaplacedandroutedNCDle.SmartGuide™ technologyautomaticallyenablestiming-drivenpackingandplacementinMAP(map

-timing),whichimprovesdesignperformanceandtimingforhighlyutilizeddesigns.

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Chapter7:MAP

Youmayobtainbetterresultsifyouusethemap-timingoptiontocreateaplacedand routedNCDguidelebeforeenablingSmartGuidetechnology .SmartGuidetechnology canbeenabledfromthecommandlineorfromtheHierarchypaneoftheDesignpanel inProjectNavigator.

Syntax

-smartguidedesign_name.ncd

NoteSmartGuidetechnologywillgiveyouahigherguidepercentageifanNGMle

isavailable.TheNGMlecontainsinformationonthetransformationsdoneinthe MAPprocess.SeetheMAPProcesssectionofthischapterforinformationonhow MAPdetectstheNGMle.

WithSmartGuidetechnology ,allguidingisdoneinMAPattheBELlevel.Guiding includespacking,placement,androuting.SmartGuidetechnologyoptimallychanges thepackingandplacementofadesignandthenroutesnewnetsduringPAR.Therst goalofSmartGuidetechnologyistomaintaindesignimplementationontheunchanged partandmeettimingrequirementsonthechangedpart;thesecondgoalistoreduce runtime.Noticethattheunchangedpartoftheimplementationwillnotbechangedand thereforewillkeepthesametimingscore.Pathsthatfailtimingbutdonotchange shouldbe100%guided.Pathsthatfailtimingandarechangedwillbere-implemented.

TheresultsfromtheMAPrunarestoredintheoutputmapreportle(.mrp).Guide statistics,includingthenumberofguidednetsandallnew ,guided,andre-implemented componentsarelistedinthemapreport,whichisanestimatedreport.Thenalstatistics arelistedinthePARreportle(.par).Aseparateguidereportle(.grf)isgenerated byPAR.Ifyouuse-smartguideinthePARcommandline,adetailedguidereportle iscreated.Ifyoudonotuse-smartguide,asummaryguidereportleiscreated.The guidereportlelistscomponentsandnetsthatarere-implementedornew.

The-timingoptionenablesalloptionsspecictotiming-drivenpackingand placement.Thisincludesthe-oloption,whichsetstheoveralleffortlevelusedto packandplacethedesign.See-ol(OverallEffortLevel)formoreinformation.The followingoptionsareenabledwhenyouuse-timing:-logic_opt,-ntd,-ol,

-register_duplication,-x,and-xe.Seeindividualoptiondescriptionsinthis

sectionfordetails.Seealso-timing(Timing-DrivenPackingandPlacement)formore information.

-t(PlacerCostTable)

Thisoptionspeciesthecosttableusedbytheplacer.

Syntax

-t[placer_cost_table]

placer_cost_tableisthecosttabletheplaceruses(placercosttablesaredescribedinthe PARChapter).Validvaluesare1–100andthedefaultis1.

Toautomaticallycreateimplementationsusingseveraldifferentcosttables,pleaserefer totheSmartXplorersectioninthisdocument.

NoteThe-toptionisonlyavailablewhenrunningtiming-drivenpackingand placementwiththe-timingoption.

-timing(Timing-DrivenPackingandPlacement)

Thisoptionisusedtoimprovedesignperformance.ItinstructsMAPtodobothpacking andplacementofthedesign.User-generatedtimingconstraintsspeciedinaUCF/NCF ledrivethesepackingandplacementoperations.

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Note–timingisoptionalforallSpartan®-3familiesandVirtex®-4devices(defaultis

off).ItisalwaysonforSpartan-6,Virtex-5,Virtex-6,and7seriesdevices.

Syntax

-timing

Whenyouspecify-timing,placementoccursinMAPratherthaninPAR.Usingthis optionmayresultinlongerruntimesforMAP ,thoughitwillreducethePARruntime.

Timing-drivenpackingandplacementisrecommendedtoimprovedesignperformance, timing,andpackingforhighlyutilizeddesigns.Iftheunrelatedlogicnumber(shownin theDesignSummarysectionoftheMAPreport)isnon-zero,thenthe-timingoptionis usefulforpackingmorelogicinthedevice.Timing-drivenpackingandplacementis alsorecommendedwhentherearelocalclockspresentinthedesign.Iftiming-driven packingandplacementisselectedintheabsenceofusertimingconstraints,thetoolswill automaticallygenerateanddynamicallyadjusttimingconstraintsforallinternalclocks. ThisfeatureisreferredtoasPerformanceEvaluationMode.Seealso-x(Performance

EvaluationMode)formoreinformation.Thismodeallowstheclockperformanceforall

clocksinthedesigntobeevaluatedinonepass.Theperformanceachievedbythismode isnotnecessarilythebestpossibleperformanceeachclockcanachieve,insteaditisa balanceofperformancebetweenallclocksinthedesign.

-register_duplication,-x,and-xe.Seeindividualoptiondescriptionsinthis

sectionfordetails.SeealsoRe-SynthesisandPhysicalSynthesisOptimizationsinthis chapterformoreinformation.

-u(DoNotRemoveUnusedLogic)

ThisoptiontellsMAPnottoeliminateunusedcomponentsandnetsfromthedesign.

Syntax

-u

Bydefault(withoutthe-uoption),MAPeliminatesunusedcomponentsandnetsfrom thedesignbeforemapping.Unusedlogicislogicthatisundriven,doesnotdriveother logic,orlogicthatactsasa“cycle”andaffectsnodeviceoutput.When–uisspecied, MAPappliesan“S”(NOCLIP)propertytoalldanglingsignalswhichpreventstrimming frominitiatingatthatpointandcascadingthroughthedesign.Danglingcomponents maystillbetrimmedunlessadanglingsignalispresenttoaccepttheNOCLIPproperty .

-w(OverwriteExistingFiles)

ThisoptioninstructsMAPtooverwriteexistingoutputles,includinganexisting designle(NCD).

Syntax

-w

-x(PerformanceEvaluationMode)

The-xoptionisusediftherearetimingconstraintsspeciedintheuserconstraintsle, andyouwanttoexecuteaMAPandPARrunwithtool-generatedtimingconstraints insteadtoevaluatingtheperformanceofeachclockinthedesign.

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Syntax

-x

Thisoperationisreferredtoas"PerformanceEvaluation"mode.Thismodeisentered intoeitherbyusingthe-xoptionorwhennotimingconstraintsareusedina design.Thetoolscreatetimingconstraintsforeachinternalclockseparatelyandwill tighten/loosentheconstraintbasedonfeedbackduringexecution.TheMAPeffortlevel controlswhetherthefocusisonfastestruntime(STD)orbestperformance(HIGH).

NoteWhile–xignoresalluser-generatedtimingconstraints,speciedinaUCF/NCF

le,allphysicalconstraintssuchasLOCandAREA_GROUPSareused.

NoteThe-xand-ntdswitchesaremutuallyexclusive.Ifusertimingconstraintsare

notused,onlyoneautomatictimingmodemaybeselected.

-xe(ExtraEffortLevel)

The-xeoptionisavailablewhenrunningtiming-drivenpackingandplacementwith the-timingoption,andsetstheextraeffortlevel.

Syntax

-xeeffort_level

Chapter7:MAP

effort_levelcanbesetton(normal)orc(continue).when-xeissettoc,MAPcontinues toattempttoimprovepackinguntillittleornoimprovementcanbemade.

map-olhigh-xendesign.ncdoutput.ncddesign.pcf

-xt(ExtraPlacerCostTable)

Thisoptionspeciescosttablessuitedforhighlyutilizeddesigns.Thesetablescanbe usedalongwiththeregularcosttables(the-toption).

Thisoptionisavailableonlyfor7series,Spartan®-6,andVirtex®-6devices.

Syntax

-xtcost_table

cost_tableisanintegerbetween0and5(inclusive)thatwillselectvariationsofthe algorithmstoletyoumorecloselyoptimizethemtoyourdesign.Thedefaultis0.

ResynthesisandPhysicalSynthesisOptimizations

MAPprovidesoptionsthatenableadvancedoptimizationsthatarecapableofimproving timingresultsbeyondstandardimplementations.Theseadvancedoptimizationscan transformthedesignpriortoorafterplacement.

OptimizationscanbeappliedattwodifferentstagesintheXilinx®designow .Therst stagehappensrightaftertheinitialmappingofthelogictothearchitectureslices.The MAP-global_optoptiondirectsMAPtoperformglobaloptimizationroutinesonafully mappeddesign,beforeplacement.See-global_opt(GlobalOptimization)and-retiming

(RegisterRetimingDuringGlobalOptimization)formoreinformation.

Thesecondstagewhereoptimizationscanbeappliedisafterplacement,whenpaths thatdonotmeettimingareevaluatedandre-synthesized.MAPtakestheinitialnetlist, placesit,andthenanalyzesthetimingofthedesign.Whentimingisnotmet,MAP performsphysicalsynthesisoptimizationsandtransformsthenetlisttomeettiming.To enablephysicalsynthesisoptimizations,timing-drivenplacementandrouting(-timing) mustbeenabled.

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GuidedMapping

Physicalsynthesisoptimizationsareenabledwiththe-logic_opt(LogicOptimization) and-register_duplication(DuplicateRegisters)options.SeetheMAPOptionssectionof thischapterforoptiondescriptionsandusageinformation.

Inguidedmapping,anexistingNCDisusedtoguidethecurrentMAPrun.Theguide lemaybefromanystageofimplementation:unplacedorplaced,unroutedorrouted. Xilinx®recommendsgeneratinganNCDleusingthecurrentreleaseofthesoftware. Usingaguidelegeneratedbyaprevioussoftwarereleaseusuallyworks,butmay notbesupported.

NoteWhenusingguidedmappingwiththe-timingoption,Xilinxrecommendsusinga

placedNCDastheguidele.AplacedNCDisproducedbyrunningMAPwiththe

-timingoption,orrunningPAR.

SmartGuide™technologyallowsresultsfromapreviousimplementationtoguidethe nextimplementation.WhenSmartGuideisused,MAPandPARprocessesusetheNCD le,speciedwiththe-smartguideoption,toguidethenewandre-implemented componentsandnets.SmartGuidetechnologymaymoveguidedcomponentsandnets tomeettiming.TherstgoalofSmartGuidetechnologyistomeettimingrequirements; thesecondgoalistoreduceruntime.

SmartGuidetechnologyworksbestattheendofthedesigncyclewhentimingismetand smalldesignchangesarebeingmade.Ifthedesignchangeistoapaththatisdifcultto meettiming,thebestperformancewillbeobtainedwithoutSmartGuidetechnology . OtherexamplesofdesignchangesthatworkwellwithSmartGuidetechnologyare:

•Changestopinlocations

•Changestoattributesoninstantiatedcomponents

•Changesforrelaxingtimingconstraints

•ChangesforaddingaChipScope™core

InthisreleaseofXilinxsoftware,SmartGuidehasreplacedthe-gmand-gfoptions. NoteSee-smartguide(SmartGuide)formoreinformation.

MAPusestheNGMandtheNCDlesasguides.TheNGMlecontainsinformationon thetransformationsdoneintheMAPprocess.YoudonotneedtospecifytheNGMle onthecommandline.MAPinferstheappropriateNGMlefromthespeciedNCD guidele.Ifnomatchisfound,MAPlooksfortheappropriateNGMlebasedonthe embeddedname,whichmayincludethefullpathandname.IfMAPdoesnotnd anNGMleinthesamedirectoryastheNCD,thecurrentdirectory ,orbasedonthe embeddedname,itgeneratesawarning.Inthiscase,MAPusesonlytheNCDleas theguidele,whichmaybelesseffective.

NoteSmartGuidewillhaveahigherguidepercentageiftheNGMleisavailable. TheresultsfromtheMAPrunarestoredintheoutputmapreportle(.mrp).Guide

statistics,includingthenumberofguidednetsandallnew ,guided,andre-implemented componentsarelistedinthemapreport,whichisanestimatedreport.Thenalstatistics arelistedintheoutputPARreport.PARgeneratesaseparateguidereportle(.grf) whenyouusethe-smartguideoptiononthePARcommandline.TheGRFleisa detailedreportthatlistscomponentsthatarere-implementedornew.Italsolistsnets.

NoteSee-smartguide(SmartGuide)formoreinformationandotherswitchinteractions.

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SimulatingMapResults

Chapter7:MAP

WhensimulatingwithNGCles,youarenotsimulatingamappedresult,youare simulatingthelogicalcircuitdescription.WhensimulatingwithNCDles,youare simulatingthephysicalcircuitdescription.

MAPmaygenerateanerrorthatisnotdetectedintheback-annotatedsimulationnetlist. Forexample,afterrunningMAP ,youcanrunthefollowingcommandtogeneratethe back-annotatedsimulationnetlist:

netgenmapped.ncdmapped.ngm-omapped.nga

Thiscommandcreatesaback-annotatedsimulationnetlistusingthelogical-to-physical cross-referencelenamedmapped.ngm.Thiscross-referencelecontainsinformation aboutthelogicaldesignnetlist,andtheback-annotatedsimulationnetlist(mapped.nga) isactuallyaback-annotatedversionofthelogicaldesign.However,ifMAPmakesa physicalerror,forexample,implementsanActiveLowfunctionforanActiveHigh function,thiserrorwillnotbedetectedinthemapped.ngaleandwillnotappear inthesimulationnetlist.

Forexample,considerthefollowinglogicalcircuitgeneratedbyNGDBuildfroma designle,showninthefollowinggure.

LogicalCircuitRepresentation

ObservetheBooleanoutputfromthecombinatoriallogic.Supposethatafterrunning MAPfortheprecedingcircuit,youobtainthefollowingresult.

CLBConﬁguration

ObservethatMAPhasgeneratedanactivelow(C)insteadofanactivehigh(C). Consequently,theBooleanoutputforthecombinatoriallogicisincorrect.Whenyou runNetGenusingthemapped.ngmle,youcannotdetectthelogicalerrorbecausethe delaysareback-annotatedtothecorrectlogicaldesign,andnottothephysicaldesign.

OnewaytodetecttheerrorisbyrunningtheNetGencommandwithoutusingthe mapped.ngmcross-referencele.

netgenmapped.ncd-omapped.nga

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Asaresult,physicalsimulationsusingthemapped.ngaleshoulddetectaphysical error.However,thetypeoferrorisnotalwayseasilyrecognizable.Topinpointtheerror, useFPGAEditororcallXilinx®CustomerSupport.Insomecases,areportederrormay notreallyexist,andtheCLBcongurationisactuallycorrect.YoucanuseFPGAEditor todetermineiftheCLBiscorrectlymodeled.

Finally,ifboththelogicalandphysicalsimulationsdonotdiscoverexistingerrors,you mayneedtousemoretestvectorsinthesimulations.

MAPReport(MRP)File

TheMAPreport(MRP)leisanASCIItextlethatcontainsinformationaboutthe MAPrun.Thereportinformationvariesbasedonthedeviceandwhetheryouusethe

-detailoption(seethe-detail(GenerateDetailedMAPReport)section).

AnabbreviatedMRPleisshownbelowmostreportlesareconsiderablylargerthan theoneshown.Theleisdividedintoanumberofsections,andsectionsappearevenif theyareempty .ThesectionsoftheMRPleareasfollows:

•DesignInformation-ShowsyourMAPcommandline,thedevicetowhichthe

•DesignSummary-Summarizesthemapperrun,showingthenumberoferrors

•TableofContents-ListstheremainingsectionsoftheMAPreport.

•Errors-Showsanyerrorsgeneratedasaresultofthefollowing:

•Warnings-Showsanywarningsgeneratedasaresultofthefollowing:

•Informational-Showsmessagesthatusuallydonotrequireuserinterventionto

•RemovedLogicSummary-Summarizesthenumberofblocksandsignalsremoved

•RemovedLogic-Describesindetailalllogic(designcomponentsandnets)removed

designhasbeenmapped,andwhenthemappingwasperformed.

andwarnings,andhowmanyoftheresourcesinthetargetdeviceareusedby themappeddesign.

–ErrorsassociatedwiththelogicalDRCtestsperformedatthebeginningof

themapperrun.Theseerrorsdonotdependonthedevicetowhichyouare mapping.

–Errorsthemapperdiscovers(forexample,apadisnotconnectedtoanylogic,

orabidirectionalpadisplacedinthedesignbutsignalsonlypassinone directionthroughthepad).Theseerrorsmaydependonthedevicetowhich youaremapping.

–ErrorsassociatedwiththephysicalDRCrunonthemappeddesign.

–WarningsassociatedwiththelogicalDRCtestsperformedatthebeginningof

themapperrun.Thesewarningsdonotdependonthedevicetowhichyou aremapping.

–Warningsthemapperdiscovers.Thesewarningsmaydependonthedevice

towhichyouaremapping.

–WarningsassociatedwiththephysicalDRCrunonthemappeddesign.

preventaproblemlaterintheow .Thesemessagescontaininformationthatmay bevaluablelaterifproblemsdooccur.

fromthedesign.Thesectionreportsonthesekindsofremovedlogic.

fromtheinputNGDlewhenthedesignwasmapped.Generally ,logicisremoved forthefollowingreasons:

–Thedesignusesonlypartofthelogicinalibrarymacro.

–Thedesignhasbeenmappedeventhoughitisnotyetcomplete.

–Themapperhasoptimizedthedesignlogic.

–Unusedlogichasbeencreatedinerrorduringschematicentry.

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XILINX Command Line Tools User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

CommandLineToolsUser Guide

RevisionHistory

TableofContents

CommandLineProgramOverview

CommandLineSyntax

CommandLineOptions

-f(ExecuteCommandsFile)

Syntax

-h(Help)

Syntax

-intstyle(IntegrationStyle)

Syntax

-p(PartNumber)

Syntax

SpecifyingPartNumbers

InvokingCommandLinePrograms

DesignFlowOverview

DesignEntryandSynthesis

HierarchicalDesign

Partitions

PXMLFile

SchematicEntryOverview

LibraryElements

HDLEntryandSynthesis

COREGeneratorTool(FPGAsOnly)

FunctionalSimulation

Constraints

MappingConstraints(FPGAsOnly)

BlockPlacement

NetlistTranslationPrograms

DesignImplementation

Mapping(FPGAsOnly)

PlacingandRouting(FPGAsOnly)

BitstreamGeneration(FPGAsOnly)

Simulation

Back-Annotation

NetGen

FunctionalSimulation

TimingSimulation

HDL-BasedSimulation

StaticTimingAnalysis(FPGAsOnly)

DesignRuleChecker(FPGAsOnly)

Probe

ChipScope™ILAandChipScopePro

FPGADesignTips

DesignSizeandPerformance

PARTGenOverview

DeviceSupport

PARTGenInputFiles

PARTGenOutputFiles

PARTGenPartlistFiles

PARTGenPartlistFileHeader

PARTGenPackageFiles

PARTGenPackageFilesUsingthe-pOption

PARTGenPackageFilesUsingthe-vOption

PARTGenSyntax

PARTGenCommandLineOptions

Syntax

-i(OutputListofDevices,Packages,andSpeeds)

Syntax

-intstyle(IntegrationStyle)

Syntax

Syntax

-p(GeneratePartlistandPackageFiles)

Syntax

-v(GeneratePartlistandPackageFiles)

Syntax

NetGenOverview

NetGenFlows

NetGenDeviceSupport

NetGenSimulationFlow

NetGenFunctionalSimulationFlow

FunctionalSimulationforUNISIM-basedNetlists

SyntaxforNetGenFunctionalSimulation

NetGenTimingSimulationFlow

FPGATimingSimulation