Xilinx 8.2i User Manual

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Development

System

Reference Guide

8.2i

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

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The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

Copyright © 1995-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

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Preface

About This Guide

The Development System Reference Guide contains information about the command line software programs in the Xilinx Development System. Most chapters are organized as follows:

A brief summary of program functions

A syntax statement

A description of the input files used and the output files generated by the program

A listing of the commands, options, or parameters used by the program

Examples of how to use the program

For an overview of the Xilinx Development System describing how these programs are used in the design flow, see Chapter 2, “Design Flow”.

Guide Contents

The Development System Reference Guide provides detailed information about converting, implementing, and verifying designs with the Xilinx command line tools. Check the program chapters for information on what program works with each family of Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). Following is a brief overview of the contents and organization of the Development System Reference Guide:

Note: For information on timing constraints, UCF files, and PCF files, see the Constraints Guide.

Chapter 1, “Introduction” —This chapter describes some basics that are common to the different Xilinx Development System modules.

Chapter 2, “Design Flow”—This chapter describes the basic design processes: design entry, synthesis, implementation, and verification.

Chapter 3, “Tcl”—Tcl is designed to complement and extend the graphical user interface (GUI). Xilinx Tcl commands provide a batch interface that makes it convenient to execute the exact same script or steps over and over again.

Chapter 4, “PARTGen”—PARTGen allows you to obtain information about installed devices and families.

Chapter 5, “Logical Design Rule Check”—The Logical Design Rule Check (DRC) comprises a series of tests run to verify the logical design described by the Native Generic Database (NGD) file.

Chapter 6, “NGDBuild”—NGDBuild performs all of the steps necessary to read a netlist file in EDIF format and create an NGD (Native Generic Database) file describing the logical design reduced to Xilinx primitives.

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Chapter 7, “MAP”—MAP packs the logic defined by an NGD file into FPGA elements such as CLBs, IOBs, and TBUFs.

Chapter 8, “Physical Design Rule Check”—The physical Design Rule Check (DRC) comprises a series of tests run to discover physical errors in your design.

Chapter 9, “PAR”—PAR places and routes FPGA designs.

Chapter 10, “XPower”—XPower is a power and thermal analysis tool that generates power and thermal estimates after the PAR or CPLDfit stage of the design.

Chapter 11, “PIN2UCF,”—PIN2UCF generates pin-locking constraints in a UCF file by reading a a placed NCD file for FPGAs or GYD file for CPLDs.

Chapter 12, “TRACE”—Timing Reporter and Circuit Evaluator (TRACE) performs static timing analysis of a physical design based on input timing constraints.

Chapter 13, “Speedprint”— Speedprint lists block delays for a specified device and its speed grades.

Chapter 14, “BitGen”—BitGen creates a configuration bitstream for an FPGA design.

Chapter 15, “BSDLAnno”—BSDLAnno automatically modifies a BSDL file for postconfiguration interconnect testing.

Chapter 16, “PROMGen” —PROMGen converts a configuration bitstream (BIT) file into a file that can be downloaded to a PROM. PROMGen also combines multiple BIT files for use in a daisy chain of FPGA devices.

Chapter 17, “IBISWriter”—IBISWriter creates a list of pins used by the design, the signals inside the device that connect those pins, and the IBIS buffer model that applies to the IOB connected to the pins.

Chapter 18, “CPLDfit” —CPLDfit reads in an NGD file and fits the design into the selected CPLD architecture.

Chapter 19, “TSIM” — TSIM formats an implemented CPLD design (VM6) into a format usable by the NetGen timing simulation flow, which produces a backannotated timing file for simulation.

Chapter 20, “TAEngine” —TAEngine performs static timing analysis on a successfully implemented Xilinx CPLD design (VM6).

Chapter 21, “Hprep6” —Hprep6 takes an implemented CPLD design (VM6) from CPLDfit and generates a JEDEC (JED) programming file.

Chapter 22, “NetGen”—NetGen reads in applicable Xilinx implementation files, extracts design data, and generates netlists that are used with supported third-party simulation, equivalence checking, and static timing analysis tools.

Chapter 23, “XFLOW”—XFLOW automates the running of Xilinx implementation and simulation flows.

Chapter 24, “Data2MEM”—Data2MEM transforms CPU execution code, or pure data, into Block RAM initialization records.

“Appendix A”—This appendix gives an alphabetic listing of the files used by the Xilinx Development System.

“Appendix B” —This appendix describes the netlist reader, EDIF2NGD, and how it interacts with NGDBuild.

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Additional Resources

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

Courier font

Messages, prompts, and

speed grade: - 100

 

program files that the system

 

 

displays

 

 

 

 

Courier bold

Literal commands that you

ngdbuild design_name

 

enter in a syntactical statement

 

 

 

 

Helvetica bold

Commands that you select

File Open

 

from a menu

 

 

 

 

 

Keyboard shortcuts

Ctrl+C

 

 

 

Italic font

Variables in a syntax

ngdbuild design_name

 

statement for which you must

 

 

supply values

 

 

 

 

 

References to other manuals

See the Development System

 

 

Reference Guide for more

 

 

information.

 

 

 

 

Emphasis in text

If a wire is drawn so that it

 

 

overlaps the pin of a symbol,

 

 

the two nets are not connected.

 

 

 

Square brackets [ ]

An optional entry or

ngdbuild [option_name]

 

parameter. However, in bus

design_name

 

specifications, such as

 

 

bus[7:0], they are required.

 

 

 

 

Braces { }

A list of items from which you

lowpwr ={on|off}

 

must choose one or more

 

 

 

 

Vertical bar |

Separates items in a list of

lowpwr ={on|off}

 

choices

 

 

 

 

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Convention

Meaning or Use

Example

 

 

 

Vertical ellipsis

Repetitive material that has

IOB #1: Name = QOUT’

.

been omitted

IOB #2: Name = CLKIN’

.

 

.

.

 

.

 

 

.

 

 

 

Horizontal ellipsis . . .

Repetitive material that has

allow block block_name

 

been omitted

loc1 loc2 ... locn;

 

 

 

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

 

 

Blue text

Cross-reference link to a

See the section “Additional

 

location in the current file or

Resources” for details.

 

in another file in the current

Refer to “Title Formats” in

 

document

 

Chapter 1 for details.

 

 

 

 

 

Red text

Cross-reference link to a

See Figure 2-5 in the Virtex-II

 

location in another document

Handbook.

 

 

 

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com

 

 

for the latest speed files.

 

 

 

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Development System Reference Guide

Table of Contents

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: Introduction

Command Line Program Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

–h (Help) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Invoking Command Line Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 2: Design Flow

Design Flow Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Design Entry and Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Hierarchical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Schematic Entry Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Library Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

CORE Generator Tool (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

HDL Entry and Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Mapping Constraints (FPGAs Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Block Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Netlist Translation Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Design Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Mapping (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Placing and Routing (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Bitstream Generation (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Design Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Back-Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

NetGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Schematic-Based Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

HDL-Based Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Static Timing Analysis (FPGAs Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

In-Circuit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Design Rule Checker (FPGAs Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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Xilinx Design Download Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Probe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

ChipScope ILA and ChipScope PRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

FPGA Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Design Size and Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Global Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Data Feedback and Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Other Synchronous Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 3: Tcl

Tcl Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Xilinx Tcl Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Accessing Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Tcl Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Xilinx Namespace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Xilinx Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Tcl Commands for General Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 partition (support design preservation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 delete (delete a partition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 get (get partition properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 new (create a new partition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 properties (list available partition properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 rerun (force partition synthesis and implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . 61 set (set partition preserve property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

process (run and manage project processes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 run (run process task) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 project (create and manage projects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 clean (remove system-generated project files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 close (close the ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 get (get project properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 get_processes (get project processes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 new (create a new ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 open (open an ISE project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 properties (list project properties). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 set (set project properties, values, and options) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 set device (set device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 set family (set device family) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 set package (set device package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 set speed (set device speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 set top (set the top-level module/entity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

timing_analysis (generate timing analysis reports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 delete (delete timing analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 disable_constraints (disable timing constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 disable_cpt (disable components for path tracing control) . . . . . . . . . . . . . . . . . . . . . . . 71 enable_constraints (enable constraints for analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 enable_cpt (enable components for path tracing control) . . . . . . . . . . . . . . . . . . . . . . . . 72 get (get analysis property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 new (new timing analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 reset (reset path filters and constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 run (run analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 saveas (save analysis report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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set (set analysis properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 set_constraint (set constraint for custom analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 set_endpoints (set source and destination endpoints) . . . . . . . . . . . . . . . . . . . . . . . . . . 78 set_filter (set filter for analysis). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 set_query (set up net or timegroup report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 show_settings (generate settings report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

xfile (manage project files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 add (add file to project). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 get (get project file properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 remove (remove file from project) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Tcl Commands for Advanced Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 collection (create and manage a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 append_to (add objects to a collection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 copy (copy a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 equal (compare two collections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 foreach (iterate over elements in a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 get (get collection property) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 index (extract a collection object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 properties (list available collection properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 remove_from (remove objects from a collection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 set (set the property for all collections) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 sizeof (show the number of objects in a collection). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

object (get object information) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 get (get object properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 name (name of the object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 properties (list object properties) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 type (type of object) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

search (search and return matching objects) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Project Properties and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Example Tcl Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Sample Tcl Script for General Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Sample Tcl Script for Advanced Scripting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Chapter 4: PARTGen

PARTGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PARTGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PARTGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PARTGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PARTGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

–arch (Print Information for Specified Architecture) . . . . . . . . . . . . . . . . . . . . . . . . . . 102

–i (Print a List of Devices, Packages, and Speeds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–p (Creates Package file and Partlist Files). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–nopkgfile (No Package File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

–v (Creates Package and Partlist Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Partlist File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Device Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

PKG File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

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Chapter 5: Logical Design Rule Check

Logical DRC Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Logical DRC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Block Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Net Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Pad Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Clock Buffer Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Name Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Primitive Pin Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 6: NGDBuild

NGDBuild Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Converting a Netlist to an NGD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 NGDBuild Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 NGDBuild Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 NGDBuild Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 NGDBuild Intermediate Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 NGDBuild Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 –a (Add PADs to Top-Level Port Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 –aul (Allow Unmatched LOCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 –bm (Specify BMM Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 –dd (Destination Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 –f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 –i (Ignore UCF File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 –insert_keep_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 –intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 –l (Libraries to Search) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 –modular assemble (Module Assembly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 –modular initial (Initial Budgeting of Modular Design) . . . . . . . . . . . . . . . . . . . . . . . 124 –modular module (Active Module Implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . 125 –nt (Netlist Translation Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 –p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 –r (Ignore LOC Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 –sd (Search Specified Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 –u (Allow Unexpanded Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 –uc (User Constraints File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 –ur (Read User Rules File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 –verbose (Report All Messages) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Chapter 7: MAP

MAP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

MAP Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

MAP Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

MAP Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

MAP Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

–bp (Map Slice Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

–c (Pack CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

–cm (Cover Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

–detail (Write Out Detailed MAP Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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–equivalent_register_removal (Remove Redundant Registers) . . . . . . . . . . . . . . . . . 134 –f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 –gf (Guide NCD File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 –global_opt (Global Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 –gm (Guide Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 –gm incremental (Guide Mode incremental) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 –ignore_keep_hierarchy (Ignore KEEP_HIERARCHY Properties) . . . . . . . . . . . . . . 136 –intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 –ir (Do Not Use RLOCs to Generate RPMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 –ise (ISE Project File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 –k (Map to Input Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 –l (No logic replication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 –o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 –ol (Overall Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 –p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 –pr (Pack Registers in I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 –r (No Register Ordering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 –register_duplication (Duplicate Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 –retiming (Register Retiming During Global Optimization). . . . . . . . . . . . . . . . . . . . 139 –t (Start Placer Cost Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 –timing (Timing-Driven Packing and Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 –tx (Transform Buses) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 –u (Do Not Remove Unused Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 –xe (Extra Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

MAP Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Register Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Guided Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Simulating Map Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MAP Report (MRP) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Halting MAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Chapter 8: Physical Design Rule Check

DRC Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

DRC Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Input File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

DRC Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–e (Error Report). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–o (Output file) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–s (Summary Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–v (Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

–z (Report Incomplete Programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DRC Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

DRC Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Chapter 9: PAR

Place and Route Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

PAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Placing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

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Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Timing-driven PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Command Line Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Guided PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

PCI Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

PAR Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

PAR Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Detailed Listing of Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–gf (Guide NCD File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

–gm (Guide Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–k (Re-Entrant Routing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

–m (Multi-Tasking Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–n (Number of PAR Iterations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–nopad (No Pad). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–ol (Overall Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

–p (No Placement) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–pl (Placer Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–power (Power Aware PAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–r (No Routing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–rl (Router Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

–s (Number of Results to Save) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–t (Starting Placer Cost Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–ub (Use Bonded I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

–x (Performance Evaluation Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

–xe (Extra Effort Level) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

PAR Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Place and Route Report File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Multi Pass Place and Route (MPPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

Select I/O Utilization and Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Importing the PAD File Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Guide Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

Xplorer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Best Performance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Timing Closure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Xplorer Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Xplorer Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Xplorer Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

ReportGen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

ReportGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

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Turns Engine (PAR Multi-Tasking Option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Turns Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Turns Engine Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Turns Engine Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

Turns Engine Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

Turns Engine Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Screen Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Halting PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 10: XPower

XPower Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Files Used by XPower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 XPower Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 FPGA Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 CPLD Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

Using XPower. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 VCD Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Other Methods of Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 -l (Limit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 -ls (List Supported Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 -o (Rename Power Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 -s (Specify VCD file). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 -tb (Turn On Time Based Reporting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 -v (Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 -wx (Write XML File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 -x (Specify Settings (XML) Input File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Command Line Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Power Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Standard Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Detailed Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Advanced Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Chapter 11: PIN2UCF

PIN2UCF Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

PIN2UCF Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

PIN2UCF Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

–o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

–r (Write to a Report File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

PIN2UCF Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

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Chapter 12: TRACE

TRACE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 TRACE Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 TRACE Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Input files to TRACE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

TRACE Output Files

TRACE Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 –a (Advanced Analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 –e (Generate an Error Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 –f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 –fastpaths (Report Fastest Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 –intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 –ise (ISE Project File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 –l (Limit Timing Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 –nodatasheet (No Data Sheet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 –o (Output Timing Report File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 –run (Run Timing Analyzer Macro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 –s (Change Speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 –skew (Analyze Clock Skew for All Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 –stamp (Generates STAMP timing model files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 –u (Report Uncovered Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 –v (Generate a Verbose Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 –xml (XML Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

TRACE Command Line Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 TRACE Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Timing Verification with TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Net Delay Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Net Skew Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Path Delay Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Clock Skew and Setup Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Reporting with TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Data Sheet Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Report Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Guaranteed Setup and Hold Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Setup Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Summary Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Summary Report (Without a Physical Constraints File Specified) . . . . . . . . . . . . . . . . 231 Error Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Verbose Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 OFFSET Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 OFFSET IN Constraint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 OFFSET IN Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 OFFSET IN Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 OFFSET IN Detailed Path Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 OFFSET IN Detail Path Clock Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 OFFSET In with Phase Shifted Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 OFFSET OUT Constraint Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 OFFSET OUT Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 OFFSET OUT Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 OFFSET OUT Detail Clock Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

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OFFSET OUT Detail Path Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 PERIOD Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 PERIOD Constraints Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 PERIOD Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 PERIOD Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 PERIOD Path Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 PERIOD Constraint with PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

Halting TRACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Chapter 13: Speedprint

Speedprint Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Speedprint Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Speedprint Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–min (Display Minimum Speed Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–s (Speed Grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–t (Specify Temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

–v (Specify Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Speedprint Example Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Speedprint Example Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Chapter 14: BitGen

BitGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

BitGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

BitGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

BitGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

BitGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

–b (Create Rawbits File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

–bd (Update Block Rams) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–d (Do Not Run DRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–g (Set Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

–g (Set Configuration—Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3/-3E) . . . . 261

ActivateGCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

ActiveReconfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

CclkPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

Compress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

ConfigRate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

CRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

DCIUpdateMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DCMShutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DebugBitstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

DisableBandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DONE_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DonePin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DonePipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

DriveDone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Encrypt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

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Gclkdel0, Gclkdel1, Gclkdel2, Gclkdel3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 GSR_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 GWE_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 GTS_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 HswapenPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Key0, Key1, Key2, Key3, Key4, Key5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 KeyFile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Keyseq0, Keyseq1, Keyseq2, Keyseq3, Keyseq4, Keyseq5. . . . . . . . . . . . . . . . . . . . . . . 268

LCK_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 M0Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 M1Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 M2Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Match_cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 PartialGCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

PartialMask0, PartialMask1, PartialMask2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

PartialLeft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 PartialRight. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Persist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 PowerdownPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 ProgPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 ReadBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 SEURepair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 StartCBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 StartKey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 StartupClk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 TckPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TdiPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TdoPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TmsPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 UnusedPin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 UserID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 –j (No BIT File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 –l (Create a Logic Allocation File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 –m (Generate a Mask File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 –r (Create a Partial Bit File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 –w (Overwrite Existing Output File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Chapter 15: BSDLAnno

BSDLAnno Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

BSDLAnno Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

BSDLAnno Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

–s (Specify BSDL file). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

BSDLAnno File Composition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Entity Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Generic Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

Logical Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Package Pin-Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

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USE Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Scan Port Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 TAP Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Boundary Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Modifications to the DESIGN_WARNING Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Header Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Boundary Scan Behavior in Xilinx Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

Chapter 16: PROMGen

PROMGen Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 PROMGen Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 PROMGen Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 PROMGen Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 PROMGen Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

–b (Disable Bit Swapping—HEX Format Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –c (Checksum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –d (Load Downward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –i (Select Initial Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –l (Disable Length Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 –n (Add BIT FIles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 –o (Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 –p (PROM Format). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 –r (Load PROM File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 –s (PROM Size) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –t (Template File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –u (Load Upward) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –ver (Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –w (Overwrite Existing Output File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –x (Specify Xilinx PROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 –z (Enable Compression) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Bit Swapping in PROM Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 PROMGen Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

Chapter 17: IBISWriter

IBISWriter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

IBISWriter Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

IBISWriter Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

IBISWriter Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

IBISWriter Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

–allmodels (Include all available buffer models for this architecture) . . . . . . . . . . . . 295

–g (Set Reference Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

–intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

–ml (Multilingual Support). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

–pin (Generate Package Parasitics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

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Chapter 18: CPLDfit

CPLDfit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 CPLDfit Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 CPLDfit Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 CPLDfit Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 CPLDfit Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

–blkfanin (Specify Maximum Fanin for Function Blocks) . . . . . . . . . . . . . . . . . . . . . . 301 –exhaust (Enable Exhaustive Fitting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 –ignoredatagate (Ignore DATA_GATE Attributes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 –ignoretspec (Ignore Timing Specifications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 –init (Set Power Up Value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 –inputs (Number of Inputs to Use During Optimization) . . . . . . . . . . . . . . . . . . . . . . 302 –iostd (Specify I/O Standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 –keepio (Prevent Optimization of Unused Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 –loc (Keep Specified Location Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 –localfbk (Use Local Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 –log (Specify Log File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 –nofbnand (Disable Use of Foldback NANDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –nogclkopt (Disable Global Clock Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –nogsropt (Disable Global Set/Reset Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –nogtsopt (Disable Global Output-Enable Optimization) . . . . . . . . . . . . . . . . . . . . . . 303 –noisp (Turn Off Reserving ISP Pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –nom1opt (Disable Multi-level Logic Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –nouim (Disable FASTConnect/UIM Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –ofmt (Specify Output Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 –optimize (Optimize Logic for Density or Speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 –p (Specify Xilinx Part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 –pinfbk (Use Pin Feedback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 –power (Set Power Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 –pterms (Number of Pterms to Use During Optimization) . . . . . . . . . . . . . . . . . . . . . 304 –slew (Set Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 –terminate (Set to Termination Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 –unused (Set Termination Mode of Unused I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 –wysiwyg (Do Not Perform Optimization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Chapter 19: TSIM

TSIM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

TSIM Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

TSIM Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

TSIM Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Chapter 20: TAEngine

TAEngine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

TAEngine Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

TAEngine Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

TAEngine Output Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

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TAEngine Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 –detail (Detail Report) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 –iopath (Trace Paths) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 –l (Specify Output Filename) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

Chapter 21: Hprep6

Hprep6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Hprep6 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Hprep6 Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Hprep6 Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Hprep6 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

–autosig (Automatically Generate Signature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 –intstyle (Integration Style) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 –n (Specify Signature Value for Readback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 –nopullup (Disable Pullups) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 –s (Produce ISC File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 –tmv (Specify Test Vector File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

Chapter 22: NetGen

NetGen Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 NetGen Supported Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 NetGen Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 NetGen Functional Simulation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Notes on Functional Simulation for UNISIM-based Netlists . . . . . . . . . . . . . . . . . . . . 320 Syntax for NetGen Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Output files for NetGen Functional Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 NetGen Timing Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Syntax for NetGen Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 FPGA Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Output files for FPGA Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Input files for CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Output files for CPLD Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Options for NetGen Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 –dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 –fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 –gp (Bring Out Global Reset Net as Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

–insert_pp_buffers (Insert Path Pulse Buffers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 –mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 –module (Simulation of Active Module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 –ofmt (Output Format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 –pcf (PCF File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 –s (Change Speed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 –sim (Generate Simulation Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 –tb (Generate Testbench Template File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 –ti (Top Instance Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 –tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

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–tp (Bring Out Global 3-State Net as Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 –w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Verilog-Specific Options for Functional and Timing Simulation . . . . . . . . . . . . . . . . 326 –insert_glbl (Insert glbl.v Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–ism (Include SimPrim Modules in Verilog File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

–ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 –pf (Generate PIN File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 –sdf_anno (Include $sdf_annotate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 –sdf_path (Full Path to SDF File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–shm (Write $shm Statements in Test Fixture File). . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

–ul (Write uselib Directive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–vcd (Write $dump Statements In Test Fixture File). . . . . . . . . . . . . . . . . . . . . . . . . . . 328 VHDL-Specific Options for Functional and Timing Simulation. . . . . . . . . . . . . . . . . 328 –a (Architecture Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 –ar (Rename Architecture Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 –rpw (Specify the Pulse Width for ROC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 –tpw (Specify the Pulse Width for TOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

–xon (Select Output Behavior for Timing Violations) . . . . . . . . . . . . . . . . . . . . . . . . . . 329

NetGen Equivalence Checking Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Syntax for NetGen Equivalence Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Input files for NetGen Equivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Output files for NetGen Equivalence Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Options for NetGen Equivalence Checking Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 –dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 –ecn (Equivalence Checking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 –fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 –intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 –mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 –module (Verification of Active Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 –ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 –ngm (Design Correlation File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 –tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 –w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

NetGen Static Timing Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 Input files for Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Output files for Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Syntax for NetGen Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Options for NetGen Static Timing Analysis Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–aka (Write Also-Known-As Names as Comments) . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

–bd (Block RAM Data File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 –dir (Directory Name). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 –fn (Control Flattening a Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 –intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 –mhf (Multiple Hierarchical Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 –module (Simulation of Active Module). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 –ne (No Name Escaping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 –pcf (PCF File). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 –s (Change Speed). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

–sta (Generate Static Timing Analysis Netlist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

–tm (Top Module Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 –w (Overwrite Existing Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

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Preserving and Writing Hierarchy Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

Testbench File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Hierarchy Information File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Dedicated Global Signals in Back-Annotation Simulation . . . . . . . . . . . . . . . . . . 338

Global Signals in Verilog Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Global Signals in VHDL Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

Chapter 23: XFLOW

XFLOW Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 XFLOW Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 XFLOW Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 XFLOW Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 XFLOW Flow Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

–assemble (Module Assembly) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 –config (Create a BIT File for FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 –ecn (Create a File for Equivalence Checking) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 –fit (Fit a CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 –fsim (Create a File for Functional Simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 –implement (Implement an FPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 –initial (Initial Budgeting of Modular Design) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 –module (Active Module Implementation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 –mppr (Multi-Pass Place and Route for FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 –sta (Create a File for Static Timing Analysis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 –synth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

Synthesis Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Option Files for -synth Flow Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 –tsim (Create a File for Timing Simulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Flow Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Flow File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 User Command Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

XFLOW Option Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 Option File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

XFLOW Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –active (Active Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –ed (Copy Files to Export Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –g (Specify a Global Variable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –log (Specify Log File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 –norun (Creates a Script File Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 –o (Change Output File Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 –p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 –pd (PIMs Directory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 –rd (Copy Report Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 –wd (Specify a Working Directory). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

Running XFLOW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Using XFLOW Flow Types in Combination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Running “Smart Flow” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Using the SCR, BAT, or TCL File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Using the XIL_XFLOW_PATH Environment Variable . . . . . . . . . . . . . . . . . . . . . . . . 365

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Chapter 24: Data2MEM

Data2MEM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Data2MEM Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Data2MEM Input and Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Block RAM Memory Map (.bmm) files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Executable and Linkable Format (.elf) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Debugging Information Format DWARF (.drf) files . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Memory (.mem) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Memory (.mem) Files as Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 Bit (.bit) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

Verilog (.v) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 VHDL (.vhd) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 UCF (.ucf) files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Data2MEM Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

A: Xilinx Development System Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373

B: EDIF2NGD, and NGDBuild

EDIF2NGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

EDIF2NGD Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Input Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

EDIF2NGD Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–a (Add PADs to Top-Level Port Signals). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–aul (Allow Unmatched LOCs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–f (Execute Commands File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–intstyle (Integration Style). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

–l (Libraries to Search) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

–p (Part Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

–r (Ignore LOC Constraints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

NGDBuild . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Converting a Netlist to an NGD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

Bus Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Netlist Launcher (Netlister) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

Netlist Launcher Rules Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules and System Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

User Rules Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

Value Types in Key Statements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

System Rules File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Rules File Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Example 1: EDF_RULE System Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

Example 2: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Example 3: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

Example 4: User Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

NGDBuild File Names and Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

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Chapter 1

Introduction

This chapter describes the command line programs for the Xilinx development system. The chapter contains the following sections:

“Command Line Program Overview”

“Command Line Syntax”

“Command Line Options”

“Invoking Command Line Programs”

Command Line Program Overview

Xilinx command line programs allow you to implement and verify your design. The following table lists the programs you can use for each step in the design flow. For detailed information, see Chapter 2, “Design Flow”.

Table 1-1: Command Line Programs in the Design Flow

Design Flow Step

Command Line Program

 

 

Design Implementation

NGDBuild, MAP, PAR, Xplorer,

 

BitGen

 

 

Design Preservation

TCL

 

 

Timing Simulation and Back

NetGen

Annotation

 

(Design Verification)

 

 

 

Static Timing Analysis

TRACE

(Design Verification)

 

 

 

You can run these programs in the standard design flow or use special options to run the programs for design preservation. Each command line program has multiple options, which allow you to control how a program executes. For example, you can set options to change output file names, to set a part number for your design, or to specify files to read in when executing the program. You can also use options to create guide files and run guide mode to maintain the performance of a previously implemented design.

Some of the command line programs described in this manual underlie many of the Xilinx Graphical User Interfaces (GUIs). The GUIs can be used in conjunction with the command line programs or alone. For information on the GUIs, see the online Help provided with each Xilinx tool.

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Command Line Syntax

Command line syntax always begins with the command line program name. The program name is followed by any options and then file names. Use the following rules when specifying command line options:

Enter options in any order.

Precede options with a hyphen (-) and separate them with spaces.

Be consistent with upper case and lower case.

When an option requires a parameter, separate the parameter from the option by spaces or tabs. For example, the following shows the command line syntax for running PAR with the effort level set to medium:

Correct: par -ol med

Incorrect: par -ol med

When using options that can be specified multiple times, precede the parameter with the option letter. In this example, the -l option shows the list of libraries to search:

Correct: -l xilinxun -l synopsys

Incorrect: -l xilinxun synopsys

Enter parameters that are bound to an option after the option.

Correct: -f command_file

Incorrect: command_file -f

Use the following rules when specifying file names:

Enter file names in the order specified in the chapter that describes the command line program. In this example the correct order is program, input file, output file, and then physical constraints file.

Correct: par input.ncd output.ncd freq.pcf

Incorrect: par input.ncd freq.pcf output.ncd

Use lower case for all file extensions (for example, .ncd).

Command Line Options

The following options are common to many of the command line programs in the Xilinx Development System.

–f (Execute Commands File)

For any Xilinx Development System program, you can store command line program options and file names in a command file. You can then execute the arguments by entering the program name with the –f option followed by the name of the command file. This is useful if you frequently execute the same arguments each time you execute a program or if the command line command becomes too long.

You can use the file in the following ways:

To supply all the command options and file names for the program, as in the following example:

par -f command_file

command_file is the name of the file that contains the command options and file names.

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Command Line Options

To insert certain command options and file names within the command line, as in the following example:

par -f placeoptions -s 4 -f routeoptions design_i.ncd design_o.ncd placeoptions is the name of a file containing placement command parameters. routeoptions is the name of a file containing routing command parameters.

You create the command file in ASCII format. Use the following rules when creating the command file:

Separate program options and file names with spaces.

Precede comments with the pound sign (#).

Put new lines or tabs anywhere white space is allowed on the UNIX or DOS command line.

Put all arguments on the same line, one argument per line, or a combination of these.

All carriage returns and other non-printable characters are treated as spaces and ignored.

No line length limitation exists within the file.

Following is an example of a command file:

#command line options for par for design mine.ncd -n 10

-w 0l 5

-s 2 #will save the two best results /home/yourname/designs/xilinx/mine.ncd #directory for output designs /home/yourname/designs/xilinx/output.dir #use timing constraints file /home/yourname/designs/xilinx/mine.pcf

–h (Help)

When you enter a program name followed by –help or –h, a message displays that lists all the available options and their parameters as well as the file types for use with the program. The message also explains each of the options.

Following are descriptions for the symbols used in the help message:

Symbol

Description

[ ]

Encloses items that are optional.

{ }

Encloses items that may be repeated.

< >

Encloses a variable name or number for which you

 

must substitute information.

,Shows a range for an integer variable.

Shows the start of an option name.

:Binds a variable name to a range.

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Symbol

Description

|

Logical OR to show a choice of one out of many items.

 

The OR operator may only separate logical groups or

 

literal keywords.

( )

Encloses a logical grouping for a choice between

 

subformats.

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Following are examples of syntax used for file names:

<infile[.ncd]> shows that typing the .ncd extension is optional but that the extension must be .ncd.

<infile<.edn>> shows that the .edn extension is optional and is appended only if there is no other extension in the file name.

For architecture-specific programs, such as BitGen, you can enter the following to get a verbose help message for the specified architecture:

program_name –h architecture_name

You can redirect the help message to a file to read later or to print out by entering the following:

program_name –h > filename

On the UNIX command line, enter the following to redirect the help message to a file and return to the command prompt.

program_name –h > & filename

–intstyle (Integration Style)

You can limit screen output, based on the integration style that you are running, to warning and error messages only. When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent. The mode sets the way information is displayed in the following ways:

–intstyle {ise | xflow | silent}

–intstyle ise

This mode indicates the program is being run as part of an integrated design environment.

–intstyle xflow

This mode indicates the program is being run as part of an integrated batch flow.

–intstyle silent

This mode limits screen output to warning and error messages only.

Note: The -intstyle option is automatically invoked when running in an integrated environment, such as Project Navigator or XFLOW.

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Command Line Options

–p (Part Number)

You can use the –p option with the EDIF2NGD, NGDBuild, MAP, and XFLOW programs to specify the part into which your design will be implemented. You can specify a part number at the following different points in the design flow:

In the input netlist (does not require the –p option)

In a Netlist Constraints File (NCF) (does not require the –p option)

With the –p option when you run a netlist reader (EDIF2NGD) User Constraints File (UCF) (does not require the –p option)

With the –p option when you run NGDBuild

By the time you run NGDBuild, you must have already specified a device architecture.

With the –p option when you run MAP

When you run MAP, an architecture, device, and package must be specified, either on the MAP command line or earlier in the design flow. If you do not specify a speed, MAP selects a default speed. You can only run MAP using a part number from the architecture you specified when you ran NGDBuild.

Note: Part numbers specified in a later step of the design flow override a part number specified in an earlier step. For example, a part specified when you run MAP overrides a part specified in the input netlist.

A complete Xilinx part number consists of the following elements:

Architecture (for example, Spartan-3e)

Device (for example, xc3s100e)

Package (for example, vq100)

Speed (for example, -4)

Note: The Speedprint program lists block delays for device speed grades. The -s option allows you to specify a speed grade. If you do not specify a speed grade, Speedprint reports the default speed grade for the device you are targeting. See “–s (Speed Grade)” in Chapter 13 for details.

The following table lists multiple ways to specify a part on the command line.

Table 1-2: Part Number Examples

Specification

Examples

 

 

Architecture only

virtex

 

virtex2

 

virtex2p

 

virtex4

 

spartan2

 

spartan2e

 

spartan 3

 

spartan 3e

 

xc9500

 

xpla3

 

 

Device only

xc4vfx12

 

xc3s100e

 

 

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Chapter 1: Introduction

Table 1-2: Part Number Examples

Specification

Examples

 

 

DevicePackage

xc4fx12sf363

 

xc3s100evq100

 

 

Device–Package

xc4vfx12-sf363

 

xc3s100e-vq100

 

 

DeviceSpeed–Package

xc4vfx1210-sf363

 

xc3s100e4-vq100

 

 

DevicePackage–Speed

xc4fx12sf363-10

 

xc3s100evq100-4

 

 

Device–Speed–Package

xc4vfx12-10-sf363

 

xc3s100e-4-vq100

 

 

Device–SpeedPackage

xc4vfx12-10sf363

 

xc3s100e-4vq100

 

 

Invoking Command Line Programs

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You start Xilinx Development System command line programs by entering a command at the UNIXor DOScommand line. See the program-specific chapters in this book for the appropriate syntax

Xilinx also offers the XFLOW program, which allows you to automate the running of several programs at one time. See Chapter 23, “XFLOW” for more information.

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Chapter 2

Design Flow

This chapter describes the process for creating, implementing, verifying, and downloading designs for FPGA and CPLD devices. For a complete description of FPGAs and CPLDs, refer to the Xilinx Data Sheets at http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

This chapter contains the following sections:

“Design Flow Overview”

“Design Entry and Synthesis”

“Design Implementation”

“Design Verification”

“FPGA Design Tips”

Design Flow Overview

The standard design flow comprises the following steps:

1.Design Entry and Synthesis—In this step of the design flow, you create your design using a Xilinx-supported schematic editor, a hardware description language (HDL) for text-based entry, or both. If you use an HDL for text-based entry, you must synthesize the HDL file into an EDIF file or, if you are using the Xilinx Synthesis Technology (XST) GUI, you must synthesize the HDL file into an NGC file.

2.Design Implementation—By implementing to a specific Xilinx architecture, you convert the logical design file format, such as EDIF, that you created in the design entry and synthesis stage into a physical file format. The physical information is contained in the native circuit description (NCD) file for FPGAs and the VM6 file for CPLDs. Then you create a bitstream file from these files and optionally program a PROM or EPROM for subsequent programming of your Xilinx device.

3.Design Verification—Using a gate-level simulator or cable, you ensure that your design meets your timing requirements and functions properly. See the iMPACT online help for information about Xilinx download cables and demonstration boards.

The full design flow is an iterative process of entering, implementing, and verifying your design until it is correct and complete. The Xilinx Development System allows quick design iterations through the design flow cycle. Because Xilinx devices permit unlimited reprogramming, you do not need to discard devices when debugging your design in circuit.

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The following figure shows the standard Xilinx design flow.

Design

 

Design Verification

Entry

 

 

 

 

Functional

 

 

Simulation

Design

 

 

Synthesis

 

 

Design

 

 

Implementation

 

Static Timing

 

 

 

 

Analysis

Optimization

 

 

FPGAs

 

 

Mapping

 

 

Placement

 

 

Routing

 

 

CPLDs

Back

Timing

Annotation

Simulation

Fitting

 

 

Bitstream

 

 

Generation

 

 

Download to a

 

In-Circuit

Xilinx Device

 

Verification

 

 

X9537

Figure 2-1:

Xilinx Design Flow

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Design Flow Overview

The following figure shows the Xilinx software flow chart for FPGA designs.

 

CORE Generator

Schematic

Synthesis

HDL

 

Simulation

Testbench

 

 

Libraries

Libraries

 

 

Libraries

Stimulus

 

Symbol

 

 

 

 

 

 

 

NGC

Schematic Capture

Synthesis

 

 

Simulation

 

 

 

EDIF 2 0 0 &

NGC

 

V &

VHD &

EDIF

 

 

Constraints/NCF

(XST Netlist)

 

SDF 2.1

SDF 2.1

2 0 0

UCF

NGDBuild

NGDBuild

NGDBuild

 

 

NetGen

 

 

 

 

 

 

 

 

 

 

NGD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Constraints Editor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Floorplanner

 

 

 

 

 

 

 

MAP

 

 

NGM & PCF

 

 

 

NetGen

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NCD & PCF

TRACE &

PAR

Timing Analyzer

 

 

NCD

 

BitGen

 

BIT

PROMGen

iMPACT

X10293

Figure 2-2: Xilinx Software Design Flow (FPGAs)

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The following figure shows the Xilinx software flow chart for CPLD designs.

CORE Generator

Schematic

 

Synthesis

HDL

Simulation

Testbench

Libraries

 

Libraries

 

Libraries

Stimulus

 

 

 

Symbol

 

 

 

 

 

 

NGC

Schematic Capture

 

Synthesis

 

Simulation

 

 

EDIF 2 0 0 &

 

NGC

V &

VHD &

EDIF

 

Constraints/NCF

 

(XST Netlist)

SDF 2.1

SDF 2.1

2 0 0

NGDBuild

 

NGDBuild

NGDBuild

 

NetGen

 

 

 

NGD

 

 

 

 

 

GYD

CPLD Fitter

 

 

 

 

 

JED

VM6

 

 

 

 

 

iMPACT

Timing Analyzer

 

 

 

 

X10294

Figure 2-3: Xilinx Software Design Flow (CPLDs)

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Design Entry and Synthesis

You can enter a design with a schematic editor or a text-based tool. Design entry begins with a design concept, expressed as a drawing or functional description. From the original design, a netlist is created, then synthesized and translated into a native generic object (NGO) file. This file is fed into the Xilinx software program called NGDBuild, which produces a logical native generic database (NGD) file.

The following figure shows the design entry and synthesis process.

 

CORE Generator

 

Schematic

Synthesis

 

Libraries

Libraries

HDL

Schematic Capture

Synthesis

 

UCF

EDIF 2 0 0 &

NGC

Constraints/NCF

(XST Netlist)

 

NGDBuild

X10295

Figure 2-4: Design Entry Flow

Hierarchical Design

Design hierarchy is important in both schematic and HDL entry for the following reasons:

Helps you conceptualize your design

Adds structure to your design

Promotes easier design debugging

Makes it easier to combine different design entry methods (schematic, HDL, or state editor) for different parts of your design

Makes it easier to design incrementally, which consists of designing, implementing, and verifying individual parts of a design in stages

Reduces optimization time

Facilitates concurrent design, which is the process of dividing a design among a number of people who develop different parts of the design in parallel.

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In hierarchical designing, a specific hierarchical name identifies each library element, unique block, and instance you create. The following example shows a hierarchical name with a 2-input OR gate in the first instance of a multiplexer in a 4-bit counter:

/Acc/alu_1/mult_4/8count_3/4bit_0/mux_1/or2

Xilinx strongly recommends that you name the components and nets in your design. These names are preserved and used by the FPGA Editor tool. These names are also used for back-annotation and appear in the debug and analysis tools. If you do not name your components and nets, the schematic editor automatically generates the names. For example, if left unnamed, the software might name the previous example, as follows:

/$1a123/$1b942/$1c23/$1d235/$1e121/$1g123/$1h57

Note: It is difficult to analyze circuits with automatically generated names, because the names only have meaning for Xilinx software.

Schematic Entry Overview

Schematic tools provide a graphic interface for design entry. You can use these tools to connect symbols representing the logic components in your design. You can build your design with individual gates, or you can combine gates to create functional blocks. This section focuses on ways to enter functional blocks using library elements and the CORE Generator.

Library Elements

Primitives and macros are the “building blocks” of component libraries. Xilinx libraries provide primitives, as well as common high-level macro functions. Primitives are basic circuit elements, such as AND and OR gates. Each primitive has a unique library name, symbol, and description. Macros contain multiple library elements, which can include primitives and other macros.

You can use the following types of macros with Xilinx FPGAs:

Soft macros have pre-defined functionality but have flexible mapping, placement, and routing. Soft macros are available for all FPGAs.

Relationally placed macros (RPMs) have fixed mapping and relative placement. RPMs are available for all device families, except the XC9500 family.

Macros are not available for synthesis because synthesis tools have their own module generators and do not require RPMs. If you wish to override the module generation, you can instantiate CORE Generator modules. For most leading-edge synthesis tools, this does not offer an advantage unless it is for a module that cannot be inferred.

CORE Generator Tool (FPGAs Only)

The Xilinx CORE Generator design tool delivers parameterizable cores that are optimized for Xilinx FPGAs. The library includes cores ranging from simple delay elements to complex DSP (Digital Signal Processing) filters and multiplexers. For details, refer to the CORE Generator Guide. You can also refer to the Xilinx IP (Intellectual Property) Center Web site at http://www.xilinx.com/ipcenter, which offers the latest IP solutions. These solutions include design reuse tools, free reference designs, DSP and PCI solutions, IP implementation tools, cores, specialized system level services, and vertical application IP solutions.

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Design Entry and Synthesis

HDL Entry and Synthesis

A typical Hardware Description Language (HDL) supports a mixed-level description in which gate and netlist constructs are used with functional descriptions. This mixed-level capability enables you to describe system architectures at a high level of abstraction, then incrementally refine the detailed gate-level implementation of a design.

HDL descriptions offer the following advantages:

You can verify design functionality early in the design process. A design written as an HDL description can be simulated immediately. Design simulation at this high level, at the gate-level before implementation, allows you to evaluate architectural and design decisions.

An HDL description is more easily read and understood than a netlist or schematic description. HDL descriptions provide technology-independent documentation of a design and its functionality. Because the initial HDL design description is technology independent, you can use it again to generate the design in a different technology, without having to translate it from the original technology.

Large designs are easier to handle with HDL tools than schematic tools.

After you create your HDL design, you must synthesize it. During synthesis, behavioral information in the HDL file is translated into a structural netlist, and the design is optimized for a Xilinx device. Xilinx supports HDL synthesis tools for several third-party synthesis vendors. In addition, Xilinx offers its own synthesis tool, Xilinx Synthesis Technology (XST). See the Xilinx Synthesis Technology (XST) User Guide for information. For detailed information on synthesis, see the Synthesis and Simulation Design Guide.

Functional Simulation

After you create your design, you can simulate it. Functional simulation tests the logic in your design to determine if it works properly. You can save time during subsequent design steps if you perform functional simulation early in the design flow. See “Simulation” for more information.

Constraints

You may want to constrain your design within certain timing or placement parameters. You can specify mapping, block placement, and timing specifications.

You can enter constraints manually or use the Constraints Editor, Floorplanner, or FPGA Editor, which are graphical user interface (GUI) tools provided by Xilinx. You can use the Timing Analyzer GUI or TRACE command line program to evaluate the circuit against these constraints by generating a static timing analysis of your design. See Chapter 12, “TRACE” and the online Help provided with each GUI for information. See the Constraints Guide for detailed information on constraints.

Mapping Constraints (FPGAs Only)

You can specify how a block of logic is mapped into CLBs using an FMAP for all Spartan FPGA and Virtex FPGA families. These mapping symbols can be used in your schematic. However, if you overuse these specifications, it may be difficult to route your design.

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Block Placement

Block placement can be constrained to a specific location, to one of multiple locations, or to a location range. Locations can be specified in the schematic, with synthesis tools, or in the User Constraints File (UCF). Poor block placement can adversely affect both the placement and the routing of a design. Only I/O blocks require placement to meet external pin requirements.

Timing Specifications

You can specify timing requirements for paths in your design. PAR uses these timing specifications to achieve optimum performance when placing and routing your design.

Netlist Translation Programs

Two netlist translation programs allow you to read netlists into the Xilinx software tools. EDIF2NGD allows you to read an Electronic Data Interchange Format (EDIF) 2 0 0 file. The NGDBuild program automatically invokes these programs as needed to convert your EDIF file to an NGD file, the required format for the Xilinx software tools. NGC files output from the Xilinx XST synthesis tool are read in by NGDBuild directly.

You can find detailed descriptions of the EDIF2NGD, and NGDBuild programs in Chapter 6, “NGDBuild” and “Appendix B”.

Design Implementation

Design Implementation begins with the mapping or fitting of a logical design file to a specific device and is complete when the physical design is successfully routed and a bitstream is generated. You can alter constraints during implementation just as you did during the Design Entry step. See “Constraints” for information.

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Design Implementation

The following figure shows the design implementation process for FPGA designs:

UCF

NGDBuild

Constraints Editor

NGD

Floorplanner

 

 

MAP

FPGA Editor

 

NCD & PCF

 

TRACE &

PAR

 

Timing Analyzer

 

 

 

 

NCD

 

 

BitGen

 

 

BIT

PROMGen

iMPACT

X10296

Figure 2-5: Design Implementation Flow (FPGAs)

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The following figure shows the design implementation process for CPLD designs:

Logic Optimization

Pin Feedback Generation

Power/Slew Optimization

NGDBuild

NGD

Implementation Options

 

CPLD Fitter

Design Loader

Auto Device/Speed Selector

Logic Synthesis

Technology Mapping

Global Net Optimization

Partitioning

Export Level Generator

Exporting

Assignments

PTerm Mapping

Post-Mapping

Enhancements

Routing

RPT

GYD

VM6

Fitter Report (Text)

HPLUSAS6

VM6

HPREP6

JED

iMPACT

X9493

Figure 2-6: Design Implementation Flow (CPLDs)

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Design Implementation

Mapping (FPGAs Only)

For FPGAs, the MAP command line program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD file, which contains a logical description of the design in terms of both the hierarchical components used to develop the design and the lower-level Xilinx primitives, and any number of NMC (hard placed-and-routed macro) files, each of which contains the definition of a physical macro. MAP then maps the logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA.

The output design from MAP is an NCD file, which is a physical representation of the design mapped to the components in the Xilinx FPGA. The NCD file can then be placed and routed, using the PAR command line program. See Chapter 7, “MAP” for detailed information.

Placing and Routing (FPGAs Only)

For FPGAs, the PAR command line program takes a mapped NCD file as input, places and routes the design, and outputs a placed and routed NCD file, which is used by the bitstream generator, BitGen. The output NCD file can also act as a guide file when you reiterate placement and routing for a design to which minor changes have been made after the previous iteration. See Chapter 9, “PAR” for detailed information.

You can also use the FPGA Editor GUI tool to do the following:

Place and route critical components before running automatic place and route tools on an entire design

Modify placement and routing manually; the editor allows both automatic and manual component placement and routing

Note: For more information, see the online Help provided with the FPGA Editor.

Bitstream Generation (FPGAs Only)

For FPGAs, the BitGen command line program produces a bitstream for Xilinx device configuration. BitGen takes a fully routed NCD file as its input and produces a configuration bitstream—a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. See Chapter 14, “BitGen” for detailed information.

After you generate your BIT file, you can download it to a device using the iMPACT GUI. You can also format the BIT file into a PROM file using the PromGen command line program and then download it to a device using the iMPACT GUI. See Chapter 16, “PROMGen” of this guide or the iMPACT online help for more information.

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Design Verification

Design verification is testing the functionality and performance of your design. You can verify Xilinx designs in the following ways:

Simulation (functional and timing)

Static timing analysis

In-circuit verification

The following table lists the different design tools used for each verification type.

Table 2-1: Verification Tools

Verification Type

Tools

 

 

Simulation

Third-party simulators (integrated and

 

non-integrated)

 

 

Static Timing

TRACE (command line program)

Analysis

Timing Analyzer (GUI)

 

 

Mentor Graphics® TAU and Innoveda

 

BLAST software for use with the STAMP

 

file format (for I/O timing verification

 

only)

 

 

In-Circuit Verification

Design Rule Checker (command line

 

program)

 

Download cable

 

 

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Design verification procedures should occur throughout your design process, as shown in the following figures.

Simulation

 

 

 

Input Stimulus

 

Basic Design Flow

 

 

 

 

 

Integrated Tool

Design Entry

 

Simulation

 

 

 

Functional Simulator

 

 

 

Paths

 

 

Simulation Netlist

Translate to

NGD

 

Simulator Format

 

 

 

 

Translate to

 

Mapping, Placement

 

Simulator Format

 

 

 

and Routing

 

 

 

 

Timing Simulation Path

 

Static Timing

 

 

 

Translation

NCD

Static Timing Analysis

 

 

BitGen

 

 

 

 

In-Circuit Verification

 

Back-Annotation

 

 

 

 

BIT

In-Circuit Verification

 

NGA

 

 

 

 

Xilinx FPGA

 

 

 

 

X9556

Figure 2-7: Three Verification Methods of the Design Flow (FPGAs)

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The following figure shows the verification methods of the design flow for CPLDs.

Simulation

Input Stimulus

 

 

 

 

Basic Design Flow

 

 

 

 

Integrated Tool

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Simulation

 

 

 

 

 

 

 

 

Design Entry

 

 

 

Functional Simulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Paths

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Simulation Netlist

 

 

Translate to

 

 

 

 

 

NGD

 

 

Simulator Format

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Translate to

Optimization and

 

Simulator Format

 

Fitting

 

 

 

Timing Simulation Path

 

Static Timing

 

 

Translation

VM6

Static Timing Analysis

 

Programming

 

 

File Creation

In-Circuit Verification

 

 

Back-Annotation

 

 

 

JED

In-Circuit Verification

NGA

 

 

 

Xilinx CPLD

 

 

 

X9538

Figure 2-8: Three Verification Methods of the Design Flow (CPLDs)

Simulation

You can run functional or timing simulation to verify your design. This section describes the back-annotation process that must occur prior to timing simulation. It also describes the functional and timing simulation methods for both schematic and HDL-based designs.

Back-Annotation

Before timing simulation can occur, the physical design information must be translated and distributed back to the logical design. For FPGAs, this back-annotation process is done with a program called NetGen. For CPLDs, back-annotation is performed with the TSim Timing Simulator. These programs create a database, which translates the back-annotated information into a netlist format that can be used for timing simulation.

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The following figures show the back-annotation flows:

NGD

Logical Design

MAP

 

 

 

PCF

Simulation Netlist

NCD

 

 

 

Physical Design

 

 

(Mapped)

NetGen

Equivalence Checking

NCD

Netlist

 

 

PAR

 

Static Timing Analysis

 

 

Netlist

NCD

Physical Design

(Placed and Routed)

X10298

Figure 2-9: Back-Annotation Flow for FPGAs

 

EDIF

 

V

 

NetGen

 

SDF

 

VHD

NGD

SDF

Logical Design

 

Command line only

 

Optimization

NGA

 

and Fitting

 

VM6

TSIM

Physical Design

Timing Simulator

X10297

Figure 2-10: Back-Annotation (CPLDs)

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NetGen

NetGen is a command line program that distributes information about delays, setup and hold times, clock to out, and pulse widths found in the physical NCD design file back to the logical NGD file and generates a Verilog or VHDL netlist for use with supported timing simulation, equivalence checking, and static timing analysis tools.

NetGen reads an NCD as input. The NCD file can be a mapped-only design, or a partially or fully placed and routed design. An NGM file, created by MAP, is an optional source of input. NetGen merges mapping information from the optional NGM file with placement, routing, and timing information from the NCD file.

Note: NetGen reads an NGA file as input to generate a timing simulation netlist for CPLD designs.

See Chapter 22, “NetGen” for detailed information.

Schematic-Based Simulation

Design simulation involves testing your design using software models. It is most effective when testing the functionality of your design and its performance under worst-case conditions. You can easily probe internal nodes to check the behavior of your circuit, and then use these results to make changes in your schematic.

Simulation is performed using third-party tools that are linked to the Xilinx Development System. Use the various CAE-specific interface user guides, which cover the commands and features of the Xilinx-supported simulators, as your primary reference.

The software models provided for your simulation tools are designed to perform detailed characterization of your design. You can perform functional or timing simulation, as described in the following sections.

Functional Simulation

Functional simulation determines if the logic in your design is correct before you implement it in a device. Functional simulation can take place at the earliest stages of the design flow. Because timing information for the implemented design is not available at this stage, the simulator tests the logic in the design using unit delays.

Note: It is usually faster and easier to correct design errors if you perform functional simulation early in the design flow.

You can use integrated and non-integrated simulation tools. Integrated tools, such as Mentor Graphics or Innoveda, often contain a built-in interface that links the simulator and a schematic editor, allowing the tools to use the same netlist. You can move directly from entry to simulation when using a set of integrated tools.

Functional simulation in schematic-based tools is performed immediately after design entry in the capture environment. The schematic capture tool requires a Xilinx Unified Library and the simulator requires a library if the tools are not integrated. Most of the schematic-based tools require translation from their native database to EDIF for implementation. The return path from implementation is usually EDIF with certain exceptions in which a schematic tool is tied to an HDL simulator.

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Timing Simulation

Timing simulation verifies that your design runs at the desired speed for your device under worst-case conditions. This process is performed after your design is mapped, placed, and routed for FPGAs or fitted for CPLDs. At this time, all design delays are known.

Timing simulation is valuable because it can verify timing relationships and determine the critical paths for the design under worst-case conditions. It can also determine whether or not the design contains set-up or hold violations.

Before you can simulate your design, you must go through the back-annotation process, as described in “Back-Annotation”. During this process, NetGen creates suitable formats for various simulators.

Note: Naming the nets during your design entry is important for both functional and timing simulation. This allows you to find the nets in the simulations more easily than looking for a softwaregenerated name.

HDL-Based Simulation

Xilinx supports functional and timing simulation of HDL designs at the following points:

Register Transfer Level (RTL) simulation, which may include the following:

Instantiated UniSim library components

LogiCORE models

Post-synthesis functional simulation with one of the following:

Gate-level UniSim library components

Gate-level pre-route SimPrim library components

Post-implementation back-annotated timing simulation with the following:

SimPrim library components

Standard delay format (SDF) file

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The following figure shows when you can perform functional and timing simulation:

 

HDL

 

 

Design

 

UniSim

HDL RTL

Testbench

Library

Simulation

Stimulus

LogiBLOX

Synthesis

 

 

 

Modules

 

 

 

Post-Synthesis Gate-Level

 

CORE Generator

Functional Simulation

 

 

 

Modules

 

 

 

Xilinx

 

 

Implementation

 

SimPrim

HDL Timing

 

Simulation

 

Library

 

 

 

X9243

Figure 2-11: Simulation Points for HDL Designs

The three primary simulation points can be expanded to allow for two post-synthesis simulations. These points can be used if the synthesis tool cannot write VHDL or Verilog, or if the netlist is not in terms of UniSim components. The following table lists all the simulation points available in the HDL design flow.

Table 2-2: Five Simulation Points in HDL Design Flow

Simulation

UniSim

SimPrim

SDF

 

 

 

 

RTL

X

 

 

 

 

 

 

Post-Synthesis

X

 

 

 

 

 

 

Functional Post-NGDBuild (Optional)

 

X

 

 

 

 

 

Functional Post-MAP (Optional)

 

X

X

 

 

 

 

Post-Route Timing

 

X

X

 

 

 

 

These simulation points are described in the “Simulation Points” section of the Synthesis and Simulation Design Guide.

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Design Verification

The libraries required to support the simulation flows are described in detail in the “VHDL/Verilog Libraries and Models” section of the Synthesis and Simulation Design Guide. The flows and libraries support close functional equivalence of initialization behavior between functional and timing simulations. This is due to the addition of new methodologies and library cells to simulate Global Set/Reset (GSR) and Global 3-State (GTS) behavior.

You must address the built-in reset circuitry behavior in your designs, starting with the first simulation, to ensure that the simulations agree at the three primary points. If you do not simulate GSR behavior prior to synthesis and place and route, your RTL and post-synthesis simulations may not initialize to the same state as your post-route timing simulation. If this occurs, your various design descriptions are not functionally equivalent and your simulation results do not match.

In addition to the behavioral representation for GSR, you must add a Xilinx implementation directive. This directive is specifies to the place and route tools to use the special purpose GSR net that is pre-routed on the chip, and not to use the local asynchronous set/reset pins. Some synthesis tools can identify the GSR net from the behavioral description, and place the STARTUP module on the net to direct the implementation tools to use the global network. However, other synthesis tools interpret behavioral descriptions literally and introduce additional logic into your design to implement a function. Without specific instructions to use device global networks, the Xilinx implementation tools use general-purpose logic and interconnect resources to redundantly build functions already provided by the silicon.

Even if GSR behavior is not described, the chip initializes during configuration, and the post-route netlist has a net that must be driven during simulation. The “Understanding the Global Signals for Simulation” section of the Synthesis and Simulation Design Guide includes the methodology to describe this behavior, as well as the GTS behavior for output buffers.

Xilinx VHDL simulation supports the VITAL standard. This standard allows you to simulate with any VITAL-compliant simulator. Built-in Verilog support allows you to simulate with the Cadence Verilog-XL and other compatible simulators. Xilinx HDL simulation supports all current Xilinx FPGA and CPLD devices. Refer to the Synthesis and Simulation Design Guide for the list of supported VHDL and Verilog standards.

Static Timing Analysis (FPGAs Only)

Static timing analysis is best for quick timing checks of a design after it is placed and routed. It also allows you to determine path delays in your design. Following are the two major goals of static timing analysis:

Timing verification

This is verifying that the design meets your timing constraints.

Reporting

This is enumerating input constraint violations and placing them into an accessible file. You can analyze partially or completely placed and routed designs. The timing information depends on the placement and routing of the input design.

You can run static timing analysis using the Timing Reporter and Circuit Evaluator (TRACE) command line program. See Chapter 12, “TRACE” for detailed information. You can also use the Timing Analyzer GUI to perform this function. See the online Help provided with the Timing Analyzer for additional information. Use either tool to evaluate how well the place and route tools met the input timing constraints.

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In-Circuit Verification

As a final test, you can verify how your design performs in the target application. In-circuit verification tests the circuit under typical operating conditions. Because you can program your Xilinx devices repeatedly, you can easily load different iterations of your design into your device and test it in-circuit. To verify your design in-circuit, download your design bitstream into a device with the Parallel Cable IV or MultiPRO cable.

Note: For information about Xilinx cables and hardware, see the iMPACT online help.

Design Rule Checker (FPGAs Only)

Before generating the final bitstream, it is important to use the DRC option in BitGen to evaluate the NCD file for problems that could prevent the design from functioning properly. DRC is invoked automatically unless you use the –d option. See Chapter 8, “Physical Design Rule Check” and Chapter 14, “BitGen” and for detailed information.

Xilinx Design Download Cables

Xilinx provides the Parallel Cable IV or MultiPRO cable to download the configuration data containing the device design.

You can use the Xilinx download cables with the iMPACT Programming software for FPGA and CPLD design download and readback, and configuration data verification. The iMPACT Programming software cannot be used to perform real-time design functional verification.

Probe

The Xilinx PROBE function in FPGA Editor provides real-time debug capability good for analyzing a few signals at a time. Using PROBE a designer can quickly identify and route any internal signals to available I/O pins without having to replace and route the design. The real-time activity of the signal can then be monitored using normal lab test equipment such as logic/state analyzers and oscilloscopes.

ChipScope ILA and ChipScope PRO

The ChipScope toolset was developed to assist engineers working at the PCB level. ChipScope ILA actually embeds logic analyzer cores into your design. These logic cores allow the user to view all the internal signals and nodes within an FPGA. ChipScope ILA supports user selectable data channels from 1 to 256. The depth of the sample buffer ranges from 256 to 16384 in Virtex-II devices. Triggers are changeable in real-0time without affecting the user logic or requiring recompilation of the user design.

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FPGA Design Tips

FPGA Design Tips

The Xilinx FPGA architecture is best suited for synchronous design. Strict synchronous design ensures that all registers are driven from the same time base with no clock skew. This section describes several tips for producing high-performance synchronous designs.

Design Size and Performance

Information about design size and performance can help you to optimize your design. When you place and route your design, the resulting report files list the number of CLBs, IOBs, and other device resources available. A first pass estimate can be obtained by processing the design through the MAP program.

If you want to determine the design size and performance without running automatic implementation software, you can quickly obtain an estimate from a rough calculation based on the Xilinx FPGA architecture.

Global Clock Distribution

Xilinx clock networks guarantee small clock skew values. The following table lists the resources available for the Xilinx FPGA families.

Table 2-3: Global Clock Resources

FPGA Family

Resource

Number

Destination Pins

 

 

 

 

Spartan

BUFGS

4

Clock, control, or certain input

 

 

 

 

Virtex, Virtex-E,

BUFG

4

Clock

Spartan-II,

 

 

 

Spartan-IIE

 

 

 

 

 

 

 

Virtex-II, Virtex-II

BUFGMUX

16

Clock

Pro

 

 

 

 

 

 

 

Note: In certain devices families, global clock buffers are connected to control pin and logic inputs. If a design requires extensive routing, there may be extra routing delay to these loads.

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Chapter 2: Design Flow

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Data Feedback and Clock Enable

The following figure shows a gated clock. The gated clock’s corresponding timing diagram shows that this implementation can lead to clock glitches, which can cause the flip-flop to clock at the wrong time.

a) Gated Clock

D Q

Enable

Clock

Clock

Enable

b) Corresponding Timing Diagram

Clock

Enable

Clock

Enable

Output

X9201

Figure 2-12: Gated Clock

The following figure shows a synchronous alternative to the gated clock using a data path. The flip-flop is clocked at every clock cycle and the data path is controlled by an enable. When the enable is Low, the multiplexer feeds the output of the register back on itself. When the enable is High, new data is fed to the flip-flop and the register changes its state.

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