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Secondary Side Synchronous Post Regulator
UC1584
UC2584
UC3584
FEATURES
• Practical Operation at Switching
Frequencies up to 1MHz
• Wide Band Error Amplifier
• Undervoltage Lockout with Hysteresis
• Output Active Low During UVLO
• Soft Start/Maximum Duty Cycle
Control
• Trimmed Bandgap Reference
• Internally Regulated 15V Boost
Supply
• Short Circuit Protection with
Programmable Delay
TYPICAL APPLICATION DIAGRAM.
10
170kHz
PUSH-PULL
2
210
IRFR024
4.75kΩ
3.57kΩ 3.3Ω
33µH
COILTRONICS
CSHD
10-45L
390µF
DESCRIPTION
The UC3584 is a low voltage, Secondary Side Synchronous Post Regulator. It is intended to be used for auxiliary output voltage regulation in single
secondary winding, multiple output power supplies (for more details refer
to the Application Section of this Data sheet). The UC3584 is most suited
for systems where the main output is regulated between 5V and 14V. Output voltages regulated by the UC3584 can range from virtually 0V up to
the output voltage of the main output.
Auxiliary output voltage regulation with the UC3584 uses leading edge
modulation making it compatible to primary side peak current or voltage
mode control. The UC3584 clock circuit is synchronized to the switching
frequency utilizing the falling edge of the transformer’s secondary winding
waveform.
7µH
OS-CON
+
3.3V
++++
0.1µF
100Ω
1.5W
24.3kΩ
1500pF
1.33kΩ
3300pF
20kΩ
30.1kΩ
0.1µF
1000pF
1.5µF
AUX
120pF
FB
1
2
COMP
3
SS
4
CDLY
5
GND
SRC
6
OUT
7
VFLT
8
330µF
SYNC
CT
RT
VREG
VCC
BST2
PGND
BST1
16
15
14
13
12
10BQ040
11
10
9
+
220pF
15kΩ
1µF
0.1µF
10µF
+
SOLID
TANTALUM
1kΩ
100pF
1N4148
33µH
COLTRONICS
0.1µF
+
470µF
5V
MAIN
03/99
1N4148
UDG-99062
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
V
Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V, 30V at 2A
FLT
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 20V
SYNC Maximum Sink Current. . . . . . . . . . . . . . . . . . . . . 600µA
PWM Driver, I
PWM Driver, I
Maximum Operating Frequency . . . . . . . . . . . . . . . . . . . . 1MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 300mA
OUT
(Peak). . . . . . . . . . . . . . . . . . . . . . . . . ± 1.5A
OUT
UC1584
UC2584
UC3584
Power Dissipation at T
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . . 300°C
Currents are positive into, negative out of specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
= 60°C . . . . . . . . . . . . . . . . . . . . . . 1W
A
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View)
J, N or DW Packages
ORDERING INFORMATION
TEMPERATURE RANGE PACKAGE
UC1584J –55°C to +125°C CDIP
UC2584DW –40°C to +85°C SOIC-Wide
UC2584N PDIP
UC3584DW 0°C to +70°C SOIC-Wide
UC3584N PDIP
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, T
= 0°C to 70°C for the UC3584, –40°C to 85°C for
A
the UC2584, and –55°C to 125°C for the UC1584, VCC = 15V. TA=TJ.
PARAMETERS TEST CONDITIONS MIN TYPE MAX UNITS
Error Amplifier
FB COMP = FB 1.468 1.5 1.532 V
I
FB
COMP V
COMP V
OL
OH
V
COMP=VFB
FB = 1.6V, I
FB = 1.4V, I
= 200µA 50 400 mV
COMP
= –200µA 5.1 5.5 7 V
COMP
150 300 450 nA
AVOL 60 80 dB
PSRR (COMP) COMP = FB, VCC = 14V to 16V 60 dB
GBW Product F = 100kHz 5 10 MHz
Oscillator
Frequency R
= 3.75k, CT= 400pF, No Synchronization 500 kHz
T
Ramp Low RT= 3.75k, CT= 400pF, No Synchronization 1.75 V
Ramp High RT= 3.75k, CT= 400pF, No Synchronization 3.5 V
Ramp Amplitude RT= 3.75k, CT= 400pF, No Synchronization 1.75 V
PWM
Maximum Duty Cycle COMP = 4.5V 90 %
Minimum Duty Cycle COMP = 0V 0 %
PWM DRIVER
High V
V
SAT
V
Low V
SAT
T
RISE
T
FALL
FLT–VOUT,IOUT
OUT–VSRC,IOUT
Load = 1nF, SRC = 0V, Measure V
Load = 1nF, SRC = 0V, Measure V
= –100mA 2.5 3 V
= 50mA 0.8 2.2 V
1V to 9V 75 100 ns
OUT
9V to 1V 25 100 ns
OUT
2
UC1584
UC2584
UC3584
ELECTRICAL CHARACTERISTICS:
UC2584, and –55°C to 125°C for the UC1584, VCC = 15V. TA=TJ.
PARAMETERS TEST CONDITIONS MIN TYPE MAX UNITS
Soft Start
Charge Current 30 µA
Discharge Current 1mA
SS Delay C
Fault Latch
Charge Current 30 µA
Discharge Current 5mA
Fault Latch Delay CDLY = 500nF 50 ms
UVLO
VCC On 10.5 V
Hysteresis 1.7 V
Regulated Voltage
V
REG
VCC Regulator
VCC Boost inductor connected to 5V 14 15 16 V
I
CC
Unless otherwise specified, TA= 0°C to 70°C for the UC3584, –40°C to 85°C for the
= 500nF 50 ms
SS
I
= 0mA to 1mA 4.8 5.2 V
REG
No Load, Boost Circuitry Inactive 12 40 mA
No Load, Boost Circuitry Active (Note 1) 55 mA
Note 1: Guaranteed by design. Not 100% tested in production.
BLOCK DIAGRAM
UDG-97141
3
PIN DESCRIPTIONS
BST1: Collector of the boost switch. This is the
connection point of the external boost inductor and boost
diode. The boost converter generates the bias supply for
the UC3584 from the regulated 5V output.
BST2: See BST1. BST2 must be connected externally
to BST1 pin.
CDLY: Delay Set. External CDLY capacitor sets the
delay from the time Short Circuit condition is detected
and Fault Condition is asserted.
COMP: Output of the Voltage Error Amplifier.
CT: Connect the Timing Capacitor between CT and GND.
FB: Inverting Input of the Voltage Error Amplifier.
GND: Analog System Ground.
OUT: Output of the floating driver for an external,
N-channel MOSFET.
PGND: Power Ground. This is the reference node for the
boost bias supply regulator. PGND and GND must be
connected externally.
UC1584
UC2584
UC3584
RT: A Timing Resistor connected between RT and GND
sets the discharge current of the timing capacitor.
SRC: Source connection of the floating driver to the
external switch.
SS: Soft Start. An external capacitor is connected
between SS and GND to set the duration of the Soft
Start cycle.
SYNC: Synchronization Pin. The UC3584 is
synchronized from the falling edge of the transformer’s
secondary winding. Voltage must exceed 1V at minimum
input line.
VCC: Bias supply of the chip, approximately 15V. This is
also the output of the boost regulator. The VCC pin must
be decoupled to PGND.
VFLT: Positive rail of the floating driver’s bias supply.
Decouple to SRC using a high frequency (ceramic)
capacitor.
VREG: Output of the internal 5V regulated supply. Must
be decoupled to GND.
APPLICATION INFORMATION
Biasing the UC3584
Bias supply for the UC3584 is generated from the main
output of the power supply by a boost regulator. The inductor, diode and capacitor of the boost converter are external components, while the boost switch is internal to
the chip. The boost converter operates in a burst mode
with a built-in hysteresis of approximately 1V centered at
15V. This is a bang-bang controller and when enabled
has a fixed duty cycle of 75%.
Undervoltage Detection
The UVLO circuit of the UC3584 monitors the voltage on
VCC. During power up and power down, the pulse width
modulator and the output driver are disabled and OUT is
held active low. Operation is enabled when VCC reaches
10.5V. The UVLO circuitry has a built-in hysteresis of
1.7V (10.5V to 8.8V) thus VCC must drop below 8.8V in
order to assert UVLO again.
Precision Reference
An internal precision bandgap reference provides accurate voltages to the error amplifier and other control sections of the IC. A buffered 5V regulated voltage is also
available for external circuitry on the VREG pin. This pin
must be decoupled to the signal GND connection by a
good quality high frequency capacitor.
Oscillator and Trailing Edge Synchronization
The UC3584 is outfitted with a synchronizable oscillator
which also generates a ramp signal across the C
T capac-
itor for the PWM comparator. For easy implementation of
the leading edge pulse width modulation technique, the
oscillator has an inverted ramp waveform as shown in
Fig. 1. The free running oscillator frequency is determined by the timing components, R
T and CT, according
to the following approximate equations:
17..
MAX
8
.
09
C
T
.
()
RC
•
()
TT
R
f
OSC
93
=
T
D
−
1
−ו
28210
=
where
is the timing resistor, its value should be between
R
T
1kΩ and 100kΩ,
CTis the timing capacitor,
is the desired maximum duty cycle, and
D
MAX
is the free running oscillator frequency.
f
OSC
Figure 2 graphically depicts the measured frequency
data.
4
APPLICATION INFORMATION (cont.)
V
SEC
INTERNAL
SYNC PULSE
C
T
COMP
OUT
UC1584
UC2584
UC3584
UDG-99064
Figure 1. Trailing edge synchronization, leading edge modulation.
Edge Modulation
During normal operation the oscillator must be synchronized to the falling edge of the transformer secondary
waveform. Synchronization is achieved by connecting
SYNC to the secondary winding via a resistor divider.
The resistor divider must be chosen to provide a SYNC
pin voltage in excess of 1V at the lowest operating voltage on the transformer secondary winding. The UC3584
will generate a narrow internal synchronization pulse
which will synchronize the oscillator to the switching frequency of the main converter.
PWM and Output Driver
1. VCC within normal range (UVLO is inactive),
2. No fault condition is detected,
3. C
T
During the fast charging time of the C
low.
Ultimately, the output of the PWM circuitry controls the
conduction interval of an external N-channel MOSFET
switch in the power supply. The UC3584 employs an
on-board, floating gate driver circuit to interface to the
external switch. An external capacitor connected between VFLT and SRC acts as a floating power supply for
The UC3584 employs leading edge modulation technique to set the required on time of its output. Leading
1.E+06
edge modulation is preferred for secondary side regulation in multiple output converters to prevent ambiguity in
the primary current waveform. In fact, this is the only feasible technique to preserve compatibility with primary
side peak current mode control.
1.E+05
As Fig. 1 depicts the UC3584 utilizes voltage mode control to regulate output voltage. The output pulse width
(the on-time of the MOSFET switch) is determined on a
FREQUENCY (Hz)
cycle-by-cycle basis by comparing the output of the voltage error amplifier and the ramp waveforms across the
timing capacitor. OUT is asserted when the voltage on
COMP exceeds the voltage on CT. There are three more
1.E+04
1.E+03 1.E+04 1.E+05
conditions which must be satisfied to obtain an active
high on the OUT pin. These conditions are:
Figure 2. Oscillator frequency vs. RTwith CTas a
parameter.
is discharging.
TIMING RESISTOR (Ohms)
1500pF
capacitor is held
T
470pF
1000pF
1200pF
47pF
100pF
220pF
5
APPLICATION INFORMATION (cont.)
the driver during the on-time of the switch. Charge is being replenished to the bootstrap capacitor during the
off-time of the switch through the bootstrap diode connected between VCC and VFLT as shown in the typical
application diagram.
Soft Start
The UC3584 Soft Start circuitry is designed to implement
closed loop startup of the power supply output. During
Soft Start, the reference to the noninverting input of the
error amplifier is controlled by the voltage across the soft
start capacitor on SS. As this voltage rises, it provides an
increasing reference to the error amplifier. Once the soft
start capacitor charges above the 1.5V precision reference of the error amplifier, SS gets disconnected from
the noninverting input of the error amplifier. This technique allows the error amplifier to stay in its linear mode
and to regulate the output voltage of the power supply
according to the gradually increasing reference voltage
on its noninverting input. Further advantage of the closed
loop start up scheme is the absence of output voltage
overshoot during power up of the power supply output.
Fault Detection
Fault Detection feature is implemented to detect excessive overload conditions. Under these conditions the error amplifier output goes high to command the maximum
duty cycle. As soon as the error amplifier’s output exceeds 5V, the fault delay capacitor connected to the
CDLY pin starts charging. If C
reaches 2V before the error amplifier output falls back
capacitor voltage
DLY
UC1584
UC2584
below 5V, a fault condition is declared, the PWM output
is disabled and soft start cycle is initiated. Under persistent fault conditions the UC3584 will continuously cycle
through soft start sequence, attempting to bring the output to its regulated, nominal voltage. The value of C
capacitor should be chosen large enough to delay the
activation of the fault sequence in case of load transients
which can also cause the error amplifier output to go
high temporarily.
Error Amplifier
The Error Amplifier of the UC3584 is used to regulate the
voltage of an auxiliary output in a power supply. The
noninverting input of the error amplifier is connected to
an internal, 1.5V reference. The inverting input (FB pin)
is tied to an output voltage divider. The compensation
network of the negative feedback loop is connected between the amplifier’s output (COMP pin) and FB. The
noninverting input of the error amplifier is also connected
to the SS node through a diode. This arrangement allows
closed loop soft start for the output of a power supply
regulated by the UC3584. Closed loop soft start assures
that the error amplifier is kept in active mode and the output voltage of the converter follows the reference voltage
on its noninverting input as it ramps up (following the SS
node). If a fault condition is detected, SS node gets
pulled to ground, forcing the error amplifier’s reference
low. Consequently, the error amplifier’s output voltage
goes low and duty cycle is reduced.
DLY
UNITRODE CORPORATION
7 CONTINENTALBLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
6
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