UNITRODE UC1517, UC3517 Technical data

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UNITRODE UC1517, UC3517 Technical data

UC1517

UC1517

UC3517

Stepper Motor Drive Circuit

FEATURES

Complete Motor Driver and Encoder

Continuous Drive Capability 350mA per Phase

Contains all Required Logic for Full and Half Stepping

Bilevel Operation for Fast Step Rates

Operates as a Voltage Doubler

Useable as a Phase Generator and/or as a Driver

Power-On Reset Guarantees Safe, Predictable Power-Up

DESCRIPTION

The UC3517 contains four NPN drivers that operate in two-phase fashion for full-step and half-step motor control. The UC3517 also contains two emitter followers, two monostables, phase decoder logic, power-on reset, and low-voltage protection, making it a versatile system for driving small stepper motors or for controlling large power devices.

The emitter followers and monostables in the UC3517 are configured to apply higher-voltage pulses to the motor at each step command. This drive technique, called “Bilevel,” allows faster stepping than common resistive current limiting, yet generates less electrical noise than chopping techniques.

ABSOLUTE MAXIMUM RATINGS

Second Level Supply, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Phase Output Supply, VMM . . . . . . . . . . . . . . . . . . . . . . . . . 40V Logic Supply, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -.3V to +7V Logic Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Output Current, Each Phase . . . . . . . . . . . . . . . . . . . . . . 500mA Output Current, Emitter Follower . . . . . . . . . . . . . . . . . . -500mA Power Dissipation, (Note). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Power Dissipation, (Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Ambient Temperature, UC1517 . . . . . . . . . . . . -55°C to +125°C Ambient Temperature, UC3517 . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . -55°C to +150°C

Note: Consult Packaging section of Databook for thermal limitations and considerations of package.

BLOCK DIAGRAM

8/94

 

 

 

UC1517

 

 

 

UC3517

CONNECTION DIAGRAMS

 

 

 

DIL-16 (TOP VIEW)

PLCC-20, LCC-20

PACKAGE PIN FUNCTION

J or N Package

(TOP VIEW)

FUNCTION

PIN

 

Q & L PACKAGE

N/C

1

 

 

PB2

2

 

 

PB1

3

 

 

GND

4

 

 

PA1

5

 

 

N/C

6

 

 

PA2

7

 

 

DIR

8

 

 

STEP

9

 

 

Ø B

10

 

 

N/C

11

 

 

Ø A

12

 

 

HSM

13

 

 

INH

14

 

 

RC

15

 

 

N/C

16

 

 

LA

17

 

 

LB

18

 

 

VSS

19

 

 

VCC

20

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = -55°C to +125°C for the UC1517 and 0°C to +70°C for the UC3517, Vcc=5V, V SS = 20V, TA=TJ. Pin

numbers refer to DIL-16 package.

PARAMETER

TEST CONDITIONS

UC1517 / UC3517

UNITS

MIN

TYP

MAX

 

 

 

 

Logic Supply, VCC

Pin 16

4.75

 

5.25

V

Second Supply, VSS

Pin 15

10

 

40

V

Logic Supply Current

VINH = 0.4V

 

45

60

mA

 

VINH = 4.0V

 

12

 

mA

Input Low Voltage

Pins 6, 7, 10, 11

 

 

0.8

V

Input High Voltage

Pins 6, 7, 10, 11

2.0

 

 

V

Input Low Current

Pins 6, 7, 10, 11; V = 0V

-400

 

 

μA

Input High Current

Pins 6, 7, 10, 11; V = 5V

 

 

20

μA

Phase Output Saturation Voltage

Pins 1, 2, 4, 5; I = 350mA

 

0.6

0.85

V

Phase Output Leakage Current

Pins 1, 2, 4, 5; V = 39V

 

 

500

μA

Follower Saturation Voltage to VSS

Pins 13,14; I = 350mA

 

 

-2

V

Follower Leakage Current

Pins 13,14; V = 0V

 

 

500

μA

Output Low Voltage, Ø A, Ø B

Pins 8, 9; I = 1.6mA

 

0.1

0.4

V

Phase Turn-On Time

Pins 1, 2, 4, 5

 

2

 

μs

Phase Turn-Off Time

Pins 1, 2, 4, 5

 

1.8

 

μs

Second-Level On Time. TMONO

Pins 13,14; Figure 3 Test Circuit

275

325

375

μs

Logic Input Set-up Time, tS

Pins 6, 10; Figure 4

400

 

 

ns

Logic Input Hold Time, th

Pins 6, 10; Figure 4

0

 

 

ns

STEP Pulse Width, tP

Pin 7; Figure 4

800

 

 

ns

Timing Resistor Value

Pin 12

1k

 

100k

Ω

Timing Capacitor Value

Pin 12

0.1

 

500

nF

Power-On Threshold

Pin 16

 

4.3

 

V

Power-Off Threshold

Pin 16

 

3.8

 

V

Power Hysteresis

Pin 16

 

0.5

 

V

2

UC1517

UC3517

Figure 3. Test Circuit

PIN DESCRIPTION

VCC: VCC is the UC3517’s logic supply. Connect to a regulated 5VDC, and bypass with a 0.1μF ceramic capacitor to absorb switching transients.

VMM: VMM is the primary motor supply. It connects to the UC3517 phase outputs through the motor windings. Limit this supply to less than 40V to prevent breakdown of the phase output transistors. Select the nominal VMM voltage for the desired continuous winding current.

VSS: VSS is the secondary motor supply. It drives the LA and LB outputs of the UC3517 when a monostable in the UC3517 is active. In the bilevel application, this supply is applied to the motor to charge the winding inductance faster than the primary supply could. Typically, Vss is higher in voltage than VMM, although VSS must be less than 40V. The VSS supply should have good transient capability.

GROUND: The ground pin is the common reference for all supplies, inputs and outputs.

RC: RC controls the timing functions of the monostables in the UC3517. It is normally connected to a resistor (RT) and a capacitor (CT) to ground, as shown in Figure 3. Monostable on time is determined by the formula TON 0.69 RT CT. To keep the monostable on indefinitely, pull RC to VCC through a 50k resistor. The UC3517 contains only one RC pin for two monostables. If step rates comparable to TON are commanded, incorrect pulsing can result, so consider maximum step rates when selecting RT and CT. Keep TON T STEP MAX.

Ø A and Ø B: These logic outputs indicate half-step position. These outputs are open-collector, low-current drivers, and may directly drive TTL logic. They can also drive CMOS logic if a pull-up resistor is provided. Systems which use the UC3517 as an encoder and use a different driver can use these outputs to disable the external driver,

Figure 4. Timing Waveforms

as shown in Figure 8. The sequencing of these outputs is shown in Figure 5.

PA1, PA2, PB1, and PB2: The phase outputs pull to ground sequentially to cause motor stepping, according to the state diagram of Figure 5. The sequence of stepping on these lines, as well as with the LA and LB lines is controlled by STEP input, the DIR input, and the HSM input. Caution: If these outputs or any other IC pins are pulled too far below ground either continuously or in a transient, step memory can be lost. It is recommended that these pins be clamped to ground and supply with high-speed diodes when driving inductive loads such as motor windings or solenoids. This clamping is very important because one side of the winding can "kick" in a direction opposite the swing of the other side.

LA and LB: These outputs pull to VSS when their corresponding monostable is active, and will remain high until the monostable time elapses. Before and after, these outputs are high-impedance. For detail timing information, consult Figure 5.

STEP: This logic input clocks the logic in the UC3517 on every falling edge. Like all other UC3517 inputs, this input is TTL/CMOS compatible, and should not be pulled below ground.

DIR: This logic input controls the motor rotation direction by controlling the phase output sequence as shown in Figure 5. This signal must be stable 400ns before a falling edge on STEP, and must remain stable through the edge to insure correct stepping.

HSM: This logic input switches the UC3517 between halfstepping (HSM = low) and full-stepping (HSM = high) by controlling the phase output sequence as show in Figure 5. This line requires the same set-up time as the DIR input, and has the same hold requirement.

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