UNITRODE UC1548, UC2548, UC3548 Technical data

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Primary Side PWM Controller
UC1548 UC2548 UC3548
FEATURES
Primary Side Voltage Feed­forward Control of Isolated Power Supplies
Accurate DC Control of Secondary Side Short Circuit Current using Primary Side Average Current Mode Control
Accurate Programmable Maximum Duty Cycle Clamp
Maximum Volt-Second Product Clamp to Prevent Core Saturation
Practical Operation Up to 1MHz
High Current (2A Pk) Totem Pole
Output Driver
Wide Bandwidth (8MHz) Current Error Amplifier
Undervoltage Lockout Monitors VCC, VIN and VREF
Output Active Low During UVLO
BLOCK DIAGRAM
Low Startup Current (500µA)
DESCRIPTION
The UC3548 family of PWM control ICs uses voltage fee d­forward control to regulate the output voltage of isolated power supplies. The UC3548 resides on the primary side and has the necessary features to accurately control sec­ondary side short circuit current with average current mode control techniques. The UC3548 can be used to control a wide variety of converter topologies.
In addition to the basic functions required for pulse width modulation, the UC3548 implements a patented technique of sensing secondary current from the primary side in an isolated buck derived converter. A current waveform syn­thesizer monitors switch current and si m ul at es th e in du ctor current downslope so that the complete current waveform can be constructed on the primary side without actual sec­ondary side measurement. This information on the primary side is used by an average current mode control circuit to accurately limit maximum output current.
The UC3548 circuitry includes a precision reference, a wide bandwidth error amplifier for average current control, an oscillator to generate the system clock, latching PWM comparator and logic circuits, and a high current output
4/97
Pin numbers refer to 16-pin DIL and SOIC packages only .
UDG-95037
driver. The current error amplifier easily interfaces with an optoisolator from a secondary side voltage sensing circuit.
A full featured undervoltage lockout (UVLO) circuit is con­tained in the UC3548. UVLO monitors the supply voltage to the controller (VCC), the reference voltage (VREF), and the input line voltage (VIN). All three must be good before soft start commences. If either VCC or VIN is low, the sup­ply current required by the chip is only 500µA and the output is actively held low.
Two on board protection features set controlled limits to prevent transformer cor e saturation. Input voltage is moni­tored and pulse width is constrained to limit the maximum volt-second product applied to the transformer. A unique patented technique limits maximum duty cycle within 3% of a user programmed value.
These two features allow for more optimal use of trans­formers and switches, resulting in reduced system size and cost.
Both patents embodied in the UC3548 belong to Lambda Electronics Incorporated and are licensed for use in appli­cations emplo yin g th ese devices.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pin 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
Output Current, Source or Sink (Pin 14)
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A
Pulse (0.5µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A
Power Ground to Ground (Pin 1 to Pin 13) . . . . . . . . . . . ±0.2V
Analog Input Voltages
(Pins 3, 4, 7, 8, 12, 16) . . . . . . . . . . . . . . . . . . . . . -0.3 to 7V
Analog Input Currents, Sourc e or Sin k
(Pins 3, 4, 7, 8, 11, 12, 16) . . . . . . . . . . . . . . . . . . . . . . 1mA
CONNECTION DIAGRAMS
DIL-16, SOIC-16 (Top View) J, N, or DW Packages
UC1548 UC2548 UC3548
Analog Output Currents, Sourc e or Sin k (Pins 5 & 10) . . . 5mA
Power Dissipation at TA = 60°C . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperatu re Ran ge. . . . . . . . . . . . . . . −65°C to +150°C
Lead Temperature (Soldering 10 seconds) . . . . . . . . . . +300°C
Notes: All voltages are with respect to ground (DIL and SOIC
pin 1). Currents are positive into the specified terminal. Pin numbers refer to the 16 pin DIL and SO IC pa ckages. Consult Packaging Section of Databook for thermal limitations and considerations of packages.
PLCC-20 & LCC-20 (Top View) Q & L Packages
ELECTRICAL CHARACTERISTICS
55°C to +125°C for the UC1548, 40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test conditions are: VCC =
12V, CT = 400pF, CI = 100pF, IOFF = 100µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Real Time Current Waveform Synthesizer Ion Amplifier
Offset Voltage 0.95 1 1.05 V Slew Rate (Not e 1) 20 25 V/µs lib -2 -20 µA
IOFF Current Mirror
Input Voltage 0.95 1 1.05 V Current Gain 0.911.1A/A
Current Error Amplifier
A
VOL
Vio 12V VCC 20V, 0V VCM 5V 10 mV lib -0.5 -3 µA Voh I Vol I Source Current V GBW Product f = 200kHz 5 8 MHz Slew Rate (Not e 1) 810 V/µs
Oscillator
Frequency TA = 25°C 240 250 260 kHz
Unless otherwise stated, all specifications are over the junction temperature range of
60 100 dB
= 200µA 3.1 3.3 3.5 V
O
= 200µA0.30.6V
O
= 1V 1.4 1.6 2.0 mA
O
235 265 kH z
2
UC1548 UC2548 UC3548
ELECTRICAL CHARACTERISTICS (cont.):
temperature range of 55°C to +125°C for the UC1548, 40°C to +85°C for the UC2548, and 0°C to +70°C for the UC3548. Test conditions are: VCC = 12V, C T = 40 0p F, CI = 100 pF , IO F F = 10 0 µA, CDC = 100nF, Cvs = 100pF, and Ivs = 400µA, TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Duty Cycle Clamp
Max Duty Cycle V(D
VCC Comparator
Turn-on Threshold 13 14 V Turn-off Threshold 910 V Hysteresis 2.533.5V
UV Comparator
Turn-on Threshold 4.14.354.6 V R
HYSTERESIS
Reference
VREF T
Line Regulation 12V < VCC < 20V 4 15 mV Load Regulation 0 < I Short Circuit Current V
Output Stage
Rise & Fall Time (Note 1) Cl = 1nF 20 45 ns Output Low Saturation I
Output High Saturation I UVLO Output Low Saturation IO = 20mA 0.8 1.2 V
CC
I
I
START
I
(pre-start) VCC = 15V, V(UV) = 0 0.5 1 mA
CC
ICC (run) 22 26 mA
Note 1: Guaranteed by design. Not 100% tested in production.
Unless otherwise stated, all specifications are over the junction
) = 0.75 V
MAX
Vuv = 4.2V 77 90 103 k
= 25°C 4.95 5 5.05 V
A
0 < I
< 10mA, 12 < VCC < 20 4.93 5.07 V
O
< 10mA 3 15 mV
O
= 0V 30 50 70 mA
REF
= 20mA 0.25 0.4 V
O
I
= 200mA 1.2 2.2 V
O
= -200mA 2.0 3.0 V
O
VCC = 12V 0.2 0.4 mA
REF
73.5 76.5 79.5 %
PIN DESCRIPTIONS
CAO:
Output of the current error amplifier. Also the
resistor load for the collector of an optocoupler.
CDC:
Connect a charge balance integration capacitor from CDC to GND to achieve an accurate duty cycle clamp. This capacitor also sets the soft start time.
CI:
Output of t he inductor current waveform synthesizer.
Requires a capacitor to ground.
CT:
A capacitor from CT to GND sets the oscillator
frequency.
DMAX:
Programs maximum duty cycle with a resistive
divider from VREF to DMAX to GND.
GND:
Signal ground.
INV:
Inverting input of the current error amplifier.
IOFF:
Programs the discharge slope of the capacitor on CI to emulate the down slope of the inductor current waveform.
ION:
Input pin to inductor current waveform synthesizer.
Apply a voltage proportional to switch current to this pin.
NI:
Noninverting input of the current error amplifier.
OUT
: Output driver for the gate of a power FET.
PGND:
Power ground pin for the output driver. This ground circuit should be connected to GND at a single point.
UV:
Line voltage sense pin to insure the chip only operates with sufficient line voltage. Program with a resistive divide r from the conver ter input voltage to UV to GND.
VCC:
Chip supply voltage. Bypass with a 1µF ceramic
capacitor to PGND.
VREF:
Precision voltage reference. Bypass with a 1µF
ceramic capacitor to GND.
VS:
Volt second clamp programming pin and feedforward ramp waveform for the puls e wi dth m odulator. Connect a resistor to the input line voltage and a capacitor to GND.
3
UNDERVOLTAGE LOCKOUT
The under voltage lockout block diagram is shown in Fig­ure 1. The VCC comparator monitors chip supply voltage. Hysteretic thresholds are set at 13V and 10V to facilitate off-line app licatio ns. If the VCC comp arator is low, ICC is low (<500µA) and the output is low.
The UV comparator monitors input line voltage (V pair of resistors divides the input line to UV. Hysteretic in­put line th res h ol ds are programmed by Rv1 and Rv2. The thresholds are V V
(on) = 4.35V • (1 + Rv1/Rv2′) and
IN
(off) = 4.35V • (1 + Rv1/Rv2) where
IN
Rv2′ = Rv2||90k. The resulting hysteresis is V
(hys) = 4.35V • Rv1 / 90k.
IN
IN
). A
UC1548 UC2548 UC3548
When the UV comparator is low, I the output is low.
When both the UV and VCC comparators are high, the in­ternal bias circuitry for the remainder of the chip is activated. The CDC pin (see d iscu ssion on Maximum Duty Cycle Control and Soft Star t) and the Output are held low until VREF exceed s the 4.5V threshold of the VREF com­parator. When VREF is good, control of the output driver is transferred to the PWM circuitry and CDC is allowed to charge.
If any of the three UVLO comparators go low, the UVLO latch is s et, the output is held low, and CDC is discharged. This state will be maintained until all three comparators are high and the CDC pin is fully discharged.
is low (<500µA) and
CC
Figure 1:
Frequency Decrease as a Function of RT
Figure 2:
Undervoltage Lo ckout
Oscillator Frequency as a Function of CT
UDG-95039
Oscillator Frequency
2000 1000
500
100
20
RT = Open
100 1000 5000
50
500
C (pF)
UDG-95038
4
OSCILLATOR
A capacit or from the CT pin to GN D programs oscillator frequency, as shown in Figure 2. Frequency is determined by: F = 1 / (10k • CT). The sawtooth wave shape is generated by a charging cur­rent of 200µA and a discharge current of 1800µA. The discharge t ime of the sawtooth is guaranteed dead time
UC1548 UC2548 UC3548
for the output driver. If the maximum duty cycle control is defeated by connecting DMAX to VREF, the maximum duty cycle is limited by the oscillator to 90%. If an adjust­ment is required, an additional trim resistor RT from CT to ground can be us ed to ad just the os cillator frequency. RT should not b e less than 4 0kohms. This will allow up to a 22% decrease in frequency.
Figure 3:
Error Amplifier Gain and Phase Response over Frequency
INDUCTOR CURRENT WAVEFORM SYNTHESIZER
Average current mode c ontrol is a very useful technique to control the value of any current within a switching con­verter. Input current, output inductor current, switch current, diode current or almost any other c urrent can be controlled. In order to implement average current mode control, the value of th e current mu st be explicitly known at all times. To control output inductor current (IL) in a buck derived isolated converter, switch current provides inductor current information, but only during the on time of the switch. During the off time, switch current drops abruptly to zero, but the inductor current actually dimin­ishes with a slope dIL/dt = −Vo/L. This down slope must be synthesized in some manner on the primary side to provide the entire inductor current wavefor m for the con­trol circuit.
The patented current waveform synthesizer (Figure 4) consists of a unidirectional volta ge follower which forces the voltage on capacitor CI to follow the on time switch current waveform. A programmable discharge current synthesizes the off time por tion of the waveform. ION is
UDG-95040
the input to the follower. The discharge current is pro­grammed at IOFF.
The follower has a one volt offset, so that zero current corresponds to one volt at CI. The best utilization of the UC3548 is to translate maximum average inductor current to a 4 volt s ignal level. Given N and Ns (the tur ns ratio of the power and cur rent sense transforme rs respectively), proper scaling of IL to V(CI) requires a sens e resistor Rs as calculated from: Rs = 4V • Ns • N / IL(max). Restated , the maximum average inductor current will be limited to: IL(max) = 4V • Ns • N/Rs. IOFF and CI need to be chosen so that the ratio of dV(CI)/dt to dIL/dt is the sa me during switch off time as on time. Recommended nominal off current is 100µA. This requires CI = (100µA • N • Ns • L) / (Rs • Vo(nom)) where L is the output inductor value and Vo(nom) is the converter regulated output voltage.
5
INDUCTOR CURRENT WAVEFORM SYNTHESIZER (cont.)
There are several methods to program IOFF. If accurate maximum current control is required, IOFF must track out­put voltage. The method shown in Figure 4 derives a voltage proportional to VIN • D (where D = duty cycle). In a buck converter, output voltage is proportional to VIN D. A resistively loaded diode c onnection to the bootstrap winding yiel ds a squ are wave whose am plit ude is propor­tional to VIN and is duty cycle modulated by the control circuit. Averaging this waveform with a filter generates a primar y side replica of secondar y regulated Vo. A single pole filter is shown, but in practice a two or three pole filter provides better transient response. Filtered voltage is con­verted by ROFF to a cur rent to th e IOFF pin to co ntrol CI downslope.
If accurate system maximum current is not a critical re­quirement, Figure 5 shows the simplest method of downslope generation: a single resistor (ROFF = 40k) from IOFF to VR EF. The discharge current is then 100µA. The disadvantage to this approach is that the synthesizer continues to generate a down slope when the switch is off
even during short circuit conditions. Actual inductor downslope is closer to zero during a short circuit. The penalty is that the average current is understated by an amount appr oximately equal to the nominal inductor r ip-
ple current. Output short circuit is therefore higher than the designed maximum output current.
A third method of generating IOFF is to add a second winding to th e output inductor core (Figure 6). When the power switch is off an d inductor current flows in the free wheeling di ode, the voltage acro ss the inductor is equal to the outpu t voltage plus the diode drop. This voltage is then transformed by the second winding to the primary side of the converter. The advantages to this approach are its inherent accur acy and bandwi dth. Winding the sec­ond coil on the output inductor core while maintaining the required isolation makes this a more costly solution. In the example, ROFF = Vo / 100µA. The 4 • ROFF resist or is added to compensate the one volt input level of the IOFF pin. Without this compen sation, a minor current foldback behavior will be observed.
UC1548 UC2548 UC3548
Figure 5:
Figure 4:
Fixed IOFF
Inductor Current W ave form Synth esizer
UDG-95042
Figure 6:
6
Second Inductor Wi ndin g Gene ration of IO FF
UDG-95041
UDG-95043
FEED FORWARD PULSE WIDTH MODULATION
Pulse width modulation is achieved by comparing the out­put of the curre nt er ror am plifie r to the feed forward ramp generated at VS ( Figure 7). The charge slope of the ramp is deter mined by a resistor (RVS) from VS to VI N and a capacitor (CVS) from VS to GND. In the event that CAO is at its maximum voltage, typically 3.3V, the UC3548 will limit the power stage to a volt-second product of:
V
• TON(max) = 3.3V • Rvs • Cvs.
IN
An isolated voltage contro l loop can be implemented with a secondar y side reference, error amplifier and an opto­isolator. The optoisolator can be used to override the current amplifier output which is current limited by a 2.5k resistor. In overcurrent situations, the voltage loop turns the optoisolator off and the current error amplifier then as­sumes duty cycle control resulting in accurately limited maximum output current.
MAXIMUM DUTY CYCLE AND SOFT START
A patented technique is used to accurately program maxi­mum duty cycle. Programming is accomplished by a divider from VREF to DMAX (Figure 7). The value pro­grammed is: D(max) = Rd1 / (Rd1 + Rd2). For proper operation, the integrating capacitor, C should be larger than T(osc) / 80k, where T(osc) is the os­cillator period. C so values of C
also sets the soft star t time constant,
DC
larger than m inimum may be desired.
DC
DC
UC1548 UC2548 UC3548
The soft start time constant is approximately: T(ss) = 20k • C
DC
.
GROUND PLANES
The output d river on the UC35 48 is capable of 2A peak currents. Careful layout is es sential for correct operation of the chip. A ground plane must be employed (Figure 8). A unique sec tion of th e ground plane must be designated for high di/dt currents associated with the output stage. This point is the power ground to which to PGND pin is connected. Power ground can be separated from the rest of the ground plane and connected at a single point, al­though this is not str ictly necessar y if the high di/dt paths are well understood and accounted for. VCC should be bypassed direc tly to power ground with a good high fre­quency capacitor. The source of the power MOSFET should connect to power ground as should the return con­nection for input power to the system and the bulk input capacitor. The output should be clamped with a high cur ­rent Schot tky diode to both VCC and P GND. Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low ESR/ESL ceramic 1µF capacitors a re recommended for both VCC an d VREF. The capa citor s from CT, CDC, CI
,
and VS should likewise be connected to the signal ground plane.
Figure 7:
UDG-95044
Duty Cycle Control
7
UDG-95045-1
UC1548 UC2548 UC3548
UDG-95046
Figure 8:
Ground Plane Considerations
Figure 9:
UNITRODE CORPORATION 7 CONTINENTAL BLVD. MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460
Ty pi ca l Ap pl ic ati on - Voltage Feedf orw a r d Con t r o l Is ol ate d Forward Converter with Average Current Lim iti ng
UDG-95047-1
8
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