Texas Instruments UCC3946PWTR, UCC3946PW, UCC3946N, UCC3946DTR, UCC3946D Datasheet
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UCC1946
UCC2946
UCC3946
SLUS247B - FEBRUARY 2000
FEATURES
•
Fully Programmable Reset Threshold
•
Fully Programmable Reset Period
•
Fully Programmable Watchdog Period
•
2% Accurate Reset Threshold
•
VDD Can Go as Low as 2V
•
18µA Maximum IDD
•
Reset Valid Down to 1V
Microprocessor Supervisor with Watchdog Timer
6
7WDI
WP
8
VDD
3RES
5
POWER TO
CIRCUITRY
A3
A2
A1
A0
CLK
CLR
8-BIT COUNTER
400nA
WDO
1
GND
EDGE DETECT
WATCHDOG TIMING
100mV
1.235V
2RTH
4RP
1.235V .
400nA
POWER ON RESET
BLOCK DIAGRAM
Note: Pinout represents the 8-pin TSSOP package.
UDG-98001
DESCRIPTION
The UCC3946 is designed to provide accurate microprocessor supervi
sion, including reset and watchdog functions. During power up, the IC
asserts a reset signal RES
with VDD as low as 1V. The reset signal re
mains asserted until the VDD voltage rises and remains above the re
set threshold for the reset period. Both reset threshold and reset period
are programmable by the user. The IC is also resistant to glitches on
the VDD line. Once RES
has been deasserted, any drops below the
threshold voltage need to be of certain time duration and voltage mag
nitude to generate a reset signal. These values are shown in Figure 1.
An I/O line of the microprocessor may be tied to the watchdog input
(WDI) for watchdog functions. If the I/O line is not toggled within a set
watchdog period, programmable by the user, WDO
will be asserted.
The watchdog function will be disabled during reset conditions.
The UCC3946 is available in 8-pin SOIC(D), 8-pin DIP (N or J) and
8-pin TSSOP(PW) packages to optimize board space.
2
UCC1946
UCC2946
UCC3946
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, VDD = 2.1V to 5.5V for UCC1946 and UCC2946;
VDD = 2V to 5.5V for UCC3946; TA = 0°C to 70°C for UCC3946, –40°C to 95°C for UCC2946, and –55°C to 125°C for UCC1946;
T
A =TJ
PARAMETERS TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
UCC3946 UCC1946 & UCC2946
Operating Voltage 2.0 5.5 2.1 5.5 V
Supply Current 10 18 12 18 µA
Minimum VDD (Note 1) 1 1.1 V
Reset Section
Reset Threshold VDD Rising 1.210 1.235 1.260 1.170 1.235 1.260 V
Threshold Hysteresis 15 15 mV
Input Leakage 55nA
Output High Voltage I
SOURCE = 2mA VDD –
0.3
VDD –
0.3
V
Output Low Voltage I
SINK = 2mA 0.1 0.1 V
VDD = 1V, I
SINK = 20uA 0.2 0.4 V
VDD to Output Delay VDD = -1mV/µs (Note 2) 120 120 µs
Reset Period C
RP = 64nF 160 200 260 140 200 320 ms
Watchdog Section
WDI Input High 0.7·
V
DD
0.7·
V
DD
V
WDI Input Low 0.3·
VDD
0.3·
V
DD
V
Watchdog Period C
WP = 64nF 1.12 1.60 2.08 0.96 1.60 2.56 s
Watchdog Pulse Width 50 50 ns
Output High Voltage I
SOURCE = 2mA VDD –
0.3
VDD –
0.3
V
Output Low Voltage I
SINK = 2mA 0.1 0.1 V
Note 1: This is the minimum supply voltage where RES is considered valid.
Note 2: Guaranteed by design.Not 100% tested in production.
ABSOLUTE MAXIMUM RATINGS
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of the Databook for thermal limita
-
tions and considerations of packages.
WP
WDI
VDD
WDO
1
2
3
4
8
7
6
5
RTH
GND
RES
RP
SOIC-8, TSSOP-8, DIL-8 (Top View)
D, PW, N or J Package
CONNECTION DIAGRAM
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