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5
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7
8
16
15
14
13
12
11
10
9
SYNC
CT
RT
FB1
COMP1
CS1
OUT1
GND
VCC
REF
ENABLE2
FB2
COMP2
CS2
OUT2
PWRGND
N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
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10
9
SYNC
CT
RT
FB1
COMP1
CS1
OUT1
GND
VCC
REF
ENABLE2
FB2
COMP2
CS2
OUT2
PWRGND
PW PACKAGE
(TOP VIEW)
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
DUAL CHANNEL SYNCHRONIZED CURRENT-MODE PWM
FEATURES DESCRIPTION
• Single Oscillator Synchronizes Two PWMs
• 150-µA Startup Supply Current
• 2-mA Operating Supply Current
• Operation to 1 MHz
• Internal Soft-Start The oscillator’s sawtooth waveform can be used for
• Full-Cycle Fault Restart
• Internal Leading-Edge Blanking of the Current
Sense Signal
• 1-A Totem Pole Outputs
• 75-ns Typical Response from Current Sense
to Output
• 1.5% Tolerance Voltage Reference
The UCC3810 is a high-speed BiCMOS controller
integrating two synchronized pulse width modulators
for use in off-line and dc-to-dc power supplies. The
UCC3810 family provides perfect synchronization
between two PWMs by usin g the same oscillator.
slope compensation if required.
Using a toggle flip-flop to alternate between
modulators, the UCC3810 ensures that one PWM
does not slave, interfere, or otherwise affect the
other PWM. This toggle flip- flop also ensures that
each PWM is limited to 50% maximum duty cycle,
insuring adequate off-time to reset magnetic
elements. This device contains many of the same
elements of the UC3842 current mode controller
family, combined with the enhancements of the
UCC3802. This minimizes power supply parts count.
Enhancements include leading edge blanking of the
current sense signals, full cycle fault restart, CMOS
output drivers, and outputs which remain low even
when the supply voltage is removed.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2007, Texas Instruments Incorporated
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REF
15
FB115COMP15CS1
6
CS2
11
V
CC
16
Over-Current
Comparator
1.5 V
VCC OK
V
CC
2.5 V
Error
Amp 1
1 V
100 kW
55 kW
12.5 V
Leading
Edge
Blanking
Leading
Edge
Blanking
S Q
R
7
OUT1
Voltage
Ref
REF OK
S
Q
R
S
Q
R
4 V
0.5 V
τ − 5ms
Full Cycle
Soft Start
Error
Amp 2
2.5 V
+
−
55 kW
100 kW
1 V
10
OUT2
35 mA
VDG−92062−1
8
GND
9
PWRGND
14
ENABLES
S
Q
R
R
Oscillator
2
R
TCT
SYNCCOMP2FB2
3211213
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
J
–40°C to 85°C UCC2810DW (16) UCC2810N (16)
0°C to 70°C UCC3810DW (16) UCC3810N (16)
(1) All packages are available taped and reeled (indicated by the R suffix on the device type e.g.,
UCC2810JR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
CC
I
CC
Supply voltage
Supply current 20mA
Output peak current, OUT1, OUT2, 5% duty cycle ±1A
Output energy, OUT1, OUT2, capacitive load 20 µJ 20µJ
Analog inputs, FB1, FB2, CS1, CS2, SYNC –0.3 to 6.3V
T
J
T
stg
Operating junction temperature 150°C
Storage temperature range –65 to 150°C
Lead temperature (soldering, 10 sec) 300°C
(3)
PACKAGED DEVICES
SOP (DW) PDIP (N)
(1) (2)
(1)
UNIT
11V
(1) Currents are positive into, negative out of the specified terminal. All voltages are with respect to GND.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(3) In normal operation, V
impedance such that the V
is powered through a current-limiting resistor. Absolute maximum of 11 V applies when driven from a low
CC
current does not exceed 20 mA.
CC
BLOCK DIAGRAM
2
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4
OSC
T T
f
R C=´
COMP
CS
V
A
V
D
=
D
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels, –40°C ≤ TA≤ 85°C for the UCC2810, 0°C ≤ TA≤ 70°C for the UCC3810,
V
CC
REFERENCE
V
CC
I
O(SC)
OSCILLATOR
f
OSC
ERROR AMPLIFIER
V
FB
I
FB
f
GAIN
I
SINK
I
SRCE
CURRENT SENSE
I
CS
(1)
= 10 V
; RT= 150 k Ω , CT= 120 pF; no load; TA= TJ;(unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output voltage V
Load regulation 0 mA ≤ I
Line regulation
Output noise voltage
Long term stability
(2)
(2)
TJ= 25°C 4.925 5.000 5.075
TJ= full range, 0 mA ≤ I
≤ 5 mA 5 30
REF
≤ 5 mA 4.85 5.00 5.10
REF
UVLO stop threshold voltage, 12
0.5 V ≤ V
≤ V
CC
SHUNT
10Hz <f< 10 kHz, TJ= 25°C 235 µV
TA = 125°C, 1000 hours 5 mV
Output short circuit current -8 -25 mA
Oscillator frequency
Temperature stability
(3)
(2)
RT= 30 k Ω , CT= 120 pF 860 980 1100
RT= 150 k Ω , CT= 120 pF 190 220 250
Peak voltage 2.5
Valley voltage 0.05
Peak-to-peak amplitude 2.25 2.45 2.65
SYNC threshold voltage 0.80 1.65 2.20
SYNC input current SYNC = 5 V 30 µA
FB input voltage COMP = 2.5 V 2.44 2.50 2.56 V
FB input bias current ±1 µA
Open loop voltage gain 60 73 dB
Unity gain bandwidth
(2)
Sink current, COMP FB = 2.7 V, COMP = 1 V 0.3 1.4 3.5
Source current, COMP FB = 1.8 V, COMP = 4 V -0.2 -0.5 -0.8 mA
Minimum duty cycle COMP = 0 V 0%
Soft-start rise time, COMP ms
(4)
Gain
Maximum input signal
(5)
FB = 1.8 V, 5
Rise from 0.5 V to (REF – 1.5 V)
1.20 1.55 1.80 V/V
COMP = 5 V 0.9 1.0 1.1 V
Input bias current, CS ±200 nA
Propagation delay time (CS to OUT)
Blank time, CS
(6)
CS steps from 0 V to 1.2 V, 75
COMP = 2.5 V
Overcurrent threshold voltage, CS 1.35 1.55 1.85
COMP-to-CS offset voltage CS = 0 V 0.45 0.90 1.35
UCC2810
UCC3810
mV
kHz
2.5%
V
2 MHz
ns
55
V
(1) For UCC3810, adjust V
(2) Ensured by design. Not production tested.
above the start threshold before setting at 10 V.
CC
(3) Oscillator frequency is twice the output frequency.
(4) Current sense gain A is defined by:
(5) Parameter measured at trip point of latch with FB = 0 V.
, 0 V ≤ V
≤ 0.8 V.
CS
(6) CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay.
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UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
All parameters are the same for both channels, –40°C ≤ TA≤ 85°C for the UCC2810, 0°C ≤ TA≤ 70°C for the UCC3810,
V
= 10 V ; RT= 150 k Ω , CT= 120 pF; no load; TA= TJ;(unless otherwise specified)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM
Maximum duty cycle
Minimum on-time CS = 1.2 V, COMP = 5 V 130 ns
OUTPUT
V
V
t
R
t
F
Low-level output voltage I
OL
High-level output voltage (V
OH
Rise time, OUT C
Fall time, OUT C
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage 9.6 11.3 13.2
Stop threshold voltage 7.1 8.3 9.5 V
Start-to-stop hysteresis 1.7 3.0 4.7
ENABLE2 input bias current ENABLE2 = 0 V -20 -35 -55 µA
ENABLE2 input threshold voltage 0.80 1.53 2.00 V
OVERALL
Startup current V
Operating supply current, outputs off VCC = 10 V, FB = 2.75 V 2 3
Operating supply current, outputs on
VCC internal zener voltage ICC= 10 mA 11.0 12.9 14.0
VCC internal zener voltage minus start 0.4 1.2
threshold voltage
(2)
– OUT)
CC
RT= 150 k Ω , CT= 120 pF 45% 49% 50%
RT= 30 k Ω , CT= 120 pF 40% 45% 48%
I
= 20 mA 0.12 0.42
OUT
= 200 mA 0.48 1.10
OUT
I
= 20 mA, V
OUT
I
= –20 mA 0.15 0.42
OUT
I
= –200 mA 1.2 2.3
OUT
= 1 nF 20 50
OUT
= 1 nF 30 60
OUT
< Start threshold voltage 0.15 0.25
CC
= 0 V 0.7 1.2 V
CC
VCC = 10 V, FB = 0 V, 3.2 5.1
CS = 0 V, RT = 150 k Ω
VCC = 10 V, FB = 0 V, 8.5 14.5
CS = 0 V, RT = 30 k Ω
ns
mA
V
4
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UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
COMP1 5 O
COMP2 12 O
CS1 6 I Current sense inputs to the PWM comparators. These inputs have leading edge blanking. For
CS2 11 I
CT 2 O
ENABLE2 14 I
FB1 4 I
FB2 13 I
GND 8 – GND and PWRGND. GND and PWRGND must be electrically connected together. However, use
OUT1 7 O The high-current push-pull outputs of the PWM are intended to drive power MOSFET gates
OUT2 10 O
PWRGND 9 –
REF 15 O
RT 3 O
SYNC 1 I part. This pin is edge triggered with TTL thresholds, and requires at least a 10-ns-wide pulse. If
VCC 16 I output stages and the precision reference. Therefore, it is critical that VCC be directly bypassed to
I/O DESCRIPTION
Low impedance output of the error amplifiers.
most applications, no input filtering is required. Leading edge blanking disconnects the CS inputs
from all internal circuits for the first 55 ns of each PWM cycle. When used with very slow diodes or
in other applications where the current sense signal is unusually noisy, a small current-sense R-C
filter may be required.
The timing capacitor of the oscillator. Recommended values of CT are between 100 pF and 1 nF.
Connect the timing capacitor directly across CT and GND.
A logic input which disables PWM 2 when low. This input has no effect on PWM 1. This input is
internally pulled high. In most applications it can be left floating. In unusually noisy applications,
the input should be bypassed with a 1-nF ceramic capacitor. This input has TTL compatible
thresholds.
The high impedance inverting inputs of the error amplifiers.
To separate noise from the critical control circuits, this part has two different ground connections:
care to avoid coupling noise into GND.
through a small resistor. This resistor acts as both a current limiting resistor and as a damping
impedance to minimize ringing and overshoot.
To separate noise from the critical control circuits, this part has two different ground connections:
GND and PWRGND. GND and PWRGND must be electrically connected together.
The output of the 5-V reference. Bypass REF to GND with a ceramic capacitor ≥ 0.01-µF for best
performance.
The oscillator charging current is set by the value of the resistor connected from RT to GND. This
pin is regulated to 1 V, but the actual charging current is 10 V/RT. Recommended values of RT
are between 10 k Ω and 470 k Ω . For a given frequency, higher timing resistors give higher
maximum duty cycle and slightly lower overall power consumption.
This logic input can be used to synchronize the oscillator to a free running oscillator in another
unused, this pin can be grounded, open circuited, or connected to REF.
The power input to the device. This pin supplies current to all functions including the high current
PWRGND with an 0.1-µF ceramic capacitor.
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11
CC
T
V
IRD =
Power
Stage
Current
Sense
Resistor
Over−Current
Comparator
1.5 V
−
+
Soft
Start
+
−
Error
Amp
+
−
S
RRQ
From
Oscillator
Gate
Driver
PWM
Latch
PWM
Comparator
OUT
One
Shot
CS
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
APPLICATION INFORMATION
TIMING RESISTOR
Supply current decreases with increased R
For more information, see the detailed oscillator block diagram.
LEADING EDGE BLANKING AND CURRENT SENSE
Figure 1 shows how an external power stage is connected to the UCC3810. The gate of an external power
N-channel MOSFET is connected to OUT through a small current-limiting resistor. For most applications, a 10- Ω
resistor is adequate to limit peak current and also practical at damping resonances between the gate driver and
the MOSFET input reactance. Long gate lead length increases gate capacitance and mandates a higher series
gate resistor to damp the R-L-C tank formed by the lead, the MOSFET input reactance, and the device’s driver
output resistance.
The UCC3810 features internal leading edge blanking of the current-sense signal on both current sense inputs.
The blank time starts when OUT rises and continues for 55 ns. During that 55 ns period, the signal on CS is
ignored. For most PWM applications, this means that the CS input can be connected to the current-sense
resistor as shown in Figure 1 . However, high speed grounding practices and short lead lengths are still required
for good performance.
by the relationship:
T
Figure 1. Detailed Block Diagram
OSCILLATOR
The UCC3810 oscillator generates a sawtooth wave at CT. The sawtooth rise time is set by the resistor from RT
to GND. Since R
higher. The fall time is set by an internal transistor on-resistance of approximately 100 Ω . During the fall time, all
outputs are off and the maximum duty cycle is reduced to below 50%. Larger timing capacitors increase the
discharge time and reduce frequency. However, the percentage maximum duty cycle is only a function of the
timing resistor RT, and the internal 100- Ω discharge resistance.
ERROR AMPLIFIER OUTPUT STAGE
The UCC3810 error amplifiers are operational amplifiers with low-output resistance and high-input resistance.
The output stage of one error amplifier is shown in Figure 3 . This output stage allows the error amplifier output
to swing close to GND and as high as one diode drop below 5 V with little loss in amplifier performance.
6
is biased at 1 V, the current through R
T
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is 1 V/R
T
. The actual charging current is 10 times
T
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V
CC
I 10I
1 V
+
−
0.2 V
2.5 V
+
−
+
−
RSQ
One
Shot
SYNC
123
C
T
R
T
R
T
RON 9 100
5 V V
CC
COMP
APPLICATION INFORMATION (continued)
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
Figure 2. Oscillator
Figure 3. Error Amplifier Output Stage
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80
60
40
20
0
−20
1 k 10 k 100 k 1 M 10 M
0
45
90
135
Gain
Fhase
Gain − dB
Phase − °
f − Frequency − Hz
1 M
100 k
10 k
10 k 100 k 10 M
Oscillator Frequency − Hz
RT − Timing Resistor − W
1.2
1.15
1.1
1.05
1
0.95
0.9
0.85
0.8
−55 −35 −15 5 25 45 65 85 105 125
Oscillator Frequency − MHz
TA − Temperature − C
50
48
46
44
42
40
10 k 100 k 1 M
Duty Cycle − %
RT − Timing Resistor − W
UCC2810
UCC3810
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS
ERROR AMPLIFER GAIN AND PHASE OSCILLATOR FREQUENCY
OSCILLATOR FREQUENCY MAXIMUM DUTY CYCLE
vs vs
FREQUENCY TIMING RESISTANCE
Figure 4. Figure 5.
vs vs
TEMPERATURE TIMING RESISTANCE
8
Figure 6. Figure 7.
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10
8
6
4
2
10 k 100 k 1 M
Switching
Outputs Off
I
CC
− Input Current − mA
f − Frequency − Hz
50
48
46
44
42
40
10 k 100 k 1 M
CT = 120 pF
Duty Cycle − %
f − Frequency − Hz
DC
Input
OPTO1
OPTO2
TTL MONITOR
SYNC
HV SUP
ENABLE
5
4
12
13
1
14
3 2 8 9
15
11
10
6
7
16
V
CC
COMP1
FB1
COMP2
FB2
SYNC
ENABLE2
RTCTGND
PWR
GND
OUT1
CS1
OUT2
CS2
REF
0.1 mF
UCC3810
0.1
5
4
6
7
8
1
32
0.1
UC39432
COMP
REF
E/A+
SENSE
V
CC
COLL
I
SET
GND
0.1
5
4
6
7
8
1
32
UC39432
COMP
REF
E/A+
SENSE
V
CC
COLL
I
SET
GND
0.1
VDG−94022
OPTO2
High Voltage Out
(Monitor Raster)
0.1
OPTO1
+12 V OUT
+5 V OUT
SLUS162D – FEBRUARY 1999 – REVISED FEBRUARY 2007
TYPICAL CHARACTERISTICS (continued)
INPUT CURRENT MAXIMUM DUTY CYCLE
vs vs
OSCILLATOR FREQUENCY FREQUENCY
UCC2810
UCC3810
Figure 8. Figure 9.
Figure 10. Typical Application
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PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
UCC2810DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
UCC3810DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2810DWTR SOIC DW 16 2000 346.0 346.0 33.0
UCC3810DWTR SOIC DW 16 2000 346.0 346.0 33.0
Pack Materials-Page 2
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