•65ns Typical Delay From Shutdown to
Outputs, and 50ns Typical Delay From
Sync to Outputs
•Improved Current Sense Amplifier With
Reduced Noise Sensitivity
•Differential Current Sense with 3V
Common Mode Range
•Trimmed Oscillator Discharge Current
for Accurate Deadband Control
•Accurate 1V Shutdown Threshold
•High Current Dual Totem Pole Outputs
(1.5A peak)
•TTL Compatible Oscillator SYNC Pin
Thresholds
The UC3856 is a high performance version of the popular UC3846
series of current mode controllers, and is intended for both design
upgrades and new applications where speed and accuracy are important. All input to output delays have been minimized, and the current
sense output is slew rate limited to reduce noise sensitivity. Fast 1.5A
peak output stages have been added to allow rapid switching of
power FETs.
A low impedance TTL compatible sync output has been implemented
with a tri-state function when used as a sync input.
Internal chip grounding has been improved to minimize internal
“noise” caused when dr iving large capacitive loads. This, in conjunction with the improved differential current sense amplifier results in
enhanced noise immunity.
Other features include a trimmed oscillator current (8%) for accurate
frequency and dead time control; a 1V, 5% shutdown threshold; and
4kV minimum ESD protection on all pins.
UC1856
UC2856
UC3856
•4kV ESD Protection
BLOCK DIAGRAM
9/96
UDG-96176
ABSOLUTE MAXIMUM RATINGS
Supply V oltage....................................................................+40V
Oscillator Charging Current .................................................5mA
Power Dissipation at TA = 25°C (Note 2).......................1000mW
Power Dissipation at TC = 25°C (Note 2) ......................2000mW
Junction Temperature.......................................−55°C to +150°C
Storage Temperature Range............................−65°C to +150°C
Lead Temperature (Soldering, 10 sec.)...........................+300°C
All voltages are with respect to Ground.Currents are positive
into, negative out of the specified terminal.Consult packaging
section of databook for thermal limitations and considerations of
package.
UC1856
UC2856
UC3856
CONNECTION DIAGRAMS
DIL–16,SOIC-16 (Top View)
J or N,DW PACKAGE
PLCC-28 (Top View)
QP PACKAGE
PLCC-20 (Top View)
Q PACKAGE
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for
UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
PARAMETERTEST CONDITIONSMINTYP MAXMINTYPMAX UNITS
Reference Section
Output V oltageTJ = 25°C, Io = 1mA5.055.105.155.005.105.20V
Line RegulationVIN = 8V to 40V2020mV
Load RegulationIo =−1mA to −10mA1515mV
Total Output VariationLine, Load, and Temperature5.005.204.955.25V
Output Noise Voltage10Hz < f < 10kHz, TJ = 25°C5050µV
Long T erm StabilityTJ = 125°C, 1000 Hrs (Note 2)525525mV
Short Circuit CurrentVREF = 0V−25−45−65−25−45−65mA
Oscillator Section
Initial AccuracyTJ = 25°C180200220180200220kHz
Over Operating Range170230170230kHz
= 15V, RT = 10k, CT = 1nF , TA= TJ.
UC1856/UC2856UC3856
2
UC1856
UC2856
UC3856
ELECTRICAL CHARACTERISTICS (cont.)
+125°C for UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
PARAMETERTEST CONDITIONSMINTYP MAXMINTYPMAX UNITS
Oscillator Section (cont.)
Voltage StabilityVIN = 8V to 40V22%
Discharge CurrentTJ = 25°C, VCT = 2V7.58.08.87.58.08.8mA
Input Offset VoltageVCM = 2V510mV
Input Bias Current−1−1µA
Input Offset Current500500nA
Common Mode RangeVIN = 8V to 40V0VIN − 20VIN − 2V
Open Loop GainVo = 1.2V to 3V8010080100dB
Unity Gain BandwidthTJ = 25°C11.511.5MHz
CMRRVCM = 0V to 38V, VIN = 40V7510075100dB
PSRRVIN = 8V to 40V8010080100dB
Output Sink CurrentVID =−15mV, VcOMP = 1.2V510510mA
Output Source CurrentVID = 15mV, VCOMP = 2.5V−0.4−0.5−0.4−0.5mA
Output High LevelVID = 50mV, RL (COMP) = 15k4.34.64.94.34.64.9V
Output Low LevelVID =−50mV, RL (COMP) = 15k0.710.71V
Current Sense Amplifier Section
Amplifier Gain VCS−=0V, CL SS Open (Notes 3,4)2.52.753.02.52.753.0V/V
Maximum DifferentialCL SSOpen (Note 3)1.11.21.11.2V
Input Signal (VCS+− Vcs-)RL (COMP) = 15k
Input Offset VoltageV
CMRRVCM = 0V to 3V6060dB
PSRRVIN = 8V to 40V6060dB
Input Bias Current VCL SS = 0.5V, COMP Open (Note 3)−1−3−1−3µA
Input Offset CurrentVCL SS = 0.5V, COMP Open (Note 3)11mA
Input Common Mode Range0303V
Delay to OutputsV
Current Limit Adjust Section
Current Limit Offset V
Input Bias Current VEA+ =VREF, VEA−=0V−10−30−10−30µA
Shutdown T erminal Section
Threshold V oltage0.951.001.050.951.001.05V
Input V oltage Range0505V
CL SS = 0.5V535535mV
COMP Open (Note 3)
EA+ = VREF, EA−=0V120250120250ns
CS+ − CS−=0V to 1.5V
CS- = 0V0.430.50.570.430.50.57V
VCS+ = 0V, COMP = Open (Note 3)
Unless otherwise stated, these specifications apply for TA = −55°C to
= 15V, RT = 10k, CT = 1nF , TA= TJ.
UC1856/UC2856UC3856
3
UC1856
UC2856
UC3856
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to
+125°C for UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
UC1856/UC2856UC3856
PARAMETERTEST CONDITIONSMINTYP MAXMINTYPMAX UNITS
Shutdown Terminal Section (cont.)
Minimum Latching(Note 5)31.531.5mA
Current (ICL SS)
Maximum Non-Latching(Note 6)1.50.81.50.8mA
Current (ICL SS)
Delay to OutputsVSHUTDOWN = 0 to 1.3V6511065110ns
Output Section
Collector-Emitter V oltage4040V
Off-State Bias CurrentVC = 40V 250250µA
Output Low LevelIOUT = 20mA0.10.50.10.5V
IOUT = 200mA0.52.60.52.6V
Output High LevelIOUT =−20mA12.513.212.513.2V
IOUT =−200mA1213.11213.1V
Rise Time C1 = 1nF40804080ns
Fall TimeC1 = 1nF40804080ns
UVLO Low SaturationVIN = 0V, IOUT = 20mA0.81.50.81.5V
PWM Section
Maximum Duty Cycle454750454750%
Minimum Duty Cycle00%
Note 1: All voltages are with respect to GND.Currents are positive into, negative out of the specified terminal.
Note 2: This parameter, although guaranteed over the recommended operating conditions is not 100% tested in production.
Note 3: Parameter measured at trip point of latch with V
Note 4: Amplifier gain defined as:
G
∆
V
COMP
=
∆
VCS+
;
+ =VREF, V
EA
-=
0V.
∆
V
CS
−=
0V to 1.0V
EA
Note 5: Current into CL SS guaranteed to latch circuit into shutdown state.
Note 6: Current into CL SS guaranteed not to latch circuit into shutdown state.
= 15V, RT = 10k, CT = 1nF , TA= TJ.
4
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