Texas Instruments UC184, UC284, UC384 User Manual

VIN

UC2843

VCC

VREF

RT/CT

GROUND COMP

VFB

ISENSE

OUTPUT

UC1842, UC2842, UC3842, UC1843, UC2843, UC3843 UC1844, UC2844, UC3844, UC1845, UC2845, UC3845

SLUS223G – APRIL 1997 – REVISED JULY 2022

UCx84x Current-Mode PWM Controllers

1 Features

• Optimized for off-line and DC-to-DC converters

• Low start-up current (< 1 mA)

• Automatic feedforward compensation

• Pulse-by-pulse current limiting

• Enhanced load-response characteristics

• Undervoltage lockout with hysteresis

• Double-pulse suppression

• High-current totem-pole output

• Internally trimmed bandgap reference

• Up to 500-kHz operation

• Error amplifier with low output resistance

2 Applications

• Switching regulators of any polarity

• Transformer-coupled DC-DC converters

3 Description

The UCx84x series of control integrated circuits provide the features that are necessary to implement off-line or DC-to-DC fixed-frequency current-mode control schemes, with a minimum number of external components. The internally implemented circuits include an undervoltage lockout (UVLO), featuring a start-up current of less than 1 mA, and a precision reference trimmed for accuracy at the error amplifier input. Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, and a totem-pole output stage that is designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state.

The UCx84x family offers a variety of package options, temperature range options, choice of maximum duty cycle, and choice of turnon and turnoff thresholds and hysteresis ranges. Devices with higher turnon or turnoff hysteresis are ideal choices for offline power supplies, while the devices with a narrower hysteresis range are suited for DC-DC applications. The UC184x devices are specified for operation from –55°C to 125°C, the UC284x series is specified for operation from –40°C to 85°C, and the UC384x series is specified for operation from 0°C to 70°C.

Device Information

PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)

CDIP (8) 9.60 mm × 6.67 mm

UC184x

UC284x

UC384x

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

LCCC (20) 8.89 mm × 8.89 mm

CFP (8) 9.21 mm × 5.97 mm

SOIC (8) 4.90 mm × 3.91 mm

SOIC (14) 8.65 mm × 3.91 mm

PDIP (8) 9.81 mm × 6.35 mm

SOIC (8) 4.90 mm × 3.91 mm

SOIC (14) 8.65 mm × 3.91 mm

PDIP (8) 9.81 mm × 6.35 mm

CFP (8) 9.21 mm × 5.97 mm

(1)

Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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1 Features............................................................................1

2 Applications..................................................................... 1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics................................................9

8 Detailed Description...................................................... 11

8.1 Overview................................................................... 11

8.2 Functional Block Diagrams....................................... 11

8.3 Feature Description...................................................12

8.4 Device Functional Modes..........................................20

9 Application and Implementation.................................. 21

9.1 Application Information............................................. 21

9.2 Typical Application.................................................... 21

10 Power Supply Recommendations..............................34

11 Layout...........................................................................35

11.1 Layout Guidelines................................................... 35

11.2 Layout Example...................................................... 36

12 Device and Documentation Support..........................37

12.1 Receiving Notification of Documentation Updates..37

12.2 Support Resources................................................. 37

12.3 Trademarks.............................................................37

12.4 Electrostatic Discharge Caution..............................37

12.5 Glossary..................................................................37

13 Mechanical, Packaging, and Orderable

Information.................................................................... 37

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (April 2020) to Revision G (July 2022) Page

• Updated the numbering format for tables, figures and cross-references throughout the document...................1

Changes from Revision E (January 2017) to Revision F (April 2020) Page

• Changed UVLO Table updated ..........................................................................................................................7

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OUTPUT

VCC

VREF

GROUND

VFB

COMP

RT/CT

VCC

PWRGND

COMP

VFB

RT/CT

GROUND

OUTPUT

VREF

9 10 11 12 13

3 2 1 20 19

VCC

OUTPUT

VFB

RT/CT

GROUND

COMPNCVREF

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5 Device Comparison Table

UVLO

TURNON AT 16 V

TURNOFF AT 10 V

SUITABLE FOR OFF-LINE

SUITABLE FOR DC-DC

APPLICATIONS

UC1842 UC1843 –55°C to 125°C

UC3842 UC3843 0°C to 70°C

UC1844 UC1845 –55°C to 125°C

UC3844 UC3845 0°C to 70°C

6 Pin Configuration and Functions

TURNON AT 8.4 V

TURNOFF AT 7.6 V

APPLICATIONS

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SLUS223G – APRIL 1997 – REVISED JULY 2022

TEMPERATURE RANGE MAX DUTY CYCLE

Up to 100%UC2842 UC2843 –40°C to 85°C

Up to 50%UC2844 UC2845 –40°C to 85°C

Figure 6-1. D, JG, and P Packages 8-Pin SOIC,

CDIP, and PDIP Top View

Figure 6-3. FK Package 20-Pin LCCC Top View

NAME

COMP 1 1 2 O

SOIC,

CDIP,

PDIP

Product Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845

(8)

SOIC, CFP

(14)

LCCC

(20)

Figure 6-2. D and W Packages 14-Pin SOIC and

CFP Top View

Table 6-1. Pin Functions

TYPE DESCRIPTION

Error amplifier compensation pin. Connect external compensation components to this pin to modify the error amplifier output. The error amplifier is internally current-limited so the user can command zero duty cycle by externally forcing COMP to GROUND.

UC2845 UC3845

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OSC

1.72

RRT× C

OUTPUT

= Qg× fSW

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Table 6-1. Pin Functions (continued)

SOIC,

NAME

CDIP,

PDIP

(8)

GROUND 5 9 13 G

PWRGND — 8 12 G

ISENSE 3 5 7 I

NC — 2, 4, 6, 13

OUTPUT 6 10 15 O

RT/CT 4 7 10 I/O

SOIC, CFP

(14)

LCCC

(20)

1, 3, 4, 6,

8, 9, 11,

14, 16, 19

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TYPE DESCRIPTION

Analog ground. For device packages without PWRGND, GROUND functions as both power ground and analog ground.

Power ground. For device packages without PWRGND, GROUND functions as both power ground and analog ground

Primary-side current sense pin. Connect to current sensing resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage-mode control configuration.

— Do not connect

OUTPUT is the gate drive for the external MOSFET. OUTPUT is the output of the on-chip driver stage intended to directly drive a MOSFET. Peak currents of up to 1 A are sourced and sunk by this pin. OUTPUT is actively held low when VCC is below the turnon threshold.

Fixed frequency oscillator set point. Connect timing resistor, RRT, to VREF and timing capacitor, CCT, to GROUND from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device GROUND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.

The frequency of the oscillator can be estimated with the following

equations:

VC — 11 17 I

VCC 7 12 18 I

VFB 2 3 5 I

(1)

where f

use a timing resistor less than 5 kΩ. The frequency of the OUTPUT

gate drive of the UCx842 and UCx843, fSW, is equal to f

100% duty cycle; the frequency of the UCx844 and UCx845 is equal

to half of the f

Bias supply input for the output gate drive. For PWM controllers that do not have this pin, the gate driver is biased from the VCC pin. VC must have a bypass capacitor at least 10 times greater than the gate capacitance of the main switching FET used in the design.

Analog controller bias input that provides power to the device. Total VCC current is the sum of the quiescent VCC current and the average OUTPUT current. Knowing the switching frequency and the MOSFET gate charge, Qg, the average OUTPUT current can be calculated from:

is in Hertz, RRT is in Ohms and CCT is in Farads. Never

OSC

frequency at up to 50% duty cycle.

OSC

at up to

(2)

A bypass capacitor, typically 0.1 µF, connected directly to GROUND

with minimal trace length, is required on this pin. An additional

bypass capacitor at least 10 times greater than the gate capacitance

of the main switching FET used in the design is also required on

VCC.

Inverting input to the internal error amplifier. VFB is used to control the power converter voltage-feedback loop for stability.

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Table 6-1. Pin Functions (continued)

SOIC,

NAME

VREF 8 14 20 O

CDIP,

PDIP

(8)

SOIC, CFP

(14)

LCCC

(20)

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TYPE DESCRIPTION

5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the timing resistor. It is important for reference stability that VREF is bypassed to GROUND with a ceramic capacitor connected as close to the pin as possible. A minimum value of 0.1-µF ceramic is required. Additional VREF bypassing is required for external loads on VREF.

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VCC

and V

VFB

OUTPUT

COMP

OUTPUT

stg

ISENSE

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 7.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Low impedance source 30 V

< 30 mA Self Limiting

VCC

Analog input voltage –0.3 6.3 V

Input Voltage, Q and D Package only 30 V

Output drive current ±1 A

Error amplifier output sink current 10 mA

Output energy (capacitive load) 5 µJ

Junction temperature 150 °C

Storage temperature –65 150 °C

7.2 ESD Ratings

(1)

MIN MAX UNIT

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(1)

±3000

(2)

±3000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

and VVC

VCC

VFB

ISENSE

VCC

OUTPUT

VREF

OSC

(1) These recommended voltages for VC and POWER GROUND apply only to the D package.

(1)

Supply voltage 12 28 V

Input voltage 2.5 V

Input voltage 1 V

Supply current, externally limited 25 mA

Average output current 200 mA

Reference output current –20 mA

Oscillator frequency 100 500 kHz

UC184x –55 125

Operating free-air temperature

UC384x 0 70

7.4 Thermal Information

UCx84x

(1)

8 PINS 14 PINS 8 PINS 20 PINS

θJA

θJC(top)

θJB

THERMAL METRIC

Junction-to-ambient thermal resistance 104.8 78.2 53.7 — °C/W

Junction-to-case (top) thermal resistance 47.3 37.1 46.7 36.2 °C/W

Junction-to-board thermal resistance 45.9 32.6 31 35.4 °C/W

Junction-to-top characterization parameter 8.2 7.3 17.1 — °C/W

Junction-to-bottom characterization parameter 45.2 32.4 30.9 — °C/W

°CUC284x –40 85

UNITD (SOIC) D (SOIC) P (PDIP) FK (LCCC)

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7.4 Thermal Information (continued)

UCx84x

THERMAL METRIC

(1)

UNITD (SOIC) D (SOIC) P (PDIP) FK (LCCC)

8 PINS 14 PINS 8 PINS 20 PINS

θJC(bottom)

Junction-to-case (bottom) thermal resistance — — — 4.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) –55°C ≤ TA ≤ 125°C for the UC184x; –40°C ≤ TA ≤ 85°C for the UC284x, 0°C ≤ TA ≤ 70°C for the UC384x, V

VCC

from VREF to GROUND, RRT = 10 kΩ; CCT = 3.3 nF, TJ = TA.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REFERENCE SECTION

VREF

OSCILLATOR SECTION

OSC

RT/CT

ERROR AMPLIFIER SECTION

VFB

VOL

PSRR Power supply rejection ratio 12 ≤ VCC ≤ 25 V 60 70 dB

(snk)

(src)

COMP

High

COMP

CURRENT SENSE SECTION

Reference voltage I

= 1 mA, TJ = 25°C

VREF

Line regulation 12 ≤ VCC ≤ 25 V 6 20 mV

Load regulation 1 ≤ I

Temperature stability See

≤ 20 mA 6 25 mV

VREF

(1) (3)

Total output variation Line, load, temperature

Output noise voltage 10 Hz ≤ f

≤ 10 kHz,

OSC

Long term stability TA = 125°C, 1000 Hrs

Output short circuit –30 –100 –180 mA

Initial accuracy TJ = 25°C

(5)

Voltage stability 12 ≤ VCC ≤ 25 V 0.2% 1%

Temperature stability T

Amplitude Peak-to-peak

Input voltage V

≤ TA ≤ T

MIN

COMP

MAX

(1)

= 2.5 V

Input bias current

Unity gain bandwidth TJ = 25°C

COMP sink current V

COMP source current V

High-level output voltage V

Low Low-level output voltage V

2 ≤ V

VFB

≤ 4 V 65 90 dB

COMP

(1)

= 2.7 V, V

= 2.3 V, V

= 2.3 V, RL = 15-kΩ COMP to GROUND 5 6

= 2.7 V, RL = 15-kΩ COMP to VREF 0.7 1.1

(2)

= 15 V

; 0.1 µF capacitor from VCC to GROUND, 0.1 µF capacitor

UC184x and

4.95 5 5.05

UC284x

UC384x 4.9 5 5.1

UC184x

(1)

and UC284x

4.9 5.1

UC384x 4.82 5.18

(1)

TJ = 25°C 50 μV

(1)

47 52 57 kHz

(1)

UC184x and

2.45 2.5 2.55

UC284x

UC384x 2.42 2.5 2.58

UC184x and UC284x

UC384x –2

0.7 1 MHz

= 1.1 V 2 6

COMP

= 5 V –0.5 –0.8

COMP

0.2 0.4 mV/°C

5 25 mV

1.7 V

–1

µA

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VREF

max

;

F VREF

min

;

J:max

;

F T

J:min

;

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7.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted) –55°C ≤ TA ≤ 125°C for the UC184x; –40°C ≤ TA ≤ 85°C for the UC284x, 0°C ≤ TA ≤ 70°C for the UC384x, V

VCC

from VREF to GROUND, RRT = 10 kΩ; CCT = 3.3 nF, TJ = TA.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISENSE

Gain See

Maximum input signal V

PSRR Power supply rejection ratio 12 V ≤ V

ISENSE

DLY

Input bias current –2 –10 µA

Delay to output V

OUTPUT SECTION

Low Low-level OUTPUT voltage

OUT

High High-level OUTPUT voltage

OUT

RISE

FALL

Rise time

Fall time

(1)

UNDERVOLTAGE LOCKOUT (UVLO)

VCC

Enable threshold

UVLO off threshold

OFF

PWM

MAX

MIN

Maximum duty cycle

Minimum duty cycle 0%

TOTAL STANDBY CURRENT

VCC

Start-up current 0.5 1

Operating supply current V

VCC Zener voltage I

(4) (6)

(4)

= 5 V

COMP

≤ 25 V

VCC

stepped from 0 V to 2 V

ISENSE

= 20 mA 0.1 0.4

SINK

= 200 mA 1.5 2.2

SINK

= 20 mA 13 13.5

SOURCE

= 200 mA 12 13.5

SOURCE

= 1 nF, TJ = 25°C 50 150 ns

OUTPUT

= 1 nF, TJ = 25°C, 50 150 ns

OUTPUT

UC1842/4 and UC2842/4 15 16 17

UCx843/5 7.8 8.4 9

UC1842/4 and UC2842/4 9 10 11

UCx843/5 7 7.6 8.2

UCx842/3 95% 97% 100%

UC1844/5 and UC2844/5 46% 48% 50%

UC3844/5 47% 48% 50%

= V

VFB

ISENSE

= 25 mA 30 34 V

VCC

(2)

= 15 V

; 0.1 µF capacitor from VCC to GROUND, 0.1 µF capacitor

2.85 3 3.15 V/V

0.9 1 1.1 V

(1) (4)

(1)

70 dB

150 300 ns

= 0 V 11 17

VUC3842/4 14.5 16 17.5

VUC3842/4 8.5 10 11.5

(1) Specified by design. Not production tested. (2) Adjust VCC above the start threshold before setting at 15 V (3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

VREF

and VREF

min

are the maximum and minimum reference voltages measured over the

max

appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature. (4) Parameter measured at trip point of latch with VFB = 0 V. (5) OUTPUT switching frequency, fSW, equals the oscillator frequency, f

fSW, is one half oscillator frequency, f (6) Gain defined as: A = ΔV

COMP

/ΔV

, for the UCx844 and UCx845.

OSC

, 0 V ≤ V

ISENSE

≤ 0.8 V.

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, for the UCx842 and UCx843. OUTPUT switching frequency,

OSC

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Temperature (C)

DISCHARGE

(mA)

-75 -50 -25 0 25 50 75 100 125 150

7.4

7.6

7.8

8.2

8.4

8.6

8.8

9.2

D001

VO, Error Amp Output Voltage (V)

, Current Sense Input Threshold (V)

1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

D005

TA = 125qC TA = 25qC TA = 55qC

Freq (Hz)

Gain (dB)

10 100 1000 10000 100000 1000000 1E+7

-20 -100

0 -50

20 0

40 50

60 100

80 150

100 200

D003

Gain Phase

IO, Output Load Current (mA)

Source Saturation Voltage (V)

Sink Saturation Voltage (V)

0 100 200 300 400 500 600 700 800

-10 0

-9 1

-8 2

-7 3

-6 4

-5 5

-4 6

-3 7

-2 8

-1 9

0 10

D005

Source Saturation at 25 C Source Saturation at -55 C Sink Saturation at -55 C Sink Saturation at 25 C

Temperature (C)

(mA)

-75 -50 -25 0 25 50 75 100 125 150

100

120

140

160

180

D006

Source Current (mA)

Reference Voltage Delta (mV)

0 20 40 60 80 100 120 140 160

-60

-50

-40

-30

-20

-10

D007

Ta = 125 C Ta = 25 C Ta = -40 C

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7.6 Typical Characteristics

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Figure 7-1. Oscillator Discharge Current vs Temperature for

VCC = 15 V and V

OSC

= 2 V

Figure 7-3. Error Amplifier Open-Loop Gain and Phase vs

Frequency, VCC = 15 V, RL = 100 kΩ, and TA = 25 °C

Figure 7-2. Current Sense Input Threshold vs Error Amplifier

Output Voltage for VCC = 15 V

Figure 7-4. OUTPUT Saturation Voltage vs Load Current for

VCC = 15 V with 5-ms Input Pulses

Figure 7-5. VREF Short-Circuit Current vs Temperature for VCC

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= 15 V

UC2845 UC3845

Figure 7-6. VREF Voltage vs Source Current

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Temperature (C)

REF

(V)

-75 -50 -25 0 25 50 75 100 125 150

4.8

4.85

4.9

4.95

5.05

5.1

5.15

5.2

D008

Saturation Voltage (V)

Output Current (A)

0.01 0.1 1

Source, TA = 25°C

Sink, TA = 25°C

Source, TA = ±55°C

Sink, TA = ±55°C

CCT (nF)

DEADTIME

(Ps)

1 5 10 50 100

0.3

0.5

3030

D006

100

1 M

Frequency (Hz)

100 k

Timing Resistance (NŸ)

10 k

100 1000

(nF)

100 47 22 10

4.7

2.2 1

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7.6 Typical Characteristics (continued)

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Figure 7-7. VREF Voltage vs Temperature

Figure 7-9. Dead Time vs Timing Capacitance, C

Figure 7-8. Output Saturation

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Figure 7-10. Timing Resistance, RRT, vs Frequency

UC2845 UC3845

UCx842 UCx843

34 V

5-V

Reference

VREF Good

Logic

Internal

Bias

UVLO

Osc

PWM Latch

R 1 V

+ E/A

VCC

RT/CT

VFB

COMP

ISENSE

PWM

Comparator

VREF

OUTPUT

PWRGND

2.5 V

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8 Detailed Description

8.1 Overview

The UCx84x series of control integrated circuits provide the features necessary to implement AC-DC or DC-toDC fixed-frequency current-mode control schemes with a minimum number of external components. Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a start-up current of less than 1 mA, a precision reference trimmed for accuracy at the error amplifier input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control, and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off-state.

Major differences between members of these series are the UVLO thresholds, acceptable ambient temperature range, and maximum duty-cycle. Typical UVLO thresholds of 16 V (ON) and 10 V (OFF) on the UCx842 and UCx844 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds for the UCx843 and UCx845 devices are 8.4 V (ON) and 7.6 V (OFF), making them ideal for use with regulated input voltages used in DC-DC applications. The UCx842 and UCx843 devices operate to duty cycles approaching 100%. The UCx844 and UCx845 obtain a duty-cycle range of 0% to 50% by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle.

The UC184x-series devices are characterized for operation from –55°C to 125°C. UC284x-series devices are characterized for operation from −40°C to 85°C. The UC384x devices are characterized for operation from 0°C to 70°C.

8.2 Functional Block Diagrams

Figure 8-1. UCx842 and UCx843 Block Diagram, No Toggle

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34 V

5-V

Reference

VREF Good

Logic

Internal

Bias

UVLO

Osc

PWM Latch

R 1 V

+ E/A

VCC

RT/CT

VFB

COMP

ISENSE

PWM

Comparator

VREF

OUTPUT

PWRGND

UCx844 UCx845

2.5 V

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Figure 8-2. UCx844 and UCx845 Block Diagram, Toggle

8.3 Feature Description

8.3.1 Detailed Pin Description

8.3.1.1 COMP

The error amplifier in the UCx84x family is an open collector in parallel with a current source, with a unity-gain bandwidth of 1 MHz. The COMP terminal can both source and sink current. The error amplifier is internally current-limited, so that one can command zero duty cycle by externally forcing COMP to GROUND.

8.3.1.2 VFB

VFB is the inverting input of the error amplifier. VFB is used to control the power converter voltage-feedback loop for stability. For best stability, keep VFB lead length as short as possible and VFB stray capacitance as small as possible.

8.3.1.3 ISENSE

The UCx84x current sense input connects to the PWM comparator. Connect ISENSE to the MOSFET source current sense resistor. The PWM uses this signal to terminate the OUTPUT switch conduction. A voltage ramp can be applied to this pin to run the device with a voltage mode control configuration or to add slope compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be required. The gain of the current sense amplifier is typically 3 V/V.

8.3.1.4 RT/CT

RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to GROUND. For the best performance, keep the timing capacitor lead to GROUND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all other functions.

The UCx84x’s oscillator allows for operation to 500 kHz. The device uses an external resistor to set the charging current for the external capacitor, which determines the oscillator frequency. The recommended range of timing

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OSC

1.72

RRT× C

OUTPUT

= Qg× fSW

VCC:max

;

IN:min

;

F V

VCC:max

;

VCC

+ kQg× fSWo

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resistor values is between 5 kΩ and 100 kΩ; the recommended range of timing capacitor values is between 1 nF and 100 nF.

(3)

In this equation, the switching frequency, fSW is in Hz, RRT is in Ω, and CCT is in Farads.

8.3.1.5 GROUND

GROUND is the signal and power returning ground. TI recommends separating the signal return path and the high current gate driver path so that the signal is not affected by the switching current.

8.3.1.6 OUTPUT

The high-current bipolar totem-pole output of the UCx84x devices sinks or sources up to 1-A peak of current. The OUTPUT pin can directly drive a MOSFET. The OUTPUT of the UCx842 and UCx843 devices switches at the same frequency as the oscillator and can operate near 100% duty cycle. In the UCx844 and UCx845 devices, the switching frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop. This limits the maximum duty cycle in the UCx844 and UCx845 to < 50%. Schottky diodes may be necessary on the OUTPUT pin to prevent overshoot and undershoot due to high impedance to the supply rail and to ground, respectively. A bleeder resistor, placed between the gate and the source of the MOSFET, should be used to prevent activating the power switch with extraneous leakage currents during undervoltage lockout. An external clamp circuit may be necessary to prevent overvoltage stress on the MOSFET gate when VCC exceeds the gate voltage rating.

8.3.1.7 VCC

VCC is the power input connection for this device. In normal operation, power VCC through a current-limiting resistor. Although quiescent VCC current is only 0.5 mA, the total supply current is higher, depending on the OUTPUT current. Total VCC current is the sum of quiescent VCC current and the average OUTPUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUTPUT current can be calculated from Equation 4.

(4)

The UCx84x has a VCC supply voltage clamp of 34 V typical, but the absolute maximum value for VCC from a low-impedance source is 30 V. For applications that have a higher input voltage than the recommended VCC voltage, place a resistor in series with VCC to increase the source impedance. The maximum value of this resistor is calculated with Equation 5.

(5)

In Equation 5, V voltage and I

VCC

is the minimum voltage that is used to supply VCC, V

IN(min)

VCC(max)

is the maximum VCC clamp

is the IC supply current without considering the gate driver current and Qg is the external power

MOSFET gate charge and fSW is the switching frequency.

The turnon and turnoff thresholds for the UCx84x family are significantly different: 16 V and 10 V for the UCx842 and UCx844; 8.4 V and 7.6 V for the UCx843 and UCx855. To ensure against noise related problems, filter VCC with an electrolytic and bypass with a ceramic capacitor to ground. Keep the capacitors close to the IC pins.

8.3.1.8 VREF

VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The high-speed switching logic uses VREF as the logic power supply. The 5-V reference tolerance is ±2% for the UCx84x family. The output short-circuit current is 30 mA. For reference stability and to prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic capacitor close to the IC package.

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SENSE

ISENSE

GROUND

COMP

2 R

CSF

PWM Comparator

1 V

Error Amplifier

SENSE

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A minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition to the ceramic capacitor.

When VCC is greater than 1 V and less than the UVLO threshold, a 5-kΩ resistor pulls VREF to ground. VREF can be used as a logic output indicating power-system status because when VCC is lower than the UVLO threshold, VREF is held low.

8.3.2 Pulse-by-Pulse Current Limiting

Pulse-by-pulse limiting is inherent in the current mode control scheme. An upper limit on the peak current can be established by simply clamping the error voltage. Accurate current limiting allows optimization of magnetic and power semiconductor elements while ensuring reliable supply operation.

8.3.3 Current-Sense

An external series resistor, RCS, senses the current and converts this current into a voltage that becomes the input to the ISENSE pin. The ISENSE pin is the noninverting input to the PWM comparator. The ISENSE input is compared to a signal proportional to the error amplifier output voltage; the gain of the current sense amplifier is typically 3 V/V. The peak I

current is determined by Equation 6:

SENSE

(6)

The typical value for V

is 1 V. A small RC filter, R

ISENSE

CSF

and C

, may be required to suppress switch

CSF

transients caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic circuit impedances. The time constant of this filter should be considerably less than the switching period of the converter.

Figure 8-3. Current-Sense Circuit Schematic

8.3.4 Error Amplifier With Low Output Resistance

The error amplifier output is an open collector in parallel with a current source. With a low output resistance, various impedance networks may be used on the compensation pin input for error amplifier feedback. The error amplifier output, COMP, is frequently used as a control port for secondary-side regulation by using an external secondary-side adjustable voltage regulator, such as a TL431, to send an error signal across the secondary-to-primary isolation boundary through an opto-isolator, in this configuration connect the COMP pin directly to the opto-isolator feedback. On the primary side, the inverting input to the UCx48x error amplifier, VFB, should be connected to GROUND. With VFB tied to GROUND, the error amplifier output, COMP, is forced to its

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ISENSE

COMP

2 R

PWM Comparator

1 V

Error Amplifier

2.5 V

VFB

0.5 mA

s

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high state and sources current, typically 0.8 mA. The opto-isolator must overcome the source current capability to control the COMP pin below the error amplifier output high level, VOH.

For primary-side regulation, configure the inverting input to the error amplifier, VFB, with a resistor divider to provide a signal that is proportional to the converter output voltage being regulated. Add the voltage loop compensation components between VFB and COMP. The internal noninverting input to the error amplifier is trimmed to 2.5 V. For best stability, keep VFB lead length as short as possible and minimize the stray capacitance on VFB.

The internal resistor divider on COMP is maintained at an R:2R ratio, the specific values of these internal resistors should not be critical in any application.

Error amplifier can source or sink up to 0.5 mA.

Figure 8-4. Error-Amplifier Configuration Schematic

8.3.5 Undervoltage Lockout

The UCx84x devices feature undervoltage lockout protection circuits for controlled operation during power-up and power-down sequences. The UVLO circuit insures that VCC is adequate to make the UCx84x fully operational before enabling the output stage. Undervoltage lockout thresholds for the UCx842, UCx843, UCx844, and UCx845 devices are optimized for two groups of applications: off-line power supplies and DC-DC converters. The 6-V hysteresis in the UCx842 and UCx844 devices prevents VCC oscillations during power sequencing. This wider VCCON to VCC applications. The UCx843 and UCx845 controllers have a much narrower VCCON to VCC

range, make these devices ideally suited to off-line AC input

OFF

hysteresis and

OFF

may be used in DC to DC applications where the input is considered regulated.

Start-up current is less than 1 mA for efficient bootstrapping from the rectified input of an off-line converter, as illustrated by Figure 8-7. During normal circuit operation, VCC is developed from auxiliary winding NA with D and C R

START

During UVLO the IC draws less than 1 mA of supply current. Once crossing the turnon threshold the IC supply current increases to a maximum of 17 mA, typically 11 mA, During undervoltage lockout, the output driver is biased to a high impedance state and sinks minor amounts of current. A bleeder resistor, placed between the gate and the source of the MOSFET should be used to prevent activating the power switch with extraneous leakage currents during undervoltage lockout.

. At start-up, however, C

VCC

can be as large as 100 kΩ and still charge C

must be charged to 16 V through R

VCC

when VAC = 90 V RMS (low line). Power dissipation in

VCC

. With a start-up current of 1 mA,

START

would then be less than 350 mW even under high line (VAC= 130 V RMS) conditions.

BIAS

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(V)

OFF

(V)

UCx842 UCx844

UCx843 UCx845

8.4

7.6

7VCC

ON/OFF Command

to rest of device

< 1 mA

OFF

VCC

START

VCC

OUTPUT

GROUND

0.1 PF

VCC

•1mA

BIAS

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Figure 8-5. UVLO Threshold

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Figure 8-6. UVLO ON and OFF Profile

Figure 8-7. Providing Power to UCx84x

8.3.6 Oscillator

The oscillator allows for up to 500-kHz switching frequency. The OUTPUT gate drive is the same frequency as the oscillator in the UCx842 and UCx843 devices and can operate near 100% duty cycle. In the UCx844 and UCx845 devices, the frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop that blanks the output off every other clock cycle, resulting in a maximum duty cycle for these devices of < 50% of the switching frequency. An external resistor, RRT, connected from VREF to RT/CT sets the charging current for the timing capacitor, CCT, which is connected from RT/CT to GROUND. An RRT value greater than 5 kΩ is recommended on RT/CT to set the positive ramp time of the internal oscillator. Using a value of 5 kΩ or greater for RRT maintains a favorable ratio between the internal impedance and the external oscillator set resistor and results in minimal change in frequency over temperature. Using a value of less the recommended minimum value may result in frequency drift over temperature, part tolerances, or process variations.

The peak-to-peak amplitude of the oscillator waveform is 1.7 V in UCx84x devices. The UCx842 and UCx843 have a maximum duty cycle of approximately 100%, whereas the UCx844 and UCx845 are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most flyback and forward

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converters. For optimum IC performance the dead-time should not exceed 15% of the oscillator clock period. The discharge current, typically 6 mA at room temperature, sets the dead time, see Figure 7-9. During the discharge, or dead time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle D

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to:

MAX

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MAX

= 1 F:t

DEADTIME

× f

OSC

;

MAX

= 1 F

DEADTIME

OSC

VREF

RT/CT

GROUND

OSC

1.72

RRT× C

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(7)

Equation 8 applies to UCx842 and UCx843 units because the OUTPUT switches at the same frequency as the

oscillator and the maximum duty cycle can be as high as 100%.

(8)

Equation 8 applies to UCx844 and UCx845 units because the OUTPUT switches at half the frequency as the

oscillator and the maximum duty cycle can be as high as 50%.

When the power transistor turns off, a noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles, the voltage at RT/CT is approaching its threshold level (approximately 2.7 V, established by the internal oscillator circuit) when this spike occurs. A spike of sufficient amplitude prematurely trips the oscillator. To minimize the noise spike, choose CCT as large as possible, remembering that dead time increases with CCT. It is recommended that CCT never be less than approximately 1000 pF. Often the noise which causes this problem is caused by the OUTPUT being pulled below ground at turnoff by external parasitics. This is particularly true when driving MOSFETs. A Schottky diode clamp from GROUND to OUTPUT prevents such output noise from feeding to the oscillator.

For RRT > 5 kΩ:

8.3.7 Synchronization

The simplest method to force synchronization uses the timing capacitor, CCT, in near standard configuration. Rather than bring CCT to ground directly, a small resistor is placed in series with CCT to ground. This resistor serves as the input for the sync pulse which raises the CCT voltage above the oscillator’s internal upper threshold. The PWM is allowed to run at the frequency set by RRT and CCT until the sync pulse appears. This scheme offers several advantages including having the local ramp available for slope compensation. The UC3842/3/4/5 oscillator must be set to a lower frequency than the sync pulse stream, typically 20% with a 0.5-V pulse applied across the resistor.

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Figure 8-8. Oscillator Section Schematic

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VREF

RT/CT

GROUND

24 O

SYNC

VREF

ISENSE

30 O

500 O

1 kO

To Current

Sense Resistor

COMP

SHUTDOWN

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Figure 8-9. Synchronizing the Oscillator

8.3.8 Shutdown Technique

The PWM controller (see Figure 8-10) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (see Figure 8-10). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.

Figure 8-10. Shutdown Techniques

8.3.9 Slope Compensation

A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 8-11). Note that capacitor C filter with R

to suppress the leading-edge switch spikes.

CSF

forms a

CSF

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+ 40 hidden pages

Texas Instruments UC184, UC284, UC384 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Device Comparison Table

6 Pin Configuration and Functions

7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 Typical Characteristics

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagrams

8.3 Feature Description

8.3.1 Detailed Pin Description

8.3.1.1 COMP

8.3.1.2 VFB

8.3.1.3 ISENSE

8.3.1.4 RT/CT

8.3.1.5 GROUND

8.3.1.6 OUTPUT

8.3.1.7 VCC

8.3.1.8 VREF

8.3.2 Pulse-by-Pulse Current Limiting

8.3.3 Current-Sense

8.3.4 Error Amplifier With Low Output Resistance

8.3.5 Undervoltage Lockout

8.3.6 Oscillator

8.3.7 Synchronization

8.3.8 Shutdown Technique

8.3.9 Slope Compensation