Texas Instruments TNETE2004PAC, TNETE2004PGJ, TNETE2004PBE Datasheet

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Single-Chip Multi-PHY Solution: – Four 10BASE-T Physical-Layer (PHY)

Interfaces in One Package Minimizing PCB Footprint for Internetworking Applications

Each PHY is Half-Duplex and Full-Duplex Compliant – Full-Duplex: Independent Transmit and

Receive Channels for Operation at 20-Mbit/s Aggregate

Compliant With IEEE Std 802.3 10BASE-T Specification

Management Data Input/Output (MDIO) Serial Compliant With IEEE Std 802.3 Media-Independent Interface (MII)

Integrated Filters on Both Receive and Transmit Circuits – No External Filters Are Required – Meets IEEE Std 802.3 (Section 14.3)

Electrical Requirements

Implements IEEE Std 802.3u Auto-Negotiation to Establish the Highest Common Protocol

DSP-Based Digital Phase-Locked Loop (PLL)

Interrupt Feature on MDIO

Loopback Mode for Test Operations

Integrated Manchester Encoding/Decoding

Receive-Clock Regeneration for All Input Channels

Smart Squelch

Transmit Pulse Shaping

Collision Detection

Jabber Detection

Link-Pulse Detection

Auto-Polarity Control

Simple Connection for LED Status Indicators

Sufficient Current Drive to Directly Connect LED Status Indicators

CMOS Technology Enables Low Power Consumption

Power-Down Mode

IEEE Std 1149.1 (JTAG)† Test-Access Port (TAP)

Each Serial Network Interface (SNI) Signal Is User Programmable

Package Options Include 120-Pin Plastic Quad Flat Package (PBE) and 128-Pin Plastic Quad Flat Package (PAC)

description

The TNETE2004 QuadPHY interface device is a single-chip, multi-PHY (four 10BASE-T devices), high-performance solution for designers of 10BASE-T networking systems. The highly integrated TNETE2004 includes a user-programmable SNI signal for each PHY . Each PHY interface on the device provides Manchester encoding/decoding of data via unshielded twisted-pair (UTP) balanced cable through simple isolation transformers requiring no external filtering. Additional TNETE2004 features are smart squelch, jabber detection, auto-polarity correction, transmission wave shaping, and anti-alias filtering capabilities. Each PHY interface on the TNETE2004 is individually addressable within the TNETE2004 via the MDIO.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

†

IEEE Std 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

PHY Status and Control Signals

PHY Data I/O

IEEE 1149.1

Std

Test-Access

Port

LED Drivers

MDIO and

TNETE2004 Control

Logic

PHY 3

PHY 2

PHY 1

PHY 0

To/From 10BASE-T Network

TNETE2004 Control Signals

Manufacturing Test Data

To LED

Status

Indicators

Figure 1. TNETE2004 Architecture

The TNETE2004 provides PHY -interface functions for up to four 10BASE-T half- or full-duplex ports as shown in Figure 1. The TNETE2004 contains four independent 10BASE-T transceivers in a single chip. Each transceiver is compliant with IEEE Std 802.3, Section 14, and a compliant management serial-interface port provides information for network management.

A typical application with external components is shown in Figure 2.

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RGND0

FILMAG 23Z128,

23Z356 or equiv.

RJ45C

TGND0

23Z356 or equiv.

FILMAG 23Z128,

RGND1

TGND0

RJ45C

23Z356 or equiv.

FILMAG 23Z128,

RGND2

TGND0

RJ45C

23Z356 or equiv.

FILMAG 23Z128,

RGND3

TGND0

RJ45C

RCVN0

RCVP0 XMTN0

XMTP0

RCVN1

RCVP1 XMTN1

XMTP1

RCVN2

RCVP2 XMTN2

XMTP2

RCVN3

RCVP3 XMTN3

XMTP3

27 pF

20 MHz

TXEN(0–3) TXD(0–3) RXCLK(0–3)

DUPLEX(0–3) LINK(0–3) CRS(0–3) COL(0–3)

W–4 W–4

W–4 W–4 W–4 W–4 W–4 W–4

5 V

HF70AC8453215

TNETE2004

10 µF

0.1 µF

27 pF

0.1 µF

MDCLK MDIO

AUTONEG LOOPBACK RESET

SQE

TVDD(0-3)

RVDD(0-3)

TGND(0-3) RGND(0-3) LGND

AGND

XTAL1 XTAL2

XGND

IREF

LGND LGND LGND

50 Ω

180 Ω

25 Ω

TXCLK

W–4

TNETX3150

System

Controller

RXD(0–3)

10 kΩ

TNETX15VEPGE/ TNETX15AEPGE/ TNETX315AL

10 kΩ

CMODE0 CMODE1

5 V

10 µF

0.1 µF

GND

AGND

100 pF

Figure 2. External Components for the TNETE2004

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pin assignments

TNETE2004 power supplies are identified according to the section of the device they supply . All power supplies are labeled VDD or VSS, and each has a single-letter prefix indicating which circuit of the device they supply. L indicates a supply for control logic, R is for receiver circuits, T is for transmitter circuits, and A is for analog circuits. Each PHY-specific signal has a suffix, which is the number of the PHY, for example, carrier sense (CRS0), CRS1, and so on. If a signal name does not include a suffix, it is applicable to all PHYs.

RXCLK0

CRS0 RXD0

LINK0

DUPLEX0

LGND TGND0 XMTN0 XMTP0

DD0

RCVN0 RCVP0

RGND0

RESET

LOOPBACK

TGND1 XMTN1 XMTP1

DD1

RCVN1 RCVP1

RGND1

LGND

DUPLEX1

LINK1

RXD1 CRS1 LV

RXCLK3 CRS3 RXD3 LINK3 DUPLEX3 LGND RGND3 RCVP3 RCVN3 RV

DD3

XMTP3 XMTN3 TGND3 SQE AUTONEG RGND2 RCVP2 RCVN2 RV

DD2

XMTP2 XMTN2 TGND2 LGND DUPLEX2 LINK2 RXD2 CRS2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62

TXD0

TXEN0

COL0

LED3DUPCOL

LGND

LED3ACTIVE

LED3LINK

LED2DUPCOL

LED2ACTIVE

LED2LINK

LED1ACTIVE

LED1LINK

LED0DUPCOL

LED0ACTIVE

LGND

LED0LINK

TXCLK

MDIO

MDCLK

DEVSEL4

LGND

DEVSEL3

COL3

TXEN3

TXD3

RXCLK1

TXD1

TXEN1

COL1

TCK

TDI

TRST

TMS

IREF

ATEST

CMODE1

XTAL2

PWRDWN

RES1

COL2

TXEN2

TXD2

RXCLK2

LGND

CMODE0

PBE PACKAGE

(TOP VIEW)

LED1DUPCOL

DEVSEL2

TDO

XTAL1

LGND

AGND

LGND

XGND

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TXD0

RXCLK0

CRS0 RXD0

LINK0

DUPLEX0

LGND TGND0 TGND0 XMTN0

XMTP0 TV

DD0

RCVN0

RCVP0

RGND0

RESET

LOOPBACK

TGND1 TGND1 XMTN1

XMTP1 TV

DD1

RCVN1

RCVP1

RGND1

LGND

DUPLEX1

LINK1

RXD1 CRS1 LV

RXCLK1

TXEN3 TXD3 LV

RXCLK3 CRS3 RXD3 LINK3 DUPLEX3 LGND RGND3 RCVP3 RCVN3 RV

DD3

XMTP3 XMTN3 TGND3 TGND3 SQE AUTONEG RGND2 RCVP2 RCVN2 RV

DD2

XMTP2 XMTN2 TGND2 TGND2 LGND DUPLEX2 LINK2 RXD2 CRS2 LV

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

90 89

88 87

86 85

84 83 82 81 80 79

78 77 76 75

74 73

72 71 70 69 68 67 66

COL0

LED3DUPCOL

LGND

LED3ACTIVE

LED3LINK

LED2DUPCOL

LED2ACTIVE

LED2LINK

LED1ACTIVE

LED1LINK

LED0DUPCOL

LED0ACTIVE

LGND

LED0LINK

TXCLK

MDIO

MDCLK

DEVSEL4

LGND

DEVSEL3

COL3

RXCLK2

TXEN1

COL1

LGND

TCK

TDO

TRST

IREF

ATEST

CMODE1

XTAL2

PWRDWN

RES1

COL2

TXEN2

TXD2

LGND

CMODE0

PAC PACKAGE

(TOP VIEW)

LED1DUPCOL

DEVSEL2

TMS

XTAL1

TDI

AGND

LGND

XGND

TXEN0

121

122

123

124

125

126

127

128

TXD1

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

controller interface

TERMINAL

NO.

I/O

†

DESCRIPTION

NAME

120 128

AUTONEG 74 82 I

Auto-negotiation. When high, AUTONEG enables auto-negotiation on all four PHYs. Auto-negotiation takes place only after a reset or when a link is reestablished. AUTONEG can be overridden from the MDI.

COL0 COL1 COL2 COL3

117

34 56 93

127

40 62

103

Collision sense. When asserted, COL0–COL3 indicates that PHY0–PHY3 sensed a network collision. The active level is set by the compatibility pins (see T able 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.

CRS0 CRS1 CRS2 CRS3

2 29 61 88

4 35 67 98

Carrier sense. When asserted, CRS0–CRS3 indicates that PHY0–PHY3 is receiving a frame carrier signal. The active level is set by the compatibility pins (see T able 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.

DUPLEX0 DUPLEX1 DUPLEX2 DUPLEX3

5 26 64 85

7 32 70 95

O/D

Duplex mode. When DUPLEX0–DUPLEX3 is high, PHY0–PHY3 operates in full-duplex mode. When DUPLEX0–DUPLEX3 is low, PHY0–PHY3 operates in the half-duplex mode. There is an internal weak drive on DUPLEX0–DUPLEX3 that pulls DUPLEX0–DUPLEX3 if auto-negotiation chooses the full-duplex mode, or if full duplex is chosen by writing to an MDI register. By connecting DUPLEX0–DUPLEX3 GND or VDD, this weak drive is overridden, and the type of duplex mode is permanently set, ignoring any auto-negotiation decisions or values written to the appropriate MDI registers. To set duplex mode, connect the auto-negotiation pin low. (This turns off auto-negotiation.)

LINK0 LINK1 LINK2 LINK3

4 27 63 86

6 33 69 96

Link status. When LINK0–LINK3 is high, it indicates that PHY0–PHY3 has determined that a valid 10BASE-T link has been established. When low, LINK0–LINK3 indicates that the link has not been established.

LOOPBACK 16 20 I

Loopback. When low, LOOPBACK enables internal loopback in all four PHYs. When asserted, data is internally wrapped within each PHY and does not appear on the network. While in the looped-back state, all network lines are placed in a noncontentious state. LOOPBACK

can be

overridden by the MDI registers.

RXCLK0 RXCLK1 RXCLK2 RXCLK3

1 31 59 89

3 37 65 99

Receive clock. Receive clock source for the receive data output RXD0–RXD3. Data is valid on RXD0–RXD3 on the edges of RXCLK0–RXCLK3 specified by the currently set compatibility mode (see T able 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in T able 13.

RXD0 RXD1 RXD2 RXD3

3 28 62 87

5 34 68 97

O Receive data. Bit-wise serial-data output from PHY0–PHY3.

SQE 75 83 I

Signal quality error. When high, SQE causes each PHY to simulate a collision condition at the end of each frame transmission to test functionality of the collision-detect circuitry. SQE is overridden by SQEEN (see T able 8). SQE must be set high to interface with the TNETX3150.

TXCLK 101 111 O

Transmit clock. TXCLK is shared by all PHYs to clock in transmit data. Data is valid on TXD0-TDX3 on the edges of TXCLK specified by the currently set compatibility mode (see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.

TXD0 TXD1 TXD2 TXD3

119

32 58 91

1 38 64

101

I Transmit data. Serial-data input to PHY0–PHY3.

TXEN0 TXEN1 TXEN2 TXEN3

118

33 57 92

128

39 63

102

Transmit enable. Assert TXEN0–TXEN3 active to indicate that valid transmit data is on TXD0–TXD3. The active level is set by the compatibility pins (see T able 2) or by setting the correct pins in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.

†

I = input, O = output, O/D = open-drain output

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

miscellaneous interface

TERMINAL

NO.

TYPE

†

DESCRIPTION

NAME

120 128

ATEST 44 50 A

Analog test pin. ATEST provides access to the filter of the reference PLL. When operating correctly , ATEST presents a voltage between 1–2 V.

CMODE0 CMODE1

47 48

53 54

Compatibility mode. Eases compatibility with third-party media-access controllers (MACs) (see Table 2).

DEVSEL2 DEVSEL3 DEVSEL4

95 96 98

105 106 108

Device select. DEVSEL2–DEVSEL4 specifies the three most-significant bits of a 5-bit number used to address a PHY on the management-data interface. The two least-significant bits are set as 00, 01, 10, and 11 for PHY0–PHY3, respectively.

IREF 43 49 A

Current reference. Used to set a current reference for the analog circuitry. IREF must be connected

to ground by a 180 ± 5-Ω resistor. MDCLK 99 109 I Management-data clock. MDCLK is used to clock data in and out of the MDIO port. MDIO 100 110 I/O Management-data I/O. MDIO is the serial management-data interface.

PWRDWN 54 60 I

Power down. When asserted, PWRDWN places all four PHYs in the lower power state.

Transmitting and receiving are inhibited in this state. RES1 55 61 O Reserved RESET 15 19 I Global reset. RESET is used to reset all four PHY sections.

XTAL1 50 56 A

Crystal oscillator pins. Connect a 20-MHz crystal across XTAL1 and GND, or drive XTAL1 from a 20-MHz crystal-oscillator module.

XTAL2 51 57 A

Connect a 27-pF capacitor across XTAL2 and XT AL1 and connect a 27-pF capacitor between XT AL2 and GND. If a crystal-oscillator module is used, do not connect anything to XTAL2.

†

A = analog, I = input, O = output, I/O = 3-state input/output

JTAG interface

TERMINAL

NO.

I/O

‡

DESCRIPTION

NAME

120 128

TCK 36 42 I

Test clock. TCK is used to clock state information and test data into and out of the device during

operation of the JTAG.

TDI 37 43 I

Test data input. TDI is used to serially shift test data and test instructions into the device during

operation of the JTAG.

TDO 38 44 O

T est data output. TDO is used to serially shift test data and test instructions out of the device during

operation of the JTAG.

TMS 40 46 I Test mode select. TMS controls the operating state of the JTAG. TRST 39 45 I Test reset. TRST is used for asynchronous reset of the JT AG controller.

‡

I = input, O = output

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

LED interface

TERMINAL

NO.

I/O

†

DESCRIPTION

NAME

120 128

LED0ACTIVE LED1ACTIVE LED2ACTIVE LED3ACTIVE

105 108 111 114

115

118 121 124

LED activity indicator. The LED activity indicator is driven low for 20 ms when PHY0–PHY3 receives or transmits. LED0ACTIVE–LED3ACTIVE can sink a 10-mA current. If it receives or transmits another packet during that 20 ms, the LED does not flash, but stays on. Therefore, if packets are received or transmitted at intervals faster than 20 ms, the LED stays on continuously.

LED0DUPCOL LED1DUPCOL LED2DUPCOL LED3DUPCOL

106 109 112 116

116 119 122 126

LED duplex/collision indicator for PHY0–PHY3. This LED status pin has different meaning when in full- or half-duplex mode. In full-duplex mode, LED0DUPCOL–LED3DUPCOL is continuously driven low. In half-duplex mode, it is driven low for 20 ms after a collision. LED0DUPCOL–LED3DUPCOL can sink a 10-mA current.

LED0LINK LED1LINK LED2LINK LED3LINK

103 107 110 113

113 117 120 123

LED link indicator. The LED link indicator is driven low when PHY0–PHY3 has established a valid link. LED0LINK–LED3LINK can sink a 10-mA current.

†

O = output

10BASE-T interface

TERMINAL

NO.

TYPE

‡

DESCRIPTION

NAME

120 128

XMTN0 XMTN1 XMTN2 XMTN3

8 18 67 77

11 23 74 86

XMTP0 XMTP1 XMTP2 XMTP3

9 19 68 78

12 24 75 87

Transmit pair. Differential line-transmitter outputs from PHY0–PHY3

RCVN0 RCVN1 RCVN2 RCVN3

12 22 71 81

16 28 79 91

Receive pair for PHY0–PHY3. Differential line-receiver inputs connect to receive pair through

RCVP0 RCVP1 RCVP2 RCVP3

13 23 72 82

17 29 80 92

transformer isolation.

‡

A = analog

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

power interface

TERMINAL

NO.

TYPE

†

DESCRIPTION

NAME

120 128

AGND 45 51 GND Ground pin for analog circuitry AV

42 48 PWR VDD pin for analog circuitry

6, 25 8, 31

6, 25

35, 46

8, 31

41, 52

LGND

65, 84,71, 94

GND

Logic ground pin

94, 97,104, 107

104, 115 114, 125

30, 41 53, 60

90, 102

120

36, 47 59, 66

100, 112

PWR Logic VDD pin

RGND0

RGND1

142418

RGND2 73 81

GND

Ground pin for receiver circuitr

y RGND3 83 93 RV

DD0

DD1

DD2

DD3

11 21 70 80

15 27 78 90

PWR VDD pin for receiver circuitry

TGND0 TGND1

9, 10

21, 22

TGND2 TGND3

66 76

72, 73 84, 85

GND

Ground pin for transmit circuitr

DD0

102013, 14

25, 26

DD1

DD2

76, 77

PWR

pin for transmit circuitr

DD2

DD3

79 88, 89 XGND 49 55 GND Ground pin for crystal-oscillator circuitry XV

52 58 PWR VDD pin for crystal-oscillator circuitry

†

GND = ground, PWR = power

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Receiver

RCVP

RCVN

Digital

PLL

Decoder

Manchester

RXD

Clock

Generator

Watchdog

Timer

Line

Driver

D-to-A

Converter

Manchester

Encoder

Generator

Collision

CRS

RXCLK

JABBER

XMTP

XMTN

COL

TXCLK

TXEN

DUPLEX

SQE

AUTONEG

LINK

Remote Fault

TXD

Carrier Sense

Smart

Squelch

Elastic

Buffer

Disable

Link Fail

LOOPBACK

Link-Pulse

Detector

Auto-

Negotiation

Wave-

Shaping

Filter

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description

The TNETE2004 consists of four PHYs, with each PHY having several logical blocks (see the functional block diagram and Table 1).

Table 1. Logical Blocks

LOGICAL BLOCKS FUNCTION

Transmitter function Accepts data from the data terminal equipment (DTE) and transmits it onto the network Receiver function Receives data from the network and sends it to the DTE Collision/signal-quality error detection Indicates to the DTE any collision on the network/transmitter with valid link Jabber detection Indicates to the DTE if a packet transmission exceeds 20-ms minimum Auto-negotiation Negotiate to establish the highest common protocol Management-data interface To allow register-based management operations for each PHY module Link test A link pulse is sent to indicate a valid connection. LED status indicator Indication for link, activity, and collision Test port IEEE Std 1149.1 test-access port and boundary-scan testing

Loopback test mode

Loopback capabilities are provided to allow certain tests to be performed to validate operation of the TNETE2004.

Compatibility modes Ease connection to third-party MACs

10BASE-T differential line-transmitter function

Each differential line driver of the TNETE2004 drives a balanced, properly terminated twisted-pair transmission line with a characteristic impedance of 85 Ω to 111 Ω (see Figure 2). In the idle state, the driver maintains a minimum differential output voltage, while staying within the required common-mode voltage range.

The driver incorporates an on-chip wave-shaping stage and a high-frequency filtering stage to allow the outputs to be connected directly to isolation transformers through serial termination resistors. No external filters are required.

Serial data for transmission by a PHY is presented to the appropriate transmit data (TXD) input of the TNETE2004. To be valid, data must be synchronized on the appropriate edges of the transmit clock (TXCLK) signal, which depends on the compatibility-mode setting.

Once the transmit-enable (TXEN) pin is deasserted for a PHY, the driver maintains full differential outputs for a minimum of 250 ns, which then begins to decay to minimum differential levels.

The PHY also transmits regular link pulses in compliance with IEEE Std 802.3.

10BASE-T differential line-receiver function

The line-receiver pins of each PHY must be connected to a properly terminated transmission line by an external isolation transformer. The receiver establishes its own common-mode input-bias voltage. Data received from the network is output on RXD of the appropriate PHY and synchronized by the appropriate edges of the corresponding RXCLK signal, which depends on the compatibility-mode setting.

The receiver incorporates a squelch function to pass incoming data. This smart squelch function passes data only if the input amplitude is greater than a minimum signal threshold and if a specific pulse sequence is received. This protects input data from impulse line noise being mistaken for signal or link activity . The squelch circuits quickly deactivate if received pulses exceed the specifications; thus, overly long pulses are not mistaken as link pulses.

Carrier sense (CRS) is driven high while the squelch function is active to indicate that the circuit is allowing data to pass from the twisted pair. CRS is driven low when the squelch circuit is disabling data low.

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

collision/signal-quality error detection

When not in full-duplex mode, collisions are detected by sensing simultaneous activity on both the transmit and the receive pins. A collision detection is signified by COL on the respective PHY being driven high for the duration of the condition and for a specified time afterwards.

The TNETE2004 device also provides a signal-quality error (SQE) function. This function can be enabled or disabled only for the whole device and not for individual PHYs. When SQE is enabled, following transmission, a simulated collision is presented to a PHY. PHY tests as much of the collision-detect circuitry as possible without affecting the attached twisted-pair channels. Each PHY asserts its COL output signal high for a defined time interval relative to the last positive data edge of its transmit data input. SQE is invoked by driving SQE high or by using the TNETE2004 registers.

jabber detection

Each PHY monitors the length of the packet being transmitted. If a single packet exceeds 20 ms, a jabber condition is detected. The output is disabled, and CRS is driven low. The TNETE2004 device asserts COL, while attempts are made to transmit data, and signals link-fail for the duration of the attempts. The device also asserts COL (for half-duplex mode only) when it has detected that the transmitter has entered jabber mode. To clear the jabber function, transmission must cease for a minimum of 500 ms.

auto-negotiation

Each PHY on the device is capable of auto-negotiation as defined in IEEE Std 802.3. When enabled, this feature allows a PHY to negotiate with another PHY on the link to establish their highest common protocol. Until a PHY has completed its negotiation, it cannot assert LINK.

The only two protocols possible for the TNETE2004 are half- or full-duplex 10BASE-T. When auto-negotiation indicates that full-duplex operation is possible, a weak pullup resistor is applied to DUPLEX on the device, allowing full-duplex operation, unless the pin is pulled low externally.

link-partner register

This register contains the information for the link partner. Refer to Table 6 for the link partner’s ability-register bit functions.

expansion register

Refer to Table 7 for the bit definition on the expansion register.

next_page transmit

After exchanging the base page, which contains the information to make connection automatically , if both ends of the link indicate support for the next_page function, additional data can be exchanged. This allows extensions to the standard and proprietary extensions to exist without affecting interoperability . Refer to Figure 11 for the next_page transmit register.

management-data interface

The TNETE2004 incorporates a management-data interface to allow register-based management operations for each PHY module. Operation of the TNETE2004 is possible without use of the management-data interface, since all the signals necessary for complete functionality are accessible by way of the device pins; however, some additional features are accessible only through the management-data interface.

interrupt enable cycle

The TNETE2004 can generate interrupts via the MDIO interface after the quiescent cycle. The quiescent cycle is the cycle following the data transfer in which neither the external MAC nor the PHYs drive MDIO. The TNETE2004 indicates to the host that an interrupt is pending by driving MDIO low. This happens one clock cycle after the quiescent cycle, while MDCLK is high. When MDCLK goes low, TNETE2004 stops driving MDIO so the host can determine what caused the interrupt.

TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

link test

When not in auto-negotiation mode, the PHY sends link pulses, separated by an interval of 16 ms, on the data-out (DO) circuit. The receiver looks for valid link pulses on the input pair. If a link pulse is not received within a given time interval, the device enters a link-fail state. In this state, link pulses continue to be generated, and the receiver constantly looks for the link-pulse pattern. The device remains in this state until a valid receive packet or multiple legal link-test pulses are received.

loopback test mode

By asserting the LOOPBACK pin on the device or by setting the LOOPBACK bit in the PHY generic control register, the transmit circuit of each PHY is looped to the corresponding receive circuit closest to the twisted-pair I/O pins. Thereafter, transmit drivers do not forward any further packet data but continue to send link-test pulses.

When accessing loopback test mode from the package pins, since there is only one LOOPBACK pin on the package, all four PHYs are placed in LOOPBACK mode simultaneously. Individual PHYs can be placed in LOOPBACK mode by means of the TNETE2004 registers. While in LOOPBACK mode, all receive activities, other than link-test pulses, are ignored. However, squelch information is still processed, allowing the link status to be maintained under momentary loopback self-test.

LED status indication

The TNETE2004 has 12 pins that drive LEDs. Each PHY has the following three status LEDs: Note: The LEDs are all off when reset is active. Once reset is inactive, all the LEDs turn on for 100ms, then turn

off, and then function in the normal way. The following signals are active low. LEDxLINK – illuminates when PHYx has established a valid link LEDxACTIVE – illuminates when PHYx is transmitting or receiving data. This LED illuminates for a minimum

duration of 20 ms for each activity , but if packets are being received or transmitted faster than 20 ms, it stays on continuously.

LEDxDUPCOL – illuminates continuously when PHYx is in full-duplex mode. Illuminates for a minimum

duration of 20 ms when collisions occur in half-duplex mode. Additionally, in half-duplex mode, LED0DUPCOL–LED3DUPCOL flashes when a jabber condition is detected. This feature is not available in full-duplex mode.

IEEE Std 1149.1 (JTAG) test port

Compliant with the IEEE Std 1 149.1, the test-access port is composed of five pins. These pins interface serially with the device and the board on which the device is installed for boundary-scan testing. The TNETE2004 implements the following JTAG instructions:

000 EXTEST External boundary-scan test 001 SAMPLE/PRELOAD Initialization for boundary-scan test 100 IDCODE Scans out TNETE2004 identification code 101 HIGHZ Sets all digital output pins on the TNETE2004 to high impedance 111 BYPASS Connects 1-bit bypass register between TDI and TDO

TNETE2004 MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

autopolarity

The TNETE2004 can sense and detect reversed polarity of its receiver inputs (e.g., due to incorrect cable wiring). If, at any time, seven consecutive inverted link pulses are detected, then reversed polarity is assumed and flagged by the POLOK bit in the TNETE2004_sts register (see Table 9). If automatic polarity correction is selected by the SWAPPOLEN bit in the TNETE2004_ctl register (see T able 8), the TNETE2004 swaps its RCVP and RCVN input for the affected PHY. Once a single correct link pulse is received, good polarity is assumed, and the POLOK bit is set.

Automatic polarity correction is enabled by default after power on or reset. The polarity detect circuit must see link pulses to detect the polarity of the receive pair, so, in instances of high network activity where link pulses are sparse, there may be a slight delay before the correct polarity is established.

compatibility modes

T o ease connection to third-party MACs, the TNETE2004 provides options to reverse the polarity of some device pins. The compatibility mode is selected by the CMODE0 and CMODE1 pins, as defined in Table 2. The TNETE2004 can be programmed through the MDIO to change the polarity of each SNI (like COL or RXCLK, etc.) signal. Refer to Table 13 for more details on this function.

Table 2. Compatibility Mode Options

CMODE PIN SIGNIFICANCE

Mode 1:

CMODE0 = Low CMODE1 = Low

CRS high to indicate carrier detected COL high to indicate collision TXEN high to indicate valid data on TXD Data on RXD valid on rising edge of RXCLK Data on TXD valid on rising edge of TXCLK RXD high when no data is being received RXCLK is continuously running.

Mode 2:

CMODE0 = High CMODE1 = Low

CRS low to indicate carrier detected COL low to indicate collision TXEN low to indicate valid data on TXD Data on RXD valid on falling edge of RXCLK Data on TXD valid on falling edge of TXCLK RXD high when no data is being received RXCLK runs for seven clocks after CRS is high, then it stays high.

Mode 3:

CMODE0 = Low CMODE1 = High

CRS high to indicate carrier detected COL low to indicate collision TXEN high to indicate valid data on TXD Data on RXD valid on falling edge of RXCLK Data on TXD valid on falling edge of TXCLK RXD low when no data is being received RXCLK runs for seven clocks after CRS is low, then it stays high.

Mode 4:

CMODE0 = High CMODE1 = High

CRS high to indicate carrier detected COL high to indicate collision TXEN high to indicate valid data on TXD Data on RXD valid on rising edge of RXCLK Data on TXD valid on rising edge of TXCLK RXD low when no data is being received RXCLK is continuously running.

+ 32 hidden pages

Texas Instruments TNETE2004PAC, TNETE2004PGJ, TNETE2004PBE Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual