Texas Instruments TMS320F243PGEA, TMS320F243PGE, TMS320F241PGS, TMS320F241PGA, TMS320F241PG Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

D

High-Performance Static CMOS Technology

D

Includes the T320C2xx Core CPU
– Object-Compatible With the TMS320C2xx
– Source-Code-Compatible With

TMS320C25
– Upwardly Compatible With TMS320C5x
– 50-ns Instruction Cycle Time

D

Commercial and Industrial Temperature
Available

D

Memory
– 544 Words x 16 Bits of On-Chip

Data/Program Dual-Access RAM

(DARAM)
– 8K Words x 16 Bits of Flash EEPROM
– 224K Words x 16 Bits of Total Memory

Address Reach (’F243 only)

D

External Memory Interface (’F243 only)

D

Event-Manager Module
– Eight Compare/Pulse-Width Modulation

(PWM) Channels
– Two 16-Bit General-Purpose Timers With

Six Modes, Including Continuous Upand

Up/Down Counting
– Three 16-Bit Full Compare Units With

Deadband
– Three Capture Units (Two With

Quadrature Encoder-Pulse Interface

Capability)

D

Single 10-Bit Analog-to-Digital Converter
(ADC) Module With 8 Multiplexed Input
Channels

D

Controller Area Network (CAN) Module

D

26 Individually Programmable, Multiplexed
General-Purpose I/O (GPIO) Pins

D

Six Dedicated GPIO Pins (’F243 only)

D

Phase-Locked-Loop (PLL)-Based Clock
Module

D

Watchdog (WD) Timer Module

D

Serial Communications Interface (SCI)
Module

D

16-Bit Serial Peripheral Interface (SPI)
Module

D

Five External Interrupts (Power Drive
Protection, Reset, NMI, and Two Maskable
Interrupts)

D

Three Power-Down Modes for Low-Power
Operation

D

Scan-Based Emulation

D

Development Tools Available:
– Texas Instruments (TI) ANSI C

Compiler, Assembler/Linker, and
C-Source Debugger

– Full Range of Emulation Products

– Self-Emulation (XDS510)

– Third-Party Digital Motor Control and

Fuzzy-Logic Development Support

D

144-Pin QFP PGE Package (’F243)

D

68-Pin PLCC FN Package (’F241)

D

64-Pin QFP PG Package (’F241)

description

The TMS320F243 and TMS320F241 devices are members of the ’24x family of digital signal processor (DSP)
controllers based on the TMS320C2xx generation of 16-bit fixed-point DSPs. The ’F243 is a superset of the
’F241. These two devices share similar core and peripherals with some exceptions. For example, the ’F241
does not have an external memory interface. This new family is optimized for digital motor / motion control
applications. The DSP controllers combine the enhanced TMS320 architectural design of the ’C2xx core CPU
for low-cost, high-performance processing capabilities and several advanced peripherals optimized for
motor /motion control applications. These peripherals include the event manager module, which provides
general-purpose timers and PWM registers to generate PWM outputs, and a single,10-bit analog-to-digital
converter (ADC), which can perform conversion within 1 µs.

Copyright  1999, Texas Instruments Incorporated

TI and XDS510 are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Table of Contents

Description 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Features 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGE Package, 144-Pin QFP, ’F243 4. . . . . . . . . . . . . . . .

FN Package, 68-Pin PLCC, ’F241 5. . . . . . . . . . . . . . . . .

PG Package, 64-Pin QFP, ’F241 6. . . . . . . . . . . . . . . . . . .

Terminal Functions - ’F243 PGE Package 7. . . . . . . . . . .

Terminal Functions - ’F241 PG and FN Packages 14. . .

Functional Block Diagram 17. . . . . . . . . . . . . . . . . . . . . . .

Architectural Overview 18. . . . . . . . . . . . . . . . . . . . . . . . . .

System-Level Functions 18. . . . . . . . . . . . . . . . . . . . . . . . .

Device Memory Maps 18. . . . . . . . . . . . . . . . . . . . . . . . . .

Memory Maps 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripheral Memory Map 21. . . . . . . . . . . . . . . . . . . . . . . .

Software-Controlled Wait-State Generator 22. . . . . . . .

Digital I/O and Shared Pin Functions 23. . . . . . . . . . . . .

Digital I/O Control Registers 26. . . . . . . . . . . . . . . . . . . .

Device Reset and Interrupts 26. . . . . . . . . . . . . . . . . . . .

Clock Generation 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Low-Power Modes 34. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Block Diagram

of the ’24x DSP CPU 37. . . .

’24x Legend for the Internal Hardware 38. . . . . . . . . . .

’F243/’F241 DSP Core CPU 39. . . . . . . . . . . . . . . . . . . . .

Internal Memory 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peripherals 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Memory Interface (’F243 only) 45. . . . . . . . . .

Wait-State Generation (’F243 only) 46. . . . . . . . . . . . . .

Event-Manager (EV2) Module 47. . . . . . . . . . . . . . . . . .

Analog-to-Digital Converter (ADC) Module 50. . . . . . . .

A/D Overview 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Peripheral Interface (SPI) Module 52. . . . . . . . . .

Serial Communications Interface (SCI) Module 54. . . .

Controller Area Network (CAN) Module 56. . . . . . . . . .

Watchdog (WD) Timer Module 60. . . . . . . . . . . . . . . . . .

Scan-Based Emulation 62. . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320x24x Instruction Set 62. . . . . . . . . . . . . . . . . . . . .

Addressing Modes 62. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Repeat Feature 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Instruction Set Summary 63. . . . . . . . . . . . . . . . . . . . . . .

Development Support 69. . . . . . . . . . . . . . . . . . . . . . . . . . .

Nomenclature 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Documentation Support 72. . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 73. . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 73. . . . . . . . . . . . .

Electrical Characteristics 73. . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 74. . . . . . . . . . . . . .

Signal Transition Levels 74. . . . . . . . . . . . . . . . . . . . . . . .

Timing Parameter Symbology 75. . . . . . . . . . . . . . . . . . .

General Notes on Timing Parameters 75. . . . . . . . . . . .

Clock Characteristics and Timings 76. . . . . . . . . . . . . . . .

Clock Options 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ext Reference Crystal/Clock w/PLL Circuit Enabled 77

Low-Power Mode Timings 78. . . . . . . . . . . . . . . . . . . . . .

RS

Timings 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XF, BIO

, and MP/MC Timings 80. . . . . . . . . . . . . . . . . . .

Timing Event Manager Interface 81. . . . . . . . . . . . . . . . . .

PWM Timings 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Capture and QEP Timings 82. . . . . . . . . . . . . . . . . . . . . .

Interrupt Timings 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General-Purpose Input/Output Timings 84. . . . . . . . . . .

SPI Master Mode Timing Parameters 85. . . . . . . . . . . . .

SPI Slave Mode Timing Parameters 89. . . . . . . . . . . . . . .

External Memory Interface Read Timings 93. . . . . . . . . .

External Memory Interface Write Timings 95. . . . . . . . . .

External Memory Interface Ready-on-Read 97. . . . . . . .

External Memory Interface Ready-on-Write 98. . . . . . . .

10-Bit Dual Analog-to-Digital Converter (ADC) 99. . . . . .

ADC Operating Frequency 99. . . . . . . . . . . . . . . . . . . . .

ADC Input Pin Circuit 100. . . . . . . . . . . . . . . . . . . . . . . . .

Internal ADC Module Timings 101. . . . . . . . . . . . . . . . . .

Flash EEPROM 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming Operation 102. . . . . . . . . . . . . . . . . . . . . . .

Erase Operation 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flash-Write Operation 102. . . . . . . . . . . . . . . . . . . . . . . .

Register File Compilation 103. . . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

device features

Table 1 and Table 2 provide a comparison of the features of the ’F243 and ’F241. See the functional block
diagram for ’24x peripherals and memory.

Table 1. Hardware Features of the TMS320x24x DSP Controllers

ON-CHIP MEMORY (WORDS)

RAM

POWER CYCLE

TMS320x24x

DEVICES

DATA SPACE

CONFIGURABLE

DATA/ PROG SPACE

EXTERNAL

MEMORY

INTERFA

C

E

POWER

SUPPLY

(V)

CYCLE

TIME

(ns)

(B1 RAM - 256 WORDS)

(B2 RAM - 32 WORDS)

(B0 RAM)

INTERFACE

TMS320F243

√

TMS320F241

288

256–5

50

Table 2. Device Specifications of the TMS320x24x DSP Controllers

ON-CHIP MEMORY (WORDS)

TMS320x24x

DEVICES

ROM

FLASH

EEPROM

ADC

CHANNELS

PERIPHERALS

GPIO

PACKAGE

TYPE

PROG PROG CAN SPI

PIN COUNT

TMS320F243 – 8K 8 √ √ 32

PGE

144-PQFP

TMS320F241 – 8K 8 √ √ 26

FN 68-PLCC
PG 64-PQFP

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

V

SSO

PS

V

DDO

IS

A0
A1
PWM1/IOPA6
A2
PWM2/IOPA7
A3
PWM3/IOPB0
DNC
PWM4/IOPB1
A4
PWM5/IOPB2
A5
A6
PWM6/IOPB3
A7
PDPINT
A8
TCLKIN/IOPB7
A9
TDIR/IOPB6
A10
XINT1/IOPA2
A11
XINT2/ADCSOC/IOPD1
A12
NMI
A13
V

CCP

/WDDIS
A14
V

DDO

A15
V

SSO

NC

NC
ADCIN04
ADCIN03

NC
ADCIN02

NC
ADCIN01

NC
ADCIN00

NC

DNC

NC

V

SSO

V

SSO

V

SS

V

DD
ENA_144

RS

IOPD2
IOPD3

TCK

IOPD4

TDI

IOPD5

TDO

IOPD6

TMS

IOPD7

TRST

VIS_CLK

V

SS
D0

V

DDO

D1

V

SSO

ADCIN0ADCIN05

144

143

142

141NC140

139NC138

137NC136

135

134NC133

132

131

T1PWM/T1CMP/IOPB4

130

129

128

127

VIS_OE

126

125

124

CAP1/QEP0/IOPA3

123

STRB

122

CAP2/QEP1/IOPA4

121BR120

CAP3/IOPA5

119RD118

117

CLKOUT/IOPD0

116

CANTX/IOPC6

115

R/W

114

CANRX/IOPC7

113

112

373839404142434445464748495051525354555657585960616263646566676869

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

D2

XTAL1/CLKIN

XTAL2

MP/MC

READY

EMU0

D3

EMU1/OFF

D4

XF/IOPC0

SCIRXD/IOPA1

D9

SPISIMO/IOPC2

D10

SPISOMI/IOPC3

D11

SPICLK/IOPC4

D12

SPISTE/IOPC5

D13

D14

BIO/IOPC1

111 V

110

V

109

707172

D15

D7

WE

D6

D5

D8

PMT

DD

SSO

DDO

PGE PACKAGE

†

(TOP VIEW)

NC

T2PWM/T2CMP/IOPB5

SCITXD/IOPA0

SSO

V

VSSV

SSO

V

DS

DDO

V

SSO

V

SS

V

DD

V

SSO

V

DDO

V

ADCIN06

ADCIN07

CCA

V

SSA

V

NC

SSO

V

SSO

V

SSO

V

TMS320F243

(144-Pin QFP)

V

REFLOVREFHI

†

NC = No connection, DNC = Do not connect

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

V

DD

28 29 30 31 32 33 34

TCLKIN/IOPB7

TDIR/IOPB6

PWM1/IOPA6

PDPINT

35 36 37 38 3927

XINT1/IOPA2

XINT2/ADCSOC/IOPD1

40 41 42 43

87654321686766659 64636261

FN PACKAGE

†

(TOP VIEW)

NMI

TCK

TDI

ADCIN03

RS

TDO

TMS

ADCIN04

TRST

ADCIN02

NC

10
11
12
13
14

17
18
19
20
21
22
23
24
25
26

15
16

CANRX/IOPC7
CANTX/IOPC6

CLKOUT/IOPD0

CAP3/IOPA5

ADCIN07

V

REFHI

V

REFLO

ADCIN06
ADCIN05

60
59
58
57
56

53
52
51
50
49
48
47
46
45
44

55
54

PMT
SPISTE/IOPC5
SPICLK/IOPC4
SPISOMI/IOPC3
SPISIMO/IOPC2

BIO

/IOPC1

V

DD

V

SS

XF/IOPC0
EMU1
EMU0
XTAL2

V

DDO

SCIRXD/IOPA1
SCITXD/IOPA0

V

DDO

V

SSO

T2CMP/T2PWM/IOPB5
T1CMP/T1PWM/IOPB4

V

SS

V

CCA

V

SSA

V

SSO

V

SS

V

DDO

V

SSO

V

SSO

XTAL1/CLKIN

V

SSO

V

DDO

V

CCP

/WDDIS

CAP2/QEP1/IOPA4
CAP1/QEP0/IOPA3

TMS320F241

(68-Pin PLCC)

PWM2/IOPA7

PWM3/IOPB0

PWM4/IOPB1

PWM5/IOPB2

PWM6/IOPB3

ADCIN01

ADCIN00

DNC

†

NC = No connection, DNC = Do not connect

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

V

CCP

/WDDIS

NMI

XINT2/ADCSOC/IOPD1

XINT1/IOPA2

TDIR/IOPB6

TCLKIN/IOPB7

PDPINT
PWM6/IOPB3
PWM5/IOPB2
PWM4/IOPB1
PWM3/IOPB0

PWM2/IOPA7
PWM1/IOPA6

TRST
TMS
TDO
TDI
TCK
RS
V

SSO

DNC
ADCIN00
ADCIN01
ADCIN02
ADCIN03
ADCIN04

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

51 50 49 4847 46 45 44 43 42 41 40 39 3837 36 35 34 33

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19

PMT

SPISTE/IOPC5

SPICLK/IOPC4

SPISOMI/IOPC3

SPISIMO/IOPC2

SCIRXD/IOPA1

SCITXD/IOPA0

BIO/IOPC1

XF/IOPC0

EMU1

EMU0

XTAL2

XTAL1/CLKIN

CANRX/IOPC7

CANTX/IOPC6

CLKOUT/IOPD0

CAP3/IOPA5

CAP2/QEP1/IOPA4

CAP1/QEP0/IOPA3

T2CMP/T2PWM/IOPB5

T1CMP/T1PWM/IOPB4

ADCIN07

ADCIN06

PG PACKAGE

†

(TOP VIEW)

TMS320F241
(64-Pin QFP)

V

SSO

V

DDO

VSSV

DD

V

SSO

V

DDO

†

NC = No connection, DNC = Do not connect

VDDV

SS

V

SSA

V

CCA

V

DDO

V

SSO

V

REFHI

ADCIN05

V

REFLO

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS

ADCIN00 10
ADCIN01 8
ADCIN02 6
ADCIN03 4

p

ADCIN04 3

IIAnalog inputs to the ADC

ADCIN05 144
ADCIN06 143
ADCIN07 139

V

CCA

137 – –

Analog supply voltage for ADC (5 V). V

CCA

must be isolated from

digital supply voltage.

V

SSA

135 – – Analog ground reference for ADC

V

REFHI

141 – – ADC analog high-voltage reference input

V

REFLO

142 – – ADC analog low-voltage reference input

EVENT MANAGER

T1PWM/T1CMP/

IOPB4

130 I/O/Z I

Timer 1 compare output/general-purpose bidirectional digital I/O
(GPIO).

T2PWM/T2CMP/

IOPB5

128 I/O/Z I Timer 2 compare output/GPIO

TDIR/

IOPB6

85 I/O I

Counting direction for general-purpose (GP) timer/GPIO. If TDIR=1,
upward counting is selected. If TDIR=0, downward counting is
selected.

TCLKIN/

IOPB7

87 I/O I

External clock input for GP timer/GPIO. Note that timer can also use
the internal device clock.

CAP1/QEP0/

IOPA3

123 I/O I Capture input #1/quadrature encoder pulse input #0/GPIO

CAP2/QEP1/

IOPA4

121 I/O I Capture input #2/quadrature encoder pulse input #1/GPIO

CAP3/

IOPA5

119 I/O I Capture input #3/GPIO

PWM1/

IOPA6

102 I/O/Z I Compare/PWM output pin #1 or GPIO

PWM2/

IOPA7

100 I/O/Z I Compare/PWM output pin #2 or GPIO

PWM3/

IOPB0

98 I/O/Z I Compare/PWM output pin #3 or GPIO

PWM4/

IOPB1

96 I/O/Z I Compare/PWM output pin #4 or GPIO

PWM5/

IOPB2

94 I/O/Z I Compare/PWM output pin #5 or GPIO

PWM6/

IOPB3

91 I/O/Z I Compare/PWM output pin #6 or GPIO

PDPINT

§

89 I I

Power drive protection interrupt input. This interrupt, when activated,
puts the PWM output pins in the high-impedance state should motor
drive/power converter abnormalities, such as overvoltage or
overcurrent, etc., arise. PDPINT

is a falling-edge-sensitive interrupt.
After the falling edge, this pin must be held low for two clock cycles
for the core to recognize the interrupt.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS

SPISIMO/

IOPC2

60 I/O I SPI slave in, master out or GPIO

SPISOMI/

IOPC3

62 I/O I SPI slave out, master in or GPIO

SPICLK/

IOPC4

64 I/O I SPI clock or GPIO

SPISTE/

IOPC5

66 I/O I SPI slave transmit enable (optional) or GPIO

SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS

SCITXD/

IOPA0

56 I/O I SCI asynchronous serial port transmit data or GPIO

SCIRXD/

IOPA1

58 I/O I SCI asynchronous serial port receive data or GPIO

CONTROLLER AREA NETWORK (CAN)

CANTX/

IOPC6

115 I/O I CAN transmit data or GPIO

CANRX/

IOPC7

113 I/O I CAN receive data or GPIO

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS

RS 19 I/O I

Device reset. RS causes the ’F243/241 to terminate execution and sets
PC = 0. When RS

is brought to a high level, execution begins at location

zero of program memory. RS

affects (or sets to zero) various registers
and status bits. When the watchdog timer overflows, it initiates a system
reset pulse that is reflected on the RS

pin. This pulse is eight clock cycles

wide.

NMI

§

79 I I

Nonmaskable interrupt. When NMI is activated, the device is interrupted
regardless of the state of the INTM bit of the status register. NMI

is
(falling) edge- and low-level-sensitive. T o be recognized by the core, this
pin must be kept low for at least one clock cycle after the falling edge.

XINT1/

IOPA2

83 I/O I

External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge­sensitive. To be recognized by the core, these pins must be kept
high/low for at least one clock cycle after the edge. The edge polarity is
programmable.

XINT2/ADCSOC/

IOPD1

81 I/O I

External user interrupt 2. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be
recognized by the core, these pins must be kept high/low for at least one
clock cycle after the edge. The edge polarity is programmable.

MP/MC 43 I I

Microprocessor/Microcomputer mode select. If this pin is low during
reset, the device is put in microcomputer mode and program execution
begins at 0000h of internal program memory (flash EEPROM). A high
value during reset puts the device in microprocessor mode and program
execution begins at 0000h of external program memory.

READY 44 I I

READY is pulled low to add wait states for external accesses. READY
indicates that an external device is prepared for a bus transaction to be
completed. If the device is not ready, it pulls the READY pin low. The
processor waits one cycle and checks READY again. Note that the
processor performs READY -detection if at least one software wait state
is programmed. To meet the external READY timings, the wait-state
generator control register (WSGR) should be programmed for at least
one wait state.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED)

I/O, data, and program space strobe select signals. IS, DS, and PS are always high

ISDS105

110

O/Z 1

unless low-level asserted for access to the relevant external memory space or I/O.

p

-

p

p

PS 107

They are laced in the high-im edance state during reset, ower down, and when

EMU1/OFF is active low.

WE 112 O/Z 1

Write enable strobe. The falling edge of WE indicates that the device is driving the
external data bus (D15–D0). WE

is active on all external program, data, and I/O

writes. WE

goes in the high-impedance state when EMU1/OFF is active low.

RD 118 O 1

Read enable strobe. Read-select indicates an active, external read cycle. RD is
active on all external program, data, and I/O reads. RD

goes into the

high-impedance state when EMU1/OFF

is active low.

R/W 114 O/Z 1

Read/write signal. R/W indicates transfer direction during communication to an
external device. It is normally in read mode (high), unless low level is asserted for
performing a write operation. It is placed in the high-impedance state when
EMU1/OFF

is active low and during power down.

STRB 122 O/Z 1

External memory access strobe. STRB is always high unless asserted low to
indicate an external bus cycle. STRB

is active for all off-chip accesses. It is placed

in the high-impedance state during power down, and when EMU1/OFF

is active

low.

BR 120 O/Z 1

Bus request, global memory strobe. BR is asserted during access of
external global data memory space. BR

can be used to extend the data memory

address space by up to 32K words. BR

goes in the high-impedance state during

reset, power down, and when EMU1/OFF

is active low.

VIS_CLK 31 O 0

Visibility clock. Same as CLKOUT, but timing is aligned for external buses in
visibility mode.

ENA_144 18 I I

Active high to enable external interface signals. If pulled low, the ’F243 behaves like
an ’F241—i.e., it has no external memory and generates an illegal address if any
of the three external spaces are accessed (IS

, DS, PS asserted). This pin has an

internal pulldown.

VIS_OE 126 O 0

This pin is active (low) whenever the external databus is driving as an output during
visibility mode. Can be used by external decode logic to prevent data bus
contention while running in visibility mode.

XF

/IOPC0 49 I/O O – 1

External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction.
This pin is configured as an external flag output by all device resets. It can be used
as a GPIO, if not used as XF.

BIO

/IOPC1 55 I/O I

Branch control input. BIO is polled by the BCND pma,BIO instruction. If BIO is low,
a branch is executed. If BIO

is not used, it should be pulled high. This pin is
configured as a branch control input by all device resets. It can be used as a GPIO,
if not used as a branch control input.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS (CONTINUED)

PMT 68 I I Enables parallel module test (PMT). Do not connect, reserved for test.

V

CCP

/WDDIS 77 I I

Flash programming voltage pin and watchdog disable. This is the 5-V supply used
for flash programming. Flash cannot be programmed if this pin is held at 0 V . This
pin also works as a hardware watchdog disable, when V

CCP

/WDDIS = +5 V and

bit 6 in WDCR is set to 1.

DEDICATED I/O SIGNALS

IOPD2 20 I/O Dedicated GPIO – Port D bit 2
IOPD3 21 I/O Dedicated GPIO – Port D bit 3
IOPD4 23 I/O

Dedicated GPIO – Port D bit 4

IOPD5 25 I/O

I

Dedicated GPIO – Port D bit 5
IOPD6 27 I/O Dedicated GPIO – Port D bit 6
IOPD7 29 I/O Dedicated GPIO – Port D bit 7

DATA AND ADDRESS BUS SIGNALS

D0 33
D1 35
D2 38
D3 46
D4 48
D5 50
D6 52
D7 54
D8 57

I/O/Z

O¶Bit

x of

the 16-bit Data Bus

D9 59
D10 61
D11 63
D12 65
D13 67
D14 69
D15 71

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

11

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

DATA AND ADDRESS BUS SIGNALS (CONTINUED)

A0 104
A1 103
A2 101
A3 99
A4 95
A5 93
A6 92
A7 90
A8 88

O0Bit

x of

the 16-bit Address Bus

A9 86
A10 84
A11 82
A12 80
A13 78
A14 76
A15 74

CLOCK SIGNALS

XTAL1/CLKIN 41 I I

PLL oscillator input pin. Crystal input to PLL/clock source input to PLL.
XTAL1/CLKIN is tied to one side of a reference crystal.

XTAL2 42 O O

Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference
crystal. This pin goes in the high-impedance state when EMU1/OFF

is active low.

CLKOUT

/IOPD0 116 I/O O

Clock output. This pin outputs either the CPU clock (CLKOUT) or the watchdog
clock (WDCLK). The selection is made by the CLKSRC bit
(bit 14) of the System Control and Status Register (SCSR). This pin can be used
as a GPIO if not used as a clock output pin.

TEST SIGNALS

TCK 22 I I JTAG test clock with internal pullup
TDI 24 I I

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.

TDO 26 I/O I

JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.

TMS 28 I I

JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

TEST SIGNALS (CONTINUED)

TRST 30 I I

JTAG test reset with internal pulldown. TRST, when driven high, gives
the scan system control of the operations of the device. If this signal is
not connected or driven low, the device operates in its functional mode,
and the test reset signals are ignored.

EMU0 45 I/O I

Emulator I/O pin 0 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through the JTAG scan.

EMU1/OFF 47 I/O I

Emulator I/O pin 1 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through JTAG scan.

SUPPLY SIGNALS

14
15

36

37
40

70

V

SSO

73

– – Digital logic and buffer ground reference
108
111
117
124

129

131

34
39
72

pp

V

DDO

75

– –

Digital logic and buffer suppl

y v

oltage

106
109

17

V

DD

53

– – Digital logic supply voltage
125

16
32

V

SS

51

– –

Digital logic ground reference

127

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

13

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package (Continued)

NAME

144

QFP

TYPE

†

RESET

‡

DESCRIPTION

NO.

STATE

‡

NO CONNECTS

12

DNC

97

– –

Do not connect. Reserved for test

.

1
2
5
7
9

11

p

NC

13

– –

No internal connection made to this pin

132
133
134
136
138
140

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶

Data is in output mode when AVIS is enabled. At reset, the device comes up with A VIS mode enabled. The data bus is in output mo de while A VIS
is enabled.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F241 PG and FN Packages

NAME

64

QFP68PLCC

TYPE

†

RESET

‡

DESCRIPTION

NO. NO.

STATE

‡

INTERFACE CONTROL SIGNALS

V

CCP

/WDDIS 52 63 I I

Flash programming voltage supply pin. This is the 5-V supply used for
flash programming. Flash cannot be programmed if this pin is held at 0 V .
This pin also works as a hardware watchdog disable, when V

CCP

/WDDIS
= +5 V and bit 6 in WDCR is set to 1. Note that on ROM devices, only the
WDDIS function is valid.

ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS

ADCIN00 24 32
ADCIN01 23 31
ADCIN02 22 30
ADCIN03 21 29

p

ADCIN04 20 28

IIAnalog inputs to the ADC

ADCIN05 19 26
ADCIN06 18 25
ADCIN07 15 22

V

CCA

14 21 – –

Analog supply voltage for ADC (5 V). V

CCA

must be isolated from digital

supply voltage.

V

SSA

13 20 – – Analog ground reference for ADC

V

REFHI

16 23 – – ADC analog high-voltage reference input

V

REFLO

17 24 – – ADC analog low-voltage reference input

EVENT MANAGER

T1CMP/T1PWM/

IOPB4

12 19 I/O/Z T imer 1 compare output/general-purpose bidirectional digital I/O (GPIO).

T2CMP/T2PWM/

IOPB5

11 18 I/O/Z Timer 2 compare output/GPIO

TDIR/

IOPB6

56 67 I/O

Counting direction for GP timer/GPIO. If TDIR=1, upward counting is
selected. If TDIR=0, downward counting is selected.

TCLKIN/

IOPB7

57 68 I/O

External clock input for GP timer/GPIO. Note that timer can also use the
internal device clock.

CAP1/QEP0/

IOPA3

8 15 I/O Capture input #1/quadrature encoder pulse input #0/GPIO

CAP2/QEP1/

IOPA4

7 14 I/O

I

Capture input #2/quadrature encoder pulse input #1/GPIO

CAP3/

IOPA5

6 13 I/O

I

Capture input #3/GPIO

PWM1/

IOPA6

64 7 I/O/Z Compare/PWM output pin #1 or GPIO

PWM2/

IOPA7

63 6 I/O/Z Compare/PWM output pin #2 or GPIO

PWM3/

IOPB0

62 5 I/O/Z Compare/PWM output pin #3 or GPIO

PWM4/

IOPB1

61 4 I/O/Z Compare/PWM output pin #4 or GPIO

PWM5/

IOPB2

60 3 I/O/Z Compare/PWM output pin #5 or GPIO

PWM6/IOPB3 59 2 I/O/Z Compare/PWM output pin #6 or GPIO

PDPINT

§

58 1 I I

Power drive protection interrupt input. This interrupt, when activated, puts
the PWM output pins in the high-impedance state, should motor
drive/power converter abnormalities, such as overvoltage or overcurrent,
etc., arise. PDPINT

is a falling-edge-sensitive interrupt. After the falling
edge, this pin must be held low for two clock cycles for the core to
recognize the interrupt.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

15

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F241 PG and FN Packages (Continued)

NAME

64

QFP68PLCC

TYPE

†

RESET

‡

DESCRIPTION

NO. NO.

STATE

‡

SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS

SPISIMO/

IOPC2

45 56 I/O SPI slave in, master out or GPIO

SPISOMI/

IOPC3

46 57 I/O

SPI slave out, master in or GPIO

SPICLK/

IOPC4

47 58 I/O

I

SPI clock or GPIO

SPISTE/

IOPC5

48 59 I/O SPI slave transmit enable (optional) or GPIO

SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS

SCITXD/

IOPA0

43 54 I/O

SCI asynchronous serial port transmit data or GPIO

SCIRXD/

IOPA1

44 55 I/O

I

SCI asynchronous serial port receive data or GPIO

CONTROLLER AREA NETWORK (CAN)

CANTX/

IOPC6

4 11 I/O

CAN transmit data or GPIO

CANRX/

IOPC7

3 10 I/O

I

CAN receive data or GPIO

INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS

RS 27 35 I/O I

Device reset. RS causes the ’F243/241 to terminate execution and sets
PC = 0. When RS

is brought to a high level, execution begins at location

zero of program memory. RS

affects (or sets to zero) various registers
and status bits. When the watchdog timer overflows, it initiates a system
reset pulse that is reflected on the RS

pin. This pulse is eight clock cycles

wide.

NMI

§

53 64 I I

Nonmaskable interrupt. When NMI is activated, the device is interrupted
regardless of the state of the INTM bit of the status register. NMI

is
(falling) edge- and low-level-sensitive. T o be recognized by the core, this
pin must be kept low for at least one clock cycle after the falling edge.

XINT1/

IOPA2

55 66 I/O I

External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge­sensitive. T o be recognized by the core, these pins must be kept low/high
for at least one clock cycle after the edge. The edge polarity is
programmable.

XINT2/ADCSOC/

IOPD1

54 65 I/O I

External user interrupt 2. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be
recognized by the core, these pins must be kept low/high for at least one
clock cycle after the edge. The edge polarity is programmable.

XF

/IOPC0 39 50 I/O O – 1

External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XF
instruction. This pin is configured as an external flag output by all device
resets. It can be used as a GPIO, if not used as XF.

BIO

/IOPC1 42 53 I/O I

Branch control input. BIO is polled by the BCND pma,BIO instruction. If
BIO

is low, a branch is executed. If BIO is not used, it should be pulled
high. This pin is configured as a branch control input by all device resets.
It can be used as a GPIO, if not used as a branch control input.

PMT 49 60 I I Enables parallel module test (PMT). Do not connect, reserved for test.

CLOCK SIGNALS

XTAL1/CLKIN 35 46 I I

PLL oscillator input pin. Crystal input to PLL/clock source input to PLL.
XTAL1/CLKIN is tied to one side of a reference crystal.

XTAL2 36 47 O O

Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a
reference crystal. This pin goes in the high-impedance state when
EMU1/OFF

is active low.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

16

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F241 PG and FN Packages (Continued)

NAME

64

QFP68PLCC

TYPE

†

RESET

‡

DESCRIPTION

NO. NO.

STATE

‡

CLOCK SIGNALS (CONTINUED)

CLKOUT

/IOPD0 5 12 I/O O

Clock output. This pin outputs either the CPU clock (CLKOUT) or the
watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14)
of the System Status and Control Register (SSCR). This pin can be used as
a GPIO if not used as a clock output pin.

TEST SIGNALS

TCK 28 36 I I JTAG test clock with internal pullup
TDI 29 37 I I

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.

TDO 30 38 O I

JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.

TMS 31 39 I I

JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.

TRST 32 40 I I

JTAG test reset with internal pulldown. TRST, when driven high, gives the
scan system control of the operations of the device. If this signal is not
connected or driven low, the device operates in its functional mode, and the
test reset signals are ignored.

EMU0 37 48 I/O I

Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through the JTAG scan.

EMU1 38 49 I/O I

Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through JTAG scan.

SUPPLY SIGNALS

9 16 – –

pp

V

DD

41 52 – –

Digital logic suppl

y v

oltage (5 V)

– 42 – –
1 8 – –

pp

V

DDO

34 45 – –

Digital logic and buffer suppl

y v

oltage (5 V)

51 62 – –

– 41 – –

V

SS

10 17 – –

Digital logic ground reference

40 51 – –

– 43 – –
2 9 – –

V

SSO

26 34 – –

Digital logic and buffer ground reference
33 44 – –
50 61 – –

NO CONNECT

NC – 27 No internal connection made to this pin
DNC 25 33 – – Do not connect. Reserved for test.

†

I = input, O = output, Z = high impedance

‡

The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.

§

In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

NOTE:

Bold, italicized pin names

indicate pin function after reset.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

17

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

functional block diagram of the ’24x DSP controller

24

Á

8

PDPINT

3

2

8

7

Á

Quadrature

Encoder

Pulse (QEP)

Capture/

Units

Compare

Timers

Purpose

General-

Manager

Event

Emulation

Test/

Peripheral Bus

Timer

Watchdog

Interface

Communications

Serial-

Interface

Peripheral

Serial-

Converter

to-Digital

Analog-

Single 10-Bit

Data Bus

2

Module

Clock

Program Bus

B1/B2

DARAM

B0

DARAMFlash

EEPROM

Initialization

Interrupts

Control

Memory

†

Controller

Program

CPU

’C2xx

Shifter

Product

PREG

TREG

Multiplier

Shifter

Output

Accumulator

ALU

Shifter

Input

Registers

Mapped

Memory

Registers

Auxiliary

Registers

Control

Status/

ARAU

Register

Instruction

32

‡

4

Interrupts

Resets

General­Purpose

I/O Pins

2

CAN Module

16

16

†

’F243 only

‡

26 in ’F241

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

architectural overview

The functional block diagram provides a high-level description of each component in the ’F243/’F241 DSP
controllers. The TMS320x24x devices are composed of three main functional units: a ’C2xx DSP core, internal
memory , and peripherals. In addition to these three functional units, there are several system-level features of
the ’F243/’F241 that are distributed. These system features include the memory map, device reset, interrupts,
digital input/output (I/O), clock generation, and low-power operation.

system-level functions

device memory maps

The ’F243/’F241 devices implement three separate address spaces for program memory, data memory, and
I/O space. On the ’F243/’F241, the first 96 (0–5Fh) data memory locations are either allocated for
memory-mapped registers or reserved. This memory-mapped register space contains various control and
status registers, including those for the CPU.

All the on-chip peripherals of the ’F243/’F241 devices are mapped into data memory space. Access to these
registers is made by the CPU instructions addressing their data memory locations. Figure 1 shows the ’F243
memory map and Figure 2 shows the ’F241 memory map.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

19

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory maps

Reserved/

Illegal

Reserved/

Illegal

Reserved/

Illegal

0000

005F
0060

01FF

02FF
0300

0200

03FF
0400

7000

Peripheral Memory-

Mapped Registers
(System,WD, ADC,
SCI, SPI, CAN, I/O,

Interrupts)

73FF
7400

743F
7440

Data

Hex

007F
0080

8000

External

FFFF

7FFF

Memory-Mapped

Registers/Reserved

Addresses

On-Chip

DARAM B2

On-Chip DARAM

(B0)‡ (CNF = 0)

Reserved (CNF = 1)

On-Chip

DARAM (B1)

§

6FFF

Peripheral

Memory-Mapped

Registers

(Event Manager)

0000
002F

0030

FEFF

FDFF
FE00

Hex

1FFF

2000

External

On-Chip DARAM

(B0)† (CNF = 1)

External (CNF = 0)

Program

FF00

FFFF

Illegal

Interrupts

Reserved

†

(CNF = 1)

External (CNF = 0)

Unused

0000

External

FF0E

I/O

Hex

FFFF

Wait-State Generator

Control Register

(On-Chip)

Flash Control

Mode Register

Reserved

FEFF

FF00

FF10

FFFE

FF0F

On-Chip FLASH memory, (8K) – if MP/MC = 0
External Program Memory – if MP/MC

= 1

†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h will have the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved
when CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h will have the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

Figure 1. TMS320F243 Memory Map

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

memory maps (continued)

ВВВВВВ

ВВВВВВ

ВВВВВВ

ВВВВВВ

Reserved

Reserved

Unused

Reserved/

Illegal

Reserved/

Illegal

0000

Interrupts

002F
0030

Hex

Program

1FFF

2000

0000

005F
0060

01FF

02FF
0300

0200

03FF
0400

7000

Peripheral Memory-

Mapped Registers

(System,WD, ADC,

SCI, SPI, CAN, I/O,

Interrupts)

73FF
7400

743F
7440

Data

Hex

007F
0080

8000

Reserved

FFFF

7FFF

Memory-Mapped

Registers/Reserved

Addresses

On-Chip

DARAM B2

On-Chip DARAM

(B0)‡ (CNF = 0)

Reserved (CNF = 1)

On-Chip

DARAM (B1)

§

6FFF

Peripheral

Memory-Mapped

Registers

(Event Manager)

Illegal

FDFF

FE00

On-Chip DARAM

B0† (CNF = 1)

External (CNF = 0)

Reserved

†

(CNF = 1)

External (CNF = 0)

FEFF

FF00

Reserved

FFFF

On-Chip FLASH memory, (8K) – if MP/MC = 0
External Program Memory – if MP/MC

= 1

0000

FF0E

I/O

Hex

FFFF

Flash Control

Mode Register

FF10

FF0F

†

When CNF = 1, addresses FE00h–FEFFh and FF00h–FFFFh are mapped to the same physical block (B0) in program-memory space. For
example, a write to FE00h will have the same effect as a write to FF00h. For simplicity, addresses FE00h–FEFFh are referred to as reserved
when CNF = 1.

‡

When CNF = 0, addresses 0100h–01FFh and 0200h–02FFh are mapped to the same physical block (B0) in data-memory space. For example,
a write to 0100h will have the same effect as a write to 0200h. For simplicity , addresses 0100h–01FFh are referred to as reserved.

§

Addresses 0300h–03FFh and 0400h–04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h
has the same effect as a write to 0300h. For simplicity , addresses 0400h–04FFh are referred to as reserved.

NOTE A: There is no external memory space for program, data, or I/O in the ’F241.

Figure 2. TMS320F241 Memory Map

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

21

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

peripheral memory map

The system and peripheral control register frame contains all the data, status, and control bits to operate the
system and peripheral modules on the device (excluding the event manager). The register frame is mapped
in the data memory space.

Illegal

Global-Memory Allocation

Register

0000
0003

0004

0005

0000

Memory-Mapped Registers

and Reserved

005F
0060

On-Chip DARAM B2

02FF
0300

01FF
0200

03FF

On-Chip DARAM B1

0400

Reserved

73FF

Peripheral Frame 1 (PF1)

7400

77FF
7800

External

†

FFFF

7000–700F

Reserved

0007

Emulation Registers

and Reserved

Peripheral Frame 2 (PF2)

Reserved

On-Chip DARAM B0

Interrupt-Mask Register

Illegal

System Configuration and

Control Registers

Watchdog Timer Registers

Illegal

Digital-I/O Control Registers

Illegal

Reserved

Interrupt Mask, Vector and

Flag Registers

0006

005F

007F
0080

07FF

7000

743F
7440

7010–701F

7020–702F

7030–703F
7040–704F

7050–705F
7060–706F
7070–707F
7080–708F

7090–709F
70A0–70FF

7400–7408

7411–7419

7420–7429

742C–7431

7432–743F

Interrupt Flag Register

SPI
SCI

Illegal

External-Interrupt Registers

ADC Control Registers

General-Purpose

Timer Registers

Capture & QEP Registers

Compare, PWM, and

Deadband Registers

Reserved

7FFF
8000

Illegal

0800
6FFF

Illegal

Hex

Hex

CAN Control Registers

7100–722F

7230–73FF

†

Reserved in the ’F241

Figure 3. Peripheral Memory Map for ’F243/’F241

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

software-controlled wait-state generator

Due to the fast cycle time of the ’F243 devices, it is often necessary to operate with wait states to interface with
external logic or memory. For many systems, one wait state is adequate.

The software wait-state generator can be programmed to generate between 0 and 7 wait states for a given
space. Software wait states are configured through the wait-state generator register (WSGR). The WSGR
includes three 3-bit fields to configure wait states for the following external memory spaces: data space (DSWS),
program space (PSWS), and I/O space (ISWS). The wait-state generator enables wait states for a given
memory space based on the value of the corresponding three bits, regardless of the condition of the READY
signal. The READY signal can be used to generate additional wait states. All bits of the WSGR are set to 1 at
reset so that the device can operate from slow memory at reset. The WSGR register (shown in T able 3, T able 4
and Table 5) resides at I/O location FFFFh. This register should not be accessed in the ’F241.

Table 3. Wait-State Generator Control Register (WSGR)

15 12 11 10 9 8 6 5 3 2 0

Reserved

BVIS ISWS DSWS PSWS

0 R/W–11 R/W–111 R/W–111 R/W–111

LEGEND:
0 = Always read as zeros, R = Read Access, W= Write Access, – n = Value after reset

Table 4. Wait-State(s) Programming

PSWS, DSWS, ISWS BITS WAIT STATES FOR PROGRAM, DATA, OR I /O

000 0
001 1
010 2

011 3
100 4
101 5

110 6

111 7

Table 5. Wait-State Generator Control Register (WSGR)

BITS NAME DESCRIPTION

2–0 PSWS

External program space wait states. PSWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip program space address. The memory cycle can be further extended by using the READY
signal. The READY signal does not override the wait states generated by PSWS. These bits are set to 1 (active)
by reset (RS

).

5–3 DSWS

External data space wait states. DSWS determines that between 0 to 7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended by using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset (RS

).

8–6 ISWS

External input /output space wait state. ISWS determines that between 0 to 7 wait states are applied to all reads
and writes to off-chip I/O space. The memory cycle can be further extended by using the READY signal. The
READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active) by reset (RS

).

10–9 BVIS

Bus visibility modes. Bits 10 and 9 allow selection of various bus visibility modes while running from internal
program and/or data memory . These modes provide a method of tracing internal bus activity . These bits are set
to 11b by reset (RS

), causing internal program address and program data to be output on the external address

and data pins. See Table 6.

15–11 – Reserved

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

software-controlled wait-state generator (continued)

Table 6. Visibility Modes

BIT 10 BIT 9 VISIBILITY MODE

0 0 Bus visibility OFF (reduces power consumption and noise)
0 1 Bus visibility OFF (reduces power consumption and noise)

1 0

Data-address bus output to external address bus.
Data-data bus output to external data bus.

1 1

Program-address bus output to external address bus.
Program-data bus output to external data bus.

digital I/O and shared pin functions

The ’F243 has a total of 32 general-purpose, bidirectional, digital I/O (GPIO) pins that function as follows: six
pins are dedicated I/O pins (see T able 7) and 26 pins are shared between primary functions and I/O. The ’F241
has 26 I/O pins; all are shared with other functions. The digital I/O ports module provides a flexible method for
controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using
eight 16-bit registers. These registers are divided into two types:

D

Output Control Registers — used to control the multiplexer selection that chooses between the primary
function of a pin or the general-purpose I/O function.

D

Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.

Table 7. Dedicated I/O Pins (’F243 Only)

’F243 PIN NUMBER PIN NAME

20 IOPD2
21 IOPD3
23 IOPD4
25 IOPD5
27 IOPD6
29 IOPD7

description of shared I/O pins

The control structure for shared I/O pins is shown in Figure 4, where each pin has three bits that define its
operation:

D

Mux control bit — this bit selects between the primary function (1) and I/O function (0) of the pin.

D

I/O direction bit — if the I/O function is selected for the pin (mux control bit is set to 0), this bit determines
whether the pin is an input (0) or an output (1).

D

I/O data bit — if the I/O function is selected for the pin (mux control bit is set to 0) and the direction selected
is an input, data is read from this bit; if the direction selected is an output, data is written to this bit.

The mux control bit, I/O direction bit, and I/O data bit are in the I/O control registers.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description of shared I/O pins (continued)

Primary

Function

Pin

(Read/Write)

IOP Data Bit

In Out

0 = Input
1 = Output

01

MUX Control Bit

0 = I/O Function

1 = Primary Function

IOP DIR Bit

Primary

Function

or I/O Pin

When the MUX control bit = 1, the primary
function is selected in all cases except
for the following pins:

1. XF/IOPC0 (0 = Primary Function)

2. BIO

/IOPC1 (0 = Primary Function)

3. CLKOUT/IOPD0 (0 = Primary Function)

Note:

Figure 4. Shared Pin Configuration

A summary of shared pin configurations and associated bits is shown in Table 8.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description of shared I/O pins (continued)

Table 8. Shared Pin Configurations

PIN #

MUX CONTROL

PIN FUNCTION SELECTED I/O PORT DATA AND DIRECTION

†

144

PQFP68PLCC64QFP

REGISTER

(name.bit #)

(OCRx.n = 1) (OCRx.n = 0) REGISTER DATA BIT #‡DIR BIT #

§

’F243 ’F241

56 54 43 OCRA.0 SCITXD IOPA0 PADATDIR 0 8
58 55 44 OCRA.1 SCIRXD IOPA1 P ADATDIR 1 9

83 66 55 OCRA.2 XINT1 IOPA2 PADATDIR 2 10
123 15 8 OCRA.3 CAP1/QEP0 IOPA3 PADATDIR 3 11
121 14 7 OCRA.4 CAP2/QEP1 IOPA4 PADATDIR 4 12
119 13 6 OCRA.5 CAP3 IOPA5 PADA TDIR 5 13
102 7 64 OCRA.6 PWM1 IOPA6 PADATDIR 6 14
100 6 63 OCRA.7 PWM2 IOPA7 PADATDIR 7 15

98 5 62 OCRA.8 PWM3 IOPB0 PBDATDIR 0 8

96 4 61 OCRA.9 PWM4 IOPB1 PBDATDIR 1 9

94 3 60 OCRA.10 PWM5 IOPB2 PBDATDIR 2 10

91 2 59 OCRA.11 PWM6 IOPB3 PBDATDIR 3 11
130 19 12 OCRA.12 T1PWM/T1CMP IOPB4 PBDATDIR 4 12
128 18 11 OCRA.13 T2PWM/T2CMP IOPB5 PBDATDIR 5 13

85 67 56 OCRA.14 TDIR IOPB6 PBDATDIR 6 14

87 68 57 OCRA.15 TCLKIN IOPB7 PBDATDIR 7 15

49 50 39 OCRB.0 IOPC0 XF PCDATDIR 0 8

55 53 42 OCRB.1 IOPC1 BIO PCDATDIR 1 9

60 56 45 OCRB.2 SPISIMO IOPC2 PCDATDIR 2 10

62 57 46 OCRB.3 SPISOMI IOPC3 PCDATDIR 3 11

64 58 47 OCRB.4 SPICLK IOPC4 PCDATDIR 4 12

66 59 48 OCRB.5 SPISTE IOPC5 PCDATDIR 5 13
115 11 4 OCRB.6 CANTX IOPC6 PCDATDIR 6 14
113 10 3 OCRB.7 CANRX IOPC7 PCDATDIR 7 15

116 12 5 OCRB.8 IOPD0 CLKOUT PDDATDIR 0 8

81 65 54 OCRB.9 XINT2/ADCSOC IOPD1 PDDATDIR 1 9

†

Valid only if the I/O function is selected on the pin.

‡

If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from.

§

If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output.

NOTE: GPIO pins IOPD2 to IOPD7 are dedicated I/O pins in ’F243. These pins are not available in the ’F241.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

digital I/O control registers

T able 9 lists the registers available in the digital I/O module. As with other ’F243/’F241 peripherals, the registers
are memory-mapped to the data space.

Table 9. Addresses of Digital I/O Control Registers

ADDRESS REGISTER NAME

7090h OCRA I/O mux control register A
7092h OCRB I/O mux control register B
7098h PADATDIR I/O port A data and direction register
709Ah PBDATDIR I/O port B data and direction register
709Ch PCDATDIR I/O port C data and direction register
709Eh PDDATDIR I/O port D data and direction register

device reset and interrupts

The TMS320x24x software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’F243/’F241 recognizes three
types of interrupt sources:

D

Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.

The ’F243/’F241 devices have two sources of reset: an external reset pin and a watchdog timer timeout
(reset).

D

Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:

–

External interrupts

are generated by one of four external pins corresponding to the interrupts XINT1,

XINT2, PDPINT

, and NMI. The first three can be masked both by dedicated enable bits and by the C PU’s

interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI

, which
is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can be
locked out only by an already executing NMI

or a reset.

–

Peripheral interrupts

are initiated internally by these on-chip peripheral modules: the event manager,
SPI, SCI, WD, CAN, and ADC. They can be masked both by enable bits for each event in each peripheral
and by the CPU’s IMR, which can mask each maskable interrupt line at the DSP core.

D

Software-generated interrupts for the ’F243/’F241 devices include:
–

The INTR instruction.

This instruction allows initialization of any ’F243/’F241 interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).

–

The NMI instruction.

This instruction forces a branch to interrupt vector location 24h, the same location

used for the nonmaskable hardware interrupt NMI. NMI can be initiated by driving the NMI

pin low or by

executing an NMI instruction. This instruction globally disables maskable interrupts.

–

The TRAP instruction.

This instruction forces the CPU to branch to interrupt vector location 22h. The

TRAP instruction does

not

disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.

–

An emulator trap.

This interrupt can be generated with either an INTR instruction or a TRAP instruction.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

27

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

reset

The reset operation ensures an orderly startup sequence for the device. There are two possible causes of a
reset, as shown in Figure 5.

Signal

Reset

System Reset

Watchdog Timer Reset

External Reset (RS) Pin Active

Figure 5. Reset Signals

The two possible reset signals are generated as follows:

D

Watchdog timer reset. A watchdog-timer-generated reset occurs if the watchdog timer overflows or an
improper value is written to either the watchdog key register or the watchdog control register. (Note that
when the device is powered on, the watchdog timer is automatically active.) The watchdog timer reset is
reflected on the external RS

pin also.

D

Reset pin active. To generate an external reset pulse on the RS pin, a low-level pulse duration of at least
one CPUCLK cycle is necessary to ensure that the device recognizes the reset signal.

Once watchdog reset is activated, the external RS

pin is driven (active) low for a minimum of eight CPUCLK

cycles. This allows the TMS320x24x device to reset external system components.
The occurrence of a reset condition causes the TMS320x24x to terminate program execution and affects

various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state.

hardware-generated interrupts

The ’24x CPU supports one nonmaskable interrupt (NMI) and six maskable prioritized interrupt requests. The
’24x devices have many peripherals, and each peripheral is capable of generating one or more interrupts in
response to many events. The ’24x CPU does not have sufficient interrupt requests to handle all these
peripheral interrupt requests; therefore, a centralized interrupt controller is provided to arbitrate the interrupt
requests from all the different sources. Throughout this section, refer to Figure 6 .

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

hardware-generated interrupts (continued)

CPU

IACK

Bus

Addr

Bus

Data

PIVR & logic

PIRQR#
PIACK#

IRQ GEN

Level 6

IRQ GEN

Level 5

IRQ GEN

Level 4

IRQ GEN

Level 3

IRQ GEN

Level 2

IRQ GEN

Level 1

XINT2

XINT1

ADCINT

CANERINT

CANMBINT

TXINT

RXINT

SPIINT

CAPINT3

CAPINT2

CAPINT1

TOFINT2

TUFINT2

TCINT2

TPINT2

TOFINT1

TUFINT1

TCINT1

TPINT1

CMP3INT

CMP2INT

CMP1INT

CANERINT

CANMBINT

TXINT

RXINT

SPIINT

XINT2

XINT1

ADCINT

PDPINT

INT1

INT2

INT3

INT4

INT6

INT5

IMR

IFR

IRQ

Pulse

Gen
Unit

Figure 6. Peripheral Interrupt Expansion Block Diagram

interrupt hierarchy

The number of interrupt requests available is expanded by having two levels of hierarchy in the interrupt request
system. There are two levels of hierarchy in both the interrupt request/acknowledge hardware and in the
interrupt service routine software.

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupt request structure

1. At the lower level of the hierarchy, the peripheral interrupt requests (PIRQs) from several peripherals to the
interrupt controller are ORed together to generate a request to the CPU. There is an interrupt flag bit and
an interrupt enable bit located in the peripheral for each event that can cause a peripheral interrupt request.
There is also one PIRQ for each event. If an interrupt-causing event occurs in a peripheral, and the
corresponding interrupt enable bit is set, the interrupt request from the peripheral to the interrupt controller
is asserted. This interrupt request simply reflects the status of the peripheral’s interrupt flag gated with the
interrupt enable bit. When the interrupt flag is cleared, the interrupt request is cleared. Some peripherals
have the capability to make either a high-priority or a low-priority interrupt request. If a peripheral has this
capability , the value of its interrupt priority bit is transmitted to the interrupt controller . The interrupt request
continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by
software.

2. At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INT) requests to the CPU. The
request to the ’24x CPU is a low-going pulse of 2 CPU clock cycles. The Peripheral Interrupt Expansion
(PIE) controller generates an INT pulse when any of the PIRQs controlling that INT go active. If any of the
PIRQs capable of asserting that CPU interrupt request are still active in the cycle following an interrupt
acknowledge for that INT, another INT pulse is generated (an interrupt acknowledge clears the
highest-priority pending PIRQ). Which CPU interrupt requests get asserted by which peripheral interrupt
requests, and the relative priority of each peripheral interrupt request, is defined in the interrupt controller
and is not part of any of the peripherals. This is shown in Table 10.

TMS320F243, TMS320F241
DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

interrupt request structure (continued)

Table 10. ’F243/’F241 Interrupt Source Priority and Vectors

INTERRUPT

NAME

OVERALL

PRIORITY

CPU

INTERRUPT

AND

VECTOR

ADDRESS

BIT

POSITION IN

PIRQRx AND

PIACKRx

PERIPHERAL

INTERRUPT

VECTOR

(PIV)

MASKABLE?

SOURCE

PERIPHERAL

MODULE

DESCRIPTION

Reset 1

RSN

0000h

N/A N

RS pin,

Watchdog

Reset from pin, watchdog
timeout

Reserved 2

–

0026h

N/A N CPU Emulator Trap

NMI 3

NMI

0024h

N/A N

Nonmaskable

Interrupt

Nonmaskable interrupt

PDPINT 4 0.0 0020h Y EV

Power device protection
interrupt pin

ADCINT 5

0.1 0004h Y ADC

ADC interrupt in
high-priority mode

XINT1 6 0.2 0001h Y

External

Interrupt Logic

External interrupt pins in
high priority

XINT2 7

INT1

0.3 0011h Y

External

Interrupt Logic

External interrupt pins in
high priority

SPIINT 8

0002h

RXINT 9 0.5 0006h Y SCI

SCI receiver interrupt in
high-priority mode

TXINT 10 0.6 0007h Y SCI

SCI transmitter interrupt in

high-priority mode
CANMBINT 11
CANERINT 12
CMP1INT 13 0.9 0021h Y EV Compare 1 interrupt
CMP2INT 14 0.10 0022h Y EV Compare 2 interrupt
CMP3INT 15 0.11 0023h Y EV Compare 3 interrupt
TPINT1 16

INT2

0.12 0027h Y EV Timer 1 period interrupt

TCINT1 17

0004h

0.13 0028h Y EV Timer 1 PWM interrupt

TUFINT1 18 0.14 0029h Y EV

Timer 1 underflow

interrupt
TOFINT1 19 0.15 002Ah Y EV Timer 1 overflow interrupt
TPINT2 20 1.0 002Bh Y EV Timer 2 period interrupt
TCINT2 21

INT3

1.1 002Ch Y EV Timer 2 PWM interrupt

TUFINT2 22

0006h

1.2 002Dh Y EV

Timer 2 underflow

interrupt
TOFINT2 23 1.3 002Eh Y EV Timer 2 overflow interrupt
CAPINT1 24

1.4 0033h Y EV Capture 1 interrupt

CAPINT2 25

INT4

1.5 0034h Y EV Capture 2 interrupt

CAPINT3 26

0008h

1.6 0035h Y EV Capture 3 interrupt