Texas Instruments TLV5636ID, TLV5636CDR, TLV5636CDGKR, TLV5636CDGK, TLV5636CD Datasheet

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

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features

D

12-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time:

1 µs in Fast Mode,

3.5 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity...<0.5 LSB Typ

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5636 is a 12-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows
glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit
serial string containing 4 control and 12 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling
time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable
precision voltage reference, the TLV5636 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in
an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial
temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

MSOP
(DGK)

0°C to 70°C TLV5636CD TLV5636CDGK

–40°C to 85°C TLV5636ID TLV5636IDGK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

FS

V

DD

OUT
REF
AGND

D OR DGK PACKAGE

(TOP VIEW)

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

TLV5636

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functional block diagram

Serial

Interface

and

Control

12-Bit

DAC

Latch

CS

DIN

OUT

Power-On

Reset

x2

12

2-Bit

Control

Latch

2

Power

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

12

REF

FS

SCLK

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
FS 4 I Frame sync input
OUT 7 O DAC A analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

TLV5636

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

DD

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5636C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5636I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V
Power on Reset, POR 0.55 2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5636C 0 70

°

Operating free-air temperature, T

A

TLV5636I –40 85

°C

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. The output buffer of the

internal reference must be disabled, if an external reference is used.

TLV5636

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electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

pp

No load,

p

Fast 2.3 3.3

IDDPower su ly current

All in uts = AGND or V

DD

,

DAC latch = 0x800

Slow 1.5 1.9

mA

Power-down supply current See Figure 8 0.01 10 µA

pp

Zero scale, See Note 2 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits
INL Integral nonlinearity, end point adjusted See Note 4 ±2 ±4 LSB
DNL Differential nonlinearity See Note 5 ±0.5 ±1 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±20 mV
EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.6

% full

scale V

EG TCGain error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the dif ference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V RL = 2 kΩ ±0.25

% full

scale V

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref(OUTL)

Low reference voltage 1.003 1.024 1.045 V

V

ref(OUTH)

High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V

I

ref(source)

Output source current 1 mA

I

ref(sink)

Output sink current –1 mA
Load capacitance 100 pF

PSRR Power supply rejection ratio –65 dB

TLV5636

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electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

reference pin configured as input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 1.3 MHz

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 1 3

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 3.5 7

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 0.5 1.5

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 1 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 8

SR

Slew rate

L

,

L

,

See Note 13

Slow 1.5

V/µs

Glitch energy

DIN = 0 to 1, f

CLK

= 100 kHz,

CS

= V

DD

5 nV–S

SNR Signal-to-noise ratio 71 75
S/(N+D) Signal-to-noise + distortion

f

= 480 kSPS, f

= 1 kHz,

59 66

THD Total harmonic distortion

s

,

out

,

RL = 10 kΩ,C

L

= 100 pF

–67 –59

dB

Spurious free dynamic range 59 69

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

TLV5636

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digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–FS)

Setup time, CS low before FS falling edge 10 ns

t

su(FS-CK)

Setup time, FS low before first negative SCLK edge 8 ns

t

su(C16-FS)

Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising
edge of FS

10 ns

t

su(C16-CS)

Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of 16th positive edge to update DAC, then setup time between
FS rising edge and CS

rising edge.

10 ns

t

wH

SCLK pulse duration high 25 ns

t

wL

SCLK pulse duration low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 8 ns

t

H(D)

Hold time, data held valid after SCLK falling edge 5 ns

t

wH(FS)

FS pulse duration high 25 ns

PARAMETER MEASUREMENT INFORMATION

t

wL

SCLK

CS

DIN

FS

D15 D14 D13 D12 D1 D0 XX

1

X

2 3 4 5 15 16

X

t

wH

t

su(D)th(D)

t

su(CS-FS)

t

wH(FS)

t

su(FS-CK)

t

su(C16-FS)

t

su(C16-CS)

Figure 1. Timing Diagram

TLV5636

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TYPICAL CHARACTERISTICS

2.0685

2.0675

2.067

2.066
0 0.5 1 1.5 2 2.5 3

Output Voltage – V

2.07

2.0705

Source Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

2.071

3.5 4

2.0695

2.0698

2.068

2.0665

Slow

Fast

VDD = 3 V, REF = Int. 1 V, Input Code = 4095

Figure 2

VDD = 5 V, REF = Int. 2 V, Input Code = 4095

4.132

4.131

4.13

4.129
0 0.5 1 1.5 2 2.5 3

Output Voltage – V

4.133

4.134

Source Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

4.135

3.5 4

Slow

Fast

Figure 3

Figure 4

VDD = 3 V, REF = Int. 1 V,
Input Code = 0

Slow

Fast

1.5

1

0.5

0

0 0.5 1 1.5 2 2.5 3

Output Voltage – V

2

2.5

Sink Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

3

3.5 4

VDD = 5 V, REF = Int. 2 V,
Input Code = 0

Slow

Fast

3.5

2

1

0

0 0.5 1 1.5 2 2.5 3

Output Voltage – V

4

4.5

Sink Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

5

3.5 4

3

2.5

1.5

0.5

Figure 5

TLV5636

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TYPICAL CHARACTERISTICS

Figure 6

1.5

1

0.5
–40–30 –20–10 0 20 30

Supply Current – mA

2

2.5

SUPPLY CURRENT

vs

TEMPERATURE

3

40 50 70 9010 60 80

Fast Mode

Slow Mode

t – Temperature – ° C

VDD = 5 V, REF = 2 V,
Input Code = 4095

Figure 7

1.5

1

0.5
–40–30–20 –10 0 10 20

2

2.5

3

30 40 50 9060 70

80

Supply Current – mA

SUPPLY CURRENT

vs

TEMPERATURE

Fast Mode

Slow Mode

t – Temperature – ° C

VDD = 3 V, REF = 1 V,
Input Code = 4095

Figure 8

1.4

0.8

0.4

0

0 10203040

– Power Down Supply Current – mA

1.6

1.8

POWER DOWN SUPPLY CURRENT

vs

TIME

2

50 60 70 80

1.2

1

0.6

0.2

t – Time – µs

I

DD

Figure 9

–40
–50

–80

–100

100 1000

THD+N – Total Harmonic Distortion and Noise – dB

–20

–10

f – Frequency – Hz

TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

0

10000 100000

–30

–60

–70

–90

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

TLV5636

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TYPICAL CHARACTERISTICS

–40
–50

–80

–100

100 1000

THD – Total Harmonic Distortion – dB

–20

–10

f – Frequency – Hz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

10000 100000

–30

–60

–70

–90

Fast Mode

Slow Mode

VDD = 5 V
V

ref

= 1 V dc + 1 V p/p Sinewave

Output Full Scale

Figure 10

Figure 11

DNL – Differential Nonlinearity – LSB

Digital Input Code

DIFFERENTIAL NONLINEARITY

vs

DIGITAL INPUT CODE

1

0.5

0

–0.5

–1

0 1024 2048 3072 4096

TLV5636

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TYPICAL CHARACTERISTICS

Figure 12

–4.0

–3.0

–2.0

–1.0

0.0

1.0

2.0

3.0

4.0

0 4096

INL – Integral Nonlinearity – LSB

Digital Input Code

INTEGRAL NONLINEARITY

vs

DIGITAL INPUT CODE

1024 2048 3072

APPLICATION INFORMATION

general function

The TLV5636 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.

The output voltage (full scale determined by reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).

serial interface

The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on high-low transitions of SCLK. After 16 bits have been transferred or
FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.

The serial interface of the TLV5636 can be used in two basic modes:

D

Four wire (with chip select)

D

Three wire (without chip select)

Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). Figure 13 shows an example with two TL V5636s connected directly
to a TMS320 DSP.

TLV5636

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APPLICATION INFORMATION

serial interface (continued)

TMS320

DSP

XF0

CLKX

DX

FSX

XF1

TLV5636

CS

FS DIN SCLK

TLV5636

CS

FS DIN SCLK

Figure 13. TMS320 Interface

If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 14 shows
an example of how to connect the TLV5636 to TMS320, SPI or Microwire using only three pins.

TMS320

DSP

FSX

CLKX

DX

TLV5636

SCLK

DIN

FS

SPI

I/O

SCK

MOSI

TLV5636

SCLK

DIN

FS

Microwire

I/O

SK

SO

TLV5636

SCLK

DIN

FS

CS

CS CS

Figure 14. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write
operations must be performed to program the TL V5636. After the write operation(s), the DAC output is updated
automatically on the 16

th

positive clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

f

sclkmax

+

1

t

whmin

)

t

wlmin

+

20 MHz

The maximum update rate is:

f

updatemax

+

1

16

ǒ

t

whmin

)

t

wlmin

Ǔ

+

1.25 MHz

Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5636 has to be considered, too.

TLV5636

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APPLICATION INFORMATION

data format

The 16-bit data word for the TLV5636 consists of two parts:

D

Program bits (D15..D12)

D

New data (D11..D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

R1 SPD PWR R0 12 Data bits

SPD: Speed control bit 1 → fast mode 0 → slow mode
PWR: Power control bit 1 → power down 0 → normal operation

The following table lists the possible combination of the register select bits:

register select bits

R1 R0 REGISTER

0 0 Write data to DAC
0 1 Reserved
1 0 Reserved
1 1 Write data to control register

The meaning of the 12 data bits depends on the selected register. For the DAC register, the 12 data bits
determine the new DAC output value:

data bits: DAC

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

New DAC Value

If the control register is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:

data bits: CONTROL

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X X X X X X X X X X REF1 REF2

X: don’t care

REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.

reference bits

REF1 REF0 REFERENCE

0 0 External
0 1 1.024 V
1 0 2.048 V
1 1 External

CAUTION:

If external reference voltage is applied to the REF pin, external reference MUST be selected.

TLV5636

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APPLICATION INFORMATION

Example:

D

Set DAC output, select fast mode, select internal reference at 2.048 V:

1. Set reference voltage to 2.048 V (CONTROL register):

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0

2. Write new DAC value and update DAC output:

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 0 0 New DAC output value

The DAC output is updated on the rising clock edge after D0 is sampled.
T o output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL

register again.

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 15.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 15. Effect of Negative Offset (Single Supply)

This offset error , not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
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APPLICATION INFORMATION

power-supply bypassing and ground management

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between V

DD

and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.

Figure 16 shows the ground plane layout and bypassing technique.

0.1 µF

Analog Ground Plane

1
2
3
4

8
7
6
5

Figure 16. Power-Supply Bypassing

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

ZS

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E

G

)

Gain error is the error in slope of the DAC transfer function.

total harmonic distortion (THD)

THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal.
The value for THD is expressed in decibels.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

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spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of
the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

Effects of negative offset error for single supply devices to be added here.

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
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MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 – JUNE 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

0,15 NOM

Gage Plane

4073329/B 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05
2,95

1

0,38

1,07 MAX

Seating Plane

0,65

M

0,25

0°–6°

0,10

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

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Copyright  1999, Texas Instruments Incorporated