Texas Instruments TLV5633IPWR, TLV5633IDWR, TLV5633IPW, TLV5633CPWR, TLV5633IDW Datasheet

TLV5633C, TLV5633I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

D

12-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time vs Power
Consumption

1 µs in Fast Mode

3.5 µs in Slow Mode

D

8-Bit µController Compatible Interface

D

Differential Nonlinearity . . . <0.5 LSB Typ

D

Voltage Output Range ... 2x the
Reference V oltage

D

Monotonic Over Temperature

DW OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

DV

D2
D3
D4
D5
D6
D7
A1
A0

SPD

DD

D1
D0
CS
WE
LDAC
PWR
AGND
OUT
REF
AV

DD

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5633 is a 12-bit voltage output digital-to-analog converter (DAC) with an 8-bit microcontroller
compatible parallel interface. The 8 LSBs, the 4 MSBs, and 5 control bits are written using three different
addresses. Developed for a wide range of supply voltages, the TL V5633 can be operated from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class A
(slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of
the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable
precision voltage reference, the TL V5633 simplifies overall system design. Because of its ability to source up
to 1 mA, the internal reference can also be used as a system reference. The settling time and the reference
voltage can be chosen by a control register.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV5633CDW TLV5633CPW

–40°C to 85°C TLV5633IDW TLV5633IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SOIC
(DW)

TSSOP

(PW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLV5633C, TLV5633I

I/O/P

DESCRIPTION

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

functional block diagram

SPD

PWR

A(0,1)

CS

WE

2

Power-On

Reset

Interface

Control

5

5-Bit

Control

Latch

4

4-Bit

DAC MSW

Holding

Latch

8 8

8-Bit

DAC LSW

Holding

Latch

Voltage

Bandgap

Powerdown

and Speed

Control

2

4

REF AGND DV

PGA With

Output Enable

12 12

12-Bit

DAC

Register

DD

x2

AV

DD

OUT

D(0–7)

LDAC

Terminal Functions

TERMINAL

NAME NO.

A1, A0 7, 8 I Address input
AGND 14 P Ground
AV

DD

CS 18 I Chip select. Digital input active low, used to enable/disable inputs
D0 – D1 19, 20 I Data input
D2 – D7 1–6 I Data input
DV

DD

LDAC 16 I Load DAC. Digital input active low, used to load DAC output
OUT 13 O DAC analog voltage output
PWR 15 I Power down. Digital input active low
REF 12 I/O Analog reference voltage input/output
SPD 9 I Speed select. Digital input
WE 17 I Write enable. Digital input active low , used to latch data

11 P Positive power supply (analog part)

10 P Positive power supply (digital part)

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, DV

AV

Operating free-air temperature, T

°C

TLV5633C, TLV5633I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (DV

Supply voltage difference range, AVDD – DVDD – 2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5633C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

, AVDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

TLV5633I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

Supply voltage difference, ∆VDD = AVDD – DV
Power on reset voltage, POR 0.55 2 V
High-level digital input voltage, V
Low-level digital input voltage, V
Reference voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C

p

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ AV

reference must be disabled, if an external reference is used.

,

DD

DD

DD

IH

IL

to REF terminal (5-V supply), See Note 1 AGND 2.048 AVDD–1.5 V

ref

to REF terminal (3-V supply), See Note 1 AGND 1.024 AVDD–1.5 V

ref

L

L

p

A

5-V operation 4.5 5 5.5 V
3-V operation 2.7 3 3.3 V

0 0 0 V

2 DV

DD

0 0.8 V

2 kΩ

100 pF
TLV5633C 0 70
TLV5633I –40 85

causes clipping of the transfer function. The output buffer of the internal

DD/2

V

°

†

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3

TLV5633C, TLV5633I

REF on

DD

,

REF off

IDDPower supply current

All inputs

AGND or DV

REF on

DD

,

REF off

PSRR

Power supply rejection ratio

dB

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

electrical characteristics over recommended operating free-air temperature range, V

= 1.024 V (unless otherwise noted)

V

ref

= 2.048 V,

ref

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

AV

= 5 V,

DVDD = 5 V

No load,

p

pp

DAC latch = 0x800

Power down supply current 0.01 1 µA

pp

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:

PSRR = 20 log [(EZS(AVDDmax) – EZS(AVDDmin))/AVDDmax]

3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by:
PSRR = 20 log [(EG(AVDDmax) – EG(AVDDmin))/AVDDmax]

Zero scale, external reference, See Note 2 –60
Full scale, external reference, See Note 3 –60

=

DD

,

AV

= 3 V,

DVDD = 3 V

Fast 2.3 2.8 mA
Slow 1.3 1.6 mA

Fast 1.9 2.4 mA
Slow 0.9 1.2 mA

Fast 2.1 2.6 mA
Slow 1.2 1.5 mA

Fast 1.8 2.3 mA
Slow 0.9 1.1 mA

UNIT

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits
INL Integral nonlinearity, end point adjusted RL = 10 kΩ, CL = 100 pF, See Note 4 ±1.2 ±3 LSB
DNL Differential nonlinearity RL = 10 kΩ, CL = 100 pF, See Note 5 ±0.3 ±0.5 LSB
E

ZS

EZS TC Zero-scale-error temperature coefficient See Note 7 20 ppm/°C
E

G

EG TC Gain error temperature coefficient See Note 9 20 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

Zero-scale error (offset error at zero scale) See Note 6 ±12 mV

min

% full

scale V

).

Gain error See Note 8 ±0.3

from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text).

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

8. Gain error is the deviation from the ideal output (2V

9. Gain temperature coefficient is given by: EGTC = [EG(T

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

ref

max

) – EG (T

max

min

) – EZS(T

)]/2V

ref

min

× 106/(T

)]/2V

max

× 106/(T

ref

– T

min

– T

max

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ AVDD–0.4 V
Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kΩ ±0.29

% full

scale V

4

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Reference input bandwidth

REF

V

024 V dc

kH

10 kH

dB

in ut

50 kH

dB

TLV5633C, TLV5633I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

electrical characteristics over recommended operating free-air temperature range, V

= 1.024 V (unless otherwise noted) (Continued)

V

ref

= 2.048 V,

ref

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref(OUTL)

V

ref(OUTH)

I

ref(source)

I

ref(sink)

PSRR Power supply rejection ratio –48 dB

Low reference voltage 1.003 1.024 1.045 V
High reference voltage AVDD = DVDD > 4.75 V 2.027 2.048 2.069 V
Output source current 1 mA
Output sink current –1 mA

reference pin configured as input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage 0 AV
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Harmonic distortion, reference

p

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

= 0.2

REF = 1 Vpp + 2.048 V dc, AVDD = 5 V

pp

+ 1.

100 kHz Fast –66 dB

Fast 900
Slow 500

Fast –87

z

Slow –77
Fast –74

z

Slow –61

DD–1.5

V

z

digital inputs

I
I
C

High-level digital input current VI = DV

IH

Low-level digital input current VI = 0 V –1 µA

IL

Input capacitance 8 pF

I

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD

1 µA

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5

TLV5633C, TLV5633I

t

Output settling time, full scale

L

,

L

,

s

t

Output settling time, code to code

L

,

L

,

s

SR

Slew rate

L

,

L

,

V/µs

s

,

B

,

out

,

dB

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

operating characteristics over recommended operating free-air temperature range, V
and V

= 1.024 V, (unless otherwise noted)

ref

= 2.048 V ,

ref

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

s(FS)

s(CC)

SNR Signal-to-noise ratio 73 78
SINAD Signal-to-noise + distortion
THD Total harmonic distortion
SFDR Spurious free dynamic range 63 74

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

p

p

Glitch energy

of 0x020 to 0xFDF or 0xFDF to 0x020 respectively.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

= 10 kΩ,C

See Note 11
R

= 10 kΩ,C

See Note 12
R

= 10 kΩ,C

See Note 13
DIN = 0 to 1,

= V

CS

DD

f

= 480 kSPS, f

RL = 10 kΩ,, CL = 100 pF

= 100 pF,

= 100 pF,

= 100 pF,

f

= 100 kHz,

CLK

= 20 kHz, f

Fast 1 3
Slow 3.5 7
Fast 0.5 1.5
Slow 1 2
Fast 6 10
Slow 1.2 1.7

= 1 kHz,

61 67

–69 –62

µ

µ

5 nV–S

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–WE)

t

su(D)

t

su(A)

t

h(DA)

t

su(WE-LD)

t

wH(WE)

t

w(LD)

Setup time, CS low before negative WE edge 15 ns
Setup time, data ready before positive WE edge 10 ns
Setup time, addresses ready before positive WE edge 20 ns
Hold time, data and addresses held valid after positive WE edge 5 ns
Setup time, positive WE edge before LDAC low 5 ns
Pulse duration, WE high 20 ns
Pulse duration, LDAC low 23 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5633C, TLV5633I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

SLAS190 – MARCH 1999

PARAMETER MEASUREMENT INFORMATION

D(0–7)

A(0,1)

CS

WE

LDAC

D(0–7)

X Data X

X Address X

t

su(D)

t

su(CS-WE)

t

su(A)

t

su(WE-LD)

t

h(DA)

t

wH(WE)

t

w(LD)

Figure 1. Timing Diagram

MSWX X LSW X

A(0,1)

CS

WE

LDAC

0XX1X

Figure 2. Example of a Complete Write Cycle (MSW, LSW) Using LDAC for Update

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7