TEXAS INSTRUMENTS TLV5626 Technical data

TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

DIN

SCLK

D PACKAGE

(TOP VIEW)

1 2 3 4

8 7 6 5

OUTB REF AGND

features

Dual 8-Bit Voltage Output DAC

Programmable Internal Reference

Programmable Settling Time:

0.8 µs in Fast Mode ,

2.8 µs in Slow Mode

Compatible With TMS320 and SPI Serial

OUTA

Ports

Differential Nonlinearity <0.1 LSB Typ

Monotonic Over Temperature

applications

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

description

The TL V5626 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface.The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 2 control and 8 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. With its on-chip programmable precision voltage reference, the TLV5626 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

0°C to 70°C TLV5626CD

–40°C to 85°C TLV5626ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SOIC

(D)

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TLV5626

I/O/P

DESCRIPTION

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

functional block diagram

DIN

SCLK

Power-On

Reset

Serial

Interface

and

Control

Power

and Speed

Control

2-Bit

Control

Latch

Buffer

PGA With

Output Enable

Voltage

Bandgap

8 8

8-Bit

DAC A

Latch

8-Bit

DAC B

Latch

REF AGND V

OUTA

OUTB

Terminal Functions

TERMINAL

NAME NO.

AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUTA 4 I DAC A analog voltage output OUTB 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input V

8 P Positive power supply

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Suppl

oltage, V

Operating free-air temperature, T

°C

TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5626C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5626I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

y v

Power on threshold voltage, POR 0.55 2 V High-level digital input voltage, V Low-level digital input voltage, V Reference voltage, V Reference voltage, V Load resistance, R Load capacitance, C Clock frequency, f

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ (VDD – 0.4 V)/2 causes clipping of the transfer function. The output buffer of the

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

ref

CLK

internal reference must be disabled, if an external reference is used.

VDD = 5 V 4.5 5 5.5 V VDD = 3 V 2.7 3 3.3 V

VDD = 2.7 V to 5.5 V 2 V VDD = 2.7 V to 5.5 V 0.8 V

2 kΩ

100 pF

20 MHz TLV5626C 0 70 TLV5626I –40 85

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TLV5626

IDDPower supply current

All inputs

AGND or V

PSRR

Power supply rejection ratio

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

VDD = 5 V, Int. ref.

VDD = 3 V, Int. ref.

VDD = 5 V, Ext. ref.

VDD = 3 V, Ext. ref.

No load,

Power-down supply current 1 µA

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

DAC latch = 0x800

Zero scale, See Note 2 –65 Full scale, See Note 3 –65

Fast 4.2 7 mA Slow 2 3.6 mA

Fast 3.7 6.3 mA Slow 1.7 3.0 mA

Fast 3.8 6.3 mA Slow 1.7 3.0 mA

Fast 3.4 5.7 mA Slow 1.4 2.6 mA

UNIT

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits INL Integral nonlinearity, end point adjusted See Note 4 ±0.4 ±1 LSB DNL Differential nonlinearity See Note 5 ±0.1 ±0.5 LSB E

EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C E

EG T

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

Zero-scale error (offset error at zero scale) See Note 6 ±24 mV

Gain error See Note 8 ±0.6

Gain error temperature coefficient See Note 9 10 ppm/°C

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

8. Gain error is the deviation from the ideal output (2V

9. Gain temperature coefficient is given by: EGTC = [EG(T

– 1 LSB) with an output load of 10 k excluding the effects of the zero-error .

ref

max

) – EG (T

max

min

) – EZS(T

)]/V

× 106/(T

ref

min

)]/V

max

× 106/(T

ref

– T

min

– T

min

max

% full

scale V

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOOutput voltage RL = 10 kΩ 0 VDD–0.4 V

Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kΩ vs 10 k ±0.25

% full

scale V

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Reference input bandwidth

REF

024 V dc

Output settling time, full scale

Output settling time, code to code

Slew rate

V/µs

out

TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ref(OUTL)

ref(OUTH)

ref(source)

ref(sink)

PSRR Power supply rejection ratio –65 dB

reference pin configured as input (REF)

VIInput voltage 0 V RIInput resistance 10 MΩ CIInput capacitance 5 pF

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

Low reference voltage 1.003 1.024 1.045 V High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V Output source current 1 mA Output sink current –1 mA Load capacitance 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD–1.5

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

= 0.2

+ 1.

Fast 1.3 MHz Slow 525 kHz

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I I C

High-level digital input current VI = V

Low-level digital input current VI = 0 V –1 µA

Input capacitance 8 pF

1 µA

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

s(FS)

s(CC)

SNR Signal-to-noise ratio 53 57 S/(N+D) Signal-to-noise + distortion THD Total harmonic distortion SFDR Spurious free dynamic range 50 62

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

Glitch energy

of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

= 10 kΩ,C

See Note 11 R

= 10 kΩ,C

See Note 12 R

= 10 kΩ,C

See Note 13 DIN = 0 to 1, f

= V

= 480 kSPS, f

RL = 10 kΩ,CL = 100 pF

= 100 pF,

= 100 kHz,

CLK

= 1 kHz,

Fast 0.8 2.4 Slow 2.8 5.5 Fast 0.4 1.2 Slow 0.8 1.6 Fast 12 Slow 1.8

5 nV–S

48 47

–50 –48

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TEXAS INSTRUMENTS TLV5626 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual