Texas Instruments TLC555CP, TLC555CDR, TLC555CD, TLC555QDR, TLC555MP Datasheet

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Very Low Power Consumption

1 mW Typ at VDD = 5 V

D

Capable of Operation in Astable Mode

D

CMOS Output Capable of Swinging Rail
to Rail

D

High Output-Current Capability

Sink 100 mA Typ
Source 10 mA Typ

D

Output Fully Compatible With CMOS, TTL,
and MOS

D

Low Supply Current Reduces Spikes
During Output Transitions

D

Single-Supply Operation From 2 V to 15 V

D

Functionally Interchangeable With the
NE555; Has Same Pinout

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2

description

The TLC555 is a monolithic timing circuit
fabricated using the TI LinCMOS process. The
timer is fully compatible with CMOS, TTL, and
MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses
smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations
are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and
GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.

The TLC555C is characterized for operation from 0°C to 70°C. The TLC555I is characterized for operation from
– 40°C to 85°C. The TLC555M is characterized for operation over the full military temperature range of – 55°C
to 125°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies

available from Texas Instruments.

LinCMOS is a trademark of Texas Instruments Incorporated.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

3212019

910111213

4
5
6
7
8

18
17
16
15
14

NC
DISCH
NC
THRES
NC

NC

TRIG

NC

OUT

NC

FK PACKAGE

(TOP VIEW)

NC

GND

NC

CONT

NC

V

NC

RESET

NC

NC

DD

D, DB, JG, P, OR PW PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

GND

TRIG

OUT

RESET

V

DD

DISCH
THRES
CONT

NC – No internal connection

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

V

DD

RANGE

SMALL

OUTLINE

(D)

SSOP

(DB)

CHIP

CARRIER

(FK)

CERAMIC

DIP

(JG)

PLASTIC

DIP

(P)

TSSOP

(PW)

CHIP

FORM

(Y)

0°C to

70°C

2 V to 15 V TLC555CD TLC555CDBLE — — TLC555CP TLC555CPWLE

–40°C to

85°C

3 V to 15 V TLC555ID — — — TLC555IP —

TLC555Y

–55°C to

125°C

5 V to 15 V TLC555MD — TLC555MFK TLC555MJG TLC555MP —

The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available
left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25°C.

FUNCTION TABLE

RESET

VOLTAGE

†

TRIGGER

VOLTAGE

†

THRESHOLD

VOLTAGE

†

OUTPUT

DISCHARGE

SWITCH

<MIN Irrelevant Irrelevant L On
>MAX <MIN Irrelevant H Off
>MAX >MAX >MAX L On
>MAX >MAX <MIN As previously established

†

For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.

functional block diagram

GND

RESET

CONT

V

DD

1

THRES

TRIG

R

R

R

DISCH

OUT

S

R

R1

Pin numbers are for all packages except the FK package.
RESET can override TRIG, which can override THRES.

5

6

2

1

7

3

4

8

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC555Y chip information

This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

50

64

RESET can override TRIG, which can override THRES.

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

GND

RESETCONT

V

DD

1

THRES

TRIG

R

R

R

DISCH

OUT

S

R

R1

(5)

(6)

(2)

(1)

(7)

(3)

(8)

(4)

TLC555, TLC555Y

LinCMOS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

Template Release Date: 7–11–94

TIMERS

4

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

equivalent schematic (each channel)

THRES

CONT

TRIG RESET

V

DD

DISCH

OUT

GND

Transistors

COMPONENT COUNT

Resistors

39

5

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (any input) –0.3 to V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sink current, discharge or output 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source current, output, I

O

15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M-suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, DB, P, or PW package 260°C. . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 125°C

POWER RATING

D
DB
FK
JG

P

PW

725 mW

525 mW
1375 mW
1050 mW
1000 mW

525 mW

5.8 mW/°C

4.2 mW/°C

11.0 mW/°C

8.4 mW/°C

8.0 mW/°C

4.2 mW/°C

464 mW
336 mW
880 mW
672 mW
640 mW
336 mW

377 mW
273 mW
715 mW
546 mW
520 mW
273 mW

145 mW
105 mW
275 mW
210 mW
200 mW
105 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

DD

2 15 V

TLC555C 0 70

Operating free-air temperature range, T

A

TLC555I –40 85

°C

TLC555M –55 125

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I

TEST

TLC555C TLC555I

PARAMETER

CONDITIONS

T

A

†

MIN TYP MAX MIN TYP MAX

UNIT

25°C 0.95 1.33 1.65 1.6 2.4

VITThreshold voltage

Full range 0.85 1.75 1.5 2.5

V

25°C 10 10

p

IITThreshold current

MAX 75 150

pA

25°C 0.4 0.67 0.95 0.71 1 1.29

V

I(TRIG)

Trigger voltage

Full range 0.3 1.05 0.61 1.39

V

25°C 10 10

p

I

I(TRIG)

Trigger current

MAX 75 150

pA

25°C 0.4 1.1 1.5 0.4 1.1 1.5

V

I(RESET)

Reset voltage

Full range 0.3 2 0.3 1.8

V

25°C 10 10

p

I

I(RESET)

Reset current

MAX 75 150

pA

Control voltage (open circuit) as
a percentage of supply voltage

MAX 66.7% 66.7%

Discharge switch on-stage

25°C 0.03 0.2 0.03 0.2

gg

voltage

I

OL

= 1

mA

Full range 0.25 0.375

V

Discharge switch off-stage

25°C 0.1 0.1

gg

current

MAX 0.5 120

nA

p

25°C 1.5 1.9 1.5 1.9

VOHHigh-level output voltage

I

OH

= –

300 µA

Full range 1.5 2.5

V

p

25°C 0.07 0.3 0.07 0.3

VOLLow-level output voltage

I

OL

= 1

mA

Full range 0.35 0.4

V

pp

25°C 250 250

IDDSupply current

See Note 2

Full range 400 500

µ

A

†

Full range is 0°C to 70°C for the TLC555C and – 40°C to 85°C for the TLC555I. For conditions shown as MAX, use the appropriate value specified
in the recommended operating conditions table.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.