Texas Instruments TLC3702MJGB, TLC3702MJG, TLC3702MFKB, TLC3702MDR, TLC3702MD Datasheet
...
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Push-Pull CMOS Output Drives Capacitive
Loads Without Pullup Resistor,
I
O
= ± 8 mA
D
Very Low Power...100 µW Typ at 5 V
D
Fast Response Time ...t
PLH
= 2.7 µs Typ
With 5-mV Overdrive
D
Single-Supply Operation...3 V to 16 V
TLC3702M ...4 V to 16 V
D
On-Chip ESD Protection
description
The TLC3702 consists of two independent
micropower voltage comparators designed to
operate from a single supply and be compatible
with modern HCMOS logic systems. They are
functionally similar to the LM339 but use onetwentieth of the power for similar response times.
The push-pull CMOS output stage drives
capacitive loads directly without a powerconsuming pullup resistor to achieve the stated
response time. Eliminating the pullup resistor not
only reduces power dissipation, but also saves
board space and component cost. The output
stage is also fully compatible with TTL
requirements.
Texas Instruments LinCMOS process offers
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS process offers
extremely stable input offset voltages with large
differential input voltages. This characteristic
makes it possible to build reliable CMOS
comparators.
The TLC3702C is characterized for operation over the commercial temperature range of 0°C to 70°C. The
TLC3702I is characterized for operation over the extended industrial temperature range of –40°C to 85°C. The
TLC3702M is characterized for operation over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN–
NC
NC
1IN–
NC
1IN+
NC
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
2IN+
NC
V
NC
GND
NC
NC
DD
D, JG, OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
GND
V
DD
2OUT
2IN–
2IN+
NC – No internal connection
OUT
symbol (each comparator)
IN+
IN–
LinCMOS is a trademark of Texas Instruments Incorporated.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGES
T
A
VIOmax
at 25°C
SMALL OUTLINE
(D)
CERAMIC
(FK)
CERAMIC DIP
(JG)
PLASTIC DIP
(P)
0°C to 70°C 5 mV TLC3702CD — — TLC3702CP
–40°C to 85°C 5 mV TLC3702ID — — TLC3702IP
–55°C to 125°C 5 mV TLC3702MD TLC3702MFK TLC3702MJG —
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC3702CDR).
functional block diagram (each comparator)
V
DD
GND
OUT
Differential
Input
Circuits
IN+
IN–
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
DD
(see Note 1) –0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
ID
(see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.3 V to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
– 0.3 V to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, I
I
±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, I
O
(each output) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total supply current into V
DD
40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLC3702C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC3702I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC3702M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN–.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW 145 mW
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 672 mW 546 mW 210 mW
P 1000 mW 8.0 mW/°C 640 mW 520 mW N/A
recommended operating conditions
TLC3702C
MIN NOM MAX
UNIT
Supply voltage, V
DD
3 5 16 V
Common-mode input voltage, V
IC
– 0.2 VDD – 1.5 V
High-level output current, I
OH
–20 mA
Low-level output current, I
OL
20 mA
Operating free-air temperature, T
A
0 70 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
TLC3702C
PARAMETER
TEST CONDITIONS
†
T
A
MIN TYP MAX
UNIT
p
VDD = 5 V to 10 V,
25°C 1.2 5
VIOInput offset voltage
V
IC
=
V
ICR
min,
See Note 3
0°C to 70°C 6.5
mV
p
25°C 1 pA
IIOInput offset current
V
IC
=
2.5 V
70°C 0.3 nA
p
25°C 5 pA
IIBInput bias current
V
IC
= 2.5
V
70°C 0.6 nA
p
25°C 0 to VDD – 1
V
ICR
Common-mode input voltage range
0°C to 70°C 0 to VDD – 1.5
V
25°C 84
CMRR Common-mode rejection ratio VIC = V
ICR
min
70°C 84
dB
0°C 84
25°C 85
k
SVR
Supply-voltage rejection ratio VDD = 5 V to 10 V
70°C 85
dB
0°C 85
p
V
= 1 V,
25°C 4.5 4.7
VOHHigh-level output voltage
ID
,
IOH = –4 mA
70°C 4.3
V
p
V
= –1 V ,
25°C 210 300
VOLLow-level output voltage
ID
,
IOH = 4 mA
70°C 375
mV
pp
p
p
25°C 18 40
IDDSupply current (both comparators)
Outputs lo
w, No
load
0°C to 70°C 50
µ
A
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
TLC3702I
MIN NOM MAX
UNIT
Supply voltage, V
DD
3 5 16 V
Common-mode input voltage, V
IC
–0.2 VDD – 1.5 V
High-level output current, I
OH
–20 mA
Low-level output current, I
OL
20 mA
Operating free-air temperature, T
A
–40 85 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
TLC3702I
PARAMETER
TEST CONDITIONS
†
T
A
MIN TYP MAX
UNIT
p
VDD = 5 V to 10 V,
25°C 1.2 5
VIOInput offset voltage
DD
VIC = V
ICR
min, See Note 3
–40°C to 85°C 7
mV
p
25°C 1 pA
IIOInput offset current
V
IC
= 2.5
V
85°C 1 nA
p
25°C 5 pA
IIBInput bias current
V
IC
= 2.5
V
85°C 2 nA
p
25°C
0 to
VDD – 1
V
ICR
Common-mode input voltage range
–40°C to 85°C
0 to
VDD – 1.5
V
25°C 84
CMRR Common-mode rejection ratio VIC = V
ICR
min
85°C 84
dB
–40°C 83
25°C 85
k
SVR
Supply-voltage rejection ratio VDD = 5 V to 10 V
85°C 85
dB
–40°C 83
p
25°C 4.5 4.7
VOHHigh-level output voltage
V
ID
= 1 V,
I
OH
= –4
mA
85°C 4.3
V
p
25°C 210 300
VOLLow-level output voltage
V
ID
= –1 V,
I
OH
= –4
mA
85°C 400
mV
pp
p
p
25°C 18 40
IDDSupply current (both comparators)
Outputs lo
w,No
load
–40°C to 85°C 65
µ
A
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
TLC3702M
MIN NOM MAX
UNIT
Supply voltage, V
DD
4 5 16 V
Common-mode input voltage, V
IC
0 VDD – 1.5 V
High-level output current, I
OH
– 20 mA
Low-level output current, I
OL
20 mA
Operating free-air temperature, T
A
– 55 125 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
TLC3702M
PARAMETER
TEST CONDITIONS
†
T
A
MIN TYP MAX
UNIT
p
VDD = 5 V to 10 V,
25°C 1.2 5
VIOInput offset voltage
DD
VIC = V
ICR
min, See Note 3
–55°C to 125°C 10
mV
p
25°C 1 pA
IIOInput offset current
V
IC
= 2.5
V
125°C 15 nA
p
25°C 5 pA
IIBInput bias current
V
IC
= 2.5
V
125°C 30 nA
p
25°C
0 to
VDD – 1
V
ICR
Common-mode input voltage range
–55°C to 125°C
0 to
VDD – 1.5
V
25°C 84
CMRR Common-mode rejection ratio VIC = V
ICR
min
125°C 83
dB
–55°C 82
25°C 85
k
SVR
Supply-voltage rejection ratio VDD = 5 V to 10 V
125°C 85
dB
– 55°C 82
p
25°C 4.5 4.7
VOHHigh-level output voltage
V
ID
= 1 V,
I
OH
= –4
mA
125°C 4.2
V
p
25°C 210 300
VOLLow-level output voltage
V
ID
= –
1 V
,
I
OH
= –
4 mA
125°C 500
mV
pp
p
p
25°C 18 40
IDDSupply current (both comparators)
Outputs lo
w,
No load
–55°C to 125°C 90
µ
A
†
All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3. The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS
TLC3702C, TLC3702I
TLC3702M
UNIT
MIN TYP MAX
Overdrive = 2 mV 4.5
Overdrive = 5 mV 2.7
t
PLH
Propagation delay time, low-to-high-level output
†
f = 10 kHz,
p
Overdrive = 10 mV 1.9
µs
C
L
= 50
F
Overdrive = 20 mV 1.4
Overdrive = 40 mV 1.1
VI = 1.4 V step at IN+ 1.1
Overdrive = 2 mV 4
Overdrive = 5 mV 2.3
t
PHL
Propagation delay time, high-to-low-level output
†
f = 10 kHz,
p
Overdrive = 10 mV 1.5
µs
C
L
= 50
F
Overdrive = 20 mV 0.95
Overdrive = 40 mV 0.65
VI = 1.4 V step at IN+ 0.15
t
f
Fall time
f = 10 kHz,
CL = 50 pF
Overdrive = 50 mV 50 ns
t
r
Rise time
f = 10 kHz,
CL = 50 pF
Overdrive = 50 mV 125 ns
†
Simultaneous switching of inputs causes degradation in output response.
LinCMOS and Advanced LinCMOS are trademarks of Texas Instruments Incorporated.
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
LinCMOS
process
The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply
applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions
from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g., during board assembly . If a circuit in which one amplifier from a dual op amp is being
used and the unused pins are left open, high voltages tend to develop. If there is no provision for ESD protection,
these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage
buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI
ESD-protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
To Protect Circuit
D3
R2
Q2
D2D1
Q1
Input
GND
R1
V
DD
Figure 1. LinCMOS ESD-Protection Schematic
TLC3702
DUAL MICROPOWER LinCMOS VOLTAGE COMPARATORS
SLCS013D – NOVEMBER 1986 – REVISED NOVEMBER 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises
above the voltage on the V
DD
pin by a value equal to the VBE of Q1. The base current increases through R2
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (V
T
∼ 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is
now shunted through the n-channel enhancement-type MOSFET Q2 to V
SS
. If the voltage on the input pin
continues to rise, the breakdown voltage of the zener diode D3 is exceeded and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 V to 27 V , which is well below the
gate-oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V
ICR
and not damage the device
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
±5 mA. Figure 2 and Figure 3 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the V
DD
pin and into the device IDD or the VDD supply through R2
producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input
voltage is below the V
T
of Q2.
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 4).
Loading...