TEXAS INSTRUMENTS TL1454A, TL1454AY Technical data

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

D Two Complete PWM Control Circuits D Outputs Drive MOSFETs Directly D Oscillator Frequency . . . 50 kHz to 2 MHz D 3.6-V to 20-V Supply-Voltage Range D Low Supply Current . . . 3.5 mA Typ D Adjustable Dead-Time Control, 0% to 100% D 1.26-V Reference

description

D, N OR PW PACKAGE

(TOP VIEW)

DTC1

IN1+ IN1–

COMP1

GND

OUT1

3 4 5 6 7 8

16 15 14 13 12 11 10

REF SCP DTC2 IN2+ IN2– COMP2 V

OUT2

The TL1454A is a dual-channel pulse-width-modulation (PWM) control circuit, primarily intended for low-power, dc/dc converters. Applications include LCD displays, backlight inverters, notebook computers, and other products requiring small, high-frequency, dc/dc converters.

Each PWM channel has its own error amplifier, PWM comparator , dead-time control comparator , and MOSFET driver. The voltage reference, oscillator , undervoltage lockout, and short-circuit protection are common to both channels.

Channel 1 is configured to drive n-channel MOSFETs in step-up or flyback converters, and channel 2 is configured to drive p-channel MOSFETs in step-down or inverting converters. The operating frequency is set with an external resistor and an external capacitor, and dead time is continuously adjustable from 0 to 100% duty cycle with a resistive divider network. Soft start can be implemented by adding a capacitor to the dead-time control (DTC) network. The error-amplifier common-mode input range includes ground, which allows the TL1454A to be used in ground-sensing battery chargers as well as voltage converters.

AVAILABLE OPTIONS

PACKAGED DEVICES

–20°C to 85°C TL1454ACD TL1454ACN TL1454ACPWR TL1454ACDB TL1454ACNS TL1454AY

†

The D, DB and NS packages are available taped and reeled. Add the suffix R to the device name (e.g., TL1454ACDR). The PW package is available only left-end taped and reeled (indicated by the R suffix on the device type; e.g., TL1454ACPWR).

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

TSSOP

(PW)

†

SSOP

(DB)

SOP-EIAJ

(NS)

CHIP FORM

(Y)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

functional block diagram

GND

COMP1

IN1+

IN1–

COMP2

IN2+

IN2–

7 6 4

Error

Amplifier 1

11 13

Error

Amplifier 2

Voltage

REF

1.26 V

2.5 V

To Internal Circuitry

SCP

Comparator 2

CTRT

UVLO

and

SCP Latch

OSC

PWM

Comparator 1

PWM

Comparator 2

1.8 V

1.2 V

REF

OUT1

OUT2

1 V

SCP

Comparator 1

SCP

1 V

0.65 V

DTC1 DTC2

0.65 V

1.27 V

143

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TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TL1454AY chip information

This device, when properly assembled, displays characteristics similar to the TL1454AC. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(16)

(1)

(2) (3)

(12)(13)(14)(15)

(4) (5) (6) (7)

108

(10)(11)

(9)

(8)

CT RT

DTC1

IN1+ IN1–

COMP1

GND

(1) (2) (3)

(4) (5)

(6) (7)

(8)

(16)

REF

(15)

SCP

(14)

DTC2

(13)

TL1454AY

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(12)

(11)

(10)

(9)

IN2+ IN2–

COMP2 V

OUT2OUT1

CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

theory of operation

reference voltage

A linear regulator operating from V

generates a 2.5-V supply for the internal circuits and the 1.26-V reference,

which can source a maximum of 1 mA for external loads. A small ceramic capacitor (0.047 µF to 0.1 µF) between REF and ground is recommended to minimize noise pickup.

error amplifier

The error amplifier generates the error signal used by the PWM to adjust the power-switch duty cycle for the desired converter output voltage. The signal is generated by comparing a sample of the output voltage to the voltage reference and amplifying the difference. An external resistive divider connected between the converter output and ground, as shown in Figure 1, is generally required to obtain the output voltage sample.

The amplifier output is brought out on COMP to allow the frequency response of the amplifier to be shaped with an external RC network to stabilize the feedback loop of the converter. DC loading on the COMP output is limited to 45 µA (the maximum amplifier source current capability).

Figure 1 illustrates the sense-divider network and error-amplifier connections for converters with positive output voltages. The divider network is connected to the noninverting amplifier input because the PWM has a phase inversion; the duty cycle decreases as the error-amplifier output increases.

_ +

TL1454A

To PWM

Converter

Output

Compensation

Network

REF

COMP

IN– IN+

Figure 1. Sense Divider/Error Amplifier

Configuration for Converters with Positive Outputs

The output voltage is given by:

where V

VO+ V

= 1.26 V.

ref

1 )

The dc source resistance of the error-amplifier inputs should be 10 kΩ or less and approximately matched to minimize output voltage errors caused by the input-bias current. A simple procedure for determining appropriate values for the resistors is to choose a convenient value for R3 (10 kΩ or less) and calculate R1 and R2 using:

R3V

VO–V

R3V

ref

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TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

error amplifier

R1 and R2 should be tight-tolerance (±1% or better) devices with low and/or matched temperature coefficients to minimize output voltage errors. A device with a ±5% tolerance is suitable for R3.

REF

COMP

ref

Compensation

Network

IN– IN+

_ +

To PWM

Converter

Output

Figure 2. Sense Divider/Error Amplifier Configuration for Converters with Negative Outputs

Figure 2 shows the divider network and error-amplifier configuration for negative output voltages. In general, the comments for positive output voltages also apply for negative outputs. The output voltage is given by:

R1V

The design procedure for choosing the resistor value is to select a convenient value for R2 (instead of R3 in the procedure for positive outputs) and calculate R1 and R3 using:

R2V

R1) R

R1R

ref

V alues in the 10-kΩ to 20-kΩ range work well for R2. R3 can be omitted and the noninverting amplifier connected to ground in applications where the output voltage tolerance is not critical.

oscillator

The oscillator frequency can be set between 50 kHz and 2 MHz with a resistor connected between RT and GND and a capacitor between CT and GND (see Figure 3). Figure 6 is used to determine R

and CT for the desired

operating frequency. Both components should be tight-tolerance, temperature-stable devices to minimize frequency deviation. A 1% metal-film resistor is recommended for R capacitor is recommended for C

TL1454A

RT CT

, and a 10%, or better, NPO ceramic

Figure 3. Oscillator Timing

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TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

dead-time control (DTC) and soft start

The two PWM channels have independent dead-time control inputs so that the maximum power-switch duty cycles can be limited to less then 100%. The dead-time is set with a voltage applied to DTC; the voltage is typically obtained from a resistive divider connected between the reference and ground as shown in Figure 4. Soft start is implemented by adding a capacitor between REF and DTC.

The voltage, V

VDT+ V

where V

O(max)

, required to limit the duty cycle to a maximum value is given by:

O(max)

and V

* D

O(max)

are obtained from Figure 9, and D is the maximum duty cycle.

O(min)

* V

O(min)

* 0.65

Predicting the regulator startup or rise time is complicated because it depends on many variables, including: input voltage, output voltage, filter values, converter topology , and operating frequency. In general, the output will be in regulation within two time constants of the soft-start circuit. A five-to-ten millisecond time constant usually works well for low-power converters.

The DTC input can be grounded in applications where achieving a 100% duty cycle is desirable, such as a buck converter with a very low input-to-output differential voltage. However, grounding DTC prevents the implementation of soft start, and the output voltage overshoot at power-on is likely to be very large. A better arrangement is to omit R cycle can reach 100% and still allows the designer to implement soft start using C

(see Figure 4) and choose R

DT1

DT2

DT1

REF

DTC

= 47 kΩ. This configuration ensures that the duty

DT2

TL1454A

Figure 4. Dead-Time Control and Soft Start

PWM comparator

Each of the PWM comparators has dual inverting inputs. One inverting input is connected to the output of the error amplifier; the other inverting input is connected to the DTC terminal. Under normal operating conditions, when either the error-amplifier output or the dead-time control voltage is higher than that for the PWM triangle wave, the output stage is set inactive (OUT1 low and OUT2 high), turning the external power stage off.

undervoltage-lockout (UVLO) protection

The undervoltage-lockout circuit turns the output circuit off and resets the SCP latch whenever the supply voltage drops too low (to approximately 2.9 V) for proper operation. A hysteresis voltage of 200 mV eliminates false triggering on noise and chattering.

short-circuit protection (SCP)

The TL1454A SCP function prevents damage to the power switches when the converter output is shorted to ground. In normal operation, SCP comparator 1 clamps SCP to approximately 185 mV. When one of the converter outputs is shorted, the error amplifier output (COMP) will be driven below 1 V to maximize duty cycle and force the converter output back up. When the error amplifier output drops below 1 V, SCP comparator 1 releases SCP, and capacitor, C error-amplifier output rises above 1 V before C normal operation resumes. If C

, which is connected between SCP and GND, begins charging. If the

SCP

reaches 1 V , SCP comparator 2 turns on and sets the SCP latch, which turns

SCP

is charged to 1 V , SCP comparator 1 discharges C

SCP

off the output drives and resets the soft-start circuit. The latch remains set until the supply voltage is lowered to 2 V or less, or C

is discharged externally.

SCP

and

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TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

short-circuit protection (SCP) (continued)

The SCP time-out period must be greater than the converter start-up time or the converter will not start. Because high-value capacitor tolerances tend to be ±20% or more and IC resistor tolerances are loose as well, it is best to choose an SCP time-out period 10-to-15 times greater than the converter startup time. The value of C may be determined using Figure 6, or it can be calculated using:

SCP

80.3

SCP

where C

is in µF and T

SCP

is the time-out period in ms.

SCP

output stage

The output stage of the TL1454A is a totem-pole output with a maximum source/sink current rating of 40 mA and a voltage rating of 20 V. The output is controlled by a complementary output AND gate and is turned on (sourcing current for OUT1, sinking current for OUT2) when all the following conditions are met: 1) the oscillator triangle wave voltage is higher than both the DTC voltage and the error-amplifier output voltage, 2) the undervoltage-lockout circuit is inactive, and 3) the short-circuit protection circuit is inactive.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Error amplifier input voltage: IN1+, IN1–, IN2+, IN2– 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage: OUT1, OUT2 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current: OUT1, OUT2 ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current: OUT1, OUT2 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network GND.

(see Note 1) 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: C suffix –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

DISSIPATION RATING TABLE

PACKAGE

D 950 mW 7.6 mW/°C 608 mW 494 mW

DB 1000 mW 8.0 mW/°C 640 mW 520 mW

N 1250 mW 10.0 mW/°C 800 mW 650 mW NS 1953 mW 15.6 mW/°C 1250 mW 1015 mW PW 500 mW 4.0 mW/°C 320 mW 260 mW

TA ≤ 25°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

TL1454A, TL1454AY

25 C

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

recommended operating conditions

MIN MAX UNIT

Supply voltage, V Error amplifier common-mode input voltage –0.2 1.45 V Output voltage, V Output current, I COMP source current –45 µA COMP sink current 100 µA Reference output current 1 mA COMP dc load resistance 100 kΩ Timing capacitor , C Timing resistor , R Oscillator frequency 50 2000 kHz Operating free-air temperature, T

TL1454AC –20 85 °C

electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,

= 500 kHz (unless otherwise noted)

osc

3.6 20 V

20 V

±40 mA

10 4000 pF

5.1 100 kΩ

reference

PARAMETER TEST CONDITIONS

ref

Output voltage, REF Input regulation VOC = 3.6 V to 20 V, IO = 1 mA 2 6 mV

Output regulation IO = 0.1 mA to 1 mA 1 7.5 mV

Output voltage change with temperature

Short-circuit output current V

IO = 1 mA, TA = 25°C 1.22 1.26 1.32 IO = 1 mA

TA = T TA = 25°C to 85°C,

= 0 V 30 mA

ref

to 25°C, IO = 1 mA –12.5 –1.25 12.5

A(min)

undervoltage lockout (UVLO)

PARAMETER TEST CONDITIONS

IT+

IT–

hys

Positive-going threshold voltage 2.9 V Negative-going threshold voltage Hysteresis, V

IT+

– V

IT–

TA = 25°C

short-circuit protection (SCP)

PARAMETER TEST CONDITIONS

†

stby

I(latched)

IT(COMP)

†

This symbol is not presently listed within EIA/JEDEC standards for semiconductor symbology.

Input threshold voltage TA = 25°C 0.93 1 1.07 V Standby voltage Latched-mode input voltage Comparator threshold voltage COMP1, COMP2 1 V Input source current TA = 25°C, V

No pullup

O(SCP)

TL1454A

MIN TYP MAX

1.20 1.34

IO = 1 mA –12.5 –2.5 12.5

TL1454A

MIN TYP MAX

2.7 V

100 200 mV

TL1454A

MIN TYP MAX

140 185 230 mV

60 120 mV

= 0 –5 –15 –20 µA

UNIT

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TL1454A, TL1454AY

1.25 V,

1.25 V

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f

= 500 kHz (unless otherwise noted) (continued)

osc

oscillator

PARAMETER TEST CONDITIONS

osc

Frequency CT = 120 pF, RT = 10 kΩ 500 kHz Standard deviation of frequency 50 kHz Frequency change with voltage VCC = 3.6 V to 20 V, TA = 25°C 10 kHz

Frequency change with temperature

Maximum ramp voltage 1.8 V Minimum ramp voltage 1.1 V

dead-time control (DTC)

PARAMETER TEST CONDITIONS

I(latched)

Input threshold voltage Latched-mode input voltage 1.2 V

Common-mode input bias current DTC1, IN1+ ≈ 1.2 V 4 µA Latched-mode (source) current TA = 25°C –100 µA

TA = T TA = 25°C to 85°C

Duty cycle = 0% 0.98 1.1 1.22 Duty cycle = 100%

to 25°C –2 ±30

A(min)

TL1454A

MIN TYP MAX

–10 ±30

TL1454A

MIN TYP MAX

0.38 0.5 0.62

UNIT

kHz

UNIT

error-amplifier

PARAMETER TEST CONDITIONS

ICR

CMRR Common-mode rejection ratio 60 80 dB V

OM(max)

OM(min)

O+

O–

Input offset voltage 6 mV Input offset current Input bias current Input voltage range VCC = 3.6 V to 20 V –0.2 to 1.40 V Open-loop voltage gain RFB = 200 kΩ 70 80 dB Unity-gain bandwidth 3 MHz

Positive output voltage swing 2.3 2.43 Negative output voltage swing 0.63 0.8 Output sink current VID = –0.1 V , VO = 1.20 V 0.1 0.5 mA Output source current VID = 0.1 V, VO = 1.80 V –45 –70 µA

VO = 1.25 V, VIC = 1.25 V

TL1454A

MIN TYP MAX

100 nA

–160 –500 nA

output

PARAMETER TEST CONDITIONS

IO = –8 mA VCC–2 4.5

High-level output voltage

Low-level output voltage Output voltage rise time

Output voltage fall time

IO = –8 mA @ VCC = >10 V VCC–2.3 V IO = –40 mA IO = 40 mA @ VCC = >10 V VCC–2.3 V IO = 8 mA 0.1 0.4 IO = 40 mA

CL = 2000 pF, TA = 25°C

TL1454A

MIN TYP MAX

VCC–2 4.4

1.8 2.5 220 220

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f

= 500 kHz (unless otherwise noted) (continued)

osc

supply current

TL1454A

MIN TYP MAX

3.1 6 mA

3.5 7 mA

UNIT

CC(stby)

CC(average)

PARAMETER TEST CONDITIONS

Standby supply current

Average supply current

RT open, CT = 1.5 V, No load, VO (COMP1, COMP2) = 1.25 V,

RT = 10 kΩ, 50% duty cycle,

CT = 120 pF, Outputs open

electrical characteristics, VCC = 6 V, f

= 500 kHz, TA = 25°C (unless otherwise noted)

osc

reference

PARAMETER TEST CONDITIONS

ref

Output voltage, REF IO = 1 mA 1.26 V Input regulation VOC = 3.6 V to 20 V, IO = 1 mA 2 mV Output regulation IO = 0.1 mA to 1 mA 1 mV

Output voltage change with temperature

Short-circuit output current V

IO = 1 mA –1.25 IO = 1 mA

= 0 V 30 mA

ref

undervoltage lockout (UVLO)

PARAMETER TEST CONDITIONS

IT+

IT–

hys

Positive-going threshold voltage 2.9 V Negative-going threshold voltage 2.7 V Hysteresis, V

IT+

– V

IT–

short-circuit protection (SCP)

PARAMETER TEST CONDITIONS

†

stby

I(latched)

IT(COMP)

†

This symbol is not presently listed within EIA/JEDEC standards for semiconductor symbology.

Input threshold voltage 1 V Standby voltage Latched-mode input voltage Comparator threshold voltage COMP1, COMP2 1 V Input source current V

No pullup

O(SCP)

= 0 –15 µA

TL1454AY

MIN TYP MAX

–2.5

TL1454AY

MIN TYP MAX

200 mV

TL1454AY

MIN TYP MAX

185 mV

60 mV

UNIT

oscillator

osc

PARAMETER TEST CONDITIONS

Frequency CT = 120 pF, RT = 10 kΩ 500 kHz Standard deviation of frequency 50 kHz Frequency change with voltage VCC = 3.6 V to 20 V 10 kHz

Frequency change with temperature

Maximum ramp voltage 1.8 V Minimum ramp voltage 1.1 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TA = T TA = 25

to 25°C –2

A(min)

°C to 85°C –10

TL1454AY

MIN TYP MAX

UNIT

kHz

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

electrical characteristics, VCC = 6 V , f

= 500 kHz, TA = 25°C (unless otherwise noted) (continued)

osc

dead-time control (DTC)

TL1454AY

MIN TYP MAX

0.5

I(latched)

PARAMETER TEST CONDITIONS

Input threshold voltage Latched-mode input voltage 1.2 V

Latched-mode (source) current –100 µA

Duty cycle = 0% 1.1 Duty cycle = 100%

error-amplifier

PARAMETER TEST CONDITIONS

CMRR Common-mode rejection ratio 80 dB V

OM(max)

OM(min)

O+

O–

Input bias current VO = 1.25 V, VIC = 1.25 V –160 nA Open-loop voltage gain RFB = 200 kΩ 80 dB Unity-gain bandwidth 3 MHz

Positive output voltage swing 2.43 Negative output voltage swing 0.63 Output sink current VID = –0.1 V , VO = 1.20 V 0.5 mA Output source current VID = 0.1 V, VO = 1.80 V –70 µA

TL1454AY

MIN TYP MAX

output

PARAMETER TEST CONDITIONS

High-level output voltage

Low-level output voltage Output voltage rise time

Output voltage fall time

IO = –8 mA 4.5 IO = –40 mA IO = 8 mA 0.1 IO = 40 mA

CL = 2000 pF

TL1454AY

MIN TYP MAX

4.4

1.8 220 220

UNIT

supply current

CC(stby)

CC(average)

PARAMETER TEST CONDITIONS

Standby supply current

Average supply current

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RT open, CT = 1.5 V, No load, VO (COMP1, COMP2) = 1.25 V,

RT = 10 kΩ, 50% duty cycle,

CT = 120 pF, Outputs open

TL1454AY

MIN TYP MAX

3.1 mA

3.5 mA

UNIT

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

PARAMETER MEASUREMENT INFORMATION

Oscillator

COMP

DTC

SCP Reference

OUT1

OUT2

SCP Comparator

Output

SCP

2.9-V Typical Lockout threshold

1.8 V

1.2 V 1 V

Dead-Time 100%

L H

Dead-Time 100%

L H

2.5 V

1 V 0 V

(tpe)

0 V

Figure 5. Timing Diagram

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

TYPICAL CHARACTERISTICS

TL1454A, TL1454AY

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

OSCILLATOR FREQUENCY

TIMING RESISTANCE

10 M

100 k

f – Oscillator Frequency – Hz

VCC = 6 V TA = 25°C

1 M

CT = 300 pF

CT = 1000 pF

10 k

1 k

1 k 10 k 100 k

CT = 3900 pF

RT – Timing Resistance – Ω

CT = 10 pF

CT = 120 pF

Figure 6

OSCILLATOR PERIOD

VCC = 6 V RT = 5.1 kΩ TA = 25°C

sµ

t – Oscillation Period –

–1

TIMING CAPACITANCE

CT – Timing Capacitance – pF

Figure 7

OSCILLATOR FREQUENCY

FREE-AIR TEMPERATURE

530

VCC = 6 V RT = 10 kΩ CT = 120 pF

520

510

500

– Oscillator Frequency – kHz

490

osc

480

–50 0 50 100

TA – Free-Air Temperature – °C

Figure 8

PWM TRIANGLE WAVEFORM AMPLITUDE

TIMING CAPACITANCE

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1 1

0.9

0.8

VCC = 6 V

0.7

PWM Triangle Waveform Amplitude – V

0.6

0.5 10

RT = 5.1 kΩ TA = 25°C

Timing Capacitance – pF

O(min)

O(max)

Figure 9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

DTC INPUT THRESHOLD VOLTAGE

FREE-AIR TEMPERATURE

1.4 VCC = 6 V

RT = 5.1 kΩ CT = 1000 pF

1.2

VIT (0% Duty Cycle)

0.8

0.6

DTC Input Threshold Voltage – V

VIT (100% Duty Cycle)

0.4

–50

TA – Free-Air Temperature – °C

0 50 100

1.5

0.5

– SCP Time-Out Period – s

SCP

0 5 10 15

Figure 10

SCP TIME-OUT PERIOD

SCP CAPACITANCE

VCC = 6 V TA = 25°C

20 25

SCP Capacitance – µF

Figure 11

SCP THRESHOLD VOLTAGE

FREE-AIR TEMPERATURE

1.04

1.02

0.98

– SCP Threshold Voltage – V

0.96

0.94 –50

0 50 100

TA – Free-Air Temperature – °C

VCC = 6 V

3.5

2.5

– SCP Latch Reset Voltage – V

1.5

I(reset)

Figure 12

SCP LATCH RESET VOLTAGE

FREE-AIR TEMPERATURE

VCC = 6 V

–25 0 25 50 75 100–50

TA – Free-Air Temperature – °C

Figure 13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

TYPICAL CHARACTERISTICS

TL1454A, TL1454AY

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

– UVLO Threshold Voltage – V

IT(L)

IT(H)

3.5

2.5

1.5

1 –50

UVLO THRESHOLD VOLTAGE

FREE-AIR TEMPERATURE

IT(H)

IL(L)

–25 0 25 50 75 100

TA – Free-Air Temperature – °C

Figure 14

Duty Cycle – %

120

100

DUTY CYCLE

DTC INPUT VOLTAGE

VCC = 6 V CT = 120 pF RT = 10 kΩ TA = 25°C

0.25

I(DTC)

0.75

0.5 – DTC Input Voltage – V

1.25

1.5

Figure 15

ERROR-AMPLIFIER MAXIMUM OUTPUT VOLTAGE

SOURCE CURRENT

2.5

1.5

0.5

– Error-Amplifier Maximum Output Voltage – V

OM +

04080

Source Current – µA

VCC = 6 V VID = 0.1 V TA = 25°C

Figure 16 Figure 17

120

ERROR-AMPLIFIER MINIMUM OUTPUT VOLTAGE

SINK CURRENT

2.5 VCC = 6 V VID = 0.1 V

1.5

0.5

– Error-Amplifier Minimum Output Voltage – V

OM –

0 0.5 1 1.5

Sink Current – mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

ERROR AMPLIFIER MAXIMUM

PEAK-TO-PEAK OUTPUT VOLTAGE SWING

FREQUENCY

2.5 VCC = 6 V

TA = 25°C

1.5

Output Voltage Swing – V

0.5

– Error Amplifier Maximum Peak-to-Peak

O(PP)

1 k 10 k 100 k 1M 10 M 100 M

f – Frequency – Hz

Figure 18

– Error-Ampplifier Minimum Output Voltage Swing – V

OM+

ERROR-AMPLIFIER MINIMUM OUTPUT

VOLTAGE SWING

FREE-AIR TEMPERATURE

0.8 VCC = 6 V

No Load Amplifier 1

0.7

0.6

0.5

0.4

0.3

–25 0 25 50 75 100–50

TA – Free-Air Temperature – °C

Figure 19

ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE SHIFT

FREQUENCY

VCC = 6 V TA = 25°C

Phase Shift

Error Amplifier Open-Loop Gain – dB

–20

100 1 k 10 k 100 k 1M 10 M

Gain

f – Frequency – Hz

–0°

–36°

–72°

–108°

–144°

–180°

Figure 20

Phase Shift

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.5

2.45

2.4

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

ERROR-AMPLIFIER POSITIVE OUTPUT

VOLTAGE SWING

FREE-AIR TEMPERATURE

VCC = 6 V No Load Amplifier 1

– High-Level Output Voltage – V

– Error-Ampplifier Positive Output Voltage Swing – V

OM+

2.35 –25 0 25 50 75 100–50

– Free-Air Temperature – °C

Figure 21

HIGH-LEVEL OUTPUT VOLTAGE

OUTPUT CURRENT

VCC = 6 V TA = 25°C

– High-Level Output Voltage – V

5.5

4.5

3.5

HIGH-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

VCC = 6 V

IO = 8 mA

IO = 40 mA

020406080

IO – Output Current – mA

Figure 22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

–25 0 25 50 75 100–50

TA – Free-Air Temperature – °C

Figure 23

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

VCC = 6 V TA = 25°C

– Low-Level Output Voltage – V

020406080

IOL – Low-Level Output Current – mA

Figure 24

– Low-Level Output Voltage – mV

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

250

VCC = 6 V IO = 8 mA

200

150

100

–25 0 25 50 75 100–50

TA – Free-Air Temperature – °C

Figure 25

– Low-Level Output Voltage – V

2.5

1.5

0.5

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

VCC = 6 V IO = 40 mA

–25 0 25 50 75 100–50

TA – Free-Air Temperature – °C

Figure 26

AVERAGE SUPPLY CURRENT

FREE-AIR TEMPERATURE

VCC = 6 V RT = 10 kΩ CT = 1.5 V

COMP1, COMP2 = 1.25 V No Load

– Average Supply Current – mA

CC(a)

1 –50 –25 0 25 50 75

TA – Free-Air Temperature – °C

Figure 27

100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

TYPICAL CHARACTERISTICS

TL1454A, TL1454AY

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

STANDBY SUPPLY CURRENT

SUPPLY VOLTAGE

VCC = 6 V RT = Open CT = 1.5 V

COMP1, COMP2 = 1.25 V No Load TA = 25°C

– Standby Supply Current – mA

CC(stby)

0 5 10 15 20 25

VCC – Supply Voltage – V

Figure 28

STANDBY SUPPLY CURRENT

FREE-AIR TEMPERATURE

VCC = 6 V CT = 1.5 V RT = Open

COMP1, COMP2 = 1.25 V No Load

– Standby Supply Current – mA

CC(stby)

– 50 0 50

TA – Free-Air Temperature – °C

Figure 29

100

REFERENCE VOLTAGE

SUPPLY VOLTAGE

1.5 TA = 25°C

0.5

– Reference Voltage – V

ref

0 5 10 15 20 25

VCC – Supply Voltage – V

Figure 30

REFERENCE VOLTAGE

SUPPLY VOLTAGE

1.27

1.26

1.25

– Reference Voltage – V

1.24

ref

1.23 0 5 10 15 20 25

VCC – Supply Voltage – V

IO = 1mA TA = 25°C

Figure 31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

1.27 VCC = 6 V IO = –1 mA

1.26

1.25

– Reference Voltage – V

ref

1.24

1.23

–50

–25 0 25 50 75 100

TA – Free-Air Temperature – °C

Figure 32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.069 (1,75) MAX

0.050 (1,27)

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

PINS **

DIM

A MAX

A MIN

0.008 (0,20) NOM

Gage Plane

0°–ā8°

0.197

(5,00)

0.189

(4,80)

0.344 (8,75)

0.337

(8,55)

0.394

(10,00)

0.386 (9,80)

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

4040047/B 10/94

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad E. Falls within JEDEC MS-012

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

MECHANICAL DATA

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

2,00 MAX

0,38 0,22

0,05 MIN

0,15

5,60 5,00

8,20 7,40

Seating Plane

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

6,50

5,905,90

2016

7,50

6,90

8,50

10,50

9,907,90

10,50

9,90

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PIN SHOWN

PINS **

DIM

0.035 (0,89) MAX

0.021 (0,53)

0.015 (0,38)

0.070 (1,78) MAX

0.020 (0,51) MIN

0.100 (2,54)

0.010 (0,25)

A MAX

0.260 (6,60)

0.240 (6,10)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.010 (0,25) NOM

A MIN

Seating Plane

0.775

(19,69)

0.745

(18,92)

0.775

(19,69)

0.745

(18,92)

0.920

(23.37)

0.850

(21.59)

0.975

(24,77)

0.940

(23,88)

0.310 (7,87)

0.290 (7,37)

0°–ā15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

14 Pin Only

4040049/C 7/95

TL1454A, TL1454AY DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

MECHANICAL DATA

NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

1,27

2,00 MAX

0,51 0,35

5,60 5,00

0,05 MIN

0,25

8,20 7,40

Seating Plane

0,10

0,15 NOM

Gage Plane

0°–ā10°

0,25

1,05 0,55

DIM

A MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

PINS **

A MIN

10,501410,50

9,90 9,90

20 24

15,3012,90

12,30 14,70

4040062/B 02/95

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

1,20 MAX

0,10 MIN

0,32 0,17

6,70

4,70 4,30

6,10

0,13

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–ā8°

0,70 0,40

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

3,30

2,90

5,30

4,90

5,30

6,80

6,404,90

8,10

7,70

10,00

9,60

4040064/B 10/94

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Mar-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

TL1454ACD ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

TL1454ACDB ACTIVE SSOP DB 16 80 Green (RoHS &

no Sb/Br)

TL1454ACDBG4 ACTIVE SSOP DB 16 80 Green (RoHS &

no Sb/Br)

TL1454ACDBR ACTIVE SSOP DB 16 2000 Green (RoHS &

no Sb/Br)

TL1454ACDBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS &

no Sb/Br)

TL1454ACDG4 ACTIVE SOIC D 16 40 Green (RoHS &

no Sb/Br)

TL1454ACDR ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

TL1454ACDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &

no Sb/Br)

TL1454ACN ACTIVE PDIP N 16 25 Pb-Free

TL1454ACNE4 ACTIVE PDIP N 16 25 Pb-Free

TL1454ACNSR ACTIVE SO NS 16 2000 Green (RoHS &

no Sb/Br)

TL1454ACNSRG4 ACTIVE SO NS 16 2000 Green(RoHS &

no Sb/Br)

TL1454ACPW ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

TL1454ACPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

no Sb/Br)

TL1454ACPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

TL1454ACPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

16-Mar-2007

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

TL1454ACDBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

TL1454ACDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

TL1454ACNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL1454ACPWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL1454ACDBR SSOP DB 16 2000 346.0 346.0 33.0

TL1454ACDR SOIC D 16 2500 346.0 346.0 33.0

TL1454ACNSR SO NS 16 2000 346.0 346.0 33.0

TL1454ACPWR TSSOP PW 16 2000 346.0 346.0 29.0

Pack Materials-Page 2

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS TL1454A, TL1454AY Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

description

functional block diagram

TL1454AY chip information

theory of operation

reference voltage

error amplifier

error amplifier

oscillator

dead-time control (DTC) and soft start

PWM comparator

undervoltage-lockout (UVLO) protection

short-circuit protection (SCP)

output stage

recommended operating conditions

reference

undervoltage lockout (UVLO)

short-circuit protection (SCP)

oscillator

dead-time control (DTC)

error-amplifier

output

supply current

reference

undervoltage lockout (UVLO)

short-circuit protection (SCP)

oscillator

dead-time control (DTC)

error-amplifier

output

supply current

PARAMETER MEASUREMENT INFORMATION

TYPICAL CHARACTERISTICS

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE