TEXAS INSTRUMENTS TL1454A, TL1454AY Technical data

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

D Two Complete PWM Control Circuits
D Outputs Drive MOSFETs Directly
D Oscillator Frequency . . . 50 kHz to 2 MHz
D 3.6-V to 20-V Supply-Voltage Range
D Low Supply Current . . . 3.5 mA Typ
D Adjustable Dead-Time Control, 0% to 100%
D 1.26-V Reference

description

D, N OR PW PACKAGE

(TOP VIEW)

CT

1

RT

2

DTC1

IN1+
IN1–

COMP1

GND

OUT1

3
4
5
6
7
8

16
15
14
13
12
11
10

9

REF
SCP
DTC2
IN2+
IN2–
COMP2
V

CC

OUT2

The TL1454A is a dual-channel pulse-width-mod­ulation (PWM) control circuit, primarily intended
for low-power, dc/dc converters. Applications
include LCD displays, backlight inverters, note­book computers, and other products requiring
small, high-frequency, dc/dc converters.

Each PWM channel has its own error amplifier, PWM comparator , dead-time control comparator , and MOSFET
driver. The voltage reference, oscillator , undervoltage lockout, and short-circuit protection are common to both
channels.

Channel 1 is configured to drive n-channel MOSFETs in step-up or flyback converters, and channel 2 is
configured to drive p-channel MOSFETs in step-down or inverting converters. The operating frequency is set
with an external resistor and an external capacitor, and dead time is continuously adjustable from 0 to 100%
duty cycle with a resistive divider network. Soft start can be implemented by adding a capacitor to the dead-time
control (DTC) network. The error-amplifier common-mode input range includes ground, which allows the
TL1454A to be used in ground-sensing battery chargers as well as voltage converters.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

–20°C to 85°C TL1454ACD TL1454ACN TL1454ACPWR TL1454ACDB TL1454ACNS TL1454AY

†

The D, DB and NS packages are available taped and reeled. Add the suffix R to the device name (e.g., TL1454ACDR). The PW package is
available only left-end taped and reeled (indicated by the R suffix on the device type; e.g., TL1454ACPWR).

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

TSSOP

(PW)

†

SSOP

(DB)

SOP-EIAJ

(NS)

CHIP FORM

(Y)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2002, Texas Instruments Incorporated

1

TL1454A, TL1454AY
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

functional block diagram

GND

COMP1

IN1+

IN1–

COMP2

IN2+

IN2–

7
6
4

+

5

_

Error

Amplifier 1

11
13

+

12

_

Error

Amplifier 2

V

CC

10

Voltage

REF

1.26 V

2.5 V

To Internal
Circuitry

SCP

Comparator 2

CTRT

21

UVLO

and

SCP Latch

OSC

PWM

Comparator 1

PWM

Comparator 2

1.8 V

1.2 V

16

REF

V

CC

8

OUT1

V

CC

9

OUT2

1 V

SCP

Comparator 1

SCP

15

1 V

0.65 V

DTC1 DTC2

0.65 V

1.27 V

143

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

TL1454AY chip information

This device, when properly assembled, displays characteristics similar to the TL1454AC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

(16)

86

(1)

(2) (3)

(12)(13)(14)(15)

(4) (5) (6) (7)

108

(10)(11)

(9)

(8)

CT
RT

DTC1

IN1+
IN1–

COMP1

GND

(1)
(2)
(3)

(4)
(5)

(6)
(7)

(8)

(16)

REF

(15)

SCP

(14)

DTC2

(13)

TL1454AY

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(12)

(11)

(10)

(9)

IN2+
IN2–

COMP2
V

CC

OUT2OUT1

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.

3

TL1454A, TL1454AY
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

theory of operation

reference voltage

A linear regulator operating from V

generates a 2.5-V supply for the internal circuits and the 1.26-V reference,

CC

which can source a maximum of 1 mA for external loads. A small ceramic capacitor (0.047 µF to 0.1 µF) between
REF and ground is recommended to minimize noise pickup.

error amplifier

The error amplifier generates the error signal used by the PWM to adjust the power-switch duty cycle for the
desired converter output voltage. The signal is generated by comparing a sample of the output voltage to the
voltage reference and amplifying the difference. An external resistive divider connected between the converter
output and ground, as shown in Figure 1, is generally required to obtain the output voltage sample.

The amplifier output is brought out on COMP to allow the frequency response of the amplifier to be shaped with
an external RC network to stabilize the feedback loop of the converter. DC loading on the COMP output is limited
to 45 µA (the maximum amplifier source current capability).

Figure 1 illustrates the sense-divider network and error-amplifier connections for converters with positive output
voltages. The divider network is connected to the noninverting amplifier input because the PWM has a phase
inversion; the duty cycle decreases as the error-amplifier output increases.

_
+

TL1454A

To PWM

Converter

Output

Compensation

V

O

Network

R3

R1

REF

COMP

IN–
IN+

R2

Figure 1. Sense Divider/Error Amplifier

Configuration for Converters with Positive Outputs

The output voltage is given by:

R1

where V

VO+ V

= 1.26 V.

ref

ref

ǒ

1 )

R2

Ǔ

The dc source resistance of the error-amplifier inputs should be 10 kΩ or less and approximately matched to
minimize output voltage errors caused by the input-bias current. A simple procedure for determining appropriate
values for the resistors is to choose a convenient value for R3 (10 kΩ or less) and calculate R1 and R2 using:

R3V

VO–V

R3V

V

ref

O

ref

O

R

+

1

R

+

2

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

error amplifier

R1 and R2 should be tight-tolerance (±1% or better) devices with low and/or matched temperature coefficients
to minimize output voltage errors. A device with a ±5% tolerance is suitable for R3.

REF

COMP

ref

Compensation

Network

R3

IN–
IN+

_
+

To PWM

R2

R1

Converter

Output

V

O

Figure 2. Sense Divider/Error Amplifier Configuration for Converters with Negative Outputs

Figure 2 shows the divider network and error-amplifier configuration for negative output voltages. In general,
the comments for positive output voltages also apply for negative outputs. The output voltage is given by:

R1V

V

+*

O

R

2

The design procedure for choosing the resistor value is to select a convenient value for R2 (instead of R3 in
the procedure for positive outputs) and calculate R1 and R3 using:

R2V

R

R

+*

1

+

3

R1) R

V

R1R

O

ref

2

2

V alues in the 10-kΩ to 20-kΩ range work well for R2. R3 can be omitted and the noninverting amplifier connected
to ground in applications where the output voltage tolerance is not critical.

oscillator

The oscillator frequency can be set between 50 kHz and 2 MHz with a resistor connected between RT and GND
and a capacitor between CT and GND (see Figure 3). Figure 6 is used to determine R

and CT for the desired

T

operating frequency. Both components should be tight-tolerance, temperature-stable devices to minimize
frequency deviation. A 1% metal-film resistor is recommended for R
capacitor is recommended for C

.

T

TL1454A

RT CT

21

R

T

C

T

, and a 10%, or better, NPO ceramic

T

Figure 3. Oscillator Timing

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TL1454A, TL1454AY
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

dead-time control (DTC) and soft start

The two PWM channels have independent dead-time control inputs so that the maximum power-switch duty
cycles can be limited to less then 100%. The dead-time is set with a voltage applied to DTC; the voltage is
typically obtained from a resistive divider connected between the reference and ground as shown in Figure 4.
Soft start is implemented by adding a capacitor between REF and DTC.

The voltage, V

VDT+ V

where V

O(max)

, required to limit the duty cycle to a maximum value is given by:

DT

O(max)

and V

ǒ

* D

V

O(max)

are obtained from Figure 9, and D is the maximum duty cycle.

O(min)

* V

O(min)

Ǔ

* 0.65

Predicting the regulator startup or rise time is complicated because it depends on many variables, including:
input voltage, output voltage, filter values, converter topology , and operating frequency. In general, the output
will be in regulation within two time constants of the soft-start circuit. A five-to-ten millisecond time constant
usually works well for low-power converters.

The DTC input can be grounded in applications where achieving a 100% duty cycle is desirable, such as a buck
converter with a very low input-to-output differential voltage. However, grounding DTC prevents the
implementation of soft start, and the output voltage overshoot at power-on is likely to be very large. A better
arrangement is to omit R
cycle can reach 100% and still allows the designer to implement soft start using C

(see Figure 4) and choose R

DT1

R

DT2

R

DT1

C

SS

16

REF

DTC

= 47 kΩ. This configuration ensures that the duty

DT2

TL1454A

SS

.

Figure 4. Dead-Time Control and Soft Start

PWM comparator

Each of the PWM comparators has dual inverting inputs. One inverting input is connected to the output of the
error amplifier; the other inverting input is connected to the DTC terminal. Under normal operating conditions,
when either the error-amplifier output or the dead-time control voltage is higher than that for the PWM triangle
wave, the output stage is set inactive (OUT1 low and OUT2 high), turning the external power stage off.

undervoltage-lockout (UVLO) protection

The undervoltage-lockout circuit turns the output circuit off and resets the SCP latch whenever the supply
voltage drops too low (to approximately 2.9 V) for proper operation. A hysteresis voltage of 200 mV eliminates
false triggering on noise and chattering.

short-circuit protection (SCP)

The TL1454A SCP function prevents damage to the power switches when the converter output is shorted to
ground. In normal operation, SCP comparator 1 clamps SCP to approximately 185 mV. When one of the
converter outputs is shorted, the error amplifier output (COMP) will be driven below 1 V to maximize duty cycle
and force the converter output back up. When the error amplifier output drops below 1 V, SCP comparator 1
releases SCP, and capacitor, C
error-amplifier output rises above 1 V before C
normal operation resumes. If C

, which is connected between SCP and GND, begins charging. If the

SCP

reaches 1 V , SCP comparator 2 turns on and sets the SCP latch, which turns

SCP

is charged to 1 V , SCP comparator 1 discharges C

SCP

off the output drives and resets the soft-start circuit. The latch remains set until the supply voltage is lowered
to 2 V or less, or C

is discharged externally.

SCP

SCP

and

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

short-circuit protection (SCP) (continued)

The SCP time-out period must be greater than the converter start-up time or the converter will not start. Because
high-value capacitor tolerances tend to be ±20% or more and IC resistor tolerances are loose as well, it is best
to choose an SCP time-out period 10-to-15 times greater than the converter startup time. The value of C
may be determined using Figure 6, or it can be calculated using:

T

+

SCP

80.3

C

SCP

SCP

where C

is in µF and T

SCP

is the time-out period in ms.

SCP

output stage

The output stage of the TL1454A is a totem-pole output with a maximum source/sink current rating of 40 mA
and a voltage rating of 20 V. The output is controlled by a complementary output AND gate and is turned on
(sourcing current for OUT1, sinking current for OUT2) when all the following conditions are met: 1) the oscillator
triangle wave voltage is higher than both the DTC voltage and the error-amplifier output voltage, 2) the
undervoltage-lockout circuit is inactive, and 3) the short-circuit protection circuit is inactive.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

Error amplifier input voltage: IN1+, IN1–, IN2+, IN2– 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage: OUT1, OUT2 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current: OUT1, OUT2 ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak output current: OUT1, OUT2 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T
Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network GND.

(see Note 1) 23 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

: C suffix –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

A

†

DISSIPATION RATING TABLE

PACKAGE

D 950 mW 7.6 mW/°C 608 mW 494 mW

DB 1000 mW 8.0 mW/°C 640 mW 520 mW

N 1250 mW 10.0 mW/°C 800 mW 650 mW
NS 1953 mW 15.6 mW/°C 1250 mW 1015 mW
PW 500 mW 4.0 mW/°C 320 mW 260 mW

TA ≤ 25°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

POWER RATING

TA = 85°C

7

TL1454A, TL1454AY

T

A

25 C

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)
CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

recommended operating conditions

MIN MAX UNIT

Supply voltage, V
Error amplifier common-mode input voltage –0.2 1.45 V
Output voltage, V
Output current, I
COMP source current –45 µA
COMP sink current 100 µA
Reference output current 1 mA
COMP dc load resistance 100 kΩ
Timing capacitor , C
Timing resistor , R
Oscillator frequency 50 2000 kHz
Operating free-air temperature, T

CC

O

O

T

T

A

TL1454AC –20 85 °C

electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,

= 500 kHz (unless otherwise noted)

f

osc

3.6 20 V

20 V

±40 mA

10 4000 pF

5.1 100 kΩ

reference

PARAMETER TEST CONDITIONS

V

I

ref

OS

Output voltage, REF
Input regulation VOC = 3.6 V to 20 V, IO = 1 mA 2 6 mV

Output regulation IO = 0.1 mA to 1 mA 1 7.5 mV

p

Output voltage change with temperature

Short-circuit output current V

p

IO = 1 mA, TA = 25°C 1.22 1.26 1.32
IO = 1 mA

TA = T
TA = 25°C to 85°C,

= 0 V 30 mA

ref

to 25°C, IO = 1 mA –12.5 –1.25 12.5

A(min)

undervoltage lockout (UVLO)

PARAMETER TEST CONDITIONS

V

IT+

V

IT–

V

hys

Positive-going threshold voltage 2.9 V
Negative-going threshold voltage
Hysteresis, V

IT+

– V

IT–

TA = 25°C

short-circuit protection (SCP)

PARAMETER TEST CONDITIONS

V

IT

†

V

stby

V

I(latched)

V

IT(COMP)

†

This symbol is not presently listed within EIA/JEDEC standards for semiconductor symbology.

Input threshold voltage TA = 25°C 0.93 1 1.07 V
Standby voltage
Latched-mode input voltage
Comparator threshold voltage COMP1, COMP2 1 V
Input source current TA = 25°C, V

No pullup

O(SCP)

TL1454A

MIN TYP MAX

1.20 1.34

IO = 1 mA –12.5 –2.5 12.5

TL1454A

MIN TYP MAX

2.7 V

100 200 mV

TL1454A

MIN TYP MAX

140 185 230 mV

60 120 mV

= 0 –5 –15 –20 µA

UNIT

V

mV

UNIT

UNIT

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL1454A, TL1454AY

V

O

1.25 V,

V

IC

1.25 V

DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM)

CONTROL CIRCUIT

SLVS423 A– MAY 2002 – REVISED SEPTEMBER 2002

electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
f

= 500 kHz (unless otherwise noted) (continued)

osc

oscillator

PARAMETER TEST CONDITIONS

f

osc

Frequency CT = 120 pF, RT = 10 kΩ 500 kHz
Standard deviation of frequency 50 kHz
Frequency change with voltage VCC = 3.6 V to 20 V, TA = 25°C 10 kHz

Frequency change with temperature

Maximum ramp voltage 1.8 V
Minimum ramp voltage 1.1 V

dead-time control (DTC)

PARAMETER TEST CONDITIONS

V

IT

V

I(latched)

I

IB

Input threshold voltage
Latched-mode input voltage 1.2 V

Common-mode input bias current DTC1, IN1+ ≈ 1.2 V 4 µA
Latched-mode (source) current TA = 25°C –100 µA

p

TA = T
TA = 25°C to 85°C

Duty cycle = 0% 0.98 1.1 1.22
Duty cycle = 100%

to 25°C –2 ±30

A(min)

TL1454A

MIN TYP MAX

–10 ±30

TL1454A

MIN TYP MAX

0.38 0.5 0.62

UNIT

kHz

UNIT

V

error-amplifier

PARAMETER TEST CONDITIONS

V

IO

I

IO

I

IB

V

ICR

A

V

CMRR Common-mode rejection ratio 60 80 dB
V

OM(max)

V

OM(min)

I

O+

I

O–

Input offset voltage 6 mV
Input offset current
Input bias current
Input voltage range VCC = 3.6 V to 20 V –0.2 to 1.40 V
Open-loop voltage gain RFB = 200 kΩ 70 80 dB
Unity-gain bandwidth 3 MHz

Positive output voltage swing 2.3 2.43
Negative output voltage swing 0.63 0.8
Output sink current VID = –0.1 V , VO = 1.20 V 0.1 0.5 mA
Output source current VID = 0.1 V, VO = 1.80 V –45 –70 µA

VO = 1.25 V, VIC = 1.25 V

TL1454A

MIN TYP MAX

100 nA

–160 –500 nA

output

PARAMETER TEST CONDITIONS

IO = –8 mA VCC–2 4.5

V

OH

V

OL

t

rv

t

fv

High-level output voltage

Low-level output voltage
Output voltage rise time

Output voltage fall time

IO = –8 mA @ VCC = >10 V VCC–2.3 V
IO = –40 mA
IO = 40 mA @ VCC = >10 V VCC–2.3 V
IO = 8 mA 0.1 0.4
IO = 40 mA

CL = 2000 pF, TA = 25°C

p

TL1454A

MIN TYP MAX

VCC–2 4.4

1.8 2.5
220
220

UNIT

V

UNIT

V

V

ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9