Texas Instruments THS6132EVM User Manual

THS6132EVM

User’s G uide

November 2002 High Performance Linear Products

SLOU154

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

EVM IMPORTANT NOTICE

Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EV ALUATION

PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.

Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER W ARRANTIES, EXPRESSED,
IMPLIED, OR S TATUTOR Y, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.

TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.

Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.

Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any

machine, process, or combination in which such TI products or services might be or are used.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the specified input and output ranges described in
the EVM User’s Guide.

Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User ’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.

Mailing Address:

Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

Copyright  2002, Texas Instruments Incorporated

Information About Cautions and Warnings

This book may contain cautions and warnings.

Information About Cautions and Warnings

Preface

Read This First

FCC Warning

This is an example of a caution statement.
A caution statement describes a situation that could potentially

damage your software or equipment.

This is an example of a warning statement.
A warning statement describes a situation that could potentially

cause harm to you.

The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.

This equipment is intended for use in a laboratory test environment only. It ge n­erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en­vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.

v

Trademarks

Electrostatic Sensitive Components

This EVM contains components that can potentially be damaged by
electrostatic discharge. Always transport and store the EVM in its
supplied ESD bag when not in use. Handle using an antistatic
wristband. Operate on an antistatic work surface. For more
information on proper handling, refer to SSYA008.

Related Documentation From Texas Instruments

The URL’s below are correct as of the date of publication of this manual. T exas
Instruments applications apologizes if they change over time.

- THS6132 data sheet (SLLS543)

Trademarks

- Application report (SLMA002), PowerPAD Thermally Enhanced Package,

http://www-s.ti.com/sc/psheets/slma004/slma002.pdf

- Application report (SLMA004), PowerPAD Made Easy,

http://www-s.ti.com/sc/psheets/slma004/slma004.pdf

- Application report (SSYA008), Electrostatic Discharge (ESD),

http://www-s.ti.com/sc/psheets/ssya008/ssya008.pdf

- Application report (SLOA100), Active Output Impedance for ADSL Line

Drivers, http://www-s.ti.com/sc/psheets/sloa100/sloa100.pdf

PowerPAD is a trademark of Texas Instruments.

vi

Contents

Contents

1 Introduction and Description 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Evaluation Module Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 THS6132EVM Operating Conditions 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 EVM Default Configuration 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Using the THS6132EVM 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 THS6132EVM Applications 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Standard Gain Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Active Termination 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Receive Path Implementation 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 High-Pass Filter 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Single-Ended to Differential Conversion 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Single-Ended Gain Stages 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 EVM Hardware Description 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

Contents

Figures

1-1 Full Schematic of the Populated Circuit on the THS6132EVM (Default Configuration) 1-3. .

2-1 Interconnection Diagram 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1 Default Configuration Operation 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-2 Differential Positive Feedback 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3 Implementation of the Receive Signal Path 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-4 ADSL Spectrum and High-Pass Filter Response 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-5 Single-Ended Amplifier Configuration 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1 Top Layer 1 (Signals for THS6132EVM) 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2 Internal Plane (Layer 2) (Ground 1 Plane) 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-3 Internal Plane (Layer 3) (Power Plane) 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-4 Bottom (Layer 4) (Ground and Signal) 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables

4-1 THS6132EVM Bill of Material 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-2 THS6132EVM Bill of Material for Items 25 and 26 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

Chapter 1

Introduction and Description

The Texas Instruments THS6132 evaluation module (EVM) helps designers
evaluate the performance of the THS6132 operational amplifier. Also, this
EVM is a good example of high-speed PCB design.

Two packages of the THS6132, THS6132PWP, and THS6132RGU, are
supported by this EVM. The schematics and the bill of materials indicate any
differences associated with the two packages.

This document details the THS6132EVM. It includes a list of EVM features, a
brief description of the module illustrated with a series of schematic diagrams,
EVM specifications, details on connecting and using the EVM, and a
discussion of high-speed amplifier design considerations.

This EVM enables the user to implement various circuits to clarify the available
configurations presented by the schematic of the EVM. The user is not limited
to the circuit configurations presented. The EVM provides enough hardware
hooks that the only limitation should be the creativity of the user.

Topic Page

1.1 Evaluation Module Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 THS6132EVM Operating Conditions 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 EVM Default Configuration 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction and Description

1-1

Evaluation Module Features

1.1 Evaluation Module Features

The THS6132EVM provides a platform for developing high-speed operational
amplifier application circuits. It contains the THS6132 high-speed dual
operational amplifier, a number of passive components, and various features
and footprints that enable the user to experiment with, test, and verify various
operational amplifier circuit implementations. The PC board measures 4.21 by

3.01 inches. THS6132 high-speed operational amplifier EVM features include:

- Active termination capability (R3 and R12)

- Snubber circuit (R1 and C1), for use with active termination

- Hooks for a receive path signal (TP1 through TP4)

- Noninverting gain configuration for DSL

- High-pass filter (HPF) function for ADSL (C2 and R23)

- Short-loop length for the power supply differential high-frequency path

(C12, C14)

1.2 THS6182EVM Operating Conditions

Supply voltage range, ±V
Supply current, I

For complete THS6132 amplifier IC specifications, parameter measurement
information, and additional application information, see the THS6132 data
sheet (SLLS543).

1.3 EVM Default Configuration

As delivered, the EVM has a fully functional example circuit, requiring added
power supplies, a signal source, and monitoring instrument. See Figure 1-1
for the complete EVM schematic.

The default configuration has a differential gain of 2.22, as determined by R2,
R23, and R1 1 in combination with series matching resistors R6, R7, R15, and
R16, and a 50-Ω load on the outputs at J1 and J3.

Some components such as R20, R21, R24–R29, C3–C12, FB1, FB2, JP1,
JP2, J5–J9, and TP8–TP10, etc., are omitted on the application schematics
of Chapter 3 for clarity.

CC

(see the device data sheet)

CC

±5 to ±15 Vdc (see the device data sheet)

1-2

EVM Default Configuration

Figure 1-1.Full Schematic of the Populated Circuit on the THS6132EVM (Default

Configuration)

IN1

U1A

J2

Z1 R9

0  0 

R8

*

R10

49.9 
R4

14 (21)

R5

*

2 (4)

THS6132

+

-

TP1

15 (23)

12.4 
R2
1 k

R6

TP2

R7

49.9 

J1

OUT1

*

C2

R3

*

Z2 R18

0 

R17

IN2

J4

*

TP6 TP7TP5

C20

22 F 22 F

C6

22 F

**

* Not Installed
** Installed Near U1

+VCC H

+

**

+VCC L

+

J8

J7

0.1 F

R23

Z3

500 

*

R13

*

R14

*

12 (20)

3 (5)

0 

R19

49.9 
J9

-VCC H

FB4

+V H**-V H

C14

1  of

50 V 10 k

FB1

+V H

-V H

C12

1  of

50 V

J5

-VCC L

FB3

C16

C17C18

0.1 F0.1 F

FB2

C7

22 F
C8C10

0.1 F0.1 F

R12

THS6132

­+

+

+

**

*

U1B

11 (18)

J6

GND

TP3

R29

10 k

R30

R11
1 k

R22

R15

TP10

R21

TP10

JP2

100 k

JP3

100 k

+VH

-VH

R1

+V

C1

*

*

TP4

+V

10 k

R26

10 k

7 (10)

18 (26)
17 (25)

8 (15)
9 (16)

4 (7)

21 (33)

R25

6 (9)

R16

49.9 12.4 

R20

100 k

BIAS-2

BIAS-3

GND

TP9

R28

5 (8)

BIAS-1

VREF

U1C

THS6132

J3

OUT2

+V

JP1

10 k

1 (2)

16 (27, 28, 29)

10 (12, 13, 14)

R24

10 k

TP8

R27

0 k

+VL

-VL

Note: 1. Component pin numbers shown are for THS6132RGW while pin numbers in parentheses are for THS6132VFP.
Note: 2. The pin marked 21 (33) is connected to the PowerPAD.

Introduction and Description

1-3

1-4

This section describes how to connect the THS6132EVM to test equipment.
It is recommended that the user connect the EVM as described in this section
to avoid damage to the EVM or the THS6132 installed on the board.

Figure 2-1. Interconnection Diagram

Chapter 2

Using the THS6132EVM

Using the THS6132EVM

2-1

Figure 2-1 shows the connections to measure the output signal of output 1
while a single-ended signal is inserted into EVM channel 1’s noninverting
input. If the oscilloscope input is connected to J3 and the signal source is
connected to J2, EVM channel 2 is also configured for a noninverting signal
path. When the oscilloscope’s input impedance is 50 Ω, the voltage gain from
J2 to J3 is 1.33 V.

If a balanced (differential) signal is inserted into J2 and J4, a balanced signal
is present at J1 and J3.

2-2

Chapter 3

THS6132EVM Applications

Example applications are presented in this chapter. These applications
demonstrate the most popular circuits, but many other circuits can be
constructed. The user is encouraged to experiment with different circuits,
exploring new and creative design techniques.

Topic Page

3.1 Standard Gain Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Active Termination 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Receive Path Implementation 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 High-Pass Filter 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Single-Ended to Differential Conversion 3-8. . . . . . . . . . . . . . . . . . . . . . . .

3.6 Single-Ended Gain Stages 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS6132EVM Applications

3-1

Standard Gain Configuration

3.1 Standard Gain Configuration

The THS6132EVM default configuration is a fully differential input, fully
differential output gain of about 2.2 (at the output connectors using an
instrument with 50-Ω load on each input). A simplified schematic is shown in
Figure 3-1. This gain is calculated according to an equation that is similar to
the one that describes an instrumentation amplifier:

VO(diff)

where
R2 = R11

Series resistors R6, R7, R15 and R16 affect output voltage at J1 and J3. The
designer needs to take the voltage divider law into account for their load
impedance and R6, R7, R15 and R16. When a designer monitors the output
at TP1 and TP3 using a high-impedance differential probe, the default gain is
5 V.

Figure 3-1.Default Configuration Operation

J2

IN1

Z1
0  0 

R9

R10

44.9  R2

2 (4)

14(21)

VI(diff)

+

-

+ 1 )

U1A

THS6132

15 (23)

2 R2

R23

TP1

R6

12.4  49.9 

1 k

TP2

R7

(1)Differential gain +

J1

OUT1

C2

0.1 F

R23
500 

U1B

3 (5)

THS6182

­+

J4

IN2

Note: Component pin numbers shown are for THS6132RGW while pin numbers in parentheses are for THS6132VFP.

Z2 R18

0  0 

R19

44.9 

12 (20)

TP3

11 (18)

R11
1 k

R15

12.4 

TP4

R16

49.9 

J3

OUT2

3-2

3.2 Active Termination

Although this application is specifically for use as an ADSL line driver, the
principals shown can be applied to other applications.

Active termination is a technique that allows the designer to use a small value
resistor for the series resistance (R6 and, or R15). The circuit then utilizes
positive feedback to make the impedance of this resistor appear much larger ,
when looking from the line-side. This accomplishes two things:

- A very small resistance exists between the amplifier and the transformer.

This lowers the output voltage swing range required from the driver stage.

- Proper matching impedance appears when looking from the line to the

amplifier.

Figure 3-2 shows the basic circuit for differential positive feedback.

Figure 3-2.Differential Positive Feedback

J2

Vin1

Z1 R9

0  0 

R10

49.9 

U1A
THS6132

2

+

14

-

2(5)

TP1
Vo1

R2 = RF

1 k 

Active Termination

R6 = Rs

12.4 

J4

Vin2

Z2 R18

0  0 

R19

49.9 

C2

0.1 F

R23 = 2 RG

500 

12

-

3

+

U1B

THS6132

R3 = Rp
2 k 

R12 = Rp
2 k 

TP3

Vo2

11

R11 = RF

12 k 

R15 = Rs

12.4 

C1

R1

TP2

Vout+

TP4

Vout+

1:n

Note: Component pin numbers shown are for THS6132RGW while pin numbers in parentheses are for THS6132VFP.

THS6132EVM Applications

V Line

Line =

100 

3-3

Active Termination

Active feedback creates larger impedance (Z) than what is actually placed
there by series resistors RS:

R

1–

S

R

F

R

P

(2)Z(W) +

The important thing to consider is that regardless of the forward gain from V
to VO, the active impedance (Z) value remains constant.

Solving equation 2 for Rp, the following equation is produced:

R

+

P

Using Z = 50 Ω and values from Figure 3-2 in equation 3, yields 1330 Ω for
RP.

Now that the return impedance is corrected, forward voltage gain from input
to output is calculated. Equation 3 shows the simplified forward gain from V
to VO.

V

+

V

V

where

R

F

R

S

1 *

P

R

RG|| R

F

Ǔǒ

P

F

Ǔ

P

R

L

RL)R

if RLtt R

Ǔ

S

P

+

LINE

2n

1 ) ǒ

1 * ǒ

2

R
R

"

O

"

in

R

+

L

(3)R

(4)A

(5)

in

in

3-4

With a transformer ratio( n ) of 1 and a R
When the value RL and the values in Figure 3-2 are used in equation 4, the

resulting voltage gain is 14.5. Because RG does not affect the value of the
apparent output impedance of the circuit, voltage gain can be adjusted by
changing RG.

The reader is cautioned that active termination is a very complex topic, with
many considerations. Carefully read the Texas Instruments Application
Report Active Output Impedance for ADSL Line Drivers, (SLOA100) to gain
a more complete understanding of the topic and all the subtle implications of
active termination.

R1 and C1 are located on the EVM so that a snubber circuit may be
implemented. Some transformers have a high resonant frequency (as low as
25 MHz but as high as 150 MHz). When using traditional termination (just R6,
and R15—no active termination), there is typically not a reason to use these
components. But, when active termination is used, the effective impedance of
these two resistor values drops substantially. Thus, there can be very small

of 100 Ω, RL is 50 Ω.

LINE

Active Termination

resistor isolation between the amplifier and the transformer, causing a
resonance problem. Couple this with the feedback path of R3 and R12, and
this can cause the amplifier to oscillate. The snubber is utilized to eliminate this
oscillation. As a rule of thumb, to select the proper snubber values, select:

R19 + 2

LINE

2

n

(6)

R

Then select C5:

C1 +

2 p R1 F

1

(7)

C

where FC = at least 10X the highest operating frequency (1.104 MHz is the
highest ADSL operating frequency). 20X or even larger may be preferable.

THS6132EVM Applications

3-5

Receive Path Implementation

3.3 Receive Path Implementation

Test points TP1 through TP4 are located on the EVM to facilitate the addition
of the receive signal path to the signal chain as shown in Figure 3-3. When
implementing the receive path, a hybrid must be used, as ADSL is full duplex.
The hybrid cancels out the TX signal and allows the RX signal from the line to
come through. The THS6132 EVM does not have receive or hybrid circuitry
included. Texas Instruments assumes that the customer has a proprietary
hybrid design, and therefore they would prefer to implement it. The user should
know their nominal line impedance characteristics and thus should be able to
match them better. Texas Instruments does have an EVM that contains a
THS6062 ADSL receiver, and this EVM can be purchased separately to
facilitate construction of a complete ADSL transmit/receive interface.

Figure 3-3.Implementation of the Receive Signal Path

2R

J2

Vin1

Z1

0  0 

R9

R10

49.9 

2 (4)

14 (21)

+

-

U1A

THS6132

15 (23)

TP1
Vo1

R6 = Rs

12.4 

R2 = RF

1 k

R

+V

U2A

8

THS6062

2

-

3

+

4

R

RX Vout+

7

J4

Vin2

Z2

0  0 

R18

R19

49.9 

12 (20)

3 (5)

C2

0.1 F

R23=2 RG
500 

U1B

THS6132

­+

R3 = Rp

? k

R12 = Rp
? k

11 (18)

R11 = RF

R15 = Rs

12.4 

TP3

Vo 2

C1

R1

2R

TP2

Vout+

TP4

Vout-

V Line

1:n

TP4
Line =

100 

R

R

U2B

6

5

THS6062

­+

RX Vout-

1

Note: Component pin numbers shown are for THS6132RGW while pin numbers in parentheses are for THS6132VFP.

3-6

3.4 High-Pass Filter

Because ADSL CPE is designed to transmit from 25.875 kHz to 138 kHz, C2
and R23 can be used to implement an HPF function. These are selected to be
20X lower than 25 kHz (1.25 kHz). Some designs use a capacitor—some do
not. This path allows for a common gain setting between the two channels.
This helps (but does not assure) the signals are truly differential.

Figure 3-4 compares the frequency spectrum of ADSL to a simulation of the
high-pass filter on the THS6132EVM.

Figure 3-4.ADSL Spectrum and High-Pass Filter Response

(Above not on a logarithmic scale)

High-Pass Filter

Note that the high-pass filter function is not a true high-pass filter. C2 in series
with R23 creates a zero at about 10 Hz. As the frequency decreases from
about 3 kHz to 10 Hz, the circuit changes from a gain stage into two unity gain
buffers.

THS6132EVM Applications

3-7

Single-Ended to Differential Conversion

3.5 Single-Ended to Differential Conversion

The circuit shown in Figure 3-1 is used for single-ended to differential
conversion by grounding one input and supplying a single-ended signal to the
other input. Because one amplifier is configured as a noninverting amplifier
and the other as an inverting circuit, the gain of the noninverting channel is one
greater than the other. This gain difference can be eliminated by changing the
feedback resistor value of the inverting stage to increase the gain by one.

If active termination is used as Figure 3-2 and Figure 3-3 indicate and a
single-ended to differential conversion is desired, the changed value of the
feedback resistor of the inverting stage also requires a change of RP. The
same equation (2) is used to determine the new RP for that stage.

3-8

3.6 Single-Ended Gain Stages

Although ADSL is the obvious application for the THS6132 EVM, it can also
be configured for other applications. If the common gain resistor R8 is
removed, there is an array of components that allows various dc- and
ac-coupled gain stages to be constructed.

Referring to Figure 3-5, for example, two dc coupled gain stages are formed
by removing R9 and adding R4 and R14. The output impedance is changed
to 75 Ω by changing R6 and R15 to 24.9 Ω. There are many other possibilities.

Figure 3-5.Single-Ended Amplifier Configuration

J2

IN1

Z1 R9

0  0 

49.9 

R10

R5

1 k

2 (4)

14 (21)

+

-

U1A
THS6132

15 (23)

Single-Ended Gain Stages

TP1

R6

24.9  49.9 

R2
1 k

TP2

R7

J1

OUT1

R14

1 k

J4

IN2

Note: Component pin numbers shown are for THS6132RGW while pin numbers in parentheses are for THS6132VFP.

Z2 R18

0  0 

49.9 

R19

12 (20)

3 (5)

U1B

THS6132

­+

TP3

11 (18)

R11
1 k

R15

24.9 

TP4

R16

49.9 

J3

OUT2

THS6132EVM Applications

3-9

EVM Hardware Description

This chapter describes the EVM hardware. It includes the EVM parts list, and
printed circuit-board layout.

Table 4-1.THS6132EVM Bill of Material

SMD

Reference

Size

Item Description

1 Bead, ferrite, 3A, 80 Ω 1206 FB1, FB2,

2 CAP, 22 µF, tantalum, 25 V, 10% D C6, C7, C16,

3 Open 1206 C1 1
4 CAP, 0.1 µF, ceramic, X7R, 50 V 1206 C2 1 (AVX)

5 CAP, 0.1 µF, ceramic, Y5V, 50 V 1206 C12, C14 2 (AVX)

6 CAP, 1.0 µF, ceramic, XR7, 50 V 0805 C8, C10, C17,

7 Open 0805 R3, R4, R5,

8 Resistor, 0 Ω, 1/8 W 0805 R9, R18, R27 3 (Phycomp)

9 Resistor, 100 Ω, 1/8 W, 1% 0805 R20, R21, R22 3 (Phycomp)

10 Resistor, 500 Ω, 1/8 W, 1% 0805 R23 1 (Phycomp)

11 Resistor, 1 kΩ, 1/8 W, 1% 0805 R2, R11 2 (Phycomp)

12 Resistor, 10 kΩ, 1/8 W, 1% 0805 R24, R25,

13 Open 1206 R1, R8, R17,

14 Resistor, 0 Ω, 1/4 W 1206 Z1, Z2, 2 (Phycomp)

15 Resistor, 12.4 Ω, 1/4 W, 1% 1206 R6, R15 2 (Phycomp)

16 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R7, R10, R16,

Designator

FB3, FB4

C20

C18

R12, R13, R14

R26, R28,
R29, R30

Z3

R19

PCB
QTY

Manufacturer’s Part # Distributor’s Part #

4 (Steward)

HI1206N800R-00

4 (AVX) TAJD226K025R (Garrett)

12065C104KAT2A

12065G105ZAT2A

4 (AVX) 8055C104KAT2A (Garrett)

6

9C08052A0R00JLHFT

9C08052A1000FKHFT

9C08052A5000FKHFT

9C08052A1001FKHFT

6 (Phycomp)

9C08052A1002FKHFT

4

9C12063A0R00JLHFT

9C12063A12R4FKRFT

4 (Phycomp)

9C12063A49R9FKRFT

Chapter 4

(Digi-Key)
240-1010-1-ND

TAJD226K025R

(Garrett)
12065C104KAT2A

(Garrett)
12065G105ZAT2A

08055C104KAT2A

(Garrett)
9C08052A0R00JLHFT

(Garrett)
9C08052A1000FKHFT

(Garrett)
9C08052A5000FKHFT

(Garrett)
9C08052A1001FKHFT

(Garrett)
9C08052A1002FKHFT

(Garrett)
9C12063A0R00JLHFT

(Garrett)
9C12063A12R4FKRFT

(Garrett)
9C12063A49R9FKRFT

EVM Hardware Description

4-1

Table 4-1. THS6132EVM Bill of Material (Continued)

SMD

Reference

Size

Item Description

17 Connector, BNC, vertical, PCB J1, J2, J3, J4 4 (Amphenol) 31-5329 (Newark) 89F2885
18 Jack, banana, receptance, 0.25”

diameter hole

19 Header, 0.1” centers, 0.025”

square pins
20 Shunts JP1, JP2, JP3 3 (Sullins) SSC02SYAN (Digi-Key) S9002-ND
21 Test point, black TP5, TP6, TP7 3 (Keystone) 5001 (Digi-Key) 5001K-ND
22 Test points, red TP1, TP2, TP3,

23 Standoff, 4-40 hex, 0.625” length 4 (Keystone) 1804 (Allied) 839-2089
24 Screw, Phillips, 4-40, .250” 4 SHR-0440-016-SN
25 See Table 4-2
26 See Table 4-2

Designator

J5, J6, J7, J8,

J9

2

JP1, JP2, JP3 3 (Sullins) PZC36SAAN (Digi-Key)

POS.

TP4, TP8, TP9,
TP10, TP11

PCB

QTY

Manufacturer’s Part # Distributor’s Part #

5 (HH Smith) 101 (Newark) 35F865

S1011-36-ND

8 (Keystone) 5000 (Digi-Key) 5000K-ND

Table 4-2.THS6132EVM Bill of Material for Items 25 and 26

PCB

Part Number

QTY

Item Description Reference Designator

25 IC, THS6132 U1 1 (TI) THS6132VFP (TI) THS6132RGW
26 Printed-circuit board 1 (TI) EDGE #6442732 (TI) EDGE #6443085

VFP Package

Part Nmuber
RGW Package

Figure 4-1.Top Layer 1 (Signals for THS6132EVM)

4-2

Figure 4-2.Internal Plane (Layer 2) (Ground 1 Plane)

Figure 4-3.Internal Plane (Layer 3) (Power Plane)

EVM Hardware Description

4-3

Figure 4-4.Bottom (Layer 4) (Ground and Signal)

4-4