TEXAS INSTRUMENTS THS3091, THS3095 Technical data

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−

OUT

TOTAL HARMONIC DISTORTION

FREQUENCY

TYPICAL ARBITARY WAVEFORM

GENERATOR OUTPUT DRIVE CIRCUIT

−90

−80

−70

−60

−50

−40

−20

1 M 10 M 100 M

f − Frequency − Hz

Total Harmonic Distortion − dBc

G = 5, RF = 1 kΩ, RL = 100 Ω, VS = ±15 V

100 k

−30

VO = 20 V

VO = 10 V

VO = 5 V

VO = 2 V

−

THS3091

−

THS4271

IOUT1

IOUT2

DAC5686

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HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK

OPERATIONAL AMPLIFIERS

FEATURES DESCRIPTION

• Low Distortion

– 77 dBc HD2 at 10 MHz, R – 69 dBc HD3 at 10 MHz, R

• Low Noise – 14 pA/ √ Hz Noninverting Current Noise and VDSL line drivers. – 17 pA/ √ Hz Inverting Current Noise – 2 nV/ √ Hz Voltage Noise

• High Slew Rate: 7300 V/µs (G = 5, V

• Wide Bandwidth: 210 MHz (G = 2, R

• High Output Current Drive: ± 250 mA

• Wide Supply Range: ± 5 V to ± 15 V

• Power-Down Feature: (THS3095 Only)

APPLICATIONS

• High-Voltage Arbitrary Waveform

• Power FET Driver

• Pin Driver

• VDSL Line Driver

L L

= 1 k Ω = 1 k Ω

= 20 V

= 100 Ω )

)

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

The THS3091 and THS3095 are high-voltage, low-distortion, high-speed, current-feedback amplifiers designed to operate over a wide supply range of ± 5 V to ± 15 V for applications requiring large, linear output signals such as Pin, Power FET,

The THS3095 features a power-down pin (PD) that puts the amplifier in low power standby mode, and lowers the quiescent current from 9.5 mA to 500 µA.

The wide supply range combined with total harmonic distortion as low as -69 dBc at 10 MHz, in addition, to the high slew rate of 7300 V/µs makes the THS3091/5 ideally suited for high-voltage arbitrary waveform driver applications. Moreover, having the ability to handle large voltage swings driving into high-resistance and high-capacitance loads while maintaining good settling time performance makes the devices ideal for Pin driver and PowerFET driver applications.

The THS3091 and THS3095 are offered in an 8-pin SOIC (D), and the 8-pin SOIC (DDA) packages with PowerPAD™.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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D, DDATOP VIEW

1 2 3 4

8 7 6 5

IN−

IN+

S−

NC V

S+

OUT

NC = No Internal Connection

THS3091

Note A: The devices with the power−down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin functional range is from VS− to (VS+ − 4 V).

1 2 3 4

8 7 6 5

REF V

IN−

IN+

S−

PD V

S+

OUT

D, DDATOP VIEW

THS3095

NC = No Internal Connection See Note A.

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

PART NUMBER PACKAGE TYPE TRANSPORT MEDIA, QUANTITY

THS3091D Rails, 75

THS3091DR Tape and Reel, 2500

THS3091DDA Rails, 75

THS3091DDAR Tape and Reel, 2500

Power-down

THS3095D Rails, 75

THS3095DR Tape and Reel, 2500

THS3095DDA Rails, 75

THS3095DDAR Tape and Reel, 2500

(1) The PowerPAD is electrically isolated from all other pins.

ODERING INFORMATION

SOIC-8

SOIC-8-PP

SOIC-8

SOIC-8-PP

(1)

DISSIPATION RATING TABLE

PACKAGE Θ

D-8 38.3 97.5 1.02 W 410 mW

(3)

DDA-8

(1) This data was taken using the JEDEC standard High-K test PCB. (2) Power rating is determined with a junction temperature of 125 ° C. This is the point where distortion starts to substantially increase.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125 ° C for best performance and long-term reliability.

(3) The THS3091 and THS3095 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be

connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD™ thermally enhanced package.

( ° C/W) Θ

9.2 45.8 2.18 W 873 mW

(1)

( ° C/W)

TA= 25 ° C TA= 85 ° C

POWER RATING

TJ= 125 ° C

(2)

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THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Supply voltage V

Operating free-air temperature -40 85 ° C

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature (unless otherwise noted)

VS-to V V

(2)

stg

(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may

cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability and/or lifetime of the device.

Supply voltage 33 V

S+

Input voltage ± V Differential input voltage ± 4 V Output current 350 mA Continuous power dissipation See Dissipation Ratings Table Maximum junction temperature, 150 ° C Maximum junction temperature, continuous operation, long-term reliability 125 ° C Storage temperature -65 ° C to 150 ° C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ° C

ESD ratings CDM 1500

Dual supply ± 5 ± 15 Single supply 10 30

(1)

UNIT

HBM 2000

MM 150

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THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

VS= ± 15 V, RF= 1.21 k Ω , RL= 100 Ω , and G = 2 (unless otherwise noted)

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS

AC PERFORMANCE

G = 1, RF= 1.78 k Ω , VO= 200 mV

Small-signal bandwidth, -3 dB

0.1-dB bandwidth flatness G = 2, RF= 1.21 k Ω , VO= 200 mV Large-signal bandwidth G = 5, RF= 1 k Ω , VO= 4 V

Slew rate (25% to 75% level) V/µs TYP

Rise and fall time G = 2, VO= 5-V Settling time to 0.1% G = -2, VO= 2 VPPstep 42 Settling time to 0.01% G = -2, VO= 2 VPPstep 72 Harmonic distortion

2nd Harmonic distortion

3rd Harmonic distortion

Input voltage noise f > 10 kHz 2 nV / √ Hz TYP Noninverting input current noise f > 10 kHz 14 pA / √ Hz TYP Inverting input current noise f > 10 kHz 17 pA / √ Hz TYP

Differential gain

Differential phase

DC PERFORMANCE

Transimpedance VO= ± 7.5 V, Gain = 1 850 350 300 300 k Ω MIN Input offset voltage 0.9 3 4 4 mV MAX

Average offset voltage drift ± 10 ± 10 µV/ ° C TYP

Noninverting input bias current 4 15 20 20 µA MAX

Average bias current drift ± 20 ± 20 nA/ ° C TYP

Inverting input bias current 3.5 15 20 20 µA MAX

Average bias current drift ± 20 ± 20 nA/ ° C TYP

Input offset current 1.7 10 15 15 µA MAX

Average offset current drift ± 20 ± 20 nA/ ° C TYP

INPUT CHARACTERISTICS

Common-mode input range ± 13.6 ± 13.3 ± 13 ± 13 V MIN Common-mode rejection ratio VCM= ± 10 V 78 68 65 65 dB MIN Noninverting input resistance 1.3 M Ω TYP Noninverting input capacitance 0.1 pF TYP Inverting input resistance 30 Ω TYP Inverting input capacitance 1.4 pF TYP

G = 2, RF= 1.21 k Ω , VO= 200 mV G = 5, RF= 1 k Ω , VO= 200 mV G = 10, RF= 866 Ω , VO= 200 mV

G = 2, VO= 10-V step, RF= 1.21 k Ω 5000 G = 5, VO= 20-V step, RF= 1 k Ω 7300

, RF= 1.21 k Ω 5 ns TYP

G = 2, RF= 1.21 k Ω , VO= 2 VPP, f = 10 MHz

G = 2, RL= 150 Ω , RF= 1.21 k Ω

VCM= 0 V

PP PP

RL= 100 Ω 66 RL= 1 k Ω 77 RL= 100 Ω 74 RL= 1 k Ω 69

NTSC 0.013% PAL 0.011% NTSC 0.020 ° PAL 0.026 °

25 ° C 25 ° C UNIT

235 210 190 180

135

0 ° C to -40 ° C to MIN/TYP/

70 ° C 85 ° C MAX

MHz TYP

ns TYP

dBc TYP

TYP

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SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS

OUTPUT CHARACTERISTICS

Output voltage swing V MIN

Output current (sourcing) RL= 40 Ω 280 225 200 200 mA MIN Output current (sinking) RL= 40 Ω 250 200 175 175 mA MIN Output impedance f = 1 MHz, Closed loop 0.06 Ω TYP

POWER SUPPLY

Specified operating voltage ± 15 ± 16 ± 16 ± 16 V MAX Maximum quiescent current 9.5 10.5 11 11 mA MAX Minimum quiescent current 9.5 8.5 8 8 mA MIN Power supply rejection (+PSRR) VS+= 15.5 V to 14.5 V, VS-= 15 V 75 70 65 65 dB MIN Power supply rejection (-PSRR) VS+= 15 V, VS-= -15.5 V to -14.5 V 73 68 65 65 dB MIN

POWER-DOWN CHARACTERISTICS (THS3095 ONLY)

Power-down voltage level V MAX

Power-down quiescent current PD = 0V 500 700 800 800 µA MAX

VPDquiescent current µA MAX

Turnon time delay 90% of final value 60 Turnoff time delay 10% of final value 150

RL= 1 k Ω ± 13.2 ± 12.8 ± 12.5 ± 12.5 RL= 100 Ω ± 12.5 ± 12.1 ± 11.8 ± 11.8

Enable, REF = 0 V ≤ Power-down , REF = 0 V ≥ 2

VPD= 0 V, REF = 0 V, 11 15 20 20 VPD= 3.3 V, REF = 0 V 11 15 20 20

25 ° C 25 ° C UNIT

0 ° C to -40 ° C to MIN/TYP/

70 ° C 85 ° C MAX

µs TYP

THS3091 THS3095

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THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

ELECTRICAL CHARACTERISTICS

VS= ± 5 V, RF= 1.15 k Ω , RL= 100 Ω , and G = 2 (unless otherwise noted)

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS

AC PERFORMANCE

G = 1, RF= 1.78 k Ω , VO= 200 mV

Small-signal bandwidth, -3 dB

0.1-dB bandwidth flatness G = 2, RF= 1.15 k Ω , VO= 200 mV Large-signal bandwidth G = 2, RF= 1.15 k Ω , VO= 4 V

Slew rate (25% to 75% level) V/µs TYP

Rise and fall time G = 2, VO= 5-V step, RF= 1.21 k Ω 5 ns TYP Settling time to 0.1% G = -2, VO= 2 VPPstep 35 Settling time to 0.01% G = -2, VO= 2 VPPstep 73 Harmonic distortion

2nd Harmonic distortion

3rd Harmonic distortion

Input voltage noise f > 10 kHz 2 nV / √ Hz TYP Noninverting input current noise f > 10 kHz 14 pA / √ Hz TYP Inverting input current noise f > 10 kHz 17 pA / √ Hz TYP

Differential gain

Differential phase

DC PERFORMANCE

Transimpedance VO= ± 2.5 V, Gain = 1 700 250 200 200 k Ω MIN Input offset voltage 0.3 2 3 3 mV MAX

Average offset voltage drift ± 10 ± 10 µV/ ° C TYP

Noninverting input bias current 2 15 20 20 µA MAX

Average bias current drift ± 20 ± 20 nA/ ° C TYP

Inverting input bias current 5 15 20 20 µA MAX

Average bias current drift ± 20 ± 20 nA/ ° C TYP

Input offset current 1 10 15 15 µA MAX

Average offset current drift ± 20 ± 20 nA/ ° C TYP

INPUT CHARACTERISTICS

Common-mode input range ± 3.6 ± 3.3 ± 3 ± 3 V MIN Common-mode rejection ratio VCM= ± 2.0 V, VO= 0 V 66 60 57 57 dB MIN Noninverting input resistance 1.1 M Ω TYP Noninverting input capacitance 1.2 pF TYP Inverting input resistance 32 Ω TYP Inverting input capacitance 1.5 pF TYP

G = 2, RF= 1.15 k Ω , VO= 200 mV G = 5, RF= 1 k Ω , VO= 200 mV G = 10, RF= 866 Ω , VO= 200 mV

G = 2, VO= 5-V step, RF= 1.21 k Ω 1400 G = 5, VO= 5-V step, RF= 1 k Ω 1900

G = 2, RF= 1.15 k Ω , VO= 2 VPP, f = 10 MHz

G = 2, RL= 150 Ω , RF= 1.15 k Ω

VCM= 0 V

PP PP

RL= 100 Ω 77 RL= 1 k Ω 73 RL= 100 Ω 70 RL= 1 k Ω 68

NTSC 0.027% PAL 0.025% NTSC 0.04 ° PAL 0.05 °

25 ° C 25 ° C UNIT

190 180 160 150

160

0 ° C to -40 ° C to MIN/TYP/

70 ° C 85 ° C MAX

MHz TYP

ns TYP

dBc TYP

TYP

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SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYP OVER TEMPERATURE

PARAMETER TEST CONDITIONS

OUTPUT CHARACTERISTICS

Output voltage swing V MIN

Output current (sourcing) RL= 40 Ω 200 160 140 140 mA MIN Output current (sinking) RL= 40 Ω 180 150 125 125 mA MIN Output impedance f = 1 MHz, Closed loop 0.09 Ω TYP

POWER SUPPLY

Specified operating voltage ± 5 ± 4.5 ± 4.5 ± 4.5 V MAX Maximum quiescent current 8.2 9 9.5 9.5 mA MAX Minimum quiescent current 8.2 7 6.5 6.5 mA MIN Power supply rejection (+PSRR) VS+= 5.5 V to 4.5 V, VS–= 5 V 73 68 63 63 dB MIN Power supply rejection (-PSRR) VS+= 5 V, VS–= –4.5 V to -5.5 V 71 65 60 60 dB MIN

POWER-DOWN CHARACTERISTICS (THS3095 ONLY)

Power-down voltage level V MAX

Power-down quiescent current PD = 0V 300 500 600 600 µA MAX

VPDquiescent current µA MAX

Turnon time delay 90% of final value 60 Turnoff time delay 10% of final value 150

RL= 1 k Ω ± 3.4 ± 3.1 ± 2.8 ± 2.8 RL= 100 Ω ± 3.1 ± 2.7 ± 2.5 ± 2.5

Enable, REF = 0 V ≤ 0.8 Power-down , REF = 0 V ≥ 2

VPD= 0 V, REF = 0 V, 11 15 20 20 VPD= 3.3 V, REF = 0 V 11 15 20 20

25 ° C 25 ° C UNIT

0 ° C to -40 ° C to MIN/TYP/

70 ° C 85 ° C MAX

µs TYP

THS3091 THS3095

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THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

± 15-V GRAPHS FIGURE

Noninverting small-signal frequency response 1, 2 Inverting small-signal frequency response 3

0.1-dB gain flatness frequency response 4 Noninverting large-signal frequency response 5 Inverting large-signal frequency response 6 Capacitive load frequency response 7 Recommended R 2nd Harmonic distortion vs Frequency 9, 11 3rd Harmonic distortion vs Frequency 10, 12 2nd Harmonic distortion vs Frequency 13 3rd Harmonic distortion vs Frequency 14 Harmonic distortion vs Output voltage swing 15, 16 Slew rate vs Output voltage step 17, 18, 19 Noise vs Frequency 20 Settling time 21, 22 Quiescent current vs Supply voltage 23 Quiescent current vs Frequency 24 Output voltage vs Load resistance 25 Input bias and offset current vs Case temperature 26 Input offset voltage vs Case temperature 27 Transimpedance vs Frequency 28 Rejection ratio vs Frequency 29 Noninverting small-signal transient response 30 Inverting large-signal transient response 31, 32 Overdrive recovery time 33 Differential gain vs Number of loads 34 Differential phase vs Number of loads 35 Closed-loop output impedance vs Frequency 36 Power-down quiescent current vs Supply voltage 37 Turnon and turnoff time delay 38

ISO

vs Capacitive load 8

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SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TABLE OF GRAPHS

± 5-V GRAPHS FIGURE

Noninverting small-signal frequency response 39 Inverting small-signal frequency response 40

0.1-dB gain flatness frequency response 41 Noninverting large-signal frequency response 42 Inverting large-signal frequency response 43 Settling time 44 2nd Harmonic distortion vs Frequency 45, 47 3rd Harmonic distortion vs Frequency 46, 48 Harmonic distortion vs Output voltage swing 49, 50 Slew rate vs Output voltage step 51, 52, 53 Quiescent current vs Frequency 54 Output voltage vs Load resistance 55 Input bias and offset current vs Case temperature 56 Overdrive recovery time 57 Rejection ratio vs Frequency 58

THS3091 THS3095

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1 M 10 M 100 M 1 G

f − Frequency − Hz

Noninverting Gain − dB

Gain = 2, RL =100 Ω, VO = 200 mVPP, VS = ±15 V

RF = 750 Ω

RF = 1.21 k ΩRF = 1.21 kΩ

RF = 1.5 kΩ

−4

−2

1 M

10 M 100 M 1 G

f − Frequency − Hz

Noninverting Gain − dB

G = 1, RF = 1.78 kΩ

G = 10, RF = 866 Ω

G = 5, RF = 1 kΩ

G = 2, RF = 1.21 kΩ

RL = 100 Ω, VO = 200 mVPP, VS = ±15 V

−4

−2

1 M 10 M 100 M 1 G

f − Frequency − Hz

Inverting Gain − dB

G = −1, RF = 1.05 kΩ

G = −10, RF = 866 Ω

G = −5, RF = 909 Ω

G = −2, RF = 1 kΩ

RL = 100 Ω, VO = 200 mVPP, VS = ±15 V

−4

−2

1 M 10 M 100 M 1 G

f − Frequency − Hz

VO = 4 VPP, RL = 100 Ω, VS = ±15 V

G = −5, RF = 909 Ω

G = −2, RF = 1 kΩ

Inverting Gain − dB

1 M 10 M 100 M 1 G

f − Frequency − Hz

VO = 4 VPP, RL = 100 Ω, VS = ±15 V

G = 5, RF = 1 kΩ

G = 2, RF = 1.21 kΩ

Noninverting Gain − dB

5.7

5.8

5.9

6.1

6.2

6.3

100 k 1 M 10 M 100 M 1 G

Gain = 2, RF = 1.21 kΩ, RL = 100 Ω, VO = 200 mVPP, VS = ±15 V

f - Frequency - Hz

Noninverting Gain - dB

−2

10 M 100 M 1 G

Signal Gain − dB

Gain = 5, RL = 100 Ω, VS =±15 V

(ISO)

= 38.3 Ω

CL = 10 pF

(ISO)

= 30.9 Ω

CL = 22 pF

(ISO)

= 22.1 Ω

CL = 47 pF

(ISO)

= 15.8 Ω

CL = 100 pF

f − Frequency − Hz

10 100

− Capacitive Load − pF

Recommended

ISO

Ω

Gain = 5, RL = 100 Ω, VS = ±15 V

−

−90

−80

−70

−60

−50

−45

−40

1 M 10 M 100 M

f − Frequency − Hz

2nd Harmonic Distortion − dBc

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.21 kΩ

100 k

−85

−75

−65

−55

VO = 2 VPP, RL = 100 Ω, VS = ±15 V

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE

Figure 1. Figure 2. Figure 3.

0.1-dB GAIN FLATNESS NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE

TYPICAL CHARACTERISTICS ( ± 15 V)

FREQUENCY RESPONSE CAPTIVATE LOAD FREQUENCY

Figure 4. Figure 5. Figure 6.

CAPACITIVE LOAD vs vs

RECOMMENDED R

Figure 7. Figure 8. Figure 9.

ISO

2ND HARMONIC DISTORTION

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−100

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

2nd Harmonic Distortion − dBc

VO = 2 VPP, RL = 1 kΩ, VS = ±15 V

100 k

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.21 kΩ

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

G = 1, RF = 1.78 kΩ

100 k

3rd Harmonic Distortion − dBc

−55

−85

−75

−65

−45

VO = 2 VPP, RL = 1 kΩ, VS = ±15 V

G = 2, RF = 1.21 kΩ

-100

-90

-80

-70

-60

-50

-40

1 M 10 M 100 M

f - Frequency - Hz

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.21 kΩ

VO = 2 VPP, RL = 100 Ω, VS = ±15 V

100 k

3rd Harmonic Distortion - dBc

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

2nd Harmonic Distortion − dBc

G = 5, RF = 1 kΩ, RL = 100 Ω, VS = ±15 V

−30 VO = 20 V

VO = 10 V

VO = 2 V

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

3rd Harmonic Distortion − dBc

G = 5, RF = 1 kΩ, RL = 100 Ω, VS = ±15 V

−30

VO = 20 V

VO = 10 V

VO = 2 V

-100

-95

-90

-85

-80

-70

-60

0 2 4 6 8 10 12

Harmonic Distortion - dBc

VO - Output Voltage Swing - V

-75

-65

HD2

14 16 18 20

HD3

Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 1 MHz VS = ±15 V

200

400

600

800

1000

1200

1400

1600

1800

2000

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

− Output Voltage − V

SR − Slew Rate −

sµ V/

Gain = 1 RL = 100 Ω RF = 1.78 kΩ VS = ±15 V

Fall

Rise

-100

-90

-80

-70

-60

-40

0 2 4 6 8 10 12

Harmonic Distortion - dBc

VO - Output Voltage Swing - V

-50

Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 8 MHz VS = ±15 V

HD3

HD2

14 16 18 20

1000

2000

3000

4000

5000

6000

0 1 2 3 4 5 6 7 8 9 10

VO - Output Voltage - V

SR - Slew Rate -

sµ V/

Gain = 2 RL = 100 Ω RF = 1.21 kΩ VS = ±15 V

Fall

Rise

TYPICAL CHARACTERISTICS ( ± 15 V) (continued)

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

3RD HARMONIC DISTORTION 2ND HARMONIC DISTORTION 3RD HARMONIC DISTORTION

vs vs vs

FREQUENCY FREQUENCY FREQUENCY

Figure 10. Figure 11. Figure 12.

2ND HARMONIC DISTORTION 3RD HARMONIC DISTORTION HARMONIC DISTORTION

vs vs vs

FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING

HARMONIC DISTORTION SLEW RATE SLEW RATE

OUTPUT VOLTAGE SWING OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP

Figure 13. Figure 14. Figure 15.

vs vs vs

Figure 16. Figure 17. Figure 18.

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100

1000

10 100 1 k 10 k 100 k

f − Frequency − Hz

− Current Noise −

− Voltage Noise −

pA/ Hz

nV/

n−

-1.25

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1.25

0 1 2 3 4 5 6 7 8 9 10

t - Time - ns

- Output Voltage - VV O

Gain = -2 RL = 100 Ω RF =1 kΩ VS = ±15 V

Rising Edge

Falling Edge

1000

2000

3000

4000

5000

6000

7000

8000

0 2 4 6 8 10 12 14 16 18 20

- Output Voltage - V

SR - Slew Rate -

sµ V/

Gain = 5 RL = 100 Ω RF = 1 kΩ VS = ±15 V

Fall

Rise

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0.5

1.5

2.5

3.5

4.5

0 2 4 6 8 10 12

t - Time - ns

- Output Voltage - VV O

Gain = -2 RL = 100 Ω RF = 1 kΩ VS = ±15 V

Rising Edge

Falling Edge

6.5

7.5

8.5

9.5

3 4 5 6 7 8 9 10 11 12 13 14 15

− Quiescent Current − mAI Q

VS − Supply Voltage − ±V

TA = −40 °C

TA = 85 °C

TA = 25 °C

100 k

1 M

10 M

100 M 1 G

− Quiescent Current − mAI Q

f − Frequency − Hz

VO = 4V

VO = 2V

Gain = 5 RF = 1 kΩ, RL = 100 Ω, VS = ±15 V

-16

-12

-8

-4

10 100 1000

- Load Resistance - Ω

- Output Voltage - VV O

VS = ±15 V TA = -40 to 85°C

0.5

1.5

2.5

-40-30-20-10 0 10 20 30 40 50 60 70 80 90

- Case Temperature - °C

- Input Offset Voltage - mV

VS = ±5 V

VS = ±15 V

0.5

1.5

2.5

3.5

4.5

5.5

6.5

-40-30-20 -10 0 10 20 30 40 50 60 70 80 90

- Case Temperature - °C

- Input Bias Currents -I

- Input Offset Currents -

Aµ

IIB-

IIB+

VS = ±15 V

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYPICAL CHARACTERISTICS ( ± 15 V) (continued)

SLEW RATE NOISE

OUTPUT VOLTAGE STEP FREQUENCY SETTLING TIME

vs vs

Figure 19. Figure 20. Figure 21.

QUIESCENT CURRENT QUIESCENT CURRENT

vs vs

SETTLING TIME SUPPLY VOLTAGE FREQUENCY

Figure 22. Figure 23. Figure 24.

INPUT BIAS AND

OUTPUT VOLTAGE OFFSET CURRENT INPUT OFFSET VOLTAGE

vs vs vs

LOAD RESISTANCE CASE TEMPERATURE CASE TEMPERATURE

Figure 25. Figure 26. Figure 27.

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-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

0.25

0.3

0 10 20 30 40 50 60 70

t - Time - ns

- Output Voltage - VV O

Output

Input

Gain = 2 RL = 100 Ω R

F =

1 kΩ

VS = ±15 V

100 k 1 M 10 M 100 M 1 G

PSRR+

VS = ±15 V

Rejection Ratio − dB

f − Frequency − Hz

CMRR

PSRR−

100

100 k 1 M 10 M 100 M 1 G

f − Frequency − Hz

Transimpedance Gain − dB Ohms

VS = ±15 V and ±5 V

−20

−15

−10

−5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

−4

−3

−2

−1

t − Time − µs

− Output Voltage − V

− Input Voltage − VV I

Gain = 5, RL = 100 Ω, RF = 1 kΩ, VS = ±15 V

-12

-10

-8

-6

-4

-2

0 10 20 30 40 50 60 70

t - Time - ns

- Output Voltage - VV O

Output

Input

Gain = -5 RL = 100 Ω RF =909 Ω VS = ±15 V

−6

−5

−4

−3

−2

−1

0 5 10 15 20 25 30 35 40

t − Time − ns

− Output Voltage − VV O

Output

Input

Gain = −5 RL = 100 Ω R

F =

909 Ω

VS = ±15 V

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

0 1 2 3 4 5 6 7 8

Number of Loads - 150 Ω

Differential Gain - %

Gain = 2 RF = 1.21 kΩ VS = ±15 V 40 IRE - NTSC and Pal Worst Case ±100 IRE Ramp

NTSC

PAL

0.01

0.02

0.03

0.04

0.05

0 1 2 3 4 5 6 7 8

Number of Loads − 150 Ω

Differential Phase −

Gain = 2 RF = 1.21 kΩ VS = ±15 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp

NTSC

PAL

0.01

0.1

100

1 M 10 M 100 M 1 G

f − Frequency − Hz

Closed-Loop Output Impedance − Ω

Gain = 2, R

ISO

= 5.11 Ω , RF = 1.21 KΩ, VS = ±15 V

−

1.21 kΩ 1.21 kΩ

5.11 Ω

TYPICAL CHARACTERISTICS ( ± 15 V) (continued)

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TRANSIMPEDANCE REJECTION RATIO

vs vs NONINVERTING SMALL-SIGNAL

FREQUENCY FREQUENCY TRANSIENT RESPONSE

Figure 28. Figure 29. Figure 30.

INVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL

TRANSIENT RESPONSE TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME

Figure 31. Figure 32. Figure 33.

DIFFERENTIAL GAIN DIFFERENTIAL PHASE IMPEDANCE

vs vs vs

NUMBER OF LOADS NUMBER OF LOADS FREQUENCY

Figure 34. Figure 35. Figure 36.

CLOSED-LOOP OUTPUT

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−0.1

0.1

0.2

0.3

0 1 2 3 4 5

t − Time − ms

− Output Voltage Level − VV O

Output Voltage

PowerDown Pulse − V

Power-down Pulse

6 7

Gain = 2, V

= 0.1 Vdc RL = 100 Ω VS = ±15 V and ±5 V

100

200

300

400

500

600

3 4 5 6 7 8 9 10 11 12 13 14 15

TA = -40°C

- Supply Voltage - ±V

Powerdown Quiescent Current -

TA = 85°C

Aµ

TA = 25°C

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYPICAL CHARACTERISTICS ( ± 15 V) (continued)

POWER-DOWN QUIESCENT

CURRENT

vs TURNON AND TURNOFF

SUPPLY VOLTAGE TIME DELAY

Figure 37. Figure 38.

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−4

−2

1 M 10 M 100 M 1 G

f − Frequency − Hz

RL = 100 Ω, VO = 200 mVPP. VS = ±5 V

G = −10, RF = 866 Ω

G = −5, RF = 909 Ω

G = −2, RF = 1 kΩ

G = −1, RF = 1.05 Ω

Inverting Gain − dB

-4

-2

1 M 10 M 100 M 1 G

f - Frequency - Hz

RL = 100 Ω, VO = 200 mVPP. VS = ±5 V

G = 10, RF = 909 Ω

G = 5, RF = 1 kΩ

G = 2, RF = 1.15 kΩ

G =1, RF = 1.5 kΩ

Noninverting Gain - dB

5.7

5.8

5.9

6.1

6.2

6.3

1 M 10 M 100 M

Gain = 2, RF = 1.21 kΩ, RL = 100 Ω, VO = 200 mVPP, VS = ±5 V

f - Frequency - Hz

Noninverting Gain - dB

-1.25

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

1.25

0 1 2 3 4 5 6 7 8 9 10

t - Time - ns

- Output Voltage - VV O

Gain = -2 RL = 100 Ω RF = 1 kΩ VS = ±5 V

Rising Edge

Falling Edge

1 M 10 M 100 M 1 G

f − Frequency − Hz

G = 5, RF = 1 kΩ

G = 2, RF = 1.15 kΩ

RL = 100 Ω, VO = 4 VPP, VS = ±5 V

Noninverting Gain − dB

−4

−2

1 M 10 M 100 M 1 G

f − Frequency − Hz

G = −5, RF = 909 Ω

G = −2, RF = 1 kΩ

RL = 100 Ω, VO = 4 VPP, VS = ±5 V

Inverting Gain − dB

−100

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

2nd Harmonic Distortion − dBc

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.15 kΩ

VO = 2 VPP, RL = 100 Ω, VS = ±5 V

100 k

-100

-90

-80

-70

-60

-50

-40

1 M 10 M 100 M

f - Frequency - Hz

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.15 kΩ

VO = 2 VPP, RL = 100 Ω, VS = ±5 V

100 k

3rd Harmonic Distortion - dBc

−100

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

2nd Harmonic Distortion − dBc

VO = 2 VPP, RL = 1 kΩ, VS = ±5 V

100 k

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.15 kΩ

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYPICAL CHARACTERISTICS ( ± 5 V)

NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL 0.1-dB GAIN FLATNESS

FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE

Figure 39. Figure 40. Figure 41.

NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE FREQUENCY RESPONSE SETTLING TIME

THS3091 THS3095

2ND HARMONIC DISTORTION 3RD HARMONIC DISTORTION 2ND HARMONIC DISTORTION

Figure 42. Figure 43. Figure 44.

vs vs vs

FREQUENCY FREQUENCY FREQUENCY

Figure 45. Figure 46. Figure 47.

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−100

−90

−80

−70

−60

−50

−40

1 M 10 M 100 M

f − Frequency − Hz

3rd Harmonic Distortion − dBc

VO = 2 VPP, RL = 1 kΩ, VS = ±5 V

100 k

G = 1, RF = 1.78 kΩ

G = 2, RF = 1.15 kΩ

-100

-90

-80

-70

-60

-40

-20

0 1 2 3 4 5 6

Harmonic Distortion - dBc

VO - Output Voltage Swing - V

HD2

HD3

-50

-30

Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 1 MHz VS = ±5 V

−100

−90

−80

−70

−60

−40

−20

0 1 2 3 4 5 6

Harmonic Distortion − dBc

VO − Output Voltage Swing − V

HD2

HD3

−50

−30

Gain = 5, RF = 1 kΩ RL = 100 Ω, f= 8 MHz VS = ±5 V

200

400

600

800

1000

1200

1400

1600

0 1 2 3 4 5

SR − Slew Rate − V/

− Output Voltage −V

sµ

Gain = 1 RL = 100 Ω RF = 1.21 kΩ VS = ±5 V

Fall

Rise

200

400

600

800

1000

1200

1400

1600

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

SR − Slew Rate − V/

− Output Voltage −V

sµ

Gain = 1 RL = 100 Ω RF = 1.78 kΩ VS = ±5 V

Fall

Rise

200

400

600

800

1000

1200

1400

1600

1800

2000

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

SR - Slew Rate - V/

- Output Voltage -V

sµ

Gain = 5 RL = 100 Ω RF = 1 kΩ VS = ±5 V

Fall

Rise

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

- Input Bias Current -

TC - Case Temperature - °C

VS = ±5 V

- Input Offset Current -

IB-

Aµ

IB+

100 k 1 M 10 M 100 M 1 G

− Quiescent Current − mAI

f − Frequency − Hz

VO = 4 V

VO = 2 V

Gain = 5 RF = 1 kΩ, RL = 100 Ω, VS = ±5 V

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0.5

1.5

2.5

3.5

10 100 1000

- Load Resistance - Ω

- Output Voltage - VV O

VS = ±5 V TA = -40 to 85°C

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

TYPICAL CHARACTERISTICS ( ± 5 V) (continued)

3RD HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION

vs vs vs

FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING

Figure 48. Figure 49. Figure 50.

SLEW RATE SLEW RATE SLEW RATE

vs vs vs

OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP

QUIESCENT CURRENT OUTPUT VOLTAGE OFFSET CURRENT

Figure 51. Figure 52. Figure 53.

vs vs vs

FREQUENCY LOAD RESISTANCE CASE TEMPERATURE

Figure 54. Figure 55. Figure 56.

INPUT BIAS AND

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-5

-4

-3

-2

-1

0 0.2 0.4 0.6 0.8 1

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

t - Time - µs

- Input Voltage - VV I

Gain = 5, RL = 100 Ω, RF = 1 kΩ, VS = ±5 V

- Output Voltage - AV O

100 k 1 M 10 M 100 M

VS = ±5 V

Rejection Ratio - dB

f - Frequency - Hz

PSRR-

PSRR+

CMRR

TYPICAL CHARACTERISTICS ( ± 5 V) (continued)

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

OVERDRIVE RECOVERY vs

REJECTION RATIO

TIME FREQUENCY

Figure 57. Figure 58.

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THS3091

1.21 kΩ

49.9 Ω

0.1 µF 6.8 µF

−V

−15 V

50-Ω Source

0.1 µF 6.8 µF

15 V

1.21 kΩ

49.9 Ω

50-Ω LOAD

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

APPLICATION INFORMATION

WIDEBAND, NONINVERTING OPERATION

The THS3091/5 are unity gain stable 235-MHz current-feedback operational amplifiers, designed to operate from a ± 5-V to ± 15-V power supply.

Figure 59 shows the THS3091 in a noninverting gain of 2-V/V configuration typically used to generate the performance curves. Most of the curves were characterized using signal sources with 50- Ω  source impedance, and with measurement equipment presenting a 50- Ω load impedance.

Figure 59. Wideband, Noninverting Gain

Configuration

Current-feedback amplifiers are highly dependent on the feedback resistor R

for maximum performance

and stability. Table 1 shows the optimal gain-setting resistors R

and R

at different gains to give

maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for RF. Conversely, increasing R

decreases the

bandwidth, but stability is improved.

Table 1. Recommended Resistor Values for

Optimum Frequency Response

THS3091 and THS3095 RFand RGvalues for minimal peaking

GAIN (V/V) RG( Ω ) RF( Ω )

–1 ± 15 and ± 5 1.05 k 1.05 k –2 ± 15 and ± 5 499 1 k –5 ± 15 and ± 5 182 909

–10 ± 15 and ± 5 86.6 866

with RL= 100 Ω

SUPPLY VOLTAGE

(V)

± 15 – 1.78 k

± 5 – 1.78 k

± 15 1.21 k 1.21 k

± 5 1.15 k 1.15 k

± 15 249 1 k

± 5 249 1 k

± 15 95.3 866

± 5 95.3 866

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WIDEBAND, INVERTING OPERATION

THS3091

49.9 Ω

50-Ω Source

1.21 kΩ

THS3091

499 Ω

50-Ω Source

1 kΩ

56.2 Ω

49.9 Ω

50-Ω LOAD

THS3091

499 Ω

0.1 µF 6.8 µF

−V

−15 V

50-Ω Source

0.1 µF 6.8 µF

15 V

1 kΩ

56.2 Ω

49.9 Ω

50-Ω LOAD

−

75 Ω

n Lines

O(1)

O(n)

75-Ω Transmission Line

1.21 kΩ 1.21 kΩ

−15 V

15 V

Figure 60 shows the THS3091 in a typical inverting gain configuration where the input and output impedances and signal gain from Figure 59 are retained in an inverting circuit configuration.

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Figure 60. Wideband, Inverting Gain

Configuration

SINGLE-SUPPLY OPERATION

The THS3091/5 have the capability to operate from a single-supply voltage ranging from 10 V to 30 V. When operating from a single power supply, biasing the input and output at mid-supply allows for the maximum output voltage swing. The circuits shown in Figure 61 show inverting and noninverting amplifiers configured for single-supply operations.

Figure 61. DC-Coupled, Single-Supply Operation

Video Distribution

The wide bandwidth, high slew rate, and high output drive current of the THS3091/5 matches the demands for video distribution for delivering video signals down multiple cables. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality.

Figure 62. Video Distribution Amplifier

Application

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10 100

− Capacitive Load − pF

Recommended

ISO

Ω

Gain = 5, RL = 100 Ω, VS = ±15 V

−

_ +

−V

49.9 Ω

1 kΩ

5.11 Ω

1 µF

249 Ω

100-Ω LOAD

ISO

_ +

−V

49.9 Ω

5.11 Ω

1 µF

249 Ω

27 pF

1 kΩ

100-Ω LOAD

_ +

−V

49.9 Ω

1 kΩ

Ferrite Bead

1 µF

249 Ω

100-Ω LOAD

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Driving Capacitive Loads

Applications such as FET line drivers can be highly capacitive and cause stability problems for high-speed amplifiers.

Figure 63 through Figure 68 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier’s feedback path. See Figure 63 for recommended resistor values versus capacitive load.

Figure 63. Recommended R

vs Capacitive Load

ISO

Placing a small series resistor, R

, between the

ISO

amplifier’s output and the capacitive load, as shown in Figure 64 , is an easy way of isolating the load capacitance.

Using a ferrite chip in place of R

, as shown in

ISO

Figure 65 , is another approach of isolating the output of the amplifier. The ferrite's impedance characteristic versus frequency is useful to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a ferrite with similar impedance to R

, 20 Ω - 50 Ω , at 100 MHz and low

ISO

impedance at dc. Figure 66 shows another method used to maintain

the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of R

. At high fre-

ISO

quency, the feedback is mainly via the 27-pF capacitor. The resistor R

in series with the negative

input is used to stabilize the amplifier and should be equal to the recommended value of R Replacing R

with a ferrite of similar impedance at

at unity gain.

about 100 MHz as shown in Figure 67 gives similar results with reduced dc offset and low-frequency noise. (See the ADDITIONAL REFERENCE MA- TERIAL section for expanding the usability of cur- rent-feedback amplifiers.)

Figure 64.

Figure 65.

Figure 66.

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_ +

−V

49.9 Ω

5.11 Ω

1 µF

249 Ω

27 pF

1 kΩ

100-Ω LOAD

−V

866 Ω

191 Ω

5.11 Ω

_ +

−V

1 kΩ

5.11 Ω

249 Ω

_ +

−V

1 kΩ

5.11 Ω

249 Ω

24.9 Ω

1 nF

Figure 67.

Figure 68 is shown using two amplifiers in parallel to double the output drive current to larger capacitive loads. This technique is used when more output current is needed to charge and discharge the load faster like when driving large FET transistors.

Figure 68.

Figure 69 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier.

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Figure 69. PowerFET Drive Circuit

SAVING POWER WITH POWER-DOWN FUNCTIONALITY AND SETTING THRESHOLD LEVELS WITH THE REFERENCE PIN

The THS3095 features a power-down pin (PD) which lowers the quiescent current from 9.5 mA down to 500 µA, ideal for reducing system power.

The power-down pin of the amplifier defaults to the negative supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation. To turn off the amplifier in an effort to conserve power, the power-down pin can be driven towards the positive rail. The threshold voltages for power-on and power-down are relative to the supply rails and are given in the specification tables. Below the Enable Threshold Voltage, the device is on. Above the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified.

Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain-setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs.

Figure 70 shows the total system output impedance which includes the amplifier output impedance in parallel with the feedback plus gain resistors, which cumulate to 2380 Ω . Figure 59 shows this circuit configuration for reference.

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500

1000

1500

2000

2500

100 k 1 M 10 M 100 M 1 G

−

1.21 kΩ 1.21 kΩ

50 Ω

f − Frequency − Hz

− Powerdown Output Impedance −

OPD

Ω

VS = ±15 V and ±5 V

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Figure 70. Power-down Output Impedance vs

As with most current feedback amplifiers, the internal architecture places some limitations on the system when in power-down mode. Most notably is the fact that the amplifier actually turns ON if there is a ± 0.7 V or greater difference between the two input nodes (V+ and V-) of the amplifier. If this difference exceeds ± 0.7 V, the output of the amplifier creates an output voltage equal to approximately [(V+ - V-) -0.7 V] × Gain. This also implies that if a voltage is applied to the output while in power-down mode, the V- node voltage is equal to V

O(applied)

and a large applied voltage at the output, the amplifier may actually turn ON due to the aforementioned behavior.

The time delays associated with turning the device on and off are specified as the time it takes for the amplifier to reach either 10% or 90% of the final output voltage. The time delays are in the order of microseconds because the amplifier moves in and out of the linear mode of operation in these transitions.

POWER-DOWN REFERENCE PIN OPERATION

In addition to the power-down pin, the THS3095 features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. In most split-supply applications, the reference pin is connected to ground. In either case, the user needs to be aware of voltage-level thresholds that apply to the power-down pin. The usable range at the REF pin is from V (V

PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL

- 4 V).

S+

× R

PERFORMANCE

Achieving optimum performance with a high-frequency amplifier, like the THS3091/5, requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.

Frequency

/(R

+ R

). For low gain configurations

S-

• Minimize the distance (< 0.25 in.) from the power supply pins to high-frequency 0.1-µF and 100-pF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board.

• Careful selection and placement of external components preserve the high-frequency performance of the THS3091/5. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use wirebound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2 k Ω , this parasitic capacitance can add a pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, consistent with load-driving considerations.

• Connections to other wideband devices on the board may be made with short direct traces or

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DIE

Side View (a)

DIE

End View (b)

Thermal

Pad

Bottom View (c)

0.140

0.060

0.010 vias

Top V iew

0.035

0.080

0.050

0.176

0.030

0.026

0.010

0.035

0.100

0.300

Pin 1

All Units in Inches

• Socketing a high-speed part like the THS3091/5

PowerPAD™ DESIGN CONSIDERATIONS

The THS3091/5 are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe on which the die is mounted [see Figure 71 (a) and Figure 71 (b)]. This arrangement results

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

through onboard transmission lines. For short in the lead frame being exposed as a thermal pad on connections, consider the trace and the input to the underside of the package [see Figure 71 (c)]. the next device as a lumped capacitive load. Because this thermal pad has direct thermal contact Relatively wide traces (50 mils to 100 mils) with the die, excellent thermal performance can be should be used, preferably with ground and achieved by providing a good thermal path away from power planes opened up around them. Estimate the thermal pad. Note that devices such as the the total capacitive load and determine if isolation THS3091/5 have no electrical connection between resistors on the outputs are necessary. Low the PowerPAD and the die. parasitic capacitive loads (< 4 pF) may not need an R

because the THS3091/5 are nominally

compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- Ω environment is not necessary onboard, and in fact, a higher impedance environment

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking.

improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS3091/5 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the

Figure 71. Views of Thermal Enhanced Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.

source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.

is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS3091/5 parts directly onto the board.

Figure 72. DDA PowerPAD PCB Etch and Via

Pattern

THS3091 THS3095

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Dmax



max

 T



where: P

Dmax

is the maximum power dissipation in the amplifier (W).

max

is the absolute maximum junction temperature (°C).

TA is the ambient temperature (°C).

θJA = θ

+ θ

θJC is the thermal coefficient from the silicon junctions to the

case (°C/W).

θCA is the thermal coefficient from the case to ambient air

(°C/W).

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

PowerPAD™ LAYOUT CONSIDERATIONS POWER DISSIPATION AND THERMAL

1. PCB with a top-side etch pattern is shown in Figure 72 . There should be etch for the leads as well as etch for the thermal pad.

2. Place 13 holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS3091/5 IC. These additional vias may be larger than the 10-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any potential voltage such as V acceptable as there is no electrical connection to the silicon.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS3091/5 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.

6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its 13 holes exposed. The bottom-side solder mask should cover the 13 holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process.

7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part

that is properly installed.

CONSIDERATIONS

The THS3091/5 incorporates automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately 160 ° C. When the junction temperature reduces to approximately 140 ° C, the amplifier turns on again. But, for maximum performance and reliability, the designer must ensure that the design does not exeed a junction temperature of 125 ° C. Between 125 ° C and 150 ° C, damage does not occur, but the performance of the amplifier begins to degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula.

S-

For systems where heat dissipation is more critical, the THS3091 and THS3095 are offered in an 8-pin SOIC (DDA) with PowerPAD package. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note (literature number SLMA002 ). The following graph also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.

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3.5

2.5

1.5

0.5

−40 −20 0 20 40 60 80 100

− Maximum Power Dissipation − W P

TA − Free-Air Temperature − °C

Results are With No Air Flow and PCB Size = 3”x 3”

θJA = 45.8°C/W for 8-Pin SOIC w/PowerPAD (DDA) θJA = 58.4°C/W for 8-Pin MSOP w/PowerPAD (DGN) θJA = 95°C/W for 8-Pin SOIC High−K Test PCB (D) θJA = 158°C/W for 8-Pin MSOP w/PowerPAD w/o Solder

θJA = 58.4°C/W

θJA = 95°C/W

θJA = 158°C/W

ΤJ = 125°C

θJA = 45.8°C/W

Figure 73. Maximum Power Distribution vs

Ambient Temperature

When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

DESIGN TOOLS

Evaluation Fixtures, Spice Models, and Application Support

Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS3091/5 operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device. The evaluation board can be ordered through the Texas Instruments Web site, www.ti.com, or through your local Texas Instruments sales representative.

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS3091/5 is available through the Texas Instruments Web site (www.ti.com). The Product Information Center (PIC) is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.

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VS+

VS−

FB1

VS−

6.8 µF

0.1 µF

GND

TP1 TP2

FB2

VS+

6.8 µF

VS+

0.1 µF

REF

PIN8

(2)

JP1

(2)

C10

(2)

JP2

(2)

(2) THS3095 EVM Only

R1 0 Ω

249 Ω

1 kΩ

VS−

REF

PIN8

Open

49.9 Ω R8

Open

R6 Open

49.9 Ω

THS3091DDA or THS3095DDA

THS3091 THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Figure 74. THS3091 EVM Circuit Configuration

Figure 75. THS3091 EVM Board Layout

Figure 76. THS3091 EVM Board Layout

(Second and Third Layers)

(Top Layer)

Figure 77. THS3091 EVM Board Layout

(Bottom Layer)

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SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Table 2. Bill of Materials

THS3091DDA and THS3095DDA EVM

ITEM DESCRIPTION

1 Bead, Ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 (Digi-Key) 240-1010-1-ND 2 Cap, 6.8 µF, Tanatalum, 50 V, 10% D C3, C6 2 (AVX) TAJD685K050R (Garrett) TAJD685K050R 3 Cap, 0.1 µF, ceramic, X7R, 50 V 0805 C9, C10 2 4 Cap, 0.1 µF, ceramic, X7R, 50 V 0805 C4, C7 2 (AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A 5 Resistor, 0 Ω , 1/8 W, 1% 0805 R9 1 6 Resistor, 249 Ω , 1/8 W, 1% 0805 R3 1 (KOA) RK73H2ALTD2490F (Garrett) RK73H2ALTD2490F 7 Resistor, 1 k Ω , 1/8 W, 1% 0805 R4 1 (KOA) RK73H2ALTD1001F (Garrett) RK73H2ALTD1001F 8 Open 1206 R8 1

9 Resistor, 0 Ω , 1/4 W, 1% 1206 R1 1 (KOA) RK73Z2BLTD (Garrett) RK73Z2BLTD 10 Resistor, 49.9 Ω , 1/4 W, 1% 1206 R2, R7 2 (KOA) RK73Z2BLTD49R9F (Garrett) RK73Z2BLTD49R9F 11 Open 2512 R5, R6 2

Header, 0.1-inch centers,

12 JP1, JP2 2

0.025-inch square pins

13 Connector, SMA PCB Jack J1, J2, J3 3 (Amphenol) 901-144-8RFX (Newark) 01F2208

Jack, banana receptacle,

14 J4, J5, J6 3 (SPC) 813 (Newark) 39N867

0.25-inch. dia. hole

15 Test point, black TP1, TP2 2 (Keystone) 5001 (Digi-Key) 5001K-ND

Standoff, 4-40 hex,

16 4 (Keystone) 1808 (Newark) 89F1934

0.625-inch length Screw, Phillips, 4-40,

17 4 SHR-0440-016-SN

0.25-inch IC, THS3091(3) (TI) THS3091DDA

18 U1 1

IC, THS3095(2) (TI) THS3095DDA

19 Board, printed-circuit 1

SMD REFERENCE PCB MANUFACTURER'S DISTRIBUTOR'S SIZE DESIGNATOR QTY PART NUMBER PART NUMBER

(2)

(AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A

(2)

(KOA) RK73Z2ALTD (Garrett) RK73Z2ALTD

(2)

(Sullins) PZC36SAAN (Digi-Key) S1011-36-ND

(TI) EDGE # 6446289 Rev. A (TI) EDGE # 6446290 Rev. A

(1) All items are designated for both the THS3091DDA and THS3095 EVMs unless otherwise noted. (2) THS3095 EVM only. (3) THS3091 EVM only.

(1)

(3) (2)

THS3091 THS3095

ADDITIONAL REFERENCE MATERIAL

• PowerPAD™ Made Easy, application brief (SLMA004 )

• PowerPAD™ Thermally Enhanced Package, technical brief (SLMA002 )

• Voltage Feedback vs Current Feedback Amplifiers, (SLVA051 )

• Current Feedback Analysis and Compensation (SLOA021)

• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081 )

• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013 )

• Expanding the Usability of Current-Feedback Amplifiers, 3Q 2003 Analog Applications Journal

(www.ti.com/sc/analogapps).

THERMAL PAD MECHANICAL DATA

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DDA (R-PDSO-G8)

THERMAL INFORMATION

This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from

the integrated circuit (IC).

For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Ins truments Literature No. SLMA002 and Application Brief, PowerPAD Made Easy, Texas Instruments Literature N o . SLMA004. Both documents are available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

Exposed Thermal Pad

2,85 1,27

NOTE: All linear dimensions are in millimeters

Exposed Thermal Pad Dimensions

2,85 1,27

Top View

PPTD042

PowerPAD is a trademark of Texas Instruments

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TEXAS INSTRUMENTS THS3091, THS3095 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual