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THS14F01
Technical data
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TEXAS INSTRUMENTS THS14F01, THS14F03 Technical data

查询THS14F01供应商
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
THS14F01, THS14F03
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
features
14-Bit Resolution
1 MSPS and 3 MSPS Speed Grades Available
On-Chip FIFO For Optimized Data Transfer
Differential Nonlinearity (DNL) ±0.6 LSB Typ
Integral Nonlinearity (INL) ±1.5 LSB Typ
Internal Reference
Differential Inputs
Programmable Gain Amplifier
µP Compatible Parallel Interface
Timing Compatible With TI 6000 DSP Family
3.3-V Single Supply
Power-Down Mode
Monolithic CMOS Design
PFB PACKAGE
DD
IN+AVAGND
AGND
applications
(TOP VIEW)
DD
DD
AV
AGND
DV
xDSL Front Ends Communication Industrial Control Instrumentation Automotive
A0A1FOVL
INT
CS
47 46 45 44 4348 42
IN–
1
AV
VBG
CML REF+ REF–
AGND AGND DGND
NC – No internal connection
DD
OV D13 D12
2 3 4 5 6 7 8 9 10 11 12
13
14 15
D11
DD
DV
16
DGND
17 18 19 20
D9D8D7
D10
40 39 3841
21
DD
DV
22 23 24
D5D4D3
D6
37
36 35 34 33 32 31 30 29 28 27 26 25
WR OE DGND DGND CLK DV
DD
DV
DD
D0 D1 D2 DV
DD
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
description
The THS14F01 and THS14F03 are 14-bit, 1 MSPS/ 3 MSPS, single supply analog-to-digital converters with a FIFO, internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier.
Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The THS14F01 and THS14F03 are designed for use with 3.3-V systems, and with a high-speed µP compatible parallel interface, making them the first choice for solutions based on high-performance DSPs like the TI TMS320C6000 series.
The THS14F01 and THS14F03 are available in a TQFP-48 package in standard commercial and industrial temperature ranges.
functional block diagram
VBG
IN+
IN–
CLK
1.5 V BG
PGA
0..7 dB
REF+
REF
14-Bit
ADC
6
CONTROL
LOGIC
AVAILABLE OPTIONS
T
A
0°C to 70°C
–40°C to 85°C
14 15
PACKAGED DEVICE
TQFP (PFB)
THS14F01CPFB, THS14F03CPFB
THS14F01IPFB, THS14F03IPFB
32-Word
FIFO+
Buffer
REF–
D[13:0] + OV bit
A[1:0]
CS WR OE INT FOVL
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
Terminal Functions
TERMINAL
NAME NO.
A[1:0] 40, 41 I Address input AGND 7,8, 44,
AV
DD
CLK 32 I Clock input CML 4 Reference midpoint. This pin requires a 0.1-µF capacitor to AGND. CS 37 I Chip select input. Active low DGND 9, 15, 25,
DV
DD
D[13:0] 11, 12, 13,
FOVL 39 O FIFO Overflow. Asserted when FIFO is full. Programmable polarity IN+ 48 I Positive differential analog input IN– 1 I Negative differential analog input INT 38 O Interrupt output. Asserted when FIFO trigger level is reached. Programmable polarity OE 35 I Output enable. Active low OV 10 O Out of range output REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND. REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND. VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND. WR 36 I Write signal. Active low
45, 46
2, 43, 47 P Analog power supply
33, 34
14, 20, 26,
30, 31, 42
16, 17, 18, 19, 21, 22, 23, 24, 27,
28, 29
P Analog ground
P Digital ground
P Digital power supply
I/O Data inputs/outputs
SLAS285 – JUNE 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, (AVDD to AGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, (DVDD to DGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VBG – 0.3 V to AV
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range – 0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range – 0.3 V to DV Operating free-air temperature range, T
: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS14F01, THS14F03
Clock frequenc
f
Operating free-air temperature
°C
INL
Integral nonlinearit
Best fit
LSB
THD
Total harmonic distortion
dB
SNR
Signal-to-noise ratio
dB
SINAD
Signal-to-noise ratio
distortion
dB
SFDR
Spurious free dynamic range
dB
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DV High level digital input, V Low level digital input, V Load capacitance, C
y,
Clock duty cycle 40% 50% 60%
p
CLK
DD
IH
IL
L
THS14F01 0.1 1 1 MHz THS14F03 0.1 3 3 MHz
p
C suffix 0 25 70 I suffix –40 25 85
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
I
DDA
I
DDD
DC Characteristics
DNL Differential nonlinearity ±0.6 ±1 LSB
AC Characteristics
ENOB Effective number of bits 11.2 1 1.5 Bits
†
FIFO trigger level = 10 samples. Performance is ensured with the output enable signal (OE on CLK.
Analog supply current 81 90 mA Digital supply current 5 10 mA Power 270 360 mW Power down current 20 µA
†
Resolution 14 Bits
y
Offset error IN+ = IN–, PGA = 0 dB 0.3 %FSR Gain error PGA = 0 dB 1 %FSR
†
+
p
Analog input bandwidth 140 MHz
THS14F01 THS14F03
THS14F01/3 fi = 100 kHz –81 THS14F03 fi = 1 MHz –78 THS14F01/3 fi = 100 kHz 72 THS14F03 fi = 1 MHz 70 72 THS14F01/3 fi = 100 kHz 70 THS14F03 fi = 1 MHz 69 70 THS14F01/3 fi = 100 kHz 80 THS14F03 fi = 1 MHz 73 80
) being low during no more than one rising clock edge
3 3.3 3.6 V 2 3.3 V
0 0.8 V 5 15 pF
±1.5 ±2.5 ±1.5 ±2.5
°
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VBG
f
Clock frequenc
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
electrical characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Voltage
Bandgap voltage, internal mode 1.425 1.5 1.575 V Input impedance 40 kΩ Positive reference voltage, REF+ 2.5 V Negative reference voltage, REF– 0.5 V Reference difference, ∆REF, REF+ – REF– 2 V Accuracy, internal reference 5% Temperature coefficient 40 ppm/°C Voltage coefficient 200 ppm/V
Analog Inputs
Positive analog input, IN+ 0 AV Negative analog input, IN– 0 AV Analog input voltage difference ∆Ain = IN+ – IN–, V Input impedance 25 kΩ PGA range 0 7 dB PGA step size 1 dB PGA gain error ±0.25 dB
Digital Inputs
V
IH
V
IL
Digital Outputs
V
OH
V
OL
I
OZ
Clock Timing (CS low)
CLK
t
d
High-level digital input 2 V Low-level digital input 0.8 V Input capacitance 5 pF Input current ±1 µA
High-level digital output IOH = 50 µA 2.6 V Low-level digital output IOL = 50 µA 0.4 V Output current, high impedance ±10 µA
y
Output delay time 25 ns Latency 9.5 Cycles
THS14F01, THS14F03
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
ref
V V V
DD DD
= REF+ – REF– –V
ref
THS14F01 0.1 1 1 MHz THS14F03
ref
0.1 3 3 MHz
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS14F01, THS14F03 14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS14F01/3 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results are stored in the FIFO 9.5 clock cycles after the input signal was sampled.
Analog
Input
S9
S11
S10
S12
CLK
INT
Data
to FIFO
t
w(CLK)
t
t
w(CLK)
d
C1 C2
C3
Figure 1. Sample Timing
INT goes active if the programmed FIFO level is reached. INT is either low or high active depending on the polarity bit (IP) within the control word. This signal is set synchronously to the CLK signal. It is reset by a read access to the FIFO once the number of samples in the FIFO is below the programmed threshold level.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
PARAMETER MEASUREMENT INFORMATION
The parallel interface of the THS14F01/3 ADC features 3-state buffers making it possible to directly connect it to a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available at address 0.
The timing of the control signals is described in the following sections. The FIFO can be disabled by setting FC to 0 (FIFO reset, default at power on). This makes it possible to access
the device synchronously. In this case the data is updated on every clock cycle.
Analog
Input
S9
S11
S10
S12
CLK
D[13:0]
OV
OE
A[1:0]
CS
t
w(CLK)
C0
t
en
X X
t
su(OE-ACS)
t
w(CLK)
t
d
C1 C2
C3
Figure 2. Sample Timing
t
dis
t
h(A)
t
h(CS)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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