Texas Instruments THS1408CPFB, THS1403IPFB, THS1403QPFB, THS1403CPFB, THS1401QPFB Datasheet
...
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
14-Bit Resolution
D
1, 3, and 8 MSPS Speed Grades Available
D
Differential Nonlinearity (DNL) ±0.6 LSB Typ
D
Integral Nonlinearity (INL) ±1.5 LSB Typ
D
Internal Reference
D
Differential Inputs
D
Programmable Gain Amplifier
D
µP Compatible Parallel Interface
D
Timing Compatible With TMS320C6000 DSP
D
3.3-V Single Supply
D
Power-Down Mode
D
Monolithic CMOS Design
applications
D
xDSL Front Ends
D
Communication
D
Industrial Control
D
Instrumentation
14 15
WR
OE
DGND
DGND
CLK
DV
DD
DV
DD
D0
D1
D2
DV
DD
DGND
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
IN–
AV
DD
VBG
CML
REF+
REF–
AGND
AGND
DGND
OV
D13
D12
17 18 19 20
A0A1NC
NC
47 46 45 44 4348 42
IN+AVAGND
AGND
AGND
D5D4D3
DGND
D9D8D7
D6
40 39 3841
21
22 23 24
37
13
CS
D11
D10
PFB PACKAGE
(TOP VIEW)
DD
AV
DD
DV
DD
DV
DD
DV
DD
NC – No internal connection
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 MSPS, single supply analog-to-digital converters with
an internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier .
Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios.
The THS1401, THS1403, and THS1408 are designed for use with 3.3-V systems, and with a high-speed µP
compatible parallel interface, making them the first choice for solutions based on high-performance DSPs like
the TI TMS320C6000 series.
The THS1401, THS1403, and THS1408 are available in a TQFP-48 package in standard commercial and
industrial temperature ranges.
functional block diagram
PGA
0..7 dB
REF
14-Bit
ADC
Buffer
14 15
CONTROL
LOGIC
REF+
REF–
IN+
IN–
D[13:0] + OV bit
A[1:0]
6
CLK
1.5 V
BG
VBG
CS
WR
OE
AVAILABLE OPTIONS
PACKAGED DEVICE
T
A
TQFP
(PFB)
0°C to 70°C
THS1401CPFB,
THS1403CPFB,
THS1408CPFB,
–40°C to 85°C
THS1401IPFB,
THS1403IPFB,
THS1408IPFB
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
A[1:0] 40, 41 I Address input
AGND 7,8, 44,
45, 46
P Analog ground
AV
DD
2, 43, 47 P Analog power supply
CLK 32 I Clock input
CML 4 Reference midpoint. This pin requires a 0.1-µF capacitor to AGND.
CS 37 I Chip select input. Active low
DGND 9, 15, 25,
33, 34
P Digital ground
DV
DD
14, 20, 26,
30, 31, 42
P Digital power supply
D[13:0] 11, 12, 13,
16, 17, 18,
19,21, 22,
23, 24, 27,
28, 29
I/O Data inputs/outputs
NC 38, 39 No connection, do not use. Reserved
IN+ 48 I Positive differential analog input
IN– 1 I Negative dif ferential analog input
OE 35 I Output enable. Active low
OV 10 O Out of range output
REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND.
REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND.
VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND.
WR 36 I Write signal. Active low
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, (AVDD to AGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, (DVDD to DGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range, VBG – 0.3 V to AV
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range – 0.3 V to AV
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range – 0.3 V to DV
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
Supply voltage, AVDD, DV
DD
3 3.3 3.6 V
High level digital input, V
IH
2 3.3 V
Low level digital input, V
IL
0
0.8
V
Load capacitance, C
L
5 15 pF
THS1401 0.1 1 1 MHz
Clock frequency, f
CLK
THS1403 0.1 3 3 MHz
THS1408 0.1 8 8 MHz
Clock duty cycle 40% 50% 60%
p
p
C suffix 0 25 70 °C
Operating free-air temperature
I suffix –40 25 85 °C
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
I
DDA
Analog supply current 81 90 mA
I
DDD
Digital supply current 5 10 mA
Power 270 360 mW
Power down current 20 µA
DC Characteristics
Resolution 14 Bits
DNL Differential nonlinearity ±0.6 ±1 LSB
THS1401 ±1.5 ±2.5 LSB
INL Integral nonlinearity
THS1403
Best fit
±1.5 ±2.5 LSB
THS1408 ±3 ±5 LSB
Offset error IN+ = IN–, PGA = 0 dB 0.3 %FSR
Gain error PGA = 0 dB 1 %FSR
AC Characteristics
ENOB Effective number of bits 11.2 1 1.5 Bits
THS1401/3/8 fi = 100 kHz –81
THD Total harmonic distortion
THS1403/8
fi = 1 MHz –78
dB
THS1408 fi = 4 MHz –77
THS1401/3/8 fi = 100 kHz 72
SNR Signal-to-noise ratio
THS1403/8
fi = 1 MHz 70 72
dB
THS1408 fi = 4 MHz 71
THS1401/3/8 fi = 100 kHz 70
SINAD Signal-to-noise ratio + distortion
THS1403/8
fi = 1 MHz 69 70
dB
THS1408 fi = 4 MHz 70
THS1401/3/8 fi = 100 kHz 80
SFDR Spurious free dynamic range
THS1403/8
fi = 1 MHz 73 80
dB
THS1408 fi = 4 MHz 80
Analog input bandwidth 140 MHz
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Voltage
Bandgap voltage, internal mode 1.425 1.5 1.575 V
VBG
Input impedance 40 kΩ
Positive reference voltage, REF+ 2.5 V
Negative reference voltage, REF– 0.5 V
Reference difference, ∆REF, REF+ – REF– 2 V
Accuracy, internal reference 5%
T emperature coef ficient 40 ppm/°C
Voltage coefficient 200 ppm/V
Analog Inputs
Positive analog input, IN+ 0 AV
DD
V
Negative analog input, IN– 0 AV
DD
V
Analog input voltage difference ∆Ain = IN+ – IN–, V
ref
= REF+ – REF– –V
ref
V
ref
V
Input impedance 25 kΩ
PGA range 0 7 dB
PGA step size 1 dB
PGA gain error ±0.25 dB
Digital Inputs
V
IH
High-level digital input 2 V
V
IL
Low-level digital input 0.8 V
Input capacitance 5 pF
Input current ±1 µA
Digital Outputs
V
OH
High-level digital output IOH = 50 µA 2.6 V
V
OL
Low-level digital output IOL = 50 µA 0.4 V
I
OZ
Output current, high impedance ±10 µA
Clock Timing (CS low)
THS1401 0.1 1 1 MHz
f
CLK
Clock frequency
THS1403
0.1 3 3 MHz
THS1408 0.1 8 8 MHz
t
d
Output delay time 25 ns
Latency 9.5 Cycles
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.
S9
S10
S11
S12
CLK
Data
Out
Analog
Input
C1 C2
C3
t
w(CLK)
t
w(CLK)
t
d
Figure 1. Sample Timing
The parallel interface of the THS1401/3/8 ADC features 3-state buffers making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register,
and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are
available at address 0.
The timing of the control signals is described in the following sections.
THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248 – DECEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
read timing (15-pF load)
PARAMETER MIN TYP MAX UNIT
t
su(OE–ACS)
Address and chip select setup time 4 ns
t
en
Output enable 15 ns
t
dis
Output disable
10
ns
t
h(A)
Address hold time 1 15 ns
t
h(CS)
Chip select hold time 0 ns
NOTE: All timing parameters refer to a 50% level.
DATA
ADDRESS
CS
OE
D[13:0]
O V
A[1:0]
X X
t
su(OE–ACS)
t
en
t
h(CS)
t
dis
t
h(A)
Figure 2. Read Timing
Loading...