TEXAS INSTRUMENTS THS1401-EP, THS1403-EP, THS1408-EP Technical data
查询THS1408-EP供应商
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
features
D
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
D
Extended Temperature Performance up to
–55°C to 125°C
D
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
Enhanced Product Change Notification
D
Qualification Pedigree
D
14-Bit Resolution
D
1, 3, and 8 MSPS Speed Grades
D
Differential Nonlinearity (DNL) ±0.6 LSB Typ
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
†
D
D
D
D
D
D
D
D
D
applications
D
D
D
D
D
PHP PACKAGE
(TOP VIEW)
THS1401-EP THS1403-EP THS1408-EP
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
Integral Nonlinearity (INL) ±1.5 LSB Typ
Internal Reference
Differential Inputs
Programmable Gain Amplifier
µP Compatible Parallel Interface
Timing Compatible With TMS320C6000 DSP
3.3-V Single Supply
Power-Down Mode
Monolithic CMOS Design
xDSL Front Ends
Communication
Industrial Control
Instrumentation
Automotive and Selected Military
DD
IN+AVAGND
47 46 45 44 4348 42
IN–
1
AV
VBG
CML
REF+
REF–
AGND
AGND
DGND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DD
OV
D13
D12
2
3
4
5
6
7
8
9
10
11
12
13
14 15
D11
DD
DV
16
DGND
DD
AV
AGND
AGND
17 18 19 20
D9D8D7
D10
DD
A0A1NC
DV
40 39 3841
21 22 23 24
DD
DV
D5D4D3
D6
NC
37
CS
36
35
34
33
32
31
30
29
28
27
26
25
WR
OE
DGND
DGND
CLK
DV
DD
DV
DD
D0
D1
D2
DV
DD
DGND
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1
THS1401-EP THS1403-EP THS1408-EP
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
description
The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 MSPS, single supply analog-to-digital converters with an
internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier.
Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The
THS1401, THS1403, and THS1408 are designed for use with 3.3-V systems, and with a high-speed µP compatible
parallel interface, making them the first choice for solutions based on high-performance DSPs like the TI
TMS320C6000 series.
ORDERING INFORMA TION
–40°C to 125°C PQFP – PHP THS1401QPHPEP THS1401QE
–40°C to 125°C PQFP – PHP THS1403QPHPEP THS1403QE
–55°C to 125°C PQFP – PHP THS1408MPHPEP THS1408ME
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
functional block diagram
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
VBG
IN+
IN–
CLK
1.5 V
BG
PGA
0..7 dB
REF+
REF
14-Bit
ADC
6
CONTROL
LOGIC
14 15
Buffer
REF–
D[13:0] + OV bit
A[1:0]
CS
WR
OE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1401-EP THS1403-EP THS1408-EP
I/O
DESCRIPTION
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
Terminal Functions
TERMINAL
NAME NO.
A[1:0] 40, 41 I Address input
AGND 7,8, 44,
AV
DD
CLK 32 I Clock input
CML 4 Reference midpoint. This pin requires a 0.1-µF capacitor to AGND.
CS 37 I Chip select input. Active low
DGND 9, 15, 25,
DV
DD
D[13:0] 11, 12, 13,
NC 38, 39 No connection, do not use. Reserved
IN+ 48 I Positive differential analog input
IN– 1 I Negative dif ferential analog input
OE 35 I Output enable. Active low
OV 10 O Out of range output
REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND.
REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND.
VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND.
WR 36 I Write signal. Active low
45, 46
2, 43, 47 Analog power supply
33, 34
14, 20, 26,
30, 31, 42
16, 17, 18,
19, 21, 22,
23, 24, 27,
28, 29
Analog ground
Digital ground
Digital power supply
I/O Data inputs/outputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
THS1401-EP THS1403-EP THS1408-EP
Operating free-air temperature
°C
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, (AV
Supply voltage, (DV
Reference input voltage range, VBG – 0.3 V to AV
Analog input voltage range – 0.3 V to AV
Digital input voltage range – 0.3 V to DV
Operating free-air temperature range, T
to AGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
to DGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
: Q suffix –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
†
DD
DD
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
TYP UNIT
Thermal resistance, junction-to-ambient, Θ
Thermal resistance, junction-to-case, Θ
†
Thermal resistance is modeled data, is not production tested, and is given for informational purposes only.
JA
JC
28.8 °C/W
0.79 °C/W
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, AVDD, DV
High level digital input, V
Low level digital input, V
Load capacitance, C
Clock frequency, f
Clock duty cycle 45% 50% 55%
p
CLK
DD
IH
IL
L
THS1401 0.1 1 1 MHz
THS1403 0.1 3 3 MHz
THS1408 0.1 8 8 MHz
p
Q suffix –40 25 125
M suffix –55 25 125
3 3.3 3.6 V
2 3.3 V
0
0.8
5 15 pF
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1401-EP THS1403-EP THS1408-EP
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Supply
I
DDA
I
DDD
DC Characteristics
DNL Differential nonlinearity ±0.6 ±1 LSB
INL Integral nonlinearity
AC Characteristics
ENOB Effective number of bits 11.2 11.5 Bits
THD Total harmonic distortion
SNR Signal-to-noise ratio
SINAD Signal-to-noise ratio + distortion
SFDR Spurious free dynamic range
Analog supply current AVDD = 3.6 V 81 90 mA
Digital supply current DVDD = 3.6 V 5 10 mA
Power AVDD = DVDD = 3.6 V 270 360 mW
Power down current 20 µA
Resolution 14 Bits
THS1401 ±1.5 ±2.5
THS1403
THS1408 ±3.5 ±7.5
Offset error IN+ = IN–, PGA = 0 dB 0.3 %FSR
Gain error PGA = 0 dB 1.75 %FSR
THS1401/3/8 fi = 100 kHz –81
THS1403/8
THS1408 fi = 4 MHz –77
THS1401/3/8 fi = 100 kHz 72
THS1403/8
THS1408 fi = 4 MHz 71
THS1401/3/8 fi = 100 kHz 70
THS1403/8
THS1408 fi = 4 MHz 70
THS1401/3/8 fi = 100 kHz 80
THS1403, THS1408
THS1408 fi = 4 MHz 80
Analog input bandwidth 140 MHz
Best fit
fi = 1 MHz –78
fi = 1 MHz 70 72
fi = 1 MHz 69 70
fi = 1 MHz 71 80
±2 ±3
LSB
dB
dB
dB
dB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
THS1401-EP THS1403-EP THS1408-EP
VBG
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
electrical characteristics over recommended operating free-air temperature range,
AVDD = DVDD = 3.3 V (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference Voltage
Bandgap voltage, internal mode 1.425 1.5 1.575 V
Input impedance 40 kΩ
Positive reference voltage, REF+ 2.5 V
Negative reference voltage, REF– 0.5 V
Reference difference, ∆REF, REF+ – REF– 2 V
Accuracy, internal reference 5%
Temperature coefficient 40 ppm/°C
Voltage coefficient 200 ppm/V
Analog Inputs
Positive analog input, IN+ 0 AV
Negative analog input, IN– 0 AV
Analog input voltage difference ∆Ain = IN+ – IN–, V
Input impedance 25 kΩ
PGA range 0 7 dB
PGA step size 1 dB
PGA gain error ±0.25 dB
Digital Inputs
V
IH
V
IL
Digital Outputs
V
OH
V
OL
I
OZ
Clock Timing (CS low)
f
CLK
t
d
†
This parameter is not production tested.
High-level digital input 2 V
Low-level digital input 0.8 V
Input capacitance 5 pF
Input current ±1 µA
High-level digital output IOH = 50 µA 2.6 V
Low-level digital output IOL = 50 µA 0.4 V
Output current, high impedance ±10 µA
Clock frequency
Output delay time 25 ns
Latency 9.5 Cycles
THS1401 0.1
THS1403
THS1408 0.1
= REF+ – REF– –V
ref
0.1
ref
†
†
†
ref
V
V
V
DD
DD
V
1 1 MHz
3 3 MHz
8 8 MHz
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1401-EP THS1403-EP THS1408-EP
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SGLS129A – JULY 2002 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.
Analog
Input
S9
S11
S10
S12
CLK
Data
Out
t
w(CLK)
t
t
w(CLK)
d
C1 C2
C3
Figure 1. Sample Timing
The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to
a data bus. The output buffers are enabled by driving the OE input low.
Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and
the offset register . Which register is read is determined by the address inputs A[1,0]. The ADC results are available
at address 0.
The timing of the control signals is described in the following sections.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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