TEXAS INSTRUMENTS THS1215 Technical data

T

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THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

features

D

Configurable Input Functions:
– Single-Ended
– Single-Ended With Offset
– Differential

D

3.3-V Supply Operation

D

Internal Voltage Reference

D

Out-of-Range Indicator

D

Power-Down Mode

applications

D

Camcorders

D

Digital Cameras

D

Copiers

D

Communications

D

Test Instruments

D

Baseband Digitization

DW OR PW PACKAGE

(TOP VIEW)

AGND

CON1
CON0

EXTREF

AIN+
AIN–

AGND

AV
REFT

REFB

OVRNG

DD

D11

D10

D9

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CLK
AV

DD

OE
D0
D1
D2
D3
D4
DV

DD

DGND
D5
D6
D7
D8

description

The THS1215 is a CMOS, low power, 12-bit, 15 MSPS analog-to-digital converter (ADC) that operates with a

3.3-V supply . The THS1215 gives circuit developers complete flexibility . The analog input to the THS1215 can
be either single-ended, single-ended with offset, or differential. The THS1215 provides a wide selection of
voltage references to match the user’s design requirements. For more design flexibility, the internal reference
can be bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in the THS1215’s input range.

The speed, resolution, and single-supply operation of the THS1215 are suited for applications in video,
multimedia, high-speed acquisition, and communications. The speed and resolution ideally suit charge-couple
device (CCD) input systems such as digital copiers, digital cameras, and camcorders. The wide input voltage
range between V

REFB

and V

allows the THS1215 to be designed into multiple systems.

REFT

The THS1215C is characterized for operation from 0°C to 70°C. The THS1215I is characterized for operation
from –40°C to 85°C.

AVAILABLE OPTIONS

A

0°C to 70°C THS1215CPW THS1215CDW

–40°C to 85°C THS1215IPW THS1215IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

28-TSSOP (PW) 28-SOIC (DW)

PACKAGED DEVICES

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2001, Texas Instruments Incorporated

1

THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

functional block diagram

DV

DD

CLK

AIN+

AIN–

CON0
CON1

Sample
and Hold

Configuration

Control

Circuit

Internal

Reference

Circuit

Timing Circuitry

12-Bit ADC

EXTREF

REFT

REFB

AV

DD

3-State
Output

Buffers

DGNDAGND

OVRNG

D[11:0]

OE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER

Terminal Functions

TERMINAL

NAME NO.

AGND 1, 7 I Analog ground
AV

DD

AIN+ 5 I Positive analog input
AIN– 6 I Negative analog input
CLK 28 I ADC conversion clock
CON1 2 I Configuration Input 1
CON0 3 I Configuration Input 0
DGND 19 I Digital ground
DV

DD

D11 12 O ADC data bit 11
D10 13 O ADC data bit 10
D9 14 O ADC data bit 9
D8 15 O ADC data bit 8
D7 16 O ADC data bit 7
D6 17 O ADC data bit 6
D5 18 O ADC data bit 5
D4 21 O ADC data bit 4
D3 22 O ADC data bit 3
D2 23 O ADC data bit 2
D1 24 O ADC data bit 1
D0 25 O ADC data bit 0
EXTREF 4 I Reference select input, high = external, low = internal
OVRNG 11 O Out of range indicator
OE 26 I Output enable, high = disable, low = enable
REFT 9 I/O Upper ADC reference voltage
REFB 10 I/O Lower ADC reference voltage

8, 27 I Analog supply

20 I Digital supply

THS1215

WITH POWER DOWN

SLAS292 – MARCH 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range: AV

to AGND, DVDD to DGND –0.3 to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

†

AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range, REFT, REFB to AGND –0.3 to AV
Analog input voltage range, AIN+, AIN– to AGND –0.3 to AV
Clock input voltage range, CLK to AGND –0.3 to AV
Digital input voltage range, digital input to DGND –0.3 to DV
Digital output voltage range, digital output to DGND –0.3 to DV
Operating junction temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STG

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

DD
DD
DD
DD
DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 15 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

f

s

min

to T

max

) ( unless

otherwise noted)

sampling rate and resolution

PARAMETER MIN NOM MAX UNIT

f

‡

Sample frequency 5

s

Resolution 12 Bits

The clock frequency may be extended to 5 MHz without degradation in specified performance.

‡

15 MSPS

analog inputs (all supplies = 3.3 V)

PARAMETER MIN TYP MAX UNIT

Positive analog input, AIN+ 0 AV
Negative analog input, AIN– 0 AV

MODE1 –1 V

Analog input voltage difference for zero scale ADC out, (AIN+) – (AIN–)

Analog input voltage difference for full scale ADC out, (AIN+) – (AIN–)

Switched input capacitance, C
Aperture delay time, t
Aperture uncertainty (jitter) 2 ps
DC leakage current (input = ±FS) 10 µA

d(ap)

i

MODE2 –2 V
MODE3 0 V
MODE1 1 V
MODE2 2 V
MODE3 1 V

DD
DD

6 pF
2 ns

V
V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIHHigh level input voltage

VILLow level input voltage

THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 15 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

f

s

otherwise noted) (continued)

digital inputs and outputs (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Digital Inputs

p

p

I

High level input current 1 µA

IH

I

Low level input current –1 µA

IL

C

Input capacitance 5 pF

i

Digital Outputs

V

High level output voltage I

OH

V

Low level output voltage I

OL

High impedance output current ±1 µA

tr/t

Rise/fall time CL = 10 pF 5.5 ns

f

All other inputs 0.8 × DV
CLK 0.8 × AV
All other inputs 0.2 × DV
CLK 0.2 × AV

= 50 µA DVDD–0.4 V

load

= –50 µA 0.4 V

load

DD
DD

min

to T

max

DD
DD

) (unless

V

V

power supply (CLK = 15 MHz)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

XV

DD

I

DD

I

(analog)

I

(digital)

I

I(standby)

t

(PU)

P

D

P

D(STBY)

PSRR Power supply rejection ratio ±0.1 %FS

Supply voltage (all supplies) 3 3.3 3.6 V
Supply current active – total 45 53.5 mA
Supply current active – analog 34 mA
Supply current active – digital 11 mA
Standby supply current CLK = 0 MHz 10 µA
Power-up time for references from standby 100 µs
Power dissipation CLK = 15 MHz 148 177 mW
Standby power dissipation CLK = 0 MHz 36 µW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

electrical characteristics over recommended operating conditions (AVDD = DVDD = 3.3 V,

= 15 MHz/50% duty cycle, MODE = 1, 1-V input span, internal reference, T

f

s

otherwise noted) (continued)

REFT, REFB reference voltages (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Internal Reference

V

REFT

V

REFB

V

REF

External Reference

Internal or External Reference

C

T

C

B

C

TB

Upper reference voltage 2.15 V
Lower reference voltage 1.15 V
Differential reference voltage, V
Differential reference voltage, V

Externally applied V
Externally applied V
Externally applied (V
External mode V

V

decoupling capacitor value 0.1 µF

REFT

V

decoupling capacitor value 0.1 µF

REFB

Decoupling capacitor V

REFT
REFB

REFT–VREFB

to V

REFT

REFT–VREFB
REFT–VREFB

reference voltage range 2 2.5 V
reference voltage range 1.05 1.3 V

) reference voltage range 0.75 1.05 V

impedance 9 kΩ

REFB

to V

REFT

REFB

accuracy –5% 5%

to T

min

0.95 1 1.05 V

10 µF

max

) (unless

dc accuracy (linearity)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Number of missing codes All modes 0 codes
DNL Differential nonlinearity All modes ±0.43 ±0.9 LSB
INL Integral nonlinearity All modes ±0.6 ±1.5 LSB

Offset error All modes 0.5 1.2 %FSR

Gain error All modes 0.5 3.5 %FSR

dynamic performance (all supplies = 3.3 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ENOB Effective number of bits fi = 3.58 MHz 10.7 11.1 Bits
THD Total harmonic distortion fi = 3.58 MHz –81.2 dB
SNR Signal-to-noise ratio fi = 3.58 MHz 67.4 68.9 dB
SINAD Signal-to-noise + distortion fi = 3.58 MHz 66 68.6 dB
SFDR Spurious free dynamic range fi = 3.58 MHz 72 81.7 dB

Analog input bandwidth 180 MHz

Differential phase, DP 0.12 degree
G

Differential gain 0.01%

(diff)

timing (all supplies = 3.3 V)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

f

CLK

t

d(O)

t

d(PZ)

t

d(EN)

†

The clock frequency may be extended down to 5 MHz without degradation in specified performance.

Clock frequency

Clock duty cycle 45% 50% 55%

Output delay time 19 ns

Delay time, output disable to Hi-Z output 3.2 ns

Delay time, output enable to output valid 16 19 ns

Latency 5 cycles

†

5 15 MHz

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing diagram

THS1215

3.3-V, 12-BIT, 15 MSPS, LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH POWER DOWN

SLAS292 – MARCH 2001

PARAMETER MEASUREMENT INFORMATION

Analog

CLK

OE

D[9:0]

OE

D[9:0]

S1

123456789

S2 S3

t

d(EN)

t

PIPELINE

t

d(O)

S1 S2 S3

Figure 1. Input Timing

t

d(EN)

Hi–Z Hi–Z

Data Data Data

t

d(PZ)

10

t

d(PZ)

THS1215

1.5 V

BAND

GAP

Figure 2. Output Timing

Figure 3. Reference Generation

REFT

C

T

C

TB

REFB

C

B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7