Texas Instruments THS12082QDAR, THS12082QDA Datasheet

THS12082

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS271 – MA Y 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Simultaneous Sampling of 2 Single-Ended
Signals or 1 Differential Signal

D

Integrated 16 Word FIFO

D

Signal-to-Noise and Distortion Ratio: 66 dB
at fI = 2 MHz

D

Differential Nonlinearity Error: ±1 LSB

D

Integral Nonlinearity Error: ±1.5 LSB

D

Auto-Scan Mode for 2 Inputs

D

3-V or 5-V Digital Interface Compatible

D

Low Power: 216 mW Max

D

5-V Analog Single Supply Operation

D

Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy

D

Parallel µC/DSP Interface

applications

D

Radar Applications

D

Communications

D

Control Applications

D

High-Speed DSP Front-End

D

Automotive Applications

description

The THS12082 is a CMOS, low-power, 12-bit, 8 MSPS analog-to-digital converter (ADC). The speed,
resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed
acquisition, and communications. A multistage pipelined architecture with output error correction logic provides
for no missing codes over the full operating temperature range. Internal control registers allow for programming
the ADC into the desired mode. The THS12082 consists of two analog inputs, which are sampled
simultaneously . These inputs can be selected individually and confugured to single-ended or differential inputs.
An integrated 16 word deep FIFO allows the storage of data in order to take the load off of the processor
connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In the single conversion mode, a single and
simultaneous conversion can be initiated by using the single conversion start signal (CONVST). The conversion
clock in the single conversion mode is generated internally using a clock oscillator circuit. In the continuous
conversion mode, an external clock signal is applied to the CONV_CLK input of the THS12082. The internal
clock oscillator is switched off in the continuous conversion mode.

The THS12082C is characterized for operation from 0°C to 70°C, and the THS12082I is characterized for
operation from –40°C to 85°C.

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Copyright  2000, Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

D0
D1
D2
D3
D4
D5

BV

DD

BGND

D6
D7
D8

D9
RA0/D10
RA1/D11

CONV_CLK (CONVST

)

DATA_AV

OV_FL
RESET
AINP
AINM
REFIN
REFOUT
REFP
REFM
AGND
AV

DD

CS0
CS1
WR

(R/W)
RD
DV

DD

DGND

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THS12082
12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

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AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

TSSOP

(DA)

0°C to 70°C THS12082CDA

–40°C to 85°C THS12082IDA

functional block diagram

Logic

and

Control

Control

Register

S/H

S/H

Single-Ended

and/or

Differential

MUX

12-Bit

Pipeline

ADC

+
–

REFP

REFM

1.225 V
REF

2.5 V

FIFO

16 × 12

12 12

Buffers

REFOUT

DATA_AV
OV_FL
BV

DD

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10/RA0
D11/RA1

BGND

AGND DGND

3.5 V

1.5 V

AV

DD

DV

DD

REFP

REFM

AINP

AINM

CONV_CLK (CONVST

)
CS0
CS1

RD

WR (R/W)

RESET

REFIN

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Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AINP 30 I Analog input, single-ended or positive input of differential channel A
AINM 29 I Analog input, single-ended or negative input of differential channel A
AV

DD

23 I Analog supply voltage
AGND 24 I Analog ground
BV

DD

7 I Digital supply voltage for buffer
BGND 8 I Digital ground for buffer
CONV_CLK

(CONVST

)

15 I Digital input. This input is used to apply an external conversion clock in the continuous conversion mode.

In the single conversion mode, this input functions as the conversion start (CONVST

) input. A high to low
transition on this input holds simultaneously the selected analog input channels and initiates a single
conversion of all selected analog inputs.

CS0 22 I Chip select input (active low)
CS1 21 I Chip select input (active high)
DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level

information of the internal FIFO. This signal can be configured to be active low or high and can be
configured as a static level or pulse output. See Table 7.

DGND 17 I Digital ground. Ground reference for digital circuitry.
DV

DD

18 I Digital supply voltage
D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB
RA0/D10 13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This

is required for writing to control register 0 and control register 1. See Table 8.

RA1/D11 14 I/O/Z Digital input, output (D11 = MSB). The data line D1 1 is also used as an address line (RA1) for the control

register. This is required for writing to control register 0 and control register 1. See Table 8.

OV_FL 32 O Overflow output. Indicates whether an overflow in the FIFO occurred. OV_FL is set to active high level if

an overflow occurs. It is set back to low level with a reset of the THS12082 or a reset of the FIFO.

REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin be

connected to the reference output REFOUT.

REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed
through control register 0. See Table 6.

REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed

through control register 0. See Table 6.
RESET 31 I Hardware reset of the THS12082. Sets the control register to default values.
REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference

output requires a capacitor of 10 µF to AGND for filtering and stability .
RD

†

19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,

active low as a data read select from the processor. See timing section.
WR (R/W)

†

20 I This input is programmable. It functions as a read-write input (R/W) and can also be configured as a

write-only input (WR

), which is active low and used as data write select from the processor. In this case,

the RD

input is used as a read input from the processor. See timing section.

†

The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range: DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BGND to BVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to AV

DD

–0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: THS12082C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS12082I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permenent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supply

MIN NOM MAX UNIT

AV

DD

4.75 5 5.25

Supply voltage

DV

DD

3 3.3 5.25

V

BV

DD

3 3.3 5.25

analog and reference inputs

MIN NOM MAX UNIT

Analog input voltage in single-ended configuration V

REFM

V

REFP

V
Common-mode input voltage VCM in differential configuration 1 2.5 4 V
External reference voltage,V

REFP

(optional) 3.5 AVDD–1.2 V

External reference voltage, V

REFM

(optional) 1.4 1.5 V

Input voltage difference, REFP – REFM 2 V

digital inputs

MIN NOM MAX UNIT

p

BVDD = 3 V 2 V

High-level input voltage, V

IH

BVDD = 5.25 V 2.6 V

p

BVDD = 3 V 0.6 V

Low-level input voltage, V

IL

BVDD = 5.25 V 0.6 V
Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 8 MHz
CONV_CLK pulse duration, clock high, t

w(CONV_CLKH)

DVDD = 3 V to 5.25 V 62 83 5000 ns
CONV_CLK pulse duration, clock low, t

w(CONV_CLKL)

DVDD = 3 V to 5.25 V 62 83 5000 ns

p

p

THS12082CDA 0 70

°

Operating free-air temperature, T

A

THS12082IDA –40 85

°C

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electrical characteristics over recommended operating conditions, V

REFP

= 3.5 V, V

REFM

= 1.5 V

(unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Digital inputs

I

IH

High-level input current DVDD = digital inputs –50 50 µA

I

IL

Low-level input current Digital input = 0 V –50 50 µA

C

i

Input capacitance 5 pF

Digital outputs

V

OH

High-level output voltage I

OH

= –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V

V

OL

Low-level output voltage I

OL

= 50 µA, BVDD = 3.3 V, 5 V 0.4 V

I

OZ

High-impedance-state output current CS1 = DGND, CS0 = DVDD –10 10 µA

C

O

Output capacitance 5 pF

C

L

Load capacitance at databus D0 – D11 30 pF

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electrical characteristics over recommended operating conditions, AVDD = 5 V,
DV

DD

= BVDD = 3.3-V, fs = 8 MSPS, V

REF

= internal (unless otherwise noted)

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 Bits

Accuracy

Integral nonlinearity, INL ±1.5 LSB
Differential nonlinearity , DNL ±1 LSB

After calibration in single-ended mode –15 15 mV

Offset error

After calibration in differential mode –5 5 mV

Gain error 1% FSR

Analog input

Input capacitance 15 pF
Input leakage current V

AIN

= V

REFM

to V

REFP

±10 µA

Internal voltage reference

Accuracy, V

REFP

3.33 3.5 3.67 V

Accuracy, V

REFM

1.42 1.5 1.58 V
T emperature coef ficient 50 PPM/°C
Reference noise 100 µV
Accuracy, REFOUT 2.475 2.5 2.525 V

Power supply

I

DDA

Analog supply current AVDD =5 V, BVDD = DVDD = 3.3 V 36 40 mA

I

DDD

Digital supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA

I

DDB

Buffer supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA

I

DD_P

Supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 7 mA
Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW
Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW

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electrical characteristics over recommended operating conditions, V

REF

= internal, fs = 8 MSPS,

f

I

= 2 MHz at –1dBFS (unless otherwise noted)

ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential mode 63 68 dB

SINAD

Signal-to-noise ratio

+

distortion

Single-ended mode (see Note 1) 64 dB
Differential mode 64 69 dB

SNR

Signal-to-noise ratio

Single-ended mode (see Note 1) 65 dB
Differential mode –73 –69 dB

THD

T otal harmonic distortion

Single-ended mode –73 –69 dB

ENOB

Differential mode 10.3 11 Bits

(SNR)

Effective number of bits

Single-ended mode (see Note 1) 10.4 Bits

p

Differential mode 68 75 dB

SFDR

Spurious free dynamic range

Single-ended mode 68 75 dB

Analog Input

Full-power bandwidth with a source impedance of
150 Ω in differential configuration.

Full scale sinewave, –3 dB 96 MHz

Full-power bandwidth with a source impedance of
150 Ω in single-ended configuration.

Full scale sinewave, –3 dB 54 MHz

Small-signal bandwidth with a source impedance of
150 Ω in differential configuration.

100 mVpp sinewave, –3 dB 96 MHz

Small-signal bandwidth with a source impedance of
150 Ω in single-ended configuration.

100 mVpp sinewave, –3 dB 54 MHz

NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the

sampling clock.

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timing specifications (AV

DD

= BVDD = DVDD = 5 V, V

REFP

= 3.5 V, V

REFM

= 1.5 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(DATA_AV)

Delay time 5 ns

t

d(o)

Delay time 5 ns

t

d(pipe)

Latency 5

CONV

CLK

timing specification of the single conversion mode

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

c

Clock cycle of the internal clock oscillator 119 125 131 ns

t

w1

Pulse duration, CONVST 1.5×t

c

ns

t

dA

Aperture time 1 ns

1 analog input 2×t

c

t2Time between consecutive start of single conversion

2 analog inputs 3×t

c

ns

1 analog input, TL = 1 6×t

c

2 analog inputs, TL = 2 7×t

c

ns

1 analog input, TL = 4 3×t2 +6×t

c

Delay time, DATA_AV becomes active for the trigger

2 analog inputs, TL = 4

t2 +7×t

c

ns

t

d(DATA_AV)

y, _ gg

level condition: TRIG0 = 1, TRIG1 = 1

1 analog input, TL = 8

7×t2 +6×t

c

2 analog inputs, TL = 8 3×t2 +7×t

c

ns

1 analog input, TL = 14 13×t2 +6×t

c

2 analog inputs, TL = 12 5×t2 +7×t

c

ns

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detailed description

reference voltage

The THS12082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to

3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

analog inputs

The THS12082 consists of two analog inputs, which are sampled simultaneously . These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.

analog-to-digital converter

The THS12082 uses a 12-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit
stages, which achieves a high sample rate with low power consumption. The THS12082 distributes the
conversion over several smaller ADC subblocks, refining the conversion with progressively higher accuracy as
the device passes the results from stage to stage. This distributed conversion requires a small fraction of the
number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the
stages permits the first stage to operate on a new input sample while the second through the eighth stages
operate on the seven preceding samples.

conversion modes

The conversion can be performed in two different conversion modes. In the single conversion mode, the
conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In
the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal.

sampling rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. T able
1 shows the maximum conversion rate in the continuous conversion mode for different combinations.

Table 1. Maximum Conversion Rate

CHANNEL CONFIGURATION NUMBER OF CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

1 single-ended channel 1 8 MSPS
2 single-ended channels 2 4 MSPS
1 differential channel 1 8 MSPS

The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:

fc

+

8 MSPS

# channels

Table 2 shows the maximum conversion rate in the single conversion mode.

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sampling rate (continued)

Table 2. Maximum Conversion Rate in Single Conversion Mode

CHANNEL CONFIGURATION

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

1 single-ended channel 1 4 MSPS
2 single-ended channels 2 2.67 MSPS
1 differential channel 1 4 MSPS

In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.

A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.

The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.

Figure 1 shows the timing of the single conversion mode. In this mode, up to two analog input channels can be
selected to be sampled simultaneously (see Table 2).

CONVST

AIN

Sample N

t

1

t

1

t

d(A)

t

2

t

DATA_AV

DATA_AV,

Trigger Level = 1

Figure 1. Timing of Single Conversion Mode

The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time t

DATA_A V

, until DA TA_AV becomes active is given by: t

DATA_A V

= t

pipe

+ n × tc. This
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.

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continuous conversion mode

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO. The first conversion value is written into the FIFO with a latency of 8 + TL (trigger level)
clock cycles after the FIFO reset.

Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 8 MSPS in this mode. The timing of the DA T A_A V signal is shown here in the case
of a trigger level set to 1 or 4.

Sample N

Channel 1

Sample N+1

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

Sample N+7

Channel 1

Sample N+8

Channel 1

Data N–5

Channel 1

Data N–4

Channel 1

Data N–3

Channel 1

Data N–2

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+1

Channel 1

Data N+2

Channel 1

Data N+3

Channel 1

t

d(A)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

t

c

t

d(O)

t

d(DATA_AV)

t

d(DATA_AV)

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 1

DATA_AV,

Trigger Level = 4

t

d(pipe)

50% 50%

Figure 2. Timing of Continuous Conversion Mode (1-channel operation)

Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DA TA_A V signal shown here is for a trigger
level set to 2 or 4.

AIN

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 2

DATA_AV,

Trigger Level = 4

Data N–3

Channel 2

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

Data N–1

Channel 2

Data N

Channel 1

Data N

Channel 2

Data N+1

Channel 1

Data N+1

Channel 2

t

d(DATA_AV)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

t

d(A)

Sample N

Channel 1,2

Sample N+1
Channel 1,2

Sample N+2
Channel 1,2

Sample N+3
Channel 1,2

Sample N+4
Channel 1,2

t

c

t

d(O)

t

d(Pipe)

t

d(DATA_AV)

50% 50%

Figure 3. Timing of Continuous Conversion Mode (2-channel operation)

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digital output data format

The digital output data format of the THS12082 can be in either binary format or in twos complement format.
The following tables list the digital outputs for the analog input voltages.

Table 3. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

FFFh

AIN = (V

REFP

+ V

REFM

)/2 800h

AIN = V

REFM

000h

Table 4. Twos Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

7FFh

AIN = (V

REFP

+ V

REFM

)/2 000h

AIN = V

REFM

800h

Table 5. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

V

REF

= V

REFP

– V

REFM

Vin = V

REF

FFFh
Vin = 0 800h
Vin = –V

REF

000h

Table 6. Twos Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

V

REF

= V

REFP

– V

REFM

Vin = V

REF

7FFh
Vin = 0 000h
Vin = –V

REF

800h

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