Texas Instruments SN65LVDS109DBT, SN65LVDS109DBTR, SN65LVDS117DGGR Datasheet

SN65LVDS109, SN65LVDS117

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Two Line Receivers and Eight (’109) or
Sixteen (’117) Line Drivers Meet or Exceed
the Requirements of ANSI EIA/TIA-644
Standard

D

Designed for Signaling Rates up to 632
Mbps

D

Outputs Arranged in Pairs From Each Bank

D

Enabling Logic Allows Individual Control of
Each Driver Output Pair, Plus all Outputs

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load

D

Electrically Compatible With L VDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
T ermination Networks

D

Propagation Delay Times < 4.5 ns

D

Output Skew Less Than 550 ps
Bank Skew Less Than150 ps
Part-to-Part Skew Less Than 1.5 ns

D

Total Power Dissipation Typically <500 mW
With All Ports Enabled and at 200 MHz

D

Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
VCC < 1.5 V

D

Bus-Pin ESD Protection Exceeds 12 kV

D

Packaged in Thin Shrink Small-Outline
Package With 20 mil Terminal Pitch

description

The SN65LVDS109 and SN65LVDS117 are
configured as two identical banks, each bank
having one differential line receiver connected to
either four (’109) or eight (’117) differential line
drivers. The outputs are arranged in pairs having
one output from each of the two banks. Individual
output enables are provided for each pair of
outputs and an additional enable is provided for all
outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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GND

V

CC

V

CC

GND

NC

ENM

ENA
ENB
ENC
END

NC

GND

1A
1B

GND

V

CC

V

CC

GND

2A
2B

GND

NC
ENE
ENF

ENG

ENH

NC

NC

GND

V

CC

V

CC

GND

A1Y
A1Z
A2Y
A2Z
B1Y
B1Z
B2Y
B2Z
C1Y
C1Z
C2Y
C2Z
D1Y
D1Z
D2Y
D2Z
E1Y
E1Z
E2Y
E2Z
F1Y
F1Z
F2Y
F2Z
G1Y
G1Z
G2Y
G2Z
H1Y
H1Z
H2Y
H2Z

SN65LVDS117

DGG PACKAGE

(TOP VIEW)

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GND

V

CC

GND

NC

ENM

ENA
ENB

1A
1B

GND

2A

2B
ENC
END

NC
NC

GND

V

CC

GND

A1Y
A1Z
A2Y
A2Z
NC
B1Y
B1Z
B2Y
B2Z
NC
C1Y
C1Z
C2Y
C2Z
NC
D1Y
D1Z
D2Y
D2Z

SN65LVDS109

DBT PACKAGE

(TOP VIEW)

SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The intended application of these devices, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock and data distribution trees.

The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.

SN65LVDS109, SN65LVDS117

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

B2Z

B2Y

B1Z

B1Y

A2Z

A2Y

A1Z

A1Y

ENA

ENM

ENB

1A
1B

C2Z

C2Y

C1Z

C1Y

ENC

D2Z

D2Y

D1Z

D1Y

END

E2Z

E2Y

E1Z

E1Y

ENE

F2Z

F1Z

ENF

F2Y

F1Y

2A
2B

G2Z

G2Y

G1Z

G1Y

ENG

H2Z

H2Y

H1Z

H1Y

ENH

B2Z

B2Y

B1Z

B1Y

A2Z

A2Y

A1Z

A1Y

ENA

ENM

ENB

1A
1B

C2Z

C2Y

C1Z

C1Y

ENC

D2Z

D2Y

D1Z

D1Y

END

SN65LVDS109 SN65LVDS117

2A
2B

SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

selection guide to LVDS splitters

The SN65L VDS109 and SN75LVDS117 are both members of a family of L VDS splitters and repeaters. A brief
overview of the family is provided by the following table.

LVDS SPLITTER AND REPEATER FAMILY

DEVICE

NUMBER

OF INPUTS

NUMBER OF

OUTPUTS

PACKAGE COMMENTS

SN65LVDS104 1 LVDS 4 LVDS 16-pin D 4-port LVDS repeater
SN65LVDS105 1 LVTTL 4 LVDS 16-pin D 4-port TTL-to-LVDS repeater
SN65LVDS108 1 LVDS 8 LVDS 38-pin DBT 8-port LVDS repeater
SN65LVDS109 2 LVDS 8 LVDS 38-pin DBT Dual 4-Port LVDS repeater
SN65LVDS116 1 LVDS 16 LVDS 64-pin DGG 16-port LVDS repeater
SN65LVDS117 2 LVDS 16 LVDS 64-pin DGG Dual 8-port LVDS repeater

FUNCTION TABLE

INPUTS

OUTPUTS

VID = VA – V

B

ENM ENx xY xZ

X L X Z Z
X X L Z Z

VID ≥ 100 mV H H H L

–100 mV < VID < 100 mV H H ? ?

VID ≤–100 mV H H L H

equivalent input and output schematic diagrams

300 kΩ300 kΩ

V

CC

7 V 7 V

A Input B Input

V

CC

5 Ω

7 V

Y or Z
Output

10 kΩ

7 V

300 kΩ

50 Ω

V

CC

Enable

Inputs

300 kΩ

(ENM Only)

(ENx Only)

SN65LVDS109, SN65LVDS117

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, Enable inputs –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A, B, Y or Z –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge, Y, Z, and GND (see Note 2) Class 3, A:12 kV, B: 500 V. . . . . . . . . . . . . . . . . . . . . . . . .

All pins Class 3, A: 4 kV, B: 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 85°C

POWER RATING

DBT 1277 mW 10.2 mW/°C 644 mW

DGG 2094 mW 16.7 mW/°C 1089 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Magnitude of differential input voltage, VID 0.1 3.6 V

Common-mode input voltage, V

IC

Ť

V

ID

Ť

2

2.4 –

Ť

V

ID

Ť

2

V

VCC – 0.8 V

Operating free-air temperature, T

A

–40 85 °C

SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SLLS369C – AUGUST 1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ITH+

Positive-going differential input voltage threshold

100

V

ITH–

Negative-going differential input voltage threshold

See Figure 1 and Table 1

–100

mV

VOD Differential output voltage magnitude

247 340 454

∆VOD

Change in differential output voltage magnitude
between logic states

R

L

=

100 Ω

,

V

ID

=

±100 mV

,

See Figure 1 and Figure 2

–50 50

mV

V

OC(SS)

Steady-state common-mode output voltage 1.125 1.375 V

∆V

OC(SS)

Change in steady-state common-mode output
voltage between logic states

See Figure 3

–50 50

mV

V

OC(PP)

Peak-to-peak common-mode output voltage 50 150

Enabled, RL = 100 Ω 46 64

pp

SN65LVDS109

Disabled 6 8

ICCSupply current

Enabled, RL = 100 Ω 85 122

mA

SN65LVDS117

Disabled 6 8

p

p

VI = 0 V –2 –20

IIInput current (A or B inputs)

VI = 2.4 V –1.2

µ

A

I

I(OFF)

Power-off input current (A or B inputs) VCC = 1.5 V, VI = 2.4 V 20 µA

I

IH

High-level input current (enables) VIH = 2 V 20 µA

I

IL

Low-level input current (enables) VIL = 0.8 V 10 µA

p

VOY or VOZ = 0 V ±24

IOSShort-circuit output current

VOD = 0 V ±12

mA

I

OZ

High-impedance output current VO = 0 V or V

CC

±1 µA

I

O(OFF)

Power-off output current VCC = 1.5 V, VO = 3.6 V ±1 µA

C

IN

Input capacitance (A or B inputs) VI = 0.4 sin (4E6πt) + 0.5 V 5

p

C

O

Output capacitance (Y or Z outputs) VI = 0.4 sin (4E6πt) + 0.5 V, Disabled 9.4

pF

†

All typical values are at 25°C and with a 3.3 V supply.