Texas Instruments SN65LVDS104D, SN65LVDS104DR, SN65LVDS104PW, SN65LVDS104PWR, SN65LVDS105D Datasheet

D

Receiver and Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
– SN65LVDS105 Receives Low-Voltage TTL

(LVTTL) Levels

– SN65LVDS104 Receives Differential Input

Levels, ±100 mV

D

Designed for Signaling Rates up to
630 Mbps

D

Operates From a Single 3.3-V Supply

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load

D

Propagation Delay Time
– SN65LVDS105 . . . 2.2 ns (Typ)
– SN65LVDS104 . . . 3.1 ns (Typ)

D

Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, L VCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Networks

D

Driver Outputs Are High Impedance When
Disabled or With VCC <1.5 V

D

Bus-Pin ESD Protection Exceeds 16 kV

D

SOIC and TSSOP Packaging

description

The SN65LVDS104 and SN65LVDS105 are a
differential line receiver and a LVTTL input
(respectively) connected to four differential line
drivers that implement the electrical characteris­tics of low-voltage differential signaling (LVDS).
LVDS, as specified in EIA/TIA-644 is a data
signaling technique that offers low-power, low­noise coupling, and switching speeds to transmit
data at speeds up to 655 Mbps at relatively long
distances. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to
the environment, and other system characteris­tics.)

SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

SN65LVDS104

D OR PW PACKAGE

(TOP VIEW)

EN1
EN2
EN3
V

CC

GND

EN4

1
2
3
4
5

A

6

B

7
8

16
15
14
13
12
11
10

1Y
1Z
2Y
2Z
3Y
3Z
4Y

9

4Z

logic diagram (positive logic)

’LVDS104

EN1
EN2

EN3

A
B

EN4

’LVDS105

EN1
EN2

EN3

A

EN4

SN65LVDS105

D OR PW PACKAGE

(TOP VIEW)

EN1

1

16

EN2

2

15

EN3

3

14

V

4

CC

GND

A

NC

EN4

13

5

12

6

11

7

10

8

1Y
1Z
2Y
2Z
3Y
3Z
4Y

9

4Z

1Y
1Z

2Y
2Z

3Y
3Z

4Y
4Z

1Y
1Z

2Y
2Z

3Y
3Z

4Y
4Z

The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  1999, Texas Instruments Incorporated

1

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

description (continued)

The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters. A brief overview of the
family is provided in the table below.

Selection Guide to L VDS Repeaters

DEVICE

SN65LVDS22 2 LVDS 2 LVDS 16-pin D Dual multiplexed LVDS repeater
SN65LVDS104 1 LVDS 4 LVDS 16-pin D 4-Port LVDS repeater
SN65LVDS105 1 LVTTL 4 LVDS 16-pin D 4-Port TTL-to-LVDS repeater
SN65LVDS108 1 LVDS 8 LVDS 38-pin DBT 8-Port LVDS repeater
SN65LVDS109 2 LVDS 8 LVDS 38-pin DBT Dual 4-port LVDS repeater
SN65LVDS116 1 LVDS 16 LVDS 64-pin DGG 16-Port LVDS repeater
SN65LVDS117 2 LVDS 16 LVDS 64-pin DGG Dual 8-port LVDS repeater

VID = VA - V

VID ≥ 100 mV H H L Open H L H

–100 mV < VID < 100 mV H ? ? X L Z Z

VID ≤ –100 mV H L H X X Z Z

H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don’t care

NO. INPUTS NO. OUTPUTS PACKAGE COMMENT

Function Tables

SN65LVDS104 SN65LVDS105

INPUT

B

X X Z Z L H L H
X L Z Z H H H L

#EN #Y #Z A #EN #Y #Z

OUTPUT INPUT OUTPUT

equivalent input and output schematic diagrams

V

CC

A

Input

7 V 7 V

300 kΩ300 kΩ

B
Input

EN and

A (’LVDS105)

Input

7 V

50 Ω

300 kΩ

V

10 kΩ

CC

5 Ω

Y or Z
Output

7 V

V

CC

2

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g

IC

SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC(see Note 1) –0.5 to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range, Enable inputs –0.5 to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A, B, Y or Z –0.5 to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (see Note 2); Y, Z, and GND Class 3, A:16 kV, B: 600 V. . . . . . . . . . . . . . . . . . . . . . . .

All pins Class 3, A:7 kV, B: 500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

2. T ested in accordance with MIL-STD-883C Method 3015.7

DISSIPATION RATING TABLE

PACKAGE

D 950 mW 7.6 mW/°C 494 mW

PW 774 mW 6.2 mW/°C 402 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
and with no air flow.

TA ≤ 25°C

POWER RATING

OPERATING FACTOR‡

ABOVE TA = 25°C

TA = 85°C

POWER RATING

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Magnitude of differential input voltage, VID 0.1 3.6 V

Common-mode input voltage, V

Operating free-air temperature, T

CC

IH

IL

IC

A

3 3.3 3.6 V
2 V

0.8 V

Ť

Ť

Ť

V

ID

2

–40 85 °C

2.4 –
VCC–0.8 V

Ť

V

ID

2

V

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3

SN65LVDS104, SN65LVDS105

See Figure 1 and Table 1

mV

L

,

ICCSupply current

IIInput current (A or B inputs)

A

IOSShort-circuit output current

C
See

See Figure 4

See Figure 5

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

SN65LVDS104 electrical characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

ITH+

V

ITH–

VOD Differential output voltage magnitude
∆VOD
V

OC(SS)

∆V

OC(SS)

V

OC(PP)

I

I(OFF)

I

IH

I

IL

I

OZ

I

O(OFF)

C

IN

C

O

†

All typical values are at 25°C and with a 3.3 V supply.

Positive-going differential input voltage threshold
Negative-going differential input voltage threshold

R

= 100Ω,

Change in differential output voltage magnitude between
logic states

Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltage

between logic states
Peak-to-peak common-mode output voltage 25 150 mV

pp

p

Power-off Input current VCC= 1.5 V, VI= 2.4 V 20 µA
High-level input current (enables) VIH = 2 V 20 µA
Low-level input current (enables) VIL = 0.8 V 10 µA

High-impedance output current VO = 0 V or 2.4 V ±1 µA
Power-off output current VCC = 1.5 V, VO = 2.4 V ±1 µA
Input capacitance (A or B inputs) VI = 0.4 sin (4E6πt) + 0.5 V 3 pF

Output capacitance (Y or Z outputs)

p

p

VID= ± 100 mV,
See Figure 1 and Figure 2

See Figure 3

Enabled, RL = 100Ω 23 35 mA
Disabled 3 8 mA
VI = 0 V –2 –11 –20
VI = 2.4 V –1.2 –3

VOY or VOZ = 0 V ±10 mA
VOD = 0 V ±10 mA

VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled

–100

247 340 454
–50 50

–50 50 mV

100

9.4 pF

mV

µ

SN65LVDS104 switching characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

t

PHL

t

r

t

f

t

sk(p)

t

sk(o)

t

sk(pp)

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at 25°C and with a 3.3 V supply.

‡

t

sk(o)

§

t

sk(pp)

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Propagation delay time, low-to-high-level output 2.4 3.2 4.2 ns
Propagation delay time, high-to-low-level output 2.2 3.1 4.2 ns
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t
Channel-to-channel output skew
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output 7.2 15 ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output 6 15 ns

is the magnitude of the time difference between the t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

PHL

– t

|)

PLH

§

‡

or t

PLH

of all drivers of a single device with all of their inputs connected together.

PHL

RL = 100Ω,

= 10 pF,

L

Figure 4

p

0.3 0.8 1.2 ns

0.3 0.8 1.2 ns
150 500 ps

20 100 ps

1.5 ns

8.4 15 ns

3.6 15 ns

4

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L

,

ICCSupply current

IOSShort-circuit output current

C
See

9

See Figure 9

See Figure 10

SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

SN65LVDS105 electrical characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

VOD Differential output voltage magnitude

∆VOD
V

OC(SS)

∆V

OC(SS)

V

OC(PP)

I

IH

I

IL

I

OZ

I

O(OFF)

C

IN

C

O

†

All typical values are at 25°C and with a 3.3 V supply.

Change in differential output voltage magnitude between
logic states

Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output voltage be-

tween logic states
Peak-to-peak common-mode output voltage 25 150 mV

pp

High-level input current VIH = 2 V 20 µA
Low-level input current VIL = 0.8 V 10 µA

p

High-impedance output current VO = 0 V or 2.4 V ±1 µA
Power-off output current VCC = 1.5 V, VO = 2.4 V 0.3 ±1 µA
Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 5 pF

Output capacitance (Y or Z outputs)

R

= 100Ω,
VID= ± 100 mV,
See Figure 6 and Figure 7

See Figure 8

Enabled, RL = 100Ω 23 35 mA
Disabled 0.7 6.4 mA

VOY or VOZ = 0 V ±10 mA
VOD = 0 V ±10 mA

VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled

247 340 454
–50 50

–50 50 mV

9.4 pF

mV

SN65LVDS105 switching characteristics over recommended operating conditions (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

t

PHL

t

r

t

f

t

sk(p)

t

sk(o)

t

sk(pp)

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at 25°C and with a 3.3 V supply.

‡

t

sk(o)

§

t

sk(pp)

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Propagation delay time, low-to-high-level output 1.7 2.2 3 ns
Propagation delay time, high-to-low-level output 1.4 2.3 3.5 ns
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t
Channel-to-channel output skew
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output 7.2 15 ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output 6 15 ns

is the magnitude of the time difference between the t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

PHL

– t

|)

PLH

§

‡

or t

PLH

of all drivers of a single device with all of their inputs connected together.

PHL

RL = 100Ω,

= 10 pF,

L

Figure

p

0.3 0.8 1.2 ns

0.3 0.8 1.2 ns
150 500 ps

20 100 ps

1.5 ns

8.4 15 ns

3.6 15 ns

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5

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

I

I

I

V

IA

IB

V

IB

A

V

ID

B

I

OY

Y

V

OD

I

OZ

Z

V

OY

V

V

OZ

OC

VOY)

2

Figure 1. ’LVDS104 Voltage and Current Definitions

Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages

APPLIED

VOLTAGES

V

IA

1.25 V 1.15 V 100 mV 1.2 V

1.15 V 1.25 V –100 mV 1.2 V

2.4 V 2.3 V 100 mV 2.35 V

2.3 V 2.4 V –100 mV 2.35 V

0.1 V 0 V 100 mV 0.05 V

1.5 V 0.9 V 600 mV 1.2 V

0.9 V 1.5 V –600 mV 1.2 V

2.4 V 1.8 V 600 mV 2.1 V

1.8 V 2.4 V –600 mV 2.1 V

0.6 V 0 V 600 mV 0.3 V

V

IB

0 V 0.1 V –100 mV 0.05 V

0 V 0.6 V –600 mV 0.3 V

RESULTING

DIFFERENTIAL

INPUT VOLTAGE

V

ID

RESULTING
COMMON-MODE
INPUT VOLTAGE

V

IC

V

OZ

Input

Y

V

OD

Z

100 Ω

3.75 kΩ

3.75 kΩ

±

0 V ≤ V

TEST

≤ 2.4 V

Figure 2. ’LVDS104 VOD Test Circuit

6

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SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

49.9 Ω ± 1% (2 Places)

Y

Input

Input

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T . The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

Z

V

CL = 10 pF
(2 Places)

OC

V

I

V

I

V

OC(PP)

V

O

1.4 V

1 V

V

OC(SS)

OC(PP)

Figure 3. ’LVDS104 Test Circuit and Definitions for the Driver Common-Mode Output Voltage

V

IB

Input

V

IA
t

Output

PLH

0 V

V

OD(H)

t

f

A

Input

B

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

Y

V

Z

OD

100 Ω ± 1 %

CL = 10 pF
(2 Places)

t

PHL

V

OD(L)

1.4 V

1.2 V
1 V

t

r

100%
80%

20%
0%

Figure 4. ’LVDS104 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal

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SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

1 V or 1.4 V

1.2 V

EN

EN

t

PZH

V

OY

or

V

OZ

t

PZL

V

OZ

or

V

OY

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

Y

Z

CL = 10 pF

(2 Places)

(see Note B)

49.9 Ω ± 1% (2 Places)

VOYV

t

PHZ

t

PLZ

OZ

3 V

1.5 V
0 V

≅ 1.4 V

1.25 V

1.2 V

1.2 V

1.15 V
≅ 1 V

1.2 V

Figure 5. ’LVDS104 Enable and Disable Time Circuit and Definitions

I

OY

I

I

A

V

IA

Y

V

OD

I

OZ

Z

V

OY

V

V

OZ

OC

VOY)

V

OZ

2

Figure 6. ’LVDS105 Voltage and Current Definitions

Input

Y

V

OD

Z

100 Ω

3.75 kΩ

3.75 kΩ

±

0 V ≤ V

TEST

≤ 2.4 V

Figure 7. ’LVDS105 VOD Test Circuit

8

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SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

49.9 Ω ± 1% (2 Places)

Y

Input

Input

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T . The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

Z

V
CL = 10 pF
(2 Places)

OC

V

O

V

OC(PP)

3 V

0 VA

V

OC(SS)

OC(PP)

Figure 8. ’LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage

Input

V

IA
t

Output

PLH

0 V

V

OD(H)

t

f

Y

Input

Z

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulsewidth = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

V

OD

CL = 10 pF
(2 Places)

100 Ω ± 1 %

t

PHL

V

OD(L)

3 V

1.5 V
0 V

t

r

100%
80%

20%
0%

Figure 9. ’LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential output Signal

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SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

PARAMETER MEASUREMENT INFORMATION

Y

0.8 V or 2 V

EN

EN

t

PZH

V

OY

or

V

OZ

t

PZL

V

OZ

or

V

OY

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulsewidth = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

Z

CL = 10 pF

(2 Places)

(see Note B)

49.9 Ω ± 1% (2 Places)

VOYV

t

PHZ

t

PLZ

OZ

3 V

1.5 V
0 V

≅ 1.4 V

1.25 V

1.2 V

1.2 V

1.15 V
≅ 1 V

1.2 V

Figure 10. ’LVDS105 Enable and Disable Time Circuit and Definitions

10

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SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

TYPICAL CHARACTERISTIC

SN65L VDS104

SUPPLY CURRENT

vs

SWITCHING FREQUENCY

60

55

50

VCC = 3.6 V

45

40

– Supply Current – mA

35

CC

I

30

25

50 100 150 200 250 300 350

VCC = 3.3 V

f – Frequency – MHz

VCC = 3 V

All Outputs Loaded

and Enabled

Figure 11

SN65L VDS105

SUPPLY CURRENT

vs

SWITCHING FREQUENCY

50

45

40

35

– Supply Current – mA

30

CC

I

25

20

50 100 150 200 250 300 350

VCC = 3.6 V

VCC = 3 V

VCC = 3.3 V

All Outputs Loaded

and Enabled

f – Frequency – MHz

Figure 12

4

3

2

– Low-Level Output Voltage – V

1

OL

V

0

0

DRIVER

LOW-LEVEL OUTPUT VOLTAGE

vs

LOW-LEVEL OUTPUT CURRENT

VCC = 3.3 V
TA = 25°C

2

IOL – Low-Level Output Current – mA

46

Figure 13

3.5

3

2.5

2

1.5

1

– High-Level Output Voltage – V

OH

0.5

V

0

–4

DRIVER

HIGH-LEVEL OUTPUT VOLTAGE

vs

HIGH-LEVEL OUTPUT CURRENT

VCC = 3.3 V
TA = 25°C

–3

IOH – High-Level Output Current – mA

–2 0

Figure 14

–1

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11

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

TYPICAL CHARACTERISTIC

SN65L VDS104

LOW-TO-HIGH PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

3.6

3.5

3.4
VCC = 3.3 V

3.3

3.2

3.1

3.0

2.9

PLH – Low-To-High Propagation Delay T ime – ns

t

2.8

–50 –25 0 25 50 75 100

VCC = 3.6 V

TA – Free–Air Temperature – °C

VCC = 3 V

Figure 15

SN65L VDS104

HIGH-TO-LOW PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

3.6

3.5

3.4

3.3
VCC = 3 V

3.2

3.1

3.0

2.9

PHL – High-To-Low Propagation Delay T ime – ns

t

2.8

–50 –25 0 25 50 75 100

TA – Free–Air Temperature – °C

VCC = 3.6 V

VCC = 3.3 V

Figure 16

SN65L VDS105

LOW-TO-HIGH PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.7

2.6

2.5

2.4
VCC = 3 V

2.3

2.2

VCC = 3.3 V

2.1

PLH – Low-To-High Propagation Delay T ime – ns

t

2

–50 –25 0 25 50 75 100

VCC = 3.6 V

TA – Free–Air Temperature – °C

Figure 17

SN65L VDS105

HIGH-TO-LOW PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

2.7

2.6

2.5
VCC = 3 V

2.4

2.3

VCC = 3.3 V

2.2

VCC = 3.6 V

2.1

PHL – High-To-Low Propagation Delay T ime – ns

t

2

–50 –25 0 25 50 75 100

TA – Free–Air Temperature – °C

Figure 18

12

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SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

APPLICATION INFORMATION

A L VDS receiver can be used to receive various other types of logic signals. Figure 19 through Figure 28 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.

V

DD

25 Ω

50 Ω

A

1/2 V

50

Ω

DD

0.1 µF

B

LVDS Receiver

Figure 19. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)

V

DD

50 Ω

50 Ω

1.35 V < VTT < 1.65 V

0.1 µF

A

B

LVDS Receiver

Figure 20. Center-Tap Termination (CTT)

1.14 V < VTT < 1.26 V

V

DD

50 Ω

2 kΩ

50 Ω1 kΩ

A

B

0.1 µF

LVDS Receiver

Figure 21. Gunning Transceiver Logic (GTL)

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13

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

APPLICATION INFORMATION

3.3 V

ECL

Z

0

1.47 V < VTT < 1.62 V

Z

0

Figure 22. Backplane Transceiver Logic (BTL)

3.3 V

50 Ω

33 Ω

50 Ω

A

B

120 Ω120 Ω

33 Ω

0.1 µF

A

LVDS Receiver

B

51 Ω

51 Ω

Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)

LVDS Receiver

14

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SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

APPLICATION INFORMATION

5 V

5 V

ECL

50 Ω

100 Ω

50 Ω

33 Ω

Figure 24. Postive Emitter-Coupled Logic (PECL)

3.3 V

3.3 V

7.5 kΩ

A

82 Ω82 Ω

100 Ω

A

B

33 Ω

LVDS Receiver

B

7.5 kΩ

0.1 µF

Figure 25. 3.3-V CMOS

LVDS Receiver

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15

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

APPLICATION INFORMATION

5 V

5 V

5 V

560 Ω

470 Ω

10 kΩ

560 Ω

3.32 kΩ

Figure 26. 5-V CMOS

10 kΩ

5 V

A

B

0.1 µF

A

B

LVDS Receiver

3.3 V

560 Ω

3.3 V

4.02 kΩ

Figure 27. 5-V TTL

4.02 kΩ

3.01 kΩ

Figure 28. LVTTL

3.3 V

0.1 µF

A

B

0.1 µF

LVDS Receiver

LVDS Receiver

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

APPLICATION INFORMATION

fail safe

One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair . The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the L VDS receiver
will pull each line of the signal pair to near V
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.

300 kΩ 300 kΩ

through 300-kΩ resistors as shown in Figure 10. The fail-safe

CC

V

CC

A

Rt = 100 Ω (Typ)

B

VIT ≈ 2.3 V

Y

Figure 29. Open-Circuit Fail Safe of the LVDS Receiver

It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not af fect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.

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17

SN65LVDS104, SN65LVDS105
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

8

7

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

8

14

0.008 (0,20) NOM

0°–8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

18

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

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0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

SN65LVDS104, SN65LVDS105

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SLLS396B– SEPTEMBER 1999 – REVISED DECEMBER 1999

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30

0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15

0,05

8

1

A

DIM

6,60
6,20

14

0,10

0,10

M

0,15 NOM

Gage Plane

0,25

0°–8°

2016

24

28

0,75
0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

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Copyright  1999, Texas Instruments Incorporated