TEXAS INSTRUMENTS PCI1131 Technical data
查询PCI1131供应商
D
3.3-V Core Logic With Universal PCI
Interface Compatible With 3.3-V or 5-V PCI
Signaling Environments
D
Supports PCI Local Bus Specification 2.1
D
Mix-and-Match 3.3-V/5-V PC Card16 Cards
and 3.3-V CardBus Cards
D
Supports T wo PC Card or CardBus Slots
With Hot Insertion and Removal
D
1995 PC Card-Standard Compliant
D
Low-Power Advanced Submicron CMOS
T echnology
D
Uses Serial Interface to Texas Instruments
(TI) TPS2206 Dual Power Switch
D
System Interrupts Can Be Programmed as
PCI-Style or ISA IRQ-Style Interrupts
D
ISA IRQ Interrupts Can Be Serialized Onto a
Single IRQSER Pin
D
Programmable Output Select for CLKRUN
D
Supports Burst Transfers to Maximize Data
Throughput on the PCI and CardBus Bus
D
Multifunction PCI Device With Separate
Configuration Spaces for Each Socket
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
D
Five PCI Memory Windows and T wo I/O
Windows Available to Each PC Card16
Socket
D
Two I/O Windows and Two Memory
Windows Available to Each CardBus
Socket
D
CardBus Memory Windows Can Be
Individually Selected Prefetchable or
Nonprefetchable
D
Exchangeable Card Architecture
(ExCA)-Compatible Registers Mapped in
Memory or I/O Space
D
TI Extension Registers Mapped in the PCI
Configuration Space
D
Intel 82365SL-DF Register Compatible
D
Supports 16-Bit Distributed Direct Memory
Access (DMA) on Both PC Card Sockets
D
Supports PC/PCI DMA on Both PC Card
Sockets
D
Supports Zoom Video Mode
D
Supports Ring Indicate
D
Packaged in 208-Pin Thin Plastic Quad
Flatpack
PCI1131
Table of Contents
Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Block Diagram 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Assignments – PCI-to-PC Card (16 Bit) 4. . . . . . . . . . . .
Terminal Assignments – PCI-to-CardBus Card 5. . . . . . . . . . . . . .
Terminal Functions 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions 15. . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions for PCI Interface 15. . . . .
Recommended Operating Conditions for PC Cards A and B 16.
Electrical Characteristics 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel and MPIIX are trademarks of Intel Corporation.
PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA).
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
PCI Clock/Reset Timing Requirements 18. . . . . . . . . . . . . . . . . . . . . .
PCI Timing Requirements 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information 19. . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information 20. . . . . . . . . . . . . . . .
PCI Card Cycle Timing 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Requirements 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Parameter Measurement Information 23. . . . . . . . . . . . . . . .
Mechanical Data 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
PCI1131
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
description
The TI PCI1131 is a high-performance PCI-to-PC Card controller that supports two independent PC Card
sockets compliant with the 1995 PC Card standard. The PCI1 131 provides a set of features that makes it ideal
for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard
retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and defines the new 32-bit PC Card,
called CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1 131 supports any combination of 16-bit
and CardBus PC Cards in its two sockets, powered at 3.3 V or 5 V, as required.
The PCI1 131 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either
a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA
transfers or CardBus PC Card bus-mastering cycles.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1 131
is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1131 internal datapath logic allows
the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
32-bit write buffers allow fast-posted writes to improve system-bus utilization.
An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz. Several low-power modes allow the host power-management system to further reduce
power consumption.
All unused PCI1131 inputs should be pulled high through a 43-kΩ resistor.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
system block diagram
A simplified system block diagram using the PCI1131 is provided below. The PCI950 IRQ deseralizer and the
PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that
capability.
The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface
includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV)
is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol.
The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
Other miscellaneous system interface terminals are available on the PCI1131 that include:
D
Multifunction IRQ terminals
D
SUSPEND, RI_OUT (power management control signals)
D
SPKROUT.
PCI Bus
PCI1131
INTA
INTB
TPS22xx
Power
Switch
PC Card
Socket A
PC Card
Socket B
External ZV Port
NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed
video signals too the VGA controller.
3
PCI1131
68 68
23
23
IRQSER
3
PCI930
ZV Switch
PCI950
IRQSER
Deserializer
Zoom Video
19
Zoom Video
4
Interrupt
Controller
IRQ2–15
VGA
Controller
Audio
Sub-System
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
PCI1131
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
terminal assignments – PCI-to-PC Card (16 bit)
PDV PACKAGE
(TOP VIEW)
IRQ7/PCDMAREQ
IRQ9/IRQSER
IRQ10/CLKRUN
IRQ11/PCDMAGNT
IRQ12/CLKRUN
IRQ14
IRQ15/RI_OUT
V
PCLK
RSTIN
GND
GNT
REQ
AD31
AD30
V
CCP
AD29
AD28
V
AD27
AD26
AD25
AD24
C/BE3
GND
IDSEL
AD23
AD22
AD21
AD20
V
AD19
AD18
AD17
AD16
C/BE2
FRAME
GND
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
V
PAR
C/BE1
AD15
AD14
AD13
GND
AD12
A_D10
A_D2
146
147
AD3
AD4
A_D9
144
145
AD2
CC
A_D1
V
143
GND
A_D8
142
AD1
A_CD2
A_D0
A_BVD1(STSCHG/RI)
A_WP(IOIS16)
138
140
139
141
AD0
B_D3
B_D11
B_CD1
A_BVD2(SPKR)
A_WAIT
A_VS1
A_READY(IREQ)
134
136
135
137
GND
B_D4
B_D5
B_D13
B_D12
A_A0
PCI1131 CorePCI
B_D6
133
A_A2
A_A1
132
131
B_D7
B_D14
A_REG
GND
130
129
B_D15
B_CE1
A_INPACK
A_A3
128
127
B_A10
B_CE2
A_A4
A_A5
126
125
Card A
Card B
CC
V
B_OE
IRQ3/INTA
154
AD9
GND
153
AD8
152
151
C/BE0
AD7
LATCH
V
SPKROUT/SUPEND
148
150
149
CC
AD6
AD5
V
IRQ4/INTB
IRQ5
156
155
157
158
159
160
161
162
163
164
CC
165
166
167
168
169
170
171
172
173
174
175
CC
176
177
178
179
180
181
182
183
184
185
186
CC
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
CC
202
203
204
205
206
207
208
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
AD11
AD10
CCP
DATA
CLOCK
A_A6
A_RESET
A_VS2
122
124
123
B_A11
B_IORD
B_IOWR
CCA
A_A25
V
120
121
B_A9
B_A17
A_A7
119
CCB
V
A_A12
A_A24
118
117
B_A8
B_A18
A_A15
A_A23
116
115
B_A19
B_A13
A_A22
V
114
113
GND
B_A14
CC
112
A_A16
A_A21
111
B_WE
B_A20
A_WE
A_A20
110
109
B_A21
A_A14
108
B_A16
B_A22
A_A13
A_A19
106
107
51
B_A15
B_A23
A_A18
105
A_A8
104
A_A17
103
102
A_A9
101
A_IOWR
100
A_A11
99
A_IORD
98
A_OE
97
A_CE2
96
GND
95
A_A10
94
A_CE1
93
A_D15
92
A_D7
A_D14
91
A_D6
90
A_D13
89
A_D5
88
A_D12
87
86
V
CC
A_D4
85
A_D11
84
A_D3
83
A_CD1
82
81
B_D10
80
B_D2
B_D9
79
B_D1
78
B_D8
77
76
B_D0
GND
75
B_CD2
74
B_WP(IOIS16)
73
B_BVD1(STSCHG/RI)
72
B_BVD2(SPKR)
71
B_WAIT
70
B_READY(IREQ)
69
B_VS1
68
B_A0
67
B_A1
66
B_A2
65
V
CC
64
B_REG
63
62
B_A3
B_INPACK
61
B_A4
60
B_A5
59
B_RESET
58
B_A6
57
B_VS2
56
55
B_A25
54
B_A7
B_A24
53
B_A12
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments – PCI-to-CardBus Card
PDV PACKAGE
PCI1131
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
(TOP VIEW)
IRQ7/PCDMAREQ
IRQ9/IRQSER
IRQ10/CLKRUN
IRQ11/PCDMAGNT
IRQ12/CLKRUN
IRQ14
IRQ15/RI_OUT
V
PCLK
RSTIN
GND
GNT
REQ
AD31
AD30
V
CCP
AD29
AD28
V
AD27
AD26
AD25
AD24
C/BE3
GND
IDSEL
AD23
AD22
AD21
AD20
V
AD19
AD18
AD17
AD16
C/BE2
FRAME
GND
IRDY
TRDY
DEVSEL
STOP
PERR
SERR
V
PAR
C/BE1
AD15
AD14
AD13
GND
AD12
A_CAD31
A_CAD30
A_RSVD
146
145
147
AD4
AD3
AD2
CC
A_CAD28
A_CAD29
V
142
144
143
AD1
AD0
GND
A_CCD2
A_CAD27
A_CCLKRUN
140
139
141
B_CAD2
B_CAD0
B_CCD1
A_CAUDIO
A_CSTSCHG
A_CSERR
A_CINT
136
135
138
137
GND
B_CAD6
B_CAD3
B_CAD1
B_CAD4
A_CVS1
A_CAD26
134
133
PCI1131 CorePCI
B_CAD5
B_RSVD
A_CAD24
A_CC/BE3
A_CAD25
130
129
132
131
B_CAD8
B_CAD7
B_CC/BE0
A_CREQ
A_CAD23
GND
128
127
B_CAD9
B_CAD10
A_CAD22
A_CRST
A_CAD21
124
126
125
Card A
Card B
CC
V
B_CAD11
B_CAD13
A_CAD19
A_CAD20
A_CVS2
122
121
123
B_CAD14
B_CAD15
B_CAD12
CCA
A_CAD18
A_CAD17
V
118
119
120
CCB
V
B_CAD16
B_CC/BE1
A_CC/BE2
A_CIRDY
A_CFRAME
114
116
115
117
B_CPAR
B_RSVD
B_CBLOCK
CC
A_CCLK
A_CTRDY
A_CDEVSEL
V
111
112
113
GND
B_CGNT
B_CSTOP
B_CPERR
A_CGNT
A_CSTOP
A_CPERR
A_CBLOCK
110
108
107
109
B_CCLK
B_CIRDY
B_CTRDY
B_CDEVSEL
A_CPAR
A_RSVD
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
51
B_CC/BE2
B_CFRAME
A_CC/BE1
A_CAD16
A_CAD14
A_CAD15
A_CAD12
A_CAD13
A_CAD11
A_CAD10
GND
A_CAD9
A_CC/BE0
A_CAD8
A_CAD7
A_RSVD
A_CAD5
A_CAD6
A_CAD3
A_CAD4
V
CC
A_CAD1
A_CAD2
A_CAD0
A_CCD1
B_CAD31
B_RSVD
B_CAD30
B_CAD29
B_CAD28
B_CAD27
GND
B_CCD2
B_CCLKRUN
B_CSTSCHG
B_CAUDIO
B_CSERR
B_CINT
B_CVS1
B_CAD26
B_CAD25
B_CAD24
V
CC
B_CC/BE3
B_CAD23
B_CREQ
B_CAD22
B_CAD21
B_CRST
B_CAD20
B_CVS2
B_CAD19
B_CAD18
B_CAD17
IRQ3/INTA
154
AD9
GND
153
AD8
152
151
C/BE0
AD7
LATCH
150
CC
V
V
SPKROUT/SUSPEND
148
149
AD6
AD5
IRQ4/INTB
IRQ5
156
155
157
158
159
160
161
162
163
164
CC
165
166
167
168
169
170
171
172
173
174
175
CC
176
177
178
179
180
181
182
183
184
185
186
CC
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
CC
202
203
204
205
206
207
208
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
AD11
AD10
CCP
DATA
CLOCK
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PCI1131
FUNCTION
FUNCTION
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
Terminal Functions
PCI system
TERMINAL
NAME NO.
PCLK 165 I
RSTIN
166 I
PCI address and data
TERMINAL
NAME NO.
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR 202 I/O
170
171
173
174
176
177
178
179
183
184
185
186
188
189
190
191
204
205
206
208
180
192
203
10
11
12
14
15
I/O
TYPE
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
PCI reset. When the RSTIN signal is asserted low, the PCI1131 forces all output buffers to the high-impedance
state and resets all internal registers. When asserted, the PCI1131 is nonfunctional. After RSTIN
the PCI1131 returns to the default state. When the PCI1131 SUSPEND
from any RSTIN
I/O
TYPE
Address/data bus. AD31–AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI
cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0
I/O
contain data.
1
2
3
4
6
8
9
Bus commands and byte enables. C/BE3–C/BE0 are multiplexed on the same PCI terminals. During the address
phase, C/BE3
I/O
5
The byte enables determine which byte lanes carry meaningful data. C/BE0
applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1 131 calculates
even parity across the AD and C/BE
reset (i.e., the PCI1131 internal register contents are preserved).
–C/BE0 define the bus command. During the data phase, C/BE3–C/BE0 are used as byte enables.
is deasserted,
mode is enabled, the device is protected
applies to byte 0 (AD7–AD0), C/BE1
buses and outputs the results on PAR, delayed by one clock.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION
FUNCTION
PCI interface control
TERMINAL
NAME NO.
DEVSEL
FRAME
GNT
IDSEL 182 I
IRDY
IRQ10/CLKRUN
IRQ12/CLKRUN
PERR
REQ
SERR
STOP
TRDY
197 I/O
193 I/O
168 I
195 I/O
159
161
199 I/O
169 O Request. REQ is asserted by the PCI1131 to request access to the PCI bus as a master.
200 O System error. SERR pulsed from the PCI1131 indicates an address parity error has occurred.
198 I/O Stop. STOP is driven by the current PCI target to request the master to stop the current transaction.
196 I/O
I/O
TYPE
I/O
PCI1131
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
Terminal Functions (Continued)
Device select. As a PCI target, the PCI1131 asserts DEVSEL to claim the current cycle. As a PCI master,
the PCI1131 monitors DEVSEL
Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access,
FRAME
is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data
transfers continue. When FRAME
Grant. GNT is driven by the PCI arbiter to grant the PCI1131 access to the PCI bus after the current data
transaction is complete.
Initialization device select. IDSEL selects the PCI1131 during configuration accesses. IDSEL can be
connected to one of the upper 24 PCI address lines.
Initiator ready. IRDY indicates the bus master ’s ability to complete the current data phase of the
transaction. IRDY
are sampled low (asserted). During a write, IRDY indicates that valid data is present on
TRDY
AD31–AD0. During a read, IRDY
inserted until both IRDY
the PCI1131 is the PCI bus master and an input when the PCI bus is the target.
Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and used
by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN
the system control register offset 80h, this terminal is an open-drain output. To select between IRQ10
and IRQ12 as the output, use bit 7 of register 80h.
Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been
detected.
Target ready. TRDY indicates the ability of the PCI1131 to complete the current data phase of the
transaction. TRDY
are sampled asserted. During a read, TRDY indicates that valid data is present on AD31–AD0.
IRDY
During a write, TRDY
both IRDY
and an input when the PCI1131 is the PCI bus master.
is used with TRDY. A data phase is completed on any clock where both IRDY and
is used with IRDY. A data phase is completed on any clock where both TRDY and
indicates that the PCI1131 is prepared to accept data. W ait cycles are inserted until
and TRDY are asserted together. This signal is an output when the PCI1 131 is the PCI target
until a target responds or a time-out occurs.
is sampled high (deasserted), the transaction is in the final data phase.
indicates that the master is prepared to accept data. Wait cycles are
and TRDY are low (asserted) at the same time. This signal is an output when
by setting bit 0 in
power supply
TERMINAL
NAME NO.
GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 Device ground terminals
V
V
V
V
CC
CCA
CCB
CCP
7, 31, 64, 86, 113, 143, 164, 175, 187, 201 Power supply terminal for core logic (3.3 V)
120 Power supply terminal for PC Card A (5 V or 3.3 V)
38 Power supply terminal for PC Card B (5 V or 3.3 V)
148, 172 Power supply terminal for PCI interface (5 V or 3.3 V)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
PCI1131
FUNCTION
FUNCTION
FUNCTION
PCI-TO-CARDBUS CONTROLLER UNIT
XCPS011 – DECEMBER 1997
Terminal Functions (Continued)
PC Card power switch
TERMINAL
NAME NO.
CLOCK 151 O
DATA 152 O Power switch data. DATA is used by the PCI1 131 to serially communicate socket power control information.
LATCH 150 O
interrupt
TERMINAL
NAME NO.
IRQ3/INTA
IRQ4/INTB
IRQ7/PCDMAREQ 157 O
IRQ9/IRQSER
IRQ10/CLKRUN
IRQ12/CLKRUN
IRQ11/PCDMAGNT 160 I/O
IRQ5
IRQ14
IRQ15/RI_OUT 163 I/O
I/O
TYPE
154
155
158
159
161
156
162
Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. The frequency of
the clock is derived from dividing PCICLK by 36. The maximum frequency of CLOCK is 2 MHz.
Power switch latch. LATCH is asserted by the PCI1131 to indicate to the PC Card power switch that the data
on the DATA line is valid.
I/O
TYPE
Interrupt request 3 and interrupt request 4. IRQ3/INTA–IRQ4/INTB can be connected to either PCI
or ISA interrupts. IRQ3/INTA
. When configured for IRQ3 and IRQ4, IRQ3/INTA–IRQ4/INTB must be connected to the ISA
or INTB
O
IRQ programmable interrupt controller. When IRQ3/INTA
INTB
, IRQ3/INTA–IRQ4/INTB must be connected to interrupts on the PCI bus.
Interrupt request 7. IRQ7/PCDMAREQ is software configurable and is used by the PCI1131 to
request PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When
IRQ7/PCDMAREQ
appropriate request (REQ
Interrupt request 9/serial IRQ. IRQ9/IRQSER is software configurable and indicates an interrupt
request from a PC Card to the PCI1131. When IRQ9/IRQSER is configured for IRQ9, it must be
connected to the system programmable interrupt controller. IRQSER allows all IRQ signals to be
O
serialized onto one pin. IRQ9/IRQSER is configured via bits 2–1 in the device control register of the
I/O
TI extension registers.
Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and
used by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN
I/O
bit 0 in the system control register offset 80h, this terminal is an open-drain output. T o select between
IRQ10 and IRQ12 as the output, use bit 7 of register 80h.
Interrupt request 11. IRQ11/PCDMAGNT is software configurable and is used by the PCI1131 to
accept a grant for PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When
IRQ11/PCDMAGNT
appropriate grant (GNT
Interrupt request 5 and 14. These signals are ISA interrupts. These terminals indicate an interrupt
request from one of the PC Cards. The interrupt mode is selected in the device control register of
O
the TI extension registers.
Interrupt request 15. IRQ15/RI_OUT indicates an interrupt request from one of the PC Cards.
RI_OUT
allows the RI input from the 16-bit PC Card to be output to the system. IRQ15/RI_OUT is
configured in the card control register of the TI extension registers.
is configured for PC/PCI DMA request (IRQ7), it must be connected to the
–IRQ4/INTB are software configurable as IRQ3 or INTA and as IRQ4
–IRQ4/INTB are configured for INTA and
) pin on the Intel Mobile Triton PCI I/O accelerator (MPIIX).
is configured for PC/PCI DMA grant (IRQ11), it must be connected to the
) pin on the Intel MPIIX controller.
by setting
speaker control
TERMINAL
NAME NO.
SPKROUT/
SUSPEND
8
149 O
I/O
TYPE
Speaker. SPKROUT carries the digital audio signal from the PC Card. SUSPEND places the PCI1131 in
suspend mode. SPKROUT/SUSPEND
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
is configured in the card control register of the TI extension registers.
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