TEXAS INSTRUMENTS PCA9546A Technical data
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
www.ti.com
1
FEATURES
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
• 1-of-4 Bidirectional Translating Switches • Low Standby Current
• I2C Bus and SMBus Compatible • Operating Power-Supply Voltage Range of
• Active-Low Reset Input
• Three Address Pins, Allowing up to Eight
2.3 V to 5.5 V
• 5.5-V Tolerant Inputs
Devices on the I2C Bus • 0 to 400-kHz Clock Frequency
• Channel Selection Via I2C Bus • Latch-Up Performance Exceeds 100 mA Per
• Power Up With All Switch Channels
JESD 78
Deselected • ESD Protection Exceeds JESD 22
• Low R
Switches – 2000-V Human-Body Model (A114-A)
ON
• Allows Voltage-Level Translation Between – 200-V Machine Model (A115-A)
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
– 1000-V Charged-Device Model (C101)
• No Glitch on Power Up
• Supports Hot Insertion
DESCRIPTION/ORDERING INFORMATION
The PCA9546A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair
fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can
be selected, determined by the contents of the programmable control register.
An active-low reset ( RESET) input allows the PCA9546A to recover from a situation in which one of the
downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the
channels to be deselected, as does the internal power-on reset function.
WITH RESET FUNCTION
ORDERING INFORMATION
T
A
QFN – RGV Reel of 2500 PCA9546ARGVR PD546A
QFN – RGY Reel of 1000 PCA9546ARGYR PD546A
SOIC – D Reel of 2500 PCA9546A
– 40 ° C to 85 ° C SOIC – DW Reel of 2000 PCA9546ADWR
TSSOP – PW Reel of 2000 PD546A
TVSOP – DGV
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
PACKAGE
(1) (2)
Tube of 40
Reel of 250
Tube of 40 PCA9546ADW
Reel of 250 PCA9546ADWT PREVIEW
Tube of 90
Reel of 250
Reel of 2000 PCA9546ADGVR PD546A
Reel of 250 PCA9546ADGVT PREVIEW
ORDERABLE PART NUMBER TOP-SIDE MARKING
PCA9546AD
PCA9546ADG4
PCA9546ADR
PCA9546ADRG4
PCA9546ADT
PCA9546ADTG4
PCA9546APW
PCA9546APWE4
PCA9546APWR
PCA9546APWRE4
PCA9546APWT
PCA9546APWTE4
PCA9546A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005 – 2008, Texas Instruments Incorporated
www.ti.com
D, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
RESET
SD0
SC0
SD1
SC1
GND
V
CC
SDA
SCL
A2
SC3
SD3
SC2
SD2
RGY PACKAGE
(TOP VIEW)
2
15
SDAA1
3
14
SCL
RESET
4
13
A2SD0
5
12
SC3SC0
6
11
SD3SD1
7
10
SC2SC1
1
8
A0
GND
16
9
SD2
V
CC
RGV PACKAGE
(TOP VIEW)
8
SC2
13
SD
A
16
5
A1
SC1
6
15
A0
GND
V
CC
7
14
SD2
1 12
SCL
RESET
2 11
A2SD0
10
SC3
3
SC0
4
9
SD3SD1
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The pass gates of the switches are constructed such that the V
voltage, which will be passed by the PCA9546A. This allows the use of different bus voltages on each pair, so
that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External
pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant.
pin can be used to limit the maximum high
CC
TERMINAL FUNCTIONS
NO.
D, DGV, DW, PW,
AND RGY
1 15 A0 Address input 0. Connect directly to V
2 16 A1 Address input 1. Connect directly to V
3 1 RESET Active low reset input. Connect to V
4 2 SD0 Serial data 0. Connect to V
5 3 SC0 Serial clock 0. Connect to V
6 4 SD1 Serial data 1. Connect to V
7 5 SC1 Serial clock 1. Connect to V
8 6 GND Ground
9 7 SD2 Serial data 2. Connect to V
10 8 SC2 Serial clock 2. Connect to V
11 9 SD3 Serial data 3. Connect to V
12 10 SC3 Serial clock 3. Connect to V
13 11 A2 Address input 2. Connect directly to V
14 12 SCL Serial clock line. Connect to V
15 13 SDA Serial data line. Connect to V
16 14 V
RGV
NAME DESCRIPTION
CC
Supply power
through a pullup resistor.
CC
CC
through a pullup resistor.
CC
CC
through a pullup resistor.
CC
CC
through a pullup resistor.
CC
CC
CC
CC
or ground.
CC
or ground.
CC
through a pullup resistor, if not used.
CC
through a pullup resistor.
through a pullup resistor.
through a pullup resistor.
through a pullup resistor.
or ground.
CC
through a pullup resistor.
through a pullup resistor.
2 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9546A
www.ti.com
Switch Control Logic
I2C Bus Control
Input Filter
Power-On Reset
PCA9546A
SC0
SDA
SCL
RESET
GND
SD3
SD2
SD1
SD0
SC3
SC2
SC1
V
CC
A1
A0
A2
5
14
3
16
8
11
9
6
4
12
10
7
15
1
2
13
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
BLOCK DIAGRAM
A. Pin numbers shown are for the D, DGV, DW, PW and RGY packages.
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): PCA9546A
www.ti.com
1 1 1
0
A1A2
A0
Slave Address
R/W
Fixed
Hardware
Selectable
Channel Selection Bits
(Read/Write)
Channel 0
Channel 1
Channel 2
Channel 3
B3 B2 B1 B0
3 2 1 0
XXXX
4567
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9546A is shown in Figure 1 . To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Figure 1. PCA9546A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
Control Register
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A,
which is stored in the control register (see Figure 2 ). If multiple bytes are received by the PCA9546A, it will save
the last byte received. This register can be written and read via the I2C bus.
Figure 2. Control Register
Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1 ). This register is written after the PCA9546A has been addressed. The four LSBs of the control byte are
used to determine which channel or channels are to be selected. When a channel is selected, the channel
becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in
a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition always must occur right after the acknowledge cycle.
4 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9546A
www.ti.com
2
Maximum
Typical
Minimum
VCC (V)
4.543.532.5 5 5.5
1
5
4.5
4
3.5
3
2.5
2
1.5
V
pass
(V)
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)
B7 B6 B5 B4 B3 B2 B1 B0 COMMAND
X X X X X X X
X X X X X X X
X X X X X X X
X X X X X X X
0 0 0 0 0 0 0 0
(1) Several channels can be enabled at the same time. For example, B3 =0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are
disabled, and channels 1 and 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
0 Channel 3 disabled
1 Channel 3 enabled
0 Channel 2 disabled
1 Channel 2 enabled
0 Channel 1 disabled
1 Channel 1 enabled
0 Channel 0 disabled
1 Channel 0 enabled
No channel selected,
power-up/reset default state
RESET Input
The RESET input is an active-low signal that may be used to recover from a bus-fault condition. When this signal
is asserted low for a minimum of tWL, the PCA9446A resets its registers and I2C state machine and deselects all
channels. The RESET input must be connected to V
through a pullup resistor.
CC
(1)
Power-On Reset
When power is applied to V
reached V
. At this point, the reset condition is released, and the PCA9546A registers and I2C state machine
POR
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
be lowered below 0.2 V to reset the device.
, an internal power-on reset holds the PCA9546A in a reset condition until V
CC
CC
CC
Voltage Translation
The pass-gate transistors of the PCA9546A are constructed such that the V
maximum voltage that will be passed from one I2C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
the data specified in the electrical characteristics section of this data sheet). In order for the PCA9546A to act as
a voltage translator, the V
voltage must be equal to or lower than the lowest bus voltage. For example, if the
pass
main bus is running at 5 V, and the downstream buses are 3.3 V and 2.7 V, then V
2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 3 , V
PCA9546A supply voltage is 3.5 V or lower, so the PCA9546A supply voltage could be set to 3.3 V. Pullup
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12 ).
voltage can be used to limit the
CC
must be equal to or below
pass
(max) is at 2.7 V when the
pass
has
must
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Figure 3. V
Product Folder Link(s): PCA9546A
Voltage vs V
pass
CC
www.ti.com
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
SDA
SCL
Start Condition
S
Stop Condition
P
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I2C
Multiplexer
Slave
SDA
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4 ).
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 5 ).
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master, and the devices that are controlled by the master are the slaves (see Figure 6 ).
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
6 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9546A
www.ti.com
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
A AS 1 1 1 0 A2 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2B3XXXX
Stop Condition
Slave Address
Control Register
A
NA
S 1 1 1
0 A2 A1 A0
1
SDA
P
B3 B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address Control Register
0 0 0 0
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 7 ). Setup and hold times must be taken
into account.
Figure 7. Acknowledgment on the I2C Bus
Data is transmitted to the PCA9546A control register using the write mode shown in Figure 8 .
Figure 8. Write Control Register
Data is read from the PCA9546A control register using the read mode shown in Figure 9 .
Figure 9. Read Control Register
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): PCA9546A
www.ti.com
PCA9546A
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
V
I
I
I
O
θ
JA
P
T
T
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range – 0.5 7 V
CC
Input voltage range
I
(2)
Input current ± 20 mA
Output current ± 25 mA
Continuous current through V
CC
Continuous current through GND ± 100 mA
D package 73
DGV package 120
Package thermal impedance
(3)
DW package 57
PW package 108
RGV package 51.38
RGY package 50
Total power dissipation 400 mW
tot
Storage temperature range – 65 150 ° C
stg
Operating free-air temperature range – 40 85 ° C
A
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
– 0.5 7 V
± 100 mA
° C/W
Recommended Operating Conditions
V
V
V
T
(1) All unused inputs of the device must be held at V
Supply voltage 2.3 5.5 V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Operating free-air temperature – 40 85 ° C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1)
MIN MAX UNIT
SCL, SDA 0.7 × V
A2 – A0, RESET 0.7 × V
CC
V
CC
CC
SCL, SDA – 0.5 0.3 × V
A2 – A0, RESET – 0.5 0.3 × V
or GND to ensure proper device operation. Refer to the TI application report,
CC
6
+ 0.5
CC
CC
8 Submit Documentation Feedback Copyright © 2005 – 2008, Texas Instruments Incorporated
Product Folder Link(s): PCA9546A
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
V
POR
V
pass
I
OL
Power-on reset voltage
Switch output voltage V
SCL, SDA 2.3 V to 5.5 V mA
SCL, SDA ± 1
I
I
SC3 – SC0, SD3 – SD0 ± 1
A2 – A0 ± 1
RESET ± 1
Operating mode f
I
CC
Standby mode
Δ I
CC
C
i
C
io(OFF)
R
ON
Supply-current
change
A2 – A0 4.5 6
RESET 4.5 5.5
SCL, SDA 15 19
(3)
SC3 – SC0, SD3 – SD0 6 8
Switch on-state resistance 3 V to 3.6 V 5 11 20 Ω
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA= 25 ° C.
(2) The power-on reset circuit resets the I2C bus logic with V
(3) C
depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
io(ON)
(2)
= 100 kHz VI= V
SCL
No load, VI= V
= VCC, I
SWin
V
= 0.4 V 3 7
OL
V
= 0.6 V 6 10
OL
VI= V
or GND 2.3 V to 5.5 V µ A
CC
or GND, IO= 0 3.6 V 3 11
CC
SWout
or GND V
CC
= – 100 µ A V
Low inputs VI= GND, IO= 0 3.6 V 0.1 1 µ A
High inputs VI= VCC, IO= 0 3.6 V 0.1 1
SCL or SDA input at 0.6 V,
SCL, SDA µ A
Other inputs at V
SCL or SDA input at V
Other inputs at V
VI= V
VI= V
or GND 2.3 V to 5.5 V pF
CC
or GND, Switch OFF 2.3 V to 5.5 V pF
CC
or GND
CC
– 0.6 V,
CC
or GND
CC
VO= 0.4 V, IO= 15 mA
VO= 0.4 V, IO= 10 mA 2.3 V to 2.7 V 7 16 45
< V
. V
CC
POR
must be lowered to 0.2 V to reset the device.
CC
4-CHANNEL I2C AND SMBus SWITCH
WITH RESET FUNCTION
SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008
CC
POR
5 V 3.6
4.5 V to 5.5 V 2.6 4.5
3.3 V 1.9
3 V to 3.6 V 1.6 2.8
2.5 V 1.5
2.3 V to 2.7 V 1.1 2
5.5 V 3 12
2.7 V 3 10
5.5 V 0.3 1
2.7 V 0.1 1
5.5 V 0.3 1
2.7 V 0.1 1
2.3 V to 5.5 V 8 15
4.5 V to 5.5 V 4 9 16
MIN TYP
PCA9546A
(1)
MAX UNIT
1.6 2.1 V
8 15
Copyright © 2005 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): PCA9546A
Loading...