Texas Instruments PCA8550DR, PCA8550PWR, PCA8550D, PCA8550DBR Datasheet
PCA8550
NONVOLATILE 5-BIT REGISTER
SCPS050A – MARCH 1999 – REVISED APRIL 1999
WITH I
2
C INTERFACE
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Useful for Jumperless Configuration of PC
Motherboard
D
Inputs Accept Voltages to 5.5 V
D
MUX OUT Signals are 2.5-V Outputs
D
NON-MUXED OUT Signal is a 3.3-V Output
D
Minimum of 1000 Write Cycles
D
Minimum of 10 Years Data Retention
D
Package Options Include Plastic
D, DB, OR PW PACKAGE
(TOP VIEW)
I2C SCL
2
I
C SDA
OVERRIDE
MUX IN A
MUX IN B
MUX IN C
MUX IN D
GND
1
2
3
4
5
6
7
8
V
16
CC
WP
15
NON-MUXED OUT
14
MUX SELECT
13
12
MUX OUT A
11
MUX OUT B
10
MUX OUT C
9
MUX OUT D
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
This 4-bit 1-of-2 multiplexer with I2C input interface is designed for 3-V to 3.6-V VCC operation.
The PCA8550 is designed to multiplex four bits of data from parallel inputs or from I
nonvolatile register. An additional bit of register output also is provided, which is latched to prevent changes in
the output value during the write cycle. The factory default for the contents of the register is all low. These stored
values can be read from, or written to, using the I
by the write protect (WP) input. The override (OVERRIDE
This device provides a fast-mode (400 kbit/s) or standard-mode (100 kbit/s) I
2
C bus. The ability to control writing to the register is provided
) input forces all the register outputs to a low.
2
and output. The implementation is as a slave. The device address is specified in the I
Both of the I
2
C Schmitt-trigger inputs (SCL and SDA) provide integrated pullup resistors and are 5-V tolerant.
2
C input data stored in a
C serial interface for data input
2
C interface definition table.
The PCA8550 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
MUX SELECT OVERRIDE MUX OUT
L L L L
L H
H X MUX IN
†
The latched NON-MUXED OUT state is the value present on the
NON-MUXED OUT output at the time the MUX SELECT input
transitions from the low to the high state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Nonvolatile
register
OUTPUTS
NON-MUXED
Nonvolatile
NON-MUXED
OUT
register
Latched
†
OUT
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
PCA8550
NONVOLATILE 5-BIT REGISTER
WITH I
SCPS050A – MARCH 1999 – REVISED APRIL 1999
logic diagram (positive logic)
2
C INTERFACE
V
CC
SCL
SDA
WP
OVERRIDE
MUX IN A
MUX IN B
MUX IN C
MUX IN D
1
15
I2C
Interface
Logic
2
V
CC
3
4
5
6
7
Address:
1001110
V
CC
V
CC
5-Bit Nonvolatile Register
4-Bit 1-of-2 Multiplexer
1-Bit
Transparent
Latch
14
NON-MUXED
OUT
12
MUX OUT A
11
MUX OUT B
10
MUX OUT C
9
MUX OUT D
MUX SELECT
2
13
V
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BYTE
NONVOLATILE 5-BIT REGISTER
SCPS050A – MARCH 1999 – REVISED APRIL 1999
WITH I
I2C interface
2
I
C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the serial data (SDA) input/output while the serial clock (SCL) input is high. After the start condition, the device
address byte is sent, MSB first, including the data-direction bit (R/W
general call address. After receiving the valid address byte, this device responds with an acknowledge, a low
on the SDA input/output during the high of the acknowledge-related clock pulse.
). This device does not respond to the
2
C INTERFACE
PCA8550
The data byte follows the address acknowledge. If the R/W
read from the nonvolatile register. If the R/W
bit is low, the data are from the master , to be written into the register.
bit is high, the data from this device are the values
A valid data byte is one in which the three high-order bits are low. The first valid data byte that is received is
written into the register, following the stop condition. If an invalid data byte is received, it is acknowledged, but
is not written into the register. The data byte is followed by an acknowledge sent from this device. If other data
bytes are sent from the master following the acknowledge, they are ignored by this device.
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master. If the WP input is low during the falling edge of the first valid data byte acknowledge on the SCL input
and the R/W
bit is low, the stop condition causes the I2C interface logic to write the data byte value into the
nonvolatile register. Data are written only if complete bytes are received and acknowledged. Writing to the
register takes time (t
2
the I
C interface logic does not write to the register.
Address H L L H H H L R/W
Data L L L
), during which the device does not respond to its slave address. If the WP input is high,
wr
I2C INTERFACE DEFINITION TABLE
BIT
7 (MSB) 6 5 4 3 2 1
NON-
MUXED
OUT
MUX OUTDMUX OUTCMUX OUTBMUX OUT
0 (LSB)
A
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Output voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Input/output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(SDA) (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(MUX OUT outputs) (see Note 1) –0.5 V to 2.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(NON-MUXED OUT output) (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . .
O
(VI < 0 ) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) (see Note 2) –50 mA, +10 mA. . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) (see Note 2) ±15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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