User's Guide
SLAU780–August 2018
MSP432E411Y-BGAEVM User's Guide
This guide provides an overview on how to get started quickly with the MSP432E411Y-BGAEVM,
including power, header pinouts and connections, communication interfaces, and programming interfaces.
Contents
1 Board Overview .............................................................................................................. 2
2 Power the MSP432E411Y-BGAEVM ..................................................................................... 3
2.1 Emulator Power ..................................................................................................... 3
2.2 External 3.3-V Source Only ....................................................................................... 3
2.3 External 5-V Source Only.......................................................................................... 3
2.4 External 3.3-V and 5-V Source ................................................................................... 4
2.5 Measure Current Consumption ................................................................................... 4
3 Header Pinouts and Connections ......................................................................................... 5
3.1 J11 – External Power Connector ................................................................................. 5
3.2 J6 – Power Rail Header............................................................................................ 5
3.3 J7 – External Peripheral Interface Header ...................................................................... 6
3.4 LCD Interface Header .............................................................................................. 7
3.5 J1, J2, J3, J4 – BoosterPack Interface Headers ............................................................... 9
3.6 J5 – Additional GPIO Pin Header ............................................................................... 10
4 Communication Interfaces ................................................................................................ 11
4.1 Ethernet............................................................................................................. 11
4.2 USB-OTG .......................................................................................................... 11
5 Programming Interfaces................................................................................................... 12
5.1 JTAG................................................................................................................ 12
5.2 ETM Trace ......................................................................................................... 12
5.3 BSL.................................................................................................................. 13
6 Software Development .................................................................................................... 14
6.1 Software Description.............................................................................................. 14
6.2 Source Code....................................................................................................... 14
6.3 Tool Options ....................................................................................................... 14
7 Schematics.................................................................................................................. 15
Trademarks
SimpleLink, BoosterPack, Code Composer Studio are trademarks of Texas Instruments.
Arm, Cortex, Keil are registered trademarks of Arm Limited.
IAR Embedded Workbench is a registered trademark of IAR Systems.
All other trademarks are the property of their respective owners.
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1
Board Overview
1 Board Overview
The SimpleLink™ Ethernet MSP432E411Y microcontroller EVM is an evaluation platform for SimpleLink
Arm®Cortex®-M4F-based Ethernet microcontrollers. The MSP432E411Y-BGAEVM demonstrates the
MSP432E411Y microcontroller with its on-chip 10/100 Ethernet MAC and PHY, USB 2.0, LCD controller,
External Peripheral Interface (EPI), hibernation module, motion control pulse-width modulation, and a
multitude of simultaneous serial connectivity. The MSP432E411Y-BGAEVM also features a fully compliant
40-pin BoosterPack™ plug-in module header, a user switch, two user LEDs, and dedicated reset and
wake switches.
The preprogrammed quick start application on the EVM is an application that performs a self-test on the
onboard SDRAM by writing and reading back values in memory using the MSP432E411Y EPI. The selftest blinks an LED to indicate that the test passes. Figure 1 shows the MSP432E411Y-BGAEVM with key
features highlighted.
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Figure 1. SimpleLink Ethernet MSP432E411Y Evaluation Module
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2 Power the MSP432E411Y-BGAEVM
The MSP432E411Y-BGAEVM requires a 3.3-V power supply, which can be provided in any of several
ways:
• Provide 3.3 V from an external emulator through the 20-pin Arm JTAG interface
• Provide 3.3 V directly to the 3.3V pin on the external power header (J11)
• Provide 5 V to the 5V pin on the external power header (J11) and using the onboard LDO to generate
3.3 V
• Provide 3.3 V and 5 V both to the external power header (J11)
2.1 Emulator Power
To use an external emulator as a power source, use an emulator that supplies 3.3 V to pin 1 on the Arm
20-pin JTAG interface. When 3.3 V is supplied to the board from the emulator, disconnect the output of
the onboard 3.3-V LDO (U5) from the 3.3-V power rail by removing the jumper on JP8. Figure 2 shows the
location of JP8.
Power the MSP432E411Y-BGAEVM
If USB host functionality is required from the onboard USB OTG connector, provide 5 V to the board
through the external power header (J11) or the BoosterPack header (J3).
2.2 External 3.3-V Source Only
To use an external 3.3-V source to power the EVM, connect the 3.3-V and GND lines of the supply to the
3.3V and GND pins of the external power header (J11). Disconnect the onboard 3.3-V LDO (U5) from the
3.3-V power rail by removing the jumper on JP8 to prevent back-powering the LDO. Figure 2 shows the
location of JP8. If USB host functionality is required from the onboard USB-OTG connector, also provide
5 V to the board. Use the external 3.3-V and 5-V power option in Section 2.4.
2.3 External 5-V Source Only
To use an external 5-V source to power the EVM, connect the 5-V and GND lines of the supply to the 5V
and GND pins of the external power header (J11) or to the 5V pin on the BoosterPack header (J3).
Connect the onboard 3.3-V LDO (U5) to the 3.3-V power rail by populating the jumper on JP8 to connect
the output of the LDO to the 3.3-V power rail. Figure 2 shows the location for JP8.
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Figure 2. Power Selection
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3
Power the MSP432E411Y-BGAEVM
2.4 External 3.3-V and 5-V Source
To use external 3.3-V and 5-V supplies to power the EVM, connect the 3.3-V, 5-V, and GND pins of the
supply to the 3.3V, 5V, and GND pins of the external power header (J11) or the BoosterPack headers (J1
for 3.3V and J3 for 5V). Disconnect the onboard 3.3-V LDO (U5) from the 3.3-V power rail by removing
the jumper on JP8 to prevent back-powering the LDO. Figure 2 shows the location for JP8.
2.5 Measure Current Consumption
To measure current consumption, remove the JP1, JP2, or JP3 jumpers and place an ammeter across the
header pins. Connect this jumper when not performing current measurements. Figure 3 shows the location
of JP1, JP2, and JP3. Table 1 lists which power rail to measure on each jumper.
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Figure 3. Current Measurement Headers
Table 1. Power Measurement Jumpers
Jumper Power Rail Measured
JP1 Combined VDD and VDDA
JP2 VDD
JP3 VDDA
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3 Header Pinouts and Connections
3.1 J11 – External Power Connector
Header J11 contains connections for 3.3 V, 5 V, and GND signals and is intended to be used to connect
external power supplies to the MSP432E411Y-BGAEVM. Figure 2 shows header J11, and Table 2 lists
the pinout.
Table 2. External Power Connector J11 Pinout
J11 Pin Signal
1 3.3V
2 GND
3 GND
4 5V
3.2 J6 – Power Rail Header
Header J6 contains connections for all the power rails and reference voltages used by the MSP432E411Y
device. Figure 4 shows header J6 and Table 3 lists the pinout.
Header Pinouts and Connections
Table 3. External Power Connector J6 Pinout
J6 Pin Signal Description
1 VREFA+ Reference voltage for ADC positive input
2 VREFA- Reference voltage for ADC negative input
3 VBAT Power source for hibernation module
4 VDD Positive supply for I/O
5 VSS Negative supply for I/O
6 VDDA Positive supply for analog circuits
7 AVSS Negative supply for analog circuits
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Figure 4. External Power Connector J6
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5
Header Pinouts and Connections
3.3 J7 – External Peripheral Interface Header
Header J7 contains all the signals for the MSP432E411Y’s External Peripheral Interface (EPI). The EPI
can be connected to an onboard IS42S16320F-7TL – 512 megabit SDRAM, U2, buy shorting all the
header pins on J7 horizontally, as shown in Figure 5. Alternatively, the EPI pins can be used to connect to
an external device by removing the headers on J7, and connecting to the outside pins of J7, as shown in
Figure 6.
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Figure 5. Header J7 With All Jumpers to Connect Onboard SDRAM
Figure 6. Header J7 With Jumpers Removed to Connect External Device to EPI
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Table 4 lists the pinout of J7.
Table 4. Header J7 Pinout
MSP432E411Y Signal J7 Pin J7 Pin SDRAM Signal
EP0S35 1 2 NC
EP0S34 3 4 NC
EP0S33 5 6 NC
EP0S32 7 8 NC
EP0S31 9 10 CLK
EP0S30 11 12 CKE
EP0S29 13 14 CS
EP0S28 15 16 WE
EP0S27 17 18 NC
EP0S26 19 20 NC
EP0S25 21 22 NC
EP0S24 23 24 NC
EP0S23 25 26 NC
EP0S22 27 28 NC
EP0S21 29 30 NC
EP0S20 31 32 NC
EP0S19 33 34 RAS
EP0S18 35 36 CAS
EP0S17 37 38 DQMH
EP0S16 39 40 DQML
EP0S15 41 42 DQ15
EP0S14 43 44 BA1, DQ14
EP0S13 45 46 BA0, DQ13
EP0S12 47 48 A12, DQ12
EP0S11 49 50 A11, DQ11
EP0S10 51 52 A10, DQ10
EP0S09 53 54 A9, DQ9
EP0S08 55 56 A8, DQ8
EP0S07 57 58 A7, DQ7
EP0S06 59 60 A6, DQ6
EP0S05 61 62 A5, DQ5
EP0S04 63 64 A4, DQ4
EP0S03 65 66 A3, DQ3
EP0S02 67 68 A2, DQ2
EP0S01 69 70 A1, DQ1
EP0S00 71 72 A0, DQ0
(1)
NC = no connection
Header Pinouts and Connections
(1)
3.4 LCD Interface Header
Header J9 contains all of the signals for the internal LCD controller in the MSP432E411Y to interface with
an external LCD panel, including four additional GPIO pins. The four additional GPIO pins can be used as
analog inputs to interface with a resistive touch screen. Alternatively, two of the pins (PE6 and PE7) can
be configured as I2C pins to interface with controllers that require an I2C interface. Figure 7 shows the
location of J9, and Table 5 lists the pinout of J9.
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Header Pinouts and Connections
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Figure 7. Header J9
Table 5. Header J9 Pinout
GPIO Pin Function J9 Pin J9 Pin Function GPIO Pin
GND GND 40 39 GND GND
PE7 AIN21/I2C9SDA 38 37 AIN20/I2C9SCL PE6
PP6 AIN23 36 35 AIN22 PP7
(1)
n/a
PS3 LCDDATA23 32 31 GPIO PB4
PS1 LCDDATA21 30 29 LCDDATA20 PS0
PT3 LCDDATA19 28 27 LCDDATA18 PT2
PJ5 LCDDATA17 26 25 LCDDATA16 PJ4
PJ3 LCDDATA15 24 23 LCDDATA14 PJ2
PN6 LCDDATA13 22 21 LCDDATA12 PN7
PT1 LCDDATA11 20 19 LCDDATA10 PT0
PS7 LCDDATA09 18 17 LCDDATA08 PS6
PS5 LCDDATA07 16 15 LCDDATA06 PS4
PR7 LCDDATA05 14 13 LCDDATA04 PR6
PR3 LCDDATA03 12 11 LCDDATA02 PF7
PR5 LCDDATA01 10 9 LCDDATA00 PR4
PJ6 LCDAC 8 7 GND GND
PR2 LCDLP 6 5 LCDCP PR0
PF6 LCDMCLK 4 3 LCDFP PR1
n/a 5 V 2 1 3.3 V VDD
(1)
n/a = not applicable
5 V 34 33 3.3 V VDD
NOTE: On MSP432E411Y-BGAEVM Rev A boards, LCDDATA22 is not available on the J9 header.
If a connection for LCDDATA22 is required, make the connection to J5 pin 19
(MSP432E411Y pin PS2).
8
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3.5 J1, J2, J3, J4 – BoosterPack Interface Headers
Headers J1, J2, J3, and J4 are aligned correctly and follow the pinout requirements to comply with the
BoosterPack plug-in module pinout standard, as shown on www.ti.com/byob. Figure 8 shows the pinouts
for the J1, J2, J3, and J4 headers.
Header Pinouts and Connections
Figure 8. BoosterPack Plug-in Module Header Pinout
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Header Pinouts and Connections
3.6 J5 – Additional GPIO Pin Header
Header J5 contains additional GPIO pins that are available for use. Figure 9 shows the location for J5,
and Table 6 lists the pinout.
Figure 9. Header J5 Location
Table 6. Header J5 Pinout
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MSP432E411Y Pin J5 Pin J5 Pin MSP432E411Y Pin
VDD (3.3 V) 40 39 GND
PD6 38 37 PG6
PQ5 36 35 PM5
PG2 34 33 PA1
PA0 32 31 PF3
PF4 30 29 PF2
PF0 28 27 PF1
PC0 26 25 PQ7
PG7 24 23 PQ6
PN2 22 21 PN1
PQ4 20 19 PS2
PB1 18 17 PB0
PL6 16 15 PC2
PL7 14 13 PC3
PC1 12 11 PN0
PF5 10 9 PJ0
PJ1 8 7 PH3
PG3 6 5 PG4
PG5 4 3 PD7
WAKE 2 1 HIB
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4 Communication Interfaces
4.1 Ethernet
The MSP432E411Y-BGAEVM development kit can connect directly to an Ethernet network using RJ45
connectors. The microcontroller contains a fully integrated Ethernet MAC and PHY. This integration
creates a simple, elegant, and cost-saving Ethernet circuit design. Example code is available for the lwIP
TCP/IP protocol stack. The embedded Ethernet on this device can be programmed to act as an HTTP
server, a client, or both. The design and integration of the circuit and microcontroller can also synchronize
events over the network using the IEEE 1588 precision time protocol. The existing SimpleLink SDK
network stack includes an example of using this feature.
The Ethernet jack on the EVM contains two LEDs, one green and one yellow, that are controlled by pins
PN0 and PN1 on the MSP432E411Y. When configured for Ethernet operation, the application should
control these pins directly, because the PHY-controlled LED pins have not been provided for LED
function.
4.2 USB-OTG
The EVM is USB 2.0 ready. A TPS2051B power switch is connected to and controlled by the
microcontroller USB peripheral, which manages power to the USB micro A/B connector when functioning
in a USB host. When functioning as a USB device, apply power to the EVM from an external source, (see
Section 2). USB 2.0 functionality is provided and supported directly out of the box with the target USB
micro A/B connector.
Communication Interfaces
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Programming Interfaces
5 Programming Interfaces
5.1 JTAG
The MSP432E411Y-BGAEVM supports JTAG programming through two different connectors. JA supports
the 20-pin Arm standard JTAG programming interface, and JB supports the 10-pin Arm standard miniJTAG programming interface. Figure 10 shows the two Arm JTAG connectors. When using an external
emulator, if the emulator does not provide power to the board, apply power as described in Section 2.
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Figure 10. Arm JTAG Connectors
5.2 ETM Trace
The MSP432E411Y-BGAEVM supports ETM Trace capabilities through J12 (see Figure 11).
Figure 11. Arm ETM Trace Connector
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5.3 BSL
The MSP432E411Y-BGAEVM supports BSL communication with the MSP432E411Y device through
UART, I2C, or SPI BSL. Three switch banks (S3, S4, and S5) control which BSL interface is connected to
the BSL connector, BSL. Move the corresponding switch for the desired BSL interface to the ON position,
and move the other switches to the OFF position. Figure 12 shows the BSL switches and the BSL
connector, with the switches in position to enable the SPI BSL interface. Table 7 shows which switch bank
controls which BSL Interface. Switch bank S6 connects 4.7-kΩ resistors to the I2C BSL lines if I2C pullups
are needed.
Programming Interfaces
Figure 12. BSL Area on MSP432E411Y-BGAEVM
Table 7. BSL Switch Bank Interfaces
Switch Bank BSL Interface
SW3 SPI
SW4 UART
SW5 I2C
When connecting to the MSP432E411Y device through the BSL connector:
• If R15 is populated and R7 is not (the default), the BSL host supplies the 3.3-V rail.
• If R7 is populated and R15 is not, the BSL host can sense the 3.3-V rail, which must be externally
supplied to the MSP432E411Y-BGAEVM.
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Software Development
6 Software Development
6.1 Software Description
The SimpleLink MSP432E4 Software Development Kit (SDK) provides drivers for all of the peripheral
devices supplied in the design. The Peripheral Driver Library is required to operate the on-chip peripherals
as part of the SDK. The SDK includes a set of example applications that use the Peripheral Driver Library.
These applications demonstrate the capabilities of the MSP432E411Y microcontroller and provide a
starting point for the development of the final application for use on the MSP432E411Y-BGAEVM.
6.2 Source Code
The source code is provided as part of the SimpleLink MSP432E4 SDK.
6.3 Tool Options
The source code installation includes directories containing projects, makefiles, and binaries for the
following tool-chains:
• Keil®Arm RealView Microcontroller Development System
• IAR Embedded Workbench®for Arm
• TI Code Composer Studio™ IDE for Arm and GCC compilers
For detailed information on using these tools, see the documentation included in the tool chain installation
or visit the website of the tools supplier.
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©Texas Instruments 2018
Drawn By:
Engineer:
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Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will besuitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design isproduction worthy. You should completelyvalidate and test your design implementation to confirm the system functionalityfor your application.
Version control disabledSVN Rev:
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Orderable: MSP432E411Y-BGAEVM
1 2
3 4
5 6
7 8
SW3
78H01T
1 2
3 4
SW4
78F01T
1 2
3 4
SW5
78F01T
1 2
3 4
SW6
78F01T
4.7k
R10
4.7k
R11
VDD
TP3
DNP
TP4
DNP
TP5
DNP
TP6
DNP
TP7
DNP
TP8
DNP
TP9
DNP
TP10
DNP
BSLTX
BSLRX
BSLSOMI
BSLSIMO
BSLCLK
BSLSTE
BSLSDA
BSLSCL
PA0
PA1
PA2
PA3
PA5
PA4
PB2
PB3
PB2
PB3
1 2
3 4
5 6
7 8
9 10
BSL
GND
BSLRX
BSLTXBSLSDA
BSLSCLBSLCLK
BSLSIMO
BSLSOMI
RSTn
BSLSTE
0
R150R7
DNP
4
1
2
3
J11
3V3
5V0
12
34
56
78
910
1112
1314
15
17
19
16
18
20
JA
12
34
56
78
910
JB
0
R24
0
R25
27
R17
27
R18
27
R19
27
R20
27
R21
GND TDO
SWCLKTCK
RSTn
SWDIOTMS
TDI
27
R22
BSLTX
BSLRX
GND
3V3
3V3
RSTn
TDO
TDI
SWCLKTCK
SWDIOTMS
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
16
18
20
J12
27
R40
27
R41
27
R38
27
R34
SWDIOTMS
SWCLKTCK
TDO
TDI
RSTn
TRCLK
TRD0
TRD1
TRD2
TRD3
GND
100
R39
3V3
10k
R35
10k
R36
3V3
10k
R37
JP1
JP2
JP3
3V3
VDD
VDDA
OUT
1
NR
2
3
EN
4
NC
5
IN
6
7
GND
TPS73533DRVRU5
1uF
C35
0.01uF
C37
0.1uF
C36
5V0
GND
GND
0.01uF
C39
GND
2.2uF
C38
GND
JP8
3V3
3V3
0
R42
0
R43
GND
GND
VSS
AVSS
GND
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Schematics
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7 Schematics
Figure 13. Schematics (1 of 3)
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Assembly Variant:001
©Texas Instruments 2018
Drawn By:
Engineer:
Mike Pridgen
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will besuitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design isproduction worthy. You should completelyvalidate and test your design implementation to confirm the system functionalityfor your application.
Version control disabledSVN Rev:
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TID #: N/A
Orderable: MSP432E411Y-BGAEVM
PA0
V3
PA1
W3
PA2
T6
PA3
U5
PA4
V4
PA5
W4
PA6
V5
PA7
R7
PB0
A16
PB1
B16
PB2
A17
PB3
B17
PB4
C6
PB5
B6
PB6
F2
PB7
F1
PC0/TCK/SWCLK
B15
PC1/TMS/SWDIO
C15
PC2/TDI
D14
PC3/TDO/SWO
C14
PC4
M2
PC5
M1
PC6
L2
PC7
K3
PD0
C2
PD1
C1
PD2
D2
PD3
D1
PD4
A4
PD5
B4
PD6
B3
PD7
B2
PE0
H3
PE1
H2
PE2
G1
PE3
G2
PE4
A5
PE5
B5
PE6
A7
PE7
B7
PF0
U6
PF1
V6
PF2
W6
PF3
T7
PF4
V7
PF5
W7
PF6
T8
PF7
U8
PG0
N15
PG1
T14
PG2
V11
PG3
M16
PG4
K17
PG5
K15
PG6
V12
PG7
U14
PH0
P4
PH1
R2
PH2
R1
PH3
T1
PH4
R3
PH5
T2
PH6
U2
PH7
V2
PJ0
C8
PJ1
E7
PJ2
H17
PJ3
F16
PJ4
F18
PJ5
E17
PJ6
N1
PJ7
K5
PK0
J1
PK1
J2
PK2
K1
PK3
K2
PK4
U19
PK5
V17
PK6
V16
PK7
W16
MSP432E411YTZAD
U1A
PL0
G16
PL1
H19
PL2
G18
PL3
J18
PL4
H18
PL5
G19
PL6
C18
PL7
B18
PM0
K18
PM1
K19
PM2
L18
PM3
L19
PM4
M18
PM5
G15
PM6
N19
PM7
N18
PN0
C10
PN1
B11
PN2
A11
PN3
B10
PN4
A10
PN5
B9
PN6
T12
PN7
U12
PP0
D6
PP1
D7
PP2
B13
PP3
C12
PP4
D8
PP5
B12
PP6
B8
PP7
A8
PQ0
E3
PQ1
E2
PQ2
H4
PQ3
M4
PQ4
A13
PQ5
W12
PQ6
U15
PQ7
M3
PR0
N5
PR1
N4
PR2
N2
PR3
V8
PR4
P3
PR5
P2
PR6
W9
PR7
R10
PS0
D12
PS1
D13
PS2
B14
PS3
A14
PS4
V9
PS5
T13
PS6
U10
PS7
R13
PT0
W10
PT1
V10
PT2
E18
PT3
F17
MSP432E411YTZAD
U1B
NC
C5
NC
E13
EN0RXIN
V13
EN0TXON
V14
EN0TXOP
V15
NC
V18
NC
V19
EN0RXIP
W13
RBIAS
W15
NC
W18
NC
W19
OSC0
E19
OSC1
D19
HIB
M17
RST
P18
WAKE
U18
XOSC0
T18
XOSC1
T19
MSP432E411YTZAD
U1C
VBUS
1
D-
2
D+
3
ID
4
GND
5
6781110
9
J8
SW2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PT0
PT1
PT2
PT3
PJ0
47k
R1
DNP
VSS
VDD
PA0
PA1
PA2
PA3
PA4
PA5
PB2
PB3
SW1
10k
R4
0.1uF
C5
100
R3
VDD
VSS
RSTn
WAKE
SW7
VSS
1.0M
R5
51
R2
VBAT
0.1uF
C4
VSS RSTn
RSTn
OSC0
OSC1
XOSC0
XOSC1
4.87k
R6
VSS
RBIAS
EN0RXI_P
EN0RXI_N
EN0TXO_N
EN0TXO_P
HIBn
TARGET_VBUS
VSS
33k
R31
VSS
OTGD_N
0
R29
0
R26
DNP
0
R28
DNP
0
R27
OTGD_PPL6
PL7
PL6_EXT
PL7_EXT
TARGET_ID
100
R30
PB0
D+
1
D-
2
ID
3
GND4NC
5
VBUS
6
TPD4S012DRYR
U4
VSS
OTGD_N
OTGD_P
TARGET_ID
NOTE: TPD4S012 all protection circuits are identical
Connections chose for simple routing
0.22uF
C31
TDO
TDI
SWCLKTCK
SWDIOTMS
TRCLK
TRD0
TRD1
TRD2
TRD3
10k
R33
OUT
1
GND
2
OC
3
EN
4
IN
5
TPS2051BDBVR
U3
4.7uF
C28
4.7uF
C27
VSS
5V0
VSS
10k
R32
VSSJP4
JP5
PD6
PD7
TARGET_VBUS
TARGET_VBUS
VSS
TARGET_VBUS
LCDAC
LCDCP
LCDFP
LCDLP
LCDMCLK
LCDDATA00
LCDDATA01
LCDDATA02
LCDDATA03
LCDDATA04
LCDDATA05
LCDDATA06
LCDDATA07
LCDDATA08
LCDDATA09
LCDDATA10
LCDDATA11
LCDDATA12
LCDDATA13
LCDDATA14
LCDDATA15
LCDDATA16
LCDDATA17
LCDDATA18
LCDDATA19
LCDDATA20
LCDDATA21
LCDDATA22
LCDDATA23
EPI0S00
EPI0S01
EPI0S02
EPI0S03
EPI0S04
EPI0S05
EPI0S06
EPI0S07
EPI0S08
EPI0S09
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
PB2
PB3
GND
A1
GND
A2
GND
A18
GND
A19
GND
B1
GND
B19
GND
F10
GND
H10
GND
H11
GND
H12
GND
J11
GND
J12
GND
K6
GND
K9
GND
K10
GND
K13
GND
K14
GND
L8
GND
L9
GND
M8
GND
M9
GND
M10
GND
N10
GND
P16
GND
R17
GND
V1
GND
W1
GND
W2
GNDA
G4
GNDX
R18
GNDX2
D18
VBAT
P19
VDD
G10
VDD
H9
VDD
J8
VDD
J9
VDD
J10
VDD
K7
VDD
K8
VDD
K11
VDD
K12
VDD
L10
VDD
L11
VDD
L12
VDD
M11
VDD
M12
VDD
N16
VDD
P10
VDD
P17
VDDA
F3
VDDC
E10
VDDC
H16
VREFA-
G5
VREFA+
F4
MSP432E411YTZAD
U1D
AVSS
VDDC
VDDA
VBAT
VREFA+
VREFA-
VDD
VSS
TD+
1
TD-
2
RD+
3
CT
4
CT
5
RD-
6
NC
7
8
CHS GND
1 TX+
2 TX-
3 RX+
6 RX-
4
5
7
8
9
10
11
12
Shield
13
Shield
14
J10
J0011D21BNL
330
R23
330
R16
VSS
VSS
1.0M
R14
4700pF
C18
VSS
0.1uF
C12
0.1uF
C13
VSS
VDD
49.9R849.9R949.9
R12
49.9
R13
0.1uF
C8
0.1uF
C9
VSS VSS
EN0RXI_N
EN0RXI_P
EN0TXO_N
EN0TXO_P
AIN20
AIN21
0.1uF
C19
0.1uF
C20
0.1uF
C21
0.1uF
C22
0.1uF
C17
0.1uF
C16
0.1uF
C15
0.1uF
C14
1uF
C33
2.2uF
C32
0.1uF
C34
VDDC
VSS
0.1uF
C23
0.1uF
C24
0.1uF
C25
0.1uF
C26
VDD
VDD
VDD
VSS
VSS
VSS
1uF
C29
0.1uF
C30
VDDA
AVSS
12pF
C10
12pF
C11
VSS
1
34
2
G
G
Y1
VSS
12pFC712pF
C6
VSS
JP6
JP7
PN0
PN1
D_N
D_P
VREFA+
VREFA-
VSS
VSS
AIN22
AIN23
PD2
PP0
PP1
PE4
PD3
PP4
PB6
PB7
PE1
PE2
PE3
PH5
PH6
PD4
PD5
PE0
PE5
PB5
PM4
PH4
PJ7
PK0
PK1
PK2
PM7
PP5
PH7
PD0
PD1
PP3
PM6
PB0PB1
PC0
PC1
PC2
PC3
PD7
PF0
PF5
PG7
PH3
PJ0
PL6_EXT
PL7_EXT
PN0
PN1PN2
PQ4
PQ6
PQ7
PS2
1
2
GND
3
Y2
VSS
VDD
AVSS
VDDA
12
34
56
78
910
1112
1314
15
17
19
21
23
25
27
29
31
33
35
37
39
16
18
20
22
24
26
28
30
32
34
36
38
40
J5
WAKE HIBn
PG5
PG3 PG4
PJ1
PF1
VBAT
VDD
5
4
1
2
3
6
7
J6
PA0
PA1
PD6
PF2
PF3
PF4
PM5
PG2
PQ5
PG6
VDD
VSS
2
1
3
5
6
4
7
8
D1
CDNBS08-SLVU2.8-4
Schematics
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Copyright © 2018, Texas Instruments Incorporated
MSP432E411Y-BGAEVM User's Guide
Figure 14. Schematics (2 of 3)
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
3 4
6/8/2018
MCU051A_LCD_Memory.SchDoc
SheetTitle:
Size:
Mod. Date:
File:
Sheet: of
B
http://www.ti.com
Contact:
http://www.ti.com/support
MSP432E411Y-BGAEVMProjectTitle:
Designed for:Public Release
Assembly Variant:001
©Texas Instruments 2018
Drawn By:
Engineer:
Mike Pridgen
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will besuitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design isproduction worthy. You should completelyvalidate and test your design implementation to confirm the system functionalityfor your application.
Version control disabledSVN Rev:
MCU051Number: Rev: A
TID #: N/A
Orderable: MSP432E411Y-BGAEVM
LCDAC
LCDLP
LCDMCLK
LCDDATA01
LCDDATA03
LCDDATA05
LCDDATA07
LCDDATA09
LCDDATA11
LCDDATA15
LCDDATA17
LCDDATA19
LCDDATA21
LCDDATA23
LCDDATA13
AIN23
AIN21
VSS
VDD 5V0
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
33
35
37
39
16
18
20
22
24
26
28
30
32
34
36
38
40
J9
AIN20
AIN22
LCDCP
LCDFP
LCDDATA00
LCDDATA02
LCDDATA04
LCDDATA06
LCDDATA08
LCDDATA10
LCDDATA14
LCDDATA16
LCDDATA18
LCDDATA20
LCDDATA22
LCDDATA12
VSS
VDD 5V0
VSS
VSS
VDD_SD
VDD_SD
S00
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S00
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
S13
S14
S28
S29
S30
S31
EPI0S18
EPI0S19
EPI0S20
EPI0S21
EPI0S22
EPI0S23
EPI0S24
EPI0S25
EPI0S26
EPI0S27
EPI0S28
EPI0S29
EPI0S30
EPI0S31
EPI0S32
EPI0S33
EPI0S34
EPI0S35
EPI0S01
EPI0S02
EPI0S03
EPI0S04
EPI0S05
EPI0S06
EPI0S07
EPI0S08
EPI0S09
EPI0S10
EPI0S11
EPI0S12
EPI0S13
EPI0S14
EPI0S15
EPI0S16
EPI0S17
EPI0S00
S00
S01
S02
S03
S04
S05
S06
S07
S08
S09
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
0.1uFC30.1uFC20.1uF
C1
VDD_SD
VDD
VDD_SD
VSS
GPIO !
31
GPIO !
32
GPIO !
33
GPIO !
34
Timer_Cap/GPIO !
35
Timer_Cap/GPIO !
36
PWM/GPIO !
37
PWM/GPIO !
38
PWM/GPIO !
39
PWM/GPIO !
40
GPIO !
11
SPI_CS/GPIO !
12
SPI_CS/GPIO !
13
SPI_MISO
14
SPI_MOSI
15
RST
16
GPIO
17
GPIO !
18
PWM/GPIO !
19
GND
20
J2/J4
+3.3V
1
Analog_In
2
LP_UART_RX
3
LP_UART_TX
4
GPIO !
5
AnalogIn
6
SPI_CLK
7
GPIO !
8
I2C_SCL
9
I2C_SDA
10
+5V
21
GND
22
Analog_In
23
Analog_In
24
Analog_In
25
Analog_In
26
Analog_In/I2S_WS
27
Analog_In/I2S_SCLK
28
Analog_Out/I2S_SDout
29
Analog_Out/I2S_SDin
30
J1/J3
PE1
PP0
PP1
PH4
PE4
PD3
PP4
PB6
PB7
PE5
PB5
PK0
PK1
PK2
PE0
PH5
PH6
PA2
PA3
PA4
PA5
PD4
PD5
PJ7
PM4
PE2
PE3
PM7
PP5
PH7
PD0
PD1
PD2
PP3
PM6
RSTn
VSS
VSS
VDD 5V0
JP9
VDD_SD
VSS
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
J7
TP1
DNP
TP2
DNP
VDD1DQ0
2
VDDQ
3
DQ1
4
DQ2
5
DQ3
7
DQ4
8
VDDQ9DQ5
10
DQ6
11
DQ7
13
VDD
14
DQML
15
WE
16
CAS
17
RAS
18
CS
19
BA0
20
BA1
21
VDD
27
CKE
37
CLK
38
DQMH
39
NC
40
DQ8
42
VDDQ
43
DQ9
44
DQ10
45
DQ11
47
DQ12
48
VDDQ
49
DQ13
50
DQ14
51
DQ15
53
A10
22
A0
23
A1
24
A2
25
A3
26
A4
29
A5
30
A6
31
A7
32
A8
33
A9
34
A11
35
A1236VSSQ
6
VSSQ
12
VSS
28
VSS
41
VSSQ
46
VSSQ
52
VSS
54
U2
IS42S16320F-7TL
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MSP432E411Y-BGAEVM User's Guide
Figure 15. Schematics (3 of 3)
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