TEXAS INSTRUMENTS MSP430xW42x Technical data

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption:

− Active Mode: 200 μA at 1 MHz, 2.2 V

− Standby Mode: 0.7 μA

− Off Mode (RAM Retention): 0.1 μA

D Five Power-Saving Modes D Wake-Up From Standby Mode in Less

Than 6 μs

D Frequency-Locked Loop, FLL+ D 16-Bit RISC Architecture, 125-ns

Instruction Cycle Time

D Scan IF for Background Water, Heat, and

Gas Volume Measurement

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_A With Five

Capture/Compare Registers

D Integrated LCD Driver for Up to

96 Segments

D On-Chip Comparator

D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Brownout Detector D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Bootstrap Loader in Flash Devices D Family Members Include:

− MSP430FW423: 8KB + 256B Flash Memory, 256B RAM

− MSP430FW425: 16KB + 256B Flash Memory, 512B RAM

− MSP430FW427: 32KB + 256B Flash Memory, 1KB RAM

D Available in 64-Pin Quad Flat Pack (QFP) D For Complete Module Descriptions, Refer

to the MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs.

The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 LCD segment drive capability, a scan interface, and 48 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timers make the configurations ideal for gas, heat, and water meters, industrial meters, counter applications, handheld meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

−40°C to 85°C

pin designation, MSP430xW42x

AVCCDVSSAV

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC 64-PIN QFP

MSP430FW423IPM MSP430FW425IPM MSP430FW427IPM

P6.2/SIFCH2

P6.1/SIFCH1

P6.0/SIFCH0

RST/NMI

TCK

TMS

(PM)

TDI/TCLK

TDO/TDI

P1.0/TA0.0

P1.1/TA0.0/MCLK

P1.2/TA0.1

P1.3/TA1.0/SVSOUT

P1.4/TA1.0

P6.3/SIFCH3/SIFCAOUT

P6.4/SIFCI0 P6.5/SIFCI1

P6.6/SIFCI2/SIFDACOUT

P6.7/SIFCI3/SVSIN

SIFCI

XIN

XOUT

SIFVSS

SIFCOM

P5.1/S0 P5.0/S1 P4.7/S2 P4.6/S3 P4.5/S4

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P4.4/S5

P4.3/S6

P4.2/S7

P4.1/S8

P4.0/S9

MSP430xW42x

P3.7/S10

P3.6/S11

P3.5/S12

P3.4/S13

P3.3/S14

P3.2/S15

P3.1/S16

P3.0/S17

P2.7/SIFCLKG/S18

P1.5/TA0CLK/ACLK

P1.6/CA0

P1.7/CA1

P2.0/TA0.2

P2.1/TA1.1

P5.7/R33

P5.6/R23

P5.5/R13

41 40

R03

P5.4/COM3

P5.3/COM2

P5.2/COM1

COM0

P2.2/TA1.2/S23 P2.3/TA1.3/S22

34 33

P2.4/TA1.4/S21

P2.6/CAOUT/S19

P2.5/TA1CLK/S20

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functional block diagram

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

XOUT

XIN

Oscillator

FLL+

MCLK

8 MHz

CPU

incl. 16

Registers

Emulation

Module

JTAG

Interface

DVCCDVSSAVCCAV

ACLK

MAB

MDB

Flash

32KB 16KB

8KB

POR/

Multilevel

SVS/

Brownout

RST/NMI

SMCLK

RAM

1KB 512B 256B

Scan IF

Watchdog

Timer

WDT

15/16-Bit

Port 1

8 I/O

Interrupt

Capability

Timer0_A3

3 CC Reg

Port 2

8 I/O

Interrupt

Capability

Timer1_A5

5 CC Reg

Port 3

8 I/O

Comparator_

Port 4

8 I/O

Basic

Timer 1

1 Interrupt

Vector

Segments

1,2,3,4 MUX

LCD

Port 5

8 I/O

LCD

Port 6

8 I/O

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Terminal Functions

TERMINAL

NAME NO.

SIFVSS 10 Scan IF AFE reference supply voltage. P1.0/TA0.0 53 I/O General-purpose digital I/O/Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit P1.1/TA0.0/MCLK 52 I/O General-purpose digital I/O/Timer0_A. Capture: CCI0B input/MCLK output/BSL receive

P1.2/TA0.1 51 I/O General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output P1.3/TA1.0/

SVSOUT P1.4/TA1.0 49 I/O General-purpose digital I/O/Timer1_A, capture: CCI0A input, compare: Out0 output P1.5/TA0CLK/

ACLK P1.6/CA0 47 I/O General-purpose digital I/O/Comparator_A input P1.7/CA1 46 I/O General-purpose digital I/O/Comparator_A input P2.0/TA0.2 45 I/O General-purpose digital I/O/Timer0_A, capture: CCI2A input, compare: Out2 output P2.1/TA1.1 44 I/O General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output P2.2/TA1.2/S23 35 I/O General-purpose digital I/O/Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment

P2.3/TA1.3/S22 34 I/O General-purpose digital I/O/Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment

P2.4/TA1.4/S21 33 I/O General-purpose digital I/O/Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment

P2.5/TA1CLK/S20 32 I/O General-purpose digital I/O/input of Timer1_A clock/LCD segment output 20 (see Note) P2.6/CAOUT/S19 31 I/O General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note) P2.7/SIFCLKG/

S18 P3.0/S17 29 I/O General-purpose digital I/O/ LCD segment output 17 (see Note) P3.1/S16 28 I/O General-purpose digital I/O/ LCD segment output 16 (see Note) P3.2/S15 27 I/O General-purpose digital I/O/ LCD segment output 15 (see Note) P3.3/S14 26 I/O General-purpose digital I/O/ LCD segment output 14 (see Note) P3.4/S13 25 I/O General-purpose digital I/O/LCD segment output 13 (see Note) P3.5/S12 24 I/O General-purpose digital I/O/LCD segment output 12 (see Note) P3.6/S11 23 I/O General-purpose digital I/O/LCD segment output 11 (see Note) P3.7/S10 22 I/O General-purpose digital I/O/LCD segment output 10 (see Note)

NOTE: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

64 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF

62 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF

63 Digital supply voltage, negative terminal.

50 I/O General-purpose digital I/O/Timer1_A, capture: CCI0B input/SVS: output of SVS comparator

48 I/O General-purpose digital I/O/input of Timer0_A clock/output of ACLK

30 I/O General-purpose digital I/O/Scan IF, signal SIFCLKG from internal clock generator/LCD segment

I/O

AFE, port 6, and LCD resistive divider circuitry; must not power up prior to DV

AFE. and port 6. Must be externally connected to DV

1 Digital supply voltage, positive terminal.

Note: TA0.0 is only an input on this pin.

Note: TA1.0 is only an input on this pin.

output 23 (see Note)

output 22 (see Note)

output 21 (see Note)

output 18 (see Note)

DESCRIPTION

. Internally connected to DVSS.

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MIXED SIGNAL MICROCONTROLLER

Terminal Functions (Continued)

MSP430xW42x

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

TERMINAL

NAME NO.

P4.0/S9 21 I/O General-purpose digital I/O/LCD segment output 9 (see Note) P4.1/S8 20 I/O General-purpose digital I/O/LCD segment output 8 (see Note) P4.2/S7 19 I/O General-purpose digital I/O/LCD segment output 7 (see Note) P4.3/S6 18 I/O General-purpose digital I/O/LCD segment output 6 (see Note) P4.4/S5 17 I/O General-purpose digital I/O/LCD segment output 5 (see Note) P4.5/S4 16 I/O General-purpose digital I/O/LCD segment output 4 (see Note) P4.6/S3 15 I/O General-purpose digital I/O/LCD segment output 3 (see Note) P4.7/S2 14 I/O General-purpose digital I/O/LCD segment output 2 (see Note) P5.0/S1 13 I/O General-purpose digital I/O/LCD segment output 1 (see Note) P5.1/S0 12 I/O General-purpose digital I/O/LCD segment output 0 (see Note) COM0 36 O Common output. COM0−3 are used for LCD backplanes P5.2/COM1 37 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes P5.3/COM2 38 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes P5.4/COM3 39 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes R03 40 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R13 41 I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O/output port of most positive analog LCD level (V1) P6.0/SIFCH0 59 I/O General-purpose digital I/O/Scan IF, channel 0 sensor excitation output and signal input P6.1/SIFCH1 60 I/O General-purpose digital I/O/Scan IF, channel 1 sensor excitation output and signal input P6.2/SIFCH2 61 I/O General-purpose digital I/O/Scan IF, channel 2 sensor excitation output and signal input P6.3/SIFCH3/

SIFCAOUT P6.4/SIFCI0 3 I/O General-purpose digital I/O/Scan IF, channel 0 signal input to comparator P6.5/SIFCI1 4 I/O General-purpose digital I/O/Scan IF, channel 1 signal input to comparator P6.6/SIFCI2/

SIFDACOUT P6.7/

SIFCI3/SVSIN SIFCI 7 I Scan IF input to Comparator. SIFCOM 11 O Common termination for Scan IF sensors. RST/NMI 58 I Reset input or nonmaskable interrupt input port. TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1.

NOTE: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

I/O

2 I/O General-purpose digital I/O/Scan IF, channel 3 sensor excitation output and signal input/Scan IF

comparator output

5 I/O General-purpose digital I/O/Scan IF, channel 2 signal input to comparator/10-bit DAC output

6 I/O General-purpose digital I/O/Scan IF, channel 3 signal input to comparator/SVS, analog input

DESCRIPTION

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)

Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)

Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)

Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect

autoincrement

Immediate D MOV #X,TONI MOV #45,TONI #45 −−> M(TONI)

NOTE: S = source D = destination

D MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 −−> R11

M(R10) −−> R11 R10 + 2−−> R10

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

− All clocks are active

D Low-power mode 0 (LPM0)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control remains active

D Low-power mode 1 (LPM1)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator remains enabled ACLK remains active

D Low-power mode 3 (LPM3)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled ACLK remains active

D Low-power mode 4 (LPM4)

− CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

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interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External Reset

Watchdog

Flash memory

NMI

Oscillator Fault

Flash memory access violation

Timer1_A5 TA1CCR0 CCIFG (see Note 2) Maskable 0FFFAh 13

Timer1_A5

Comparator_A CMPAIFG Maskable 0FFF6h 11

Watchdog Timer WDTIFG Maskable 0FFF4h 10

Scan IF SIFIFG0 to SIFIFG6

Timer0_A3 TA0CCR0 CCIFG (see Note 2) Maskable 0FFECh 6

Timer0_A3

I/O port P1

(eight flags)

I/O port P2

(eight flags)

Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.

WDTIFG

KEYV

(see Note 1)

NMIIFG

OFIFG

ACCVIFG

(see Notes 1 & 3)

TA1CCR1 CCIFG to

TA1CCR4 CCIFG,

TA1CTL TAIFG

(see Notes 1 & 2)

(See Note 1)

TA0CCR1 CCIFG, TA0CCR2 CCIFG,

TA0CTL TAIFG

(see Notes 1 & 2)

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

Reset 0FFFEh 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0FFF8h 12

Maskable 0FFF2h 9

Maskable 0FFEAh 5

Maskable 0FFE8h 4

Maskable 0FFE2h 1

0FFFCh 14

0FFF0h 8

0FFEEh 7

0FFE6h 3 0FFE4h 2

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address 00h ACCVIE NMIIE

Address 01h BTIE

7654 0

rw-0

7654 0321

rw-0

rw-0 rw-0 rw-0

321

OFIE WDTIE

WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is

configured in interval timer mode. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable BTIE: Basic Timer1 interrupt enable

interrupt flag register 1 and 2

Address 02h NMIIFG

Address 03h BTIFG

7654 0

rw-0 rw-1 rw-(0)

7654 0321

rw-0

321

OFIFG WDTIFG

WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,

or a reset condition at the RST

/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST

/NMI pin

BTIFG: Basic Timer1 interrupt flag

module enable registers 1 and 2

Address

04h/05h

Legend: rw:

rw-0,1: rw-(0,1):

7654 0321

Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device

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memory organization

MSP430FW423 MSP430FW425 MSP430FW427

Memory Interrupt vector Code memory

Information memory Size 256 Byte

Boot memory Size 1KB

RAM Size 256 Byte

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.

Size Flash Flash

8-bit

8-bit SFR

8KB 0FFFFh − 0FFE0h 0FFFFh − 0E000h

010FFh − 01000h

0FFFh − 0C00h

02FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

512 Byte

03FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

32KB

0FFFFh − 0FFE0h

0FFFFh − 08000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

1KB

05FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

BSL Function PM Package Pins

Data Transmit 53 - P1.0

Data Receive 52 - P1.1

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128

bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0−n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

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flash memory (continued)

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

8KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0E400h

0E3FFh

0E200h

0E1FFh

0E000h 010FFh

01080h

0107Fh

01000h

16KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0C400h

0C3FFh

0C200h

0C1FFh

0C000h

010FFh

01080h 0107Fh

01000h

32KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

08400h

083FFh

08200h

081FFh

08000h

010FFh

01080h

0107Fh

01000h

Segment 0

With Interrupt Vectors

Segment 1

Segment 2

Main Memory

Segment n−1

Segment n

Segment A

Information Memory

Segment B

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430xW42x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

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brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V have ramped to V reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when VCC reaches V

at that time. The user must insure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

watchdog timer

may not

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

comparator_A

The primary function of the comparator_A module is to support precision slope analog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals.

scan IF

The scan interface is used to measure linear or rotational motion and supports LC and resistive sensors such as GMR sensors. The scan IF incorporates a V up to four sensors.

/2 generator, a comparator, and a 10-bit DAC and supports

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timer0_A3

Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer0_A3 Signal Connections

Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number

48 - P1.5 TA0CLK TACLK

ACLK ACLK

SMCLK SMCLK 48 - P1.5 TA0CLK INCLK 53 - P1.0 TA0.0 CCI0A 52 - P1.1 TA0.0 CCI0B

51 - P1.2 TA0.1 CCI1A

CAOUT (internal) CCI1B

45 - P2.0 TA0.2 CCI2A

ACLK (internal) CCI2B

GND

Timer NA

53 - P1.0

CCR0 TA0.0

51 - P1.2

CCR1 TA0.1

45 - P2.0

CCR2 TA0.2

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timer1_A5

Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer1_A5 Signal Connections

Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number

32 - P2.5 TA1CLK TACLK

ACLK ACLK

SMCLK SMCLK 32 - P2.5 TA1CLK INCLK 49 - P1.4 TA1.0 CCI0A 50 - P1.3 TA1.0 CCI0B

DV DV

GND

44 - P2.1 TA1.1 CCI1A

CAOUT (internal) CCI1B

DV DV

GND

35 - P2.2 TA1.2 CCI2A

SIFO0sig (internal) CCI2B

DV DV

GND

34 - P2.3 TA1.3 CCI3A

SIFO1sig (internal) CCI3B

DV DV

GND

33 - P2.4 TA1.4 CCI4A

SIFO2sig (internal) CCI4B

DV DV

GND

Timer NA

49 - P1.4

CCR0 TA1.0

44 - P2.1

CCR1 TA1.1

35 - P2.2

CCR2 TA1.2

34 - P2.3

CCR3 TA1.3

33 - P2.4

CCR4 TA1.4

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peripheral file map

Watchdog Watchdog Timer control WDTCTL 0120h Timer1_A5

Timer0_A3

Flash

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

PERIPHERALS WITH WORD ACCESS

Timer1_A interrupt vector TA1IV 011Eh Timer1_A control TA1CTL 0180h Capture/compare control 0 TA1CCTL0 0182h Capture/compare control 1 TA1CCTL1 0184h Capture/compare control 2 TA1CCTL2 0186h Capture/compare control 3 TA1CCTL3 0188h Capture/compare control 4 TA1CCTL4 018Ah Reserved 018Ch Reserved 018Eh Timer1_A register TA1R 0190h Capture/compare register 0 TA1CCR0 0192h Capture/compare register 1 TA1CCR1 0194h Capture/compare register 2 TA1CCR2 0196h Capture/compare register 3 TA1CCR3 0198h Capture/compare register 4 TA1CCR4 019Ah Reserved 019Ch Reserved 019Eh Timer0_A interrupt vector TA0IV 012Eh Timer0_A control TA0CTL0 0160h Capture/compare control 0 TA0CCTL0 0162h Capture/compare control 1 TA0CCTL1 0164h Capture/compare control 2 TA0CCTL2 0166h Reserved 0168h Reserved 016Ah Reserved 016Ch Reserved 016Eh Timer0_A register TA0R 0170h Capture/compare register 0 TA0CCR0 0172h Capture/compare register 1 TA0CCR1 0174h Capture/compare register 2 TA0CCR2 0176h Reserved 0178h Reserved 017Ah Reserved 017Ch Reserved 017Eh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

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PERIPHERALS WITH WORD ACCESS (CONTINUED)

Scan IF

LCD

Comparator_A

Brownout, SVS SVS control register SVSCTL 056h FLL+ Clock

Basic Timer1

SIF timing state machine 23 SIFTSM23 01FEh : : : SIF timing state machine 0 SIFTSM0 01D0h SIF DAC register 7 SIFDACR7 01CEh : : : SIF DAC register 0 SIFDACR0 01C0h SIF control register 5 SIFCTL5 01BEh SIF control register 4 SIFCTL4 01BCh SIF control register 3 SIFCTL3 01BAh SIF control register 2 SIFCTL2 01B8h SIF control register 1 SIFCTL1 01B6h SIF processing state machine vector SIFPSMV 01B4h SIF counter CNT1/2 SIFCNT 01B2h Reserved SIFDEBUG 01B0h

PERIPHERALS WITH BYTE ACCESS

LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDCTL 090h Comparator_A port disable CAPD 05Bh Comparator_A control 2 CACTL2 05Ah Comparator_A control 1 CACTL1 059h

FLL+ Control 1 FLL_CTL1 054h FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h BT counter 2 BTCNT2 047h BT counter 1 BTCNT1 046h BT control BTCTL 040h

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peripheral file map (continued)

Port P6

Port P5

Port P4

Port P3

Port P2

Port P1

Special Functions

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

absolute maximum ratings

†

Voltage applied at VCC to VSS −0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note) −0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to V

applied to the TDI/TCLK pin when blowing the JTAG fuse.

. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

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(

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recommended operating conditions

PARAMETER MIN NOM MAX UNITS

Supply voltage during program execution (see Note 1), V

(AVCC = DVCC = VCC)

Supply voltage during program execution, SVS enabled, PORON = 1 (see Note 1 and Note 2), V

(AVCC = DVCC = VCC)

Supply voltage during programming flash memory (see Note 1), V

(AVCC = DVCC = VCC)

Supply voltage, V Operating free-air temperature range, T

(AVSS = DVSS = VSS) 0 0 V

LF selected, XTS_FLL=0 Watch crystal 32768 Hz

LFXT1 crystal frequency, f

see Note

(LFXT1)

XT1 selected, XTS_FLL=1 Ceramic resonator 450 8000 kHz XT1 selected, XTS_FLL=1 Crystal 1000 8000 kHz

Processor frequency (signal MCLK), f

(System)

NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V betweeen AVCC and DVCC can

be tolerated during power up and operation.

2. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing supply voltage. POR is going inactive when the supply voltage is raised above minimum supply voltage plus the hysteresis of the SVS circuitry.

3. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

MSP430xW42x 1.8 3.6 V

MSP430xW42x 2.0 3.6 V

MSP430FW42x 2.7 3.6 V

MSP430xW42x −40 85 °C

VCC = 1.8 V DC 4.15 VCC = 3.6 V DC 8

MHz

f (MHz)

Supply Voltage Range

During Programming of

the Flash Memory

8 MHz

Supply Voltage Range During

Program Execution

4.15 MHz

− Maximum Processor Frequency − MHz

(System)

1.8 V 3.6 V

2.7 V 3 V

VCC − Supply Voltage − V

Figure 1. Maximum Frequency vs Supply Voltage

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MSP430xW42x

(

)

(

)

(

)

(MCLK)

(SMCLK)

(DCO)

MHz

(

)

(

)

(

)

(MCLK)

(SMCLK)

(DCO)

MHz

2.2 V

Low power mode, (LPM3)

()

(

)

(LPM4)

Low power mode, (LPM4) (see Note 3)

2.2 V/3 V

μA

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AVCC + DVCC excluding external current, (see Note 1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

Active mode,

(AM)

= f

MCLK

= 32,768 Hz, XTS_FLL = 0

(ACLK)

SMCLK

= f

DCO

= 1 MHz,

= 1

= −40°C to 85°C

(FW42x: Program executes in flash)

Low-power mode, (LPM0)

(LPM0)

= f

MCLK

= 32,768 Hz, XTS_FLL = 0

(ACLK)

SMCLK

= f

DCO

= 1 MHz,

= 1

= −40°C to 85°C

FN_8=FN_4=FN_3=FN_2=0 (see Note 3)

(LPM2)

Low-power mode, (LPM2) (see Note 3) TA = −40°C to 85°C

TA = −40°C 0.95 1.4 TA = −10°C 0.8 1.3 TA = 25°C TA = 60°C T

= 85°C 1.6 2.3

(LPM3)

Low-power mode, (LPM3) (see Note 2 and Note 3)

= −40°C 1.1 1.7

TA = −10°C 1.0 1.6 TA = 25°C TA = 60°C TA = 85°C 2.0 2.6 TA = −40°C 0.1 0.5

= 25°C

LPM4

Low-power mode, (LPM4) (see Note 3)

TA = 85°C

NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. The current consumption is measured with active Basic

Timer1 and LCD (ACLK selected). The current consumption of the Comparator_A and the SVS module are specified in the respective sections.

2. The LPM3 currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal.

3. Current for brownout included.

VCC = 2.2 V 200 250

VCC = 3 V 300 350

VCC = 2.2 V 57 70

VCC = 3 V 92 100

VCC = 2.2 V 11 14 VCC = 3 V 17 22

VCC = 2.2 V

0.7 1.2

0.95 1.4

VCC = 3 V

0.9 1.5

1.1 1.7

VCC = 2.2 V/3 V

0.1 0.5

0.8 2.5

μA

current consumption of active mode versus system frequency

= I

(AM)

(AM) [1 MHz]

current consumption of active mode versus supply voltage

= I

(AM)

(AM) [3 V]

× f

(System) [MHz]

+ 140 μA/V × (VCC – 3 V)

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MSP430xW42x

(int)

for the interrupt flag, (see Note 1)

Timer_A clock frequency

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IT+

IT−

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

IT+

− V

IT−

)

inputs Px.x, TAx.x

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TAint)

External interrupt timing

Timer_A, capture timing TAx.x

Timer_A clock frequency externally applied to pin

Timer_A clock frequency SMCLK or ACLK signal selected

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

trigger signals shorter than t MCLK cycles.

Port P1, P2: P1.x to P2.x, External trigger signal

TAxCLK, INCLK

. Both the cycle and timing specifications must be met to ensure the flag is set. t

(int)

= t

(H)

(L)

VCC = 2.2 V 1.1 1.5

= 3 V 1.5 1.9

VCC = 2.2 V 0.4 0.9

= 3 V 0.9 1.3

VCC = 2.2 V 0.3 1.1 VCC = 3 V 0.45 1

MIN TYP MAX UNIT

2.2 V/3 V 1.5 cycle

2.2 V 62 3 V 50

2.2 V 8 3 V 10

cycle and time parameters are met. It may be set even with

(int)

is measured in

(int)

MHz

leakage current − Ports P1, P2, P3, P4, P5, and P6 (see Note 1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

lkg(Px.x)

NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

Leakage current Port Px Port x: V

2. The port pin must be selected as an input.

(see Note 2) VCC = 2.2 V/3 V ±50 nA

(Px.x)

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MSP430xW42x

P1.1/TA0.0/MCLK P1.5/TA0CLK/ACLK

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs − Ports P1, P2, P3, P4, P5, and P6

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage

Low-level output voltage

NOTES: 1. The maximum total current, I

specified voltage drop.

2. The maximum total current, I specified voltage drop.

output frequency

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Px.y

ACLK,

MCLK,

SMCLK

Xdc

(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)

P1.1/TA0.0/MCLK,

P1.5/TA0CLK/ACLK

Duty cycle of output frequency

OH(max)

OL(max)

OH(max)

= −1.5 mA, V = −6 mA, V = −1.5 mA, V

= −6 mA, V = 1.5 mA, V = 6 mA, V = 1.5 mA, V = 6 mA, V

and I

OL(max),

and I

OL(max),

CL = 20 pF,

= 20 pF,

= ± 1.5mA

= 20 pF

VCC = 2.2 V / 3 V

P1.1/TA0.0/MCLK, CL = 20 pF, V

= 2.2 V / 3 V

= 2.2 V, See Note 1 VCC−0.25 V

= 2.2 V, See Note 2 VCC−0.6 V

= 3 V, See Note 1 VCC−0.25 V

= 3 V, See Note 2 VCC−0.6 V

= 2.2 V, See Note 1 V

= 2.2 V, See Note 2 V

= 3 V, See Note 1 V

= 3 V, See Note 2 V

VSS+0.25

VSS+0.6

VSS+0.25

VSS+0.6

for all outputs combined, should not exceed ±12 mA to satisfy the maximum

for all outputs combined, should not exceed ±24 mA to satisfy the maximum

= 2.2 V DC 10

= 3 V DC 12

= 2.2 V 8

= 3 V 12

= f

ACLK

= f

ACLK

= f

ACLK

MCLK

= f

LFXT1

LFXT1/n

DCOCLK

= f = f

XT1

40% 60% 30% 70%

50%−

15 ns

50%−

15 ns

50%

50%+

15 ns

50%+

15 ns

MHz

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC = 2.2 V P2.4

− Typical Low-Level Output Current − mA

0.0 0.5 1.0 1.5 2.0 2.5 VOL − Low-Level Output Voltage − V

TA = 25°C

TA = 85°C

Figure 2

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

VCC = 2.2 V P2.4

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC = 3 V P2.4

− Typical Low-Level Output Current − mA

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOL − Low-Level Output Voltage − V

TA = 85°C

Figure 3

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

VCC = 3 V

−5

P2.4

TA = 25°C

−5

−10

−15

−20

− Typical High-Level Output Current − mA

−25

TA = 85°C

TA = 25°C

0.0 0.5 1.0 1.5 2.0 2.5 VOH − High-Level Output Voltage − V

Figure 4

NOTE: One output loaded at a time

−10

−15

−20

−25

−30

−35 TA = 85°C

−40

− Typical High-Level Output Current − mA

−45

−50

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

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TA = 25°C

VOH − High-Level Output Voltage − V

Figure 5

MSP430xW42x

)

d(LPM3)

Delay time

2.2 V/3 V

μs

Segment line

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

wake-up LPM3

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f = 1 MHz 6

±20 ±20 ±20

− 0.1

− 0.1 + 0.1

μs

d(LPM3

Delay time

f = 2 MHz

= 2.2 V/3 V

f = 3 MHz

RAM (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VRAMh CPU halted (see Note 1) 1.6 V

NOTES: 1. This parameter defines the minimum supply voltage when the data in the program memory RAM remain unchanged. No program

execution should take place during this supply voltage condition.

LCD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(33)

(23)

(13)

(33) −

(R03)

(R13)

(R23)

(Sxx0)

(Sxx1)

(Sxx2)

(Sxx3)

Analog voltage

(03)

Input leakage

Segment line voltage

Voltage at P5.7/R33 2.5 VCC +0.2 Voltage at P5.6/R23 Voltage at P5.5/R13

VCC = 3 V

(V33−V03) × 2/3 + V

(33)−V(03)

) × 1/3 + V

(03)

Voltage at R33/R03 2.5 VCC +0.2 R03 = V

P5.5/R13 = VCC/3 P5.6/R23 = 2 × VCC/3

= −3 μA, VCC = 3 V

(Sxx)

No load at all segment and common lines, V

= 3 V

(03)

(13)

23)

33)

(03)

(13)

(23)

(33)

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MSP430xW42x

(See Figure 6 and T

25 C

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Comparator_A (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(CC)

(Refladder/RefDiode)

CAON = 1, CARSEL = 0, CAREF = 0

CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.6/CA0 and P1.7/CA1

VCC = 2.2 V 25 40 VCC = 3 V 45 60

VCC = 2.2 V 30 50

VCC = 3 V 45 71

μA

(Ref025)

(Ref050)

(RefVT)

(IC)

(offset)

hys

Voltage @ 0.25 VCCnode

Voltage @ 0.5 VCCnode

(See Figure 6 and Figure 7)

Common-mode input voltage range

Offset voltage See Note 2 VCC = 2.2 V/3 V −30 30 mV Input hysteresis CAON = 1 VCC = 2.2 V / 3 V 0 0.7 1.4 mV

PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P1.6/CA0 and P1.7/CA1;

= 85°C

CAON = 1 VCC = 2. 2V/3 V 0 VCC−1.0 V

TA = 25°C,

Overdrive 10 mV, without filter: CAF = 0

(response LH)

TA = 25°C

Overdrive 10 mV, with filter: CAF = 1

TA = 25°C

Overdrive 10 mV, without filter: CAF = 0

(response HL)

TA = 25°C,

Overdrive 10 mV, with filter: CAF = 1

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

VCC = 2.2 V / 3 V 0.23 0.24 0.25

VCC = 2.2V / 3 V 0.47 0.48 0.50

VCC = 2.2 V 390 480 540

VCC = 3.0 V 400 490 550

VCC = 2.2 V 130 210 300 VCC = 3 V 80 150 240 VCC = 2.2 V 1.4 1.9 3.4 VCC = 3 V 0.9 1.5 2.6 VCC = 2.2 V 130 210 300 VCC = 3 V 80 150 240 VCC = 2.2 V 1.4 1.9 3.4 VCC = 3.0 V 0.9 1.5 2.6

specification.

lkg(Px.x)

μs

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

600

Typical

550

500

− Reference Voltage − mV

(RefVT)

450

400

−45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C

Figure 6

0 V

CAON

V+

V−

VCC = 3 V

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

VCC = 2.2 V

600

Typical

550

500

− Reference Voltage − mV

(RefVT)

450

400

−45 −25 −5 15 35 55 75 95 TA − Free-Air Temperature − °C

Figure 7

CAF

Low Pass Filter

To Internal Modules

CAOUT

τ ≈ 2 μs

Figure 8. Block Diagram of Comparator_A Module

CAOUT

V−

400 mV

V+

Overdrive

(response)

Figure 9. Overdrive Definition

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Set CAIFG Flag

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MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

POR brownout, reset (see Notes 1 and 2)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(BOR)

CC(start)

(B_IT−)

hys(B_IT−)

(reset)

rownout

dVCC/dt ≤ 3 V/s (see Figure 10) 0.7 × V dVCC/dt ≤ 3 V/s (see Figure 10, Figure 11, Figure 12) 1.71 V

dVCC/dt ≤ 3 V/s (see Figure 10) 70 130 180 mV Pulse length needed at RST/NMI pin to accepted reset internally,

= 2.2 V/3 V

2 μs

NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level

+ V

(B_IT−)

hys(B_IT−)

2. During power up, the CPU begins code execution following a period of t settings must not be changed until V

is ≤ 1.8 V.

≥ V

CC(min)

, where V

after VCC = V

d(BOR)

is the minimum supply voltage for the desired operating

CC(min)

(B_IT−)

+ V

hys(B_IT−)

frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout/SVS circuit.

2000 μs

(B_IT−)

. The default FLL+

1.5

(drop) − V

0.5

hys(B_IT−)

(B_IT−)

CC(start)

Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage

V = 3 V

Typical Conditions

d(BOR)

CC(drop)

V 3 V

0.001 1 1000 tpw − Pulse Width − μst

Figure 11. V

CC(drop)

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

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1 ns 1 ns

− Pulse Width − μs

MSP430xW42x

)

hys(SVS_IT−)

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

V = 3 V

Typical Conditions

1.5

(drop) − V

0.5

0.001 1 1000 tpw − Pulse Width − μs

CC(drop)

3 V

= t

tpw − Pulse Width − μs

Figure 12. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

SVS (supply voltage supervisor/monitor) (See Notes 1 and 2)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

d(SVSR)

d(SVSon)

settle

(SVSstart)

hys(SVS_IT−

(SVS_IT−)

CC(SVS)

(see Note 1)

†

The recommended operating voltage range is limited to 3.6 V.

‡

is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere

settle

between 2 and 15. The overdrive is assumed to be > 50 mV.

NOTES: 1. The current consumption of the SVS module is not included in the I

2. The SVS is not active at power up.

dVCC/dt > 30 V/ms (see Figure 13) 5 150 μs dVCC/dt ≤ 30 V/ms 2000 μs SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V 20 150 μs

‡

VLD ≠ 0

12 μs

VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13) 1.55 1.7 V

VLD = 1 70 120 155 mV

VCC/dt ≤ 3 V/s (see Figure 13)

VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied on SVSIN

VLD = 2 .. 14

(SVS_IT−)

x 0.004

VLD = 15 4.4 10.4 mV

(SVS_IT−)

x 0.008

VLD = 1 1.8 1.9 2.05 VLD = 2 1.94 2.1 2.25 VLD = 3 2.05 2.2 2.37 VLD = 4 2.14 2.3 2.48 VLD = 5 2.24 2.4 2.6 VLD = 6 2.33 2.5 2.71

VCC/dt ≤ 3 V/s (see Figure 13)

VLD = 7 2.46 2.65 2.86 VLD = 8 2.58 2.8 3 VLD = 9 2.69 2.9 3.13 VLD = 10 2.83 3.05 3.29 VLD = 11 2.94 3.2 3.42

3.99

†

VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied on SVSIN

VLD = 12 3.11 3.35 3.61 VLD = 13 3.24 3.5 3.76 VLD = 14 3.43 3.7

†

VLD = 15 1.1 1.2 1.3

VLD ≠ 0, VCC = 2.2 V/3 V 10 15 μA

current consumption data.

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

(SVS_IT−)

(SVSstart)

(B_IT−)

CC(start)

Brownout

SVS out

Set POR

Software Sets VLD>0:SVS is Active

hys(SVS_IT−)

hys(B_IT−)

Brownout

Region

Brownout

Region

d(BOR)

SVS Circuit is Active From VLD > to VCC < V

d(SVSon)

(B_IT−)

d(SVSR)

d(BOR)

Undefined

Figure 13. SVS Reset (SVSR) vs Supply Voltage

3 V

Rectangular Drop

1.5

− V 1

CC(drop)

0.5

1 10 1000

Figure 14. V

CC(drop)

Triangular Drop

CC(drop)

1 ns 1 ns

3 V

100

− Pulse Width − μs

CC(drop)

= t

t − Pulse Width − μs

With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal

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Step size between adjacent DCO taps:

(DCO)

Temperature drift, N

(DCO)

01Eh, FN_8=FN_4=FN_3=FN_2=0

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

DCO

PARAMETER TEST CONDITIONS V

=01Eh, FN_8=FN_4=FN_3=FN_2=0, D = 2, DCOPLUS= 0,

(DCOCLK)

(DCO=2)

(DCO=27)

(DCO=2)

(DCO=27)

(DCO=2)

(DCO=27)

(DCO=2)

(DCO=27)

(DCO=2)

(DCO=27)

(DCO)

= 32.738 kHz

Crystal

FN_8=FN_4=FN_3=FN_2=0 , DCOPLUS = 1

FN_8=FN_4=FN_3=FN_2=0, DCOPLUS = 1

FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1

FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1

FN_8=FN_4=0, FN_3= 1, FN_2=x;, DCOPLUS = 1

FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1

FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1

FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1

FN_8=1,FN_4=FN_3=FN_2=x,DCOPLUS = 1

Step size between adjacent DCO taps: Sn = f

DCO(Tap n+1)

Temperature drift, N

/ f

DCO(Tap n)

(see Figure 16 for taps 21 to 27)

= 01Eh, FN_8=FN_4=FN_3=FN_2=0

D = 2, DCOPLUS = 0

Drift with VCC variation, N

= 01Eh, FN_8=FN_4=FN_3=FN_2=0

(DCO)

D = 2, DCOPLUS = 0

1 < TAP ≤ 20 1.06 1.11

2.2 V/3 V 1 MHz

2.2 V 0.3 0.65 1.25

2.2 V 2.5 5.6 10.5

2.2 V 0.7 1.3 2.3

2.2 V 5.7 10.8 18

2.2 V 1.2 2 3

2.2 V 9 15.5 25

2.2 V 1.8 2.8 4.2

2.2 V 13.5 21.5 33

2.2 V 2.8 4.2 6.2

2.2 V 21 32 46

TAP = 27 1.07 1.17

2.2 V –0.2 –0.3 –0.4

2.2 V/3 V 0 5 15 %/V

MIN TYP MAX UNIT

3 V 0.3 0.7 1.3

3 V 2.7 6.1 11.3

3 V 0.8 1.5 2.5

3 V 6.5 12.1 20

3 V 1.3 2.2 3.5

3 V 10.3 17.9 28.5

3 V 2.1 3.4 5.2

3 V 16 26.6 41

3 V 4.2 6.3 9.2

3 V 30 46 70

3 V –0.2 –0.3 –0.4

MHz

%/_C

(DCO)

(DCO3V)

1.0

1.8 3.02.4 3.6

Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature

(DCO)

(DCO205C)

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1.0

20 6040 85

0−20−400

TA − °CVCC − V

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

1.17

(DCO)

- Stepsize Ratio between DCO Taps

1.11

1.07

1.06

Max

Min

12720

DCO Tap

Figure 16. DCO Tap Step Size

Legend

Tolerance at Tap 27

DCO Frequency Adjusted by Bits

to 25 in SCFI1 {N

Tolerance at Tap 2

{DCO}

}

FN_2=0 FN_3=0 FN_4=0 FN_8=0

Overlapping DCO Ranges: Uninterrupted Frequency Range

FN_2=1 FN_3=0 FN_4=0 FN_8=0

FN_2=x FN_3=1 FN_4=0 FN_8=0

FN_2=x FN_3=x FN_4=1 FN_8=0

FN_2=x FN_3=x FN_4=x FN_8=1

Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits

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crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)

PARAMETER TEST CONDITIONS V

OSCCAPx = 0h 2.2 V/3 V 0

XIN

Integrated load capacitance

OSCCAPx = 1h 2.2 V/3 V 10 OSCCAPx = 2h

2.2 V/3 V 14 OSCCAPx = 3h 2.2 V/3 V 18 OSCCAPx = 0h 2.2 V/3 V 0

XOUT

Integrated load capacitance

OSCCAPx = 1h 2.2 V/3 V 10 OSCCAPx = 2h

2.2 V/3 V 14 OSCCAPx = 3h 2.2 V/3 V 18

Input levels at XIN see Note 3 2.2 V/3 V

NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2pF. The effective load capacitor for the crystal is

XIN

x C

XOUT

) / (C

XIN

+ C

). It is independent of XTS_FLL.

XOUT

2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines must be observe:

• Keep as short a trace as possible between the ’xW42x and the crystal.

• Design a good ground plane around oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to XIN an XOUT pins.

• Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation.

This signal is no longer required for the serial programming adapter.

3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.

4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.

MIN TYP MAX UNIT

0.8×V

0.2×V

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Scan IF, port drive, port timing

PARAMETER TEST CONDITIONS V

Voltage drop due to

OL(SIFCHx)

excitation transistor’s on−resistance.

= 2.0 mA, SIFTEN = 1 3 V 0.3 V

(SIFCHx)

(see Figure 18) Voltage drop due to

OH(SIFCHx)

(see Note 1)

damping transistor’s on−resistance.

= −200 μA, SIFTEN = 1 3 V 0.1 V

(SIFCHx)

(see Figure 18)

OL(SIFCOM)

SIFCHx(tri-state)

Δt t

dSIFCH

wEx(tsm)−twSIFCH

(see Figure 18)

Change of pulse width of internal signal SIFEX(tsm) to pulse width at pin SIFCHx

I V

= 3 mA, SIFSH = 1 2.2 V/3 V 0 0.1 V

(SIFCOM)

= 0 V to AVCC, port function

(SIFCHx)

disabled, SIFSH = 1

= 3 mA,

(SIFCHx)

Ex(SIFCHx)

= 500 ns ±20%

NOTE: 1. SIFCOM=1.5V , supplied externally. (See Figure 19).

3 V −50 50 nA

2.2 V/3 V −20 20 ns

MIN TYP MAX UNIT

Ex(SIFCHx)

SIFEX(tsm)

P6.x/SIFCH.x

SIFCH(x)

Figure 18. P6.x/SIFCHx timing, SIFCHx function selected

SIFCOM

OH(SIFCHx)

(SIFCHx)

Damping Transistor

P6.x/SIFCH.x

OL(SIFCHx)

Excitation Transistor

Figure 19. Voltage drop due to on-resistance

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SIFCOM pin = 470 nF ±20%

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Scan IF, sample capacitor/Ri timing

PARAMETER TEST CONDITIONS V

SHC(SIFCHx)

(SIFCHx)

Hold

(See Note 1)

Sample capacitance at SIFCHx pin

Serial input resistance at the SIFCHx pin

SIFEx(tsm) = 1, SIFSH = 1 2.2 V/3 V 5 7 pF

SIFEx(tsm) = 1, SIFSH = 1 2.2 V/3 V 1.5 3 kΩ

Maximum hold time ΔV

< 3 mV 62 μs

sample

NOTES: 1. The sampled voltage at the sample capacitance varies less than 3 mV (ΔV

after t

, the sampled voltage may be any other value.

Hold

2. The minimum sampling time (7.6 x tau for 1/2 LSB accuracy) with maximum C t

sample(min)

~ 7.6 x C

SHC(SIFCHx)

x (Ri

(SIFCHx)

+ Ri

(source)

) with Ri

(source)

Scan IF, VCC/2 generator

PARAMETER TEST CONDITIONS V

refresh(SIFCOM)

Analog supply voltage

Scan IF VCC/2

enerator operatin supply current into AV

terminal

VCC/2 refresh frequency

AVCC = DVCC (connected together) AV

= DVSS (connected together)

at SIFCOM pin = 470 nF ±20%,

refresh(SIFCOM)

=32768 Hz

Source clock = ACLK

) during the hold time t

sample

SHC(SIFCHx)

estimated at 3 kΩ, t

2.2 V 250 350

3 V 370 450

2.2 V/3 V

MIN TYP MAX UNIT

If the voltage is sampled

Hold.

and Ri

sample(min)

(SIFCHx)

= 319 ns.

and Ri

(source)

MIN TYP MAX UNIT

2.2 3.6 V

30 32.768 kHz

(SIFCOM)

source(SIFCOM)

sink(SIFCOM)

recovery(SIFCOM)

on(SIFCOM)

VccSettle(SIFCOM)

(See Note 1)

Output voltage at pin SIFCOM

SIFCOM source current (see Note 2 and Figure 20)

SIFCOM sink current (see Note 2 and Figure 20)

Time to recover from Voltage Drop on Load

Time to reach 98% after V

CC/

2 is

switched on

Settling time to ±V

/512 (2 LSB)

after AVCC voltage change

CL at SIFCOM pin = 470 nF ±20%, I_Load = 1μA

= I

Load1

= 3 mA, t

Load2

at SIFCOM pin = 470 nF ±20%

LOAD3

= 0 mA

load(on)

= 500nS,

CL at SIFCOM pin = 470 nF ±20% f

refresh(SIFCOM)

= 32768 Hz

SIFEN =1, SIFVCC2 =1, SIFSH =0, AV

refresh(SIFCOM)

= AV

−100 mV

= 32768 Hz

AVCC = AVCC + 100mV f

refresh(SIFCOM)

= 32768 Hz

AVCC/2 −

.05

AVCC/2

AVCC/2 +

.05

2.2 V −500

3 V −900

2.2 V 150

3 V 180

2.2 V/3 V 30 μs

2.2 V/3 V

1.7 6 ms

2.2 V/3 V 80

2.2 V/3 V 3

NOTES: 1. The settling time after an AVCC voltage change is the time to for the voltage at pin SIFCOM to settle to AVCC/2 ± 2LSB.

2. The sink and source currents are a function of the voltage at the pin SIFCOM. The maximum currents are reached if SIFCOM is shorted to GND or V

. Due to the topology of the output section (refer to Figure 20) the VCC/2 generator can source relatively large

currents but can sink only small currents.

μA

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operating supply

SIFCOM pin = 470 nF ±20%

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

VCC/2

Source(SIFCOM)

SIFCOM

Sink(SIFCOM)

Figure 20. P6.x/SIFCHx timing, SIFCHx function selected

Scan IF, 10-bit DAC (See Note 1)

PARAMETER TEST CONDITIONS V

Analog supply voltage

AVCC = DVCC (connected together) AV

= DVSS (connected together)

Scan IF 10-bit DAC o

erating suppl

current into AV

refresh(SIFCOM)

= 32768 Hz

CL at SIFCOM pin = 470 nF ±20%,

terminal

2.2 V 23 45

3 V 33 60

Resolution 10 bit

= 1000 MΩ,

INL

DNL

on(SIFDAC)

Settle(SIFDAC)

= 20 pF

= 1000 MΩ,

= 20 pF

2.2 V/3 V ±2 ±5 LSB

2.2 V/3 V ±1 LSB

Zero Scale Error 2.2 V/3 V ±10 mV Gain Error 2.2 V/3 V 0.6 % Output resistance 25 50 kΩ On time after AVCC of

SIFDAC is switched on

Settling time

− V

+SIFCA

SIFDAC code = 1C0h → 240h V

SIFDAC(240h)

SIFDAC code = 240h → 1C0h, V

SIFDAC(1C0h)

= ±6 mV 2.2 V/3 V 2.0 μs

SIFDAC

− V

+SIFCA

= +6 mV

= −6 mV

2.2 V/3 V 2.0 μs

NOTES: 1. The SIFDAC operates from AVCC and SIFVSS. All parameters are based on these references.

MIN TYP MAX UNIT

2.2 3.6 V

μA

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Scan IF oscillator at

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Scan IF, Comparator

Offset

/dT

Offset

/dV

Offset

hys

on(SIFCA)

Settle(SIFCA)

PARAMETER TEST CONDITIONS V

Analog supply voltage

AVCC = DVCC (connected together) AV

= DVSS (connected together)

Scan IF comparator operating supply current into AV

Common Mode Input Voltage Range

terminal

(see Note 1) 2.2 V/3 V 0.9

Input Offset Voltage 2.2 V/3 V ±30 mV Temperature coefficient of

Offset

supply voltage

Offset

) sensitivity

Input Voltage Hysteresis V

On time after SIFCA is switched on

Settle time

= V

+terminal

+SIFCA

−terminal

− V

SIFDAC

= 0.5 x AV

− V

SIFDAC=

−12 mV → 6 mV V

= 0.5 x AV

+SIFCA

= 0.5 x V

= +6 mV

2.2 V 25 35

3 V 35 50

2.2 V/3 V 10 μV/_C

2.2 V/3 V 0.3 mV/V

2.2V 0 5.0

3.0V 0 6.0

2.2 V/3 V 2.0 us

NOTES: 1. The comparator output is reliable when at least one of the input signals is within the common mode input voltage range.

MIN TYP MAX UNIT

2.2 3.6 V

μA

− 0.5

Scan IF, SIFCLK Oscillator

PARAMETER TEST CONDITIONS V

SIFCLKG

on(SIFCLKG)

(SIFCLK)

= 0

= 8

= 15

Analog supply voltage

Scan IF oscillator operating supply current into AV

terminal

Scan IF oscillator at minimum setting

Scan IF oscillator at nominal setting

Scan IF oscillator at maximum setting

Settling time to full operation after V switched on

Frequency Change per ±1 SIFCLKFQ

(SIFCTL5)

Temperature Coefficient SIFCLKFQ Frequency vs. supply

voltage V

variation

AVCC = DVCC (connected together) AV

= DVSS (connected together)

TA=25ºC, SIFCLKFQ=0000

step

S f

(SIFCLKFQ)

SIFCLKFQ

(SIFCLK)

= f

(SIFCLKFQ + 1)

(SIFCTL5)

MIN TYP MAX UNIT

2.2 3.6 V

2.2 V 75

3 V 90

μA

SIFNOM = 0 1.8 3.2 SIFNOM = 1 0.45 0.8 SIFNOM = 0 4 SIFNOM = 1 1

MHz

SIFNOM = 0 4.48 6.8 SIFNOM = 1 1.12 1.7

2.2 V/3 V 150 500 ns

2.2 V/3 V 1.01 1.05 1.18 Hz/Hz

= 8 2.2 V/3 V 0.35 %/_C

= 8 2.2 V/3 V 2 %/V

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Flash Memory

TEST

CONDITIONS

MIN NOM MAX UNIT

CC(PGM/

ERASE)

PARAMETER

Program and Erase supply voltage 2.7 3.6 V

FTG

PGM

ERASE

CPT

CMErase

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

Flash Timing Generator frequency 257 476 kHz Supply current from DVCC during program 2.7 V/ 3.6 V 3 5 mA Supply current from DVCC during erase 2.7 V/ 3.6 V 3 7 mA Cumulative program time see Note 1 2.7 V/ 3.6 V 10 ms Cumulative mass erase time see Note 2 2.7 V/ 3.6 V 200 ms

Program/Erase endurance 10

cycles

Data retention duration TJ = 25°C 100 years Word or byte program time 35

Block program time for 1st byte or word 30 Block program time for each additional byte or word Block program end-sequence wait time

see Note 3

FTG

Mass erase time 5297 Segment erase time 4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1/f

,max = 5297x1/476kHz). To

FTG

achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine (t

FTG

= 1/f

FTG

JTAG Interface

TEST

CONDITIONS

MIN NOM MAX UNIT

2.2 V 0 5 MHz 3 V 0 10 MHz

TCK

Internal

NOTES: 1. f

2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

PARAMETER

TCK input frequency see Note 1

Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2 2.2 V/ 3 V 25 60 90 kΩ

may be restricted to meet the timing requirements of the module selected.

TCK

JTAG Fuse (see Note 1)

PARAMETER

CC(FB)

Supply voltage during fuse-blow condition TA = 25°C 2.5 V Voltage level on TDI/TCLK for fuse-blow 6 7 V Supply current into TDI/TCLK during fuse blow 100 mA Time to blow fuse 1 ms

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TEST

CONDITIONS

MIN NOM MAX UNIT

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.5, input/output with Schmitt-trigger

CAPD.x

P1SEL.x

P1DIR.x

Direction Control

From Module

P1OUT.x

Module X OUT

P1IN.x

1 0 1

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

Pad Logic

0: Input 1: Output

Bus keeper

P1.0/TA0.0 P1.1/TA0.0/MCLK P1.2/TA0.1 P1.3/TA1.0/SVSOUT P1.4/TA1.0 P1.5/TA0CLK/ACLK

Module X IN

P1IRQ.x

NOTE: 0 ≤ x ≤ 5.

PnSEL.x PnDIR.x

P1SEL.0

P1SEL.1 P1DIR.1 P1OUT.1 P1IN.1 P1IE.1 P1IFG.1 P1IES.1

P1SEL.2 P1DIR.2 P1OUT.2 P1IN.2 P1IE.2 P1IFG.2 P1IES.2

P1SEL.3 P1DIR.3 P1OUT.3 P1IN.3 P1IE.3 P1IFG.3 P1IES.3

P1SEL.4 P1DIR.4

P1SEL.5 P1DIR.5 P1OUT.5 P1IN.5 P1IE.5 P1IFG.5 P1IES.5

†

Timer0_A

‡

Timer1_A

P1IE.x

P1IFG.x

Set

P1IES.x P1SEL.x

Port Function is Active if CAPD.x = 0

P1DIR.0

Direction

Control

From Module

P1DIR.0

P1DIR.1

P1DIR.2

P1DIR.3

P1DIR.4

P1DIR.5

PnOUT.x

P1OUT.0

P1OUT.4 P1IN.4 P1IE.4 P1IFG.4 P1IES.4

Interrupt

Edge

Select

Module X

OUT

Out0 Sig.

MCLK

Out1 Sig.

SVSOUT

Out0 Sig.

ACLK

PnIN.x

†

P1IN.0

†

‡

Module X IN

CCI0A

CCI0B

CCI1A

CCI0B‡

CCI0A‡

T0ACLK

PnIE.x

†

P1IE.0 P1IFG.0 P1IES.0

†

PnIFG.x

PnIES.x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

Port P1, P1.6, P1.7 input/output with Schmitt-trigger

Pad Logic

CAPD.6

P1SEL.6

P1DIR.6 P1DIR.6

P1OUT.6

DVSS

P1IN.6

unused

P1IRQ.07

CCI1B

to Timer_Ax

Note: Port Function Is Active if CAPD.6 = 0

P1IE.7

P1IFG.7

Set

P1IES.x P1SEL.x

Interrupt

Edge

Select

Comparator_A

CAF

CAREF

Bus Keeper

Reference Block

AVcc

0: Input 1: Output

CAREF

−

P2CA

CAEX

CA0

CA1

P1.6/

CA0

CAPD.7

P1SEL.7

P1DIR.7

P1OUT.7

DVSS

P1IN.7

unused

P1IRQ.07

Note: Port Function Is Active if CAPD.7 = 0

P1IE.7

P1IFG.7

Set

P1IES.7 P1SEL.7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Interrupt

Edge

Select

Bus Keeper

0: Input 1: Output

Pad Logic

P1.7/

CA1

APPLICATION INFORMATION

input/output schematic (continued)

port P2, P2.0 to P2.7, input/output with Schmitt-trigger

P2.0, P2.1

LCDM.5 LCDM.6

P2.2 to P2.5

LCDM.7

P2.6, P2.7

0: Port Active 1: Segment xx

Function Active

Segment xx

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

Pad Logic

P2SEL.x

P2DIR.x

Direction Control

From Module

P2OUT.x

Module X OUT

P2IN.x

Module X IN

P2IRQ.x

P2IE.x

P2IFG.x

NOTE: 0 ≤ x ≤ 7

Direction

PnSEL.x PnDIR.x

P2SEL.0 P2DIR.0 P2OUT.0

P2SEL.1 P2DIR.1 P2OUT.1

P2SEL.2 P2DIR.2 P2OUT.2

P2SEL.3 P2DIR.3 P2OUT.3

P2SEL.4 P2DIR.4 P2OUT.4

Control

From Module

P2DIR.0

P2DIR.1

P2DIR.2

P2DIR.3

P2DIR.4

0 1 0 1

PnOUT.x

Set

P2IES.x P2SEL.x

Module X

OUT

Out2 Sig.

Out1 Sig.‡

Out2 Sig.‡

Out3 Sig.‡

Out4 Sig.‡

0: Input 1: Output

Bus keeper

Interrupt

Edge

Select

PnIN.x

†

P2IN.0 P2IE.0 P2IFG.0 P2IES.0

P2IN.1 P2IE.1 P2IFG.1 P2IES.1

P2IN.2 P2IE.2 P2IFG.2 P2IES.2

P2IN.3 P2IE.3 P2IFG.3 P2IES.3

P2IN.4 P2IE.4 P2IFG.4 P2IES.4

Module X IN

CCI2A

CCI1A

CCI2A

CCI3A

CCI4A

PnIE.x

†

‡

PnIFG.x

P2.x

P2.0/TA0.2 P2.1/TA1.1 P2.2/TA1.2/S23 P2.3/TA1.3/S22 P2.4/TA1.4/S21 P2.5/TA1CLK/S20 P2.6/CAOUT/S19 P2.7/SIFCLKG/S18

PnIES.x

P2SEL.5 P2DIR.5 P2OUT.5

P2SEL.6 P2DIR.6

P2SEL.7 P2DIR.7

†

Timer0_A

‡

Timer1_A

Scan IF

P2DIR.5

P2DIR.6

P2DIR.7

P2OUT.6

P2OUT.7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DVSS

CAOUT

SIFCLKG

Unused

‡

P2IE.6

P2IE.7

P2IFG.6

P2IFG.7

P2IN.5 P2IE.5 P2IFG.5 P2IES.5

P2IN.6

P2IN.7

TA1CLK1

P2IES.6

P2IES.7

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.0 to P3.7, input/output with Schmitt-trigger

LCDM.5 LCDM.6 LCDM.7

Segment xx

P3SEL.x

P3DIR.x

Direction Control

From Module

P3OUT.x

Module X OUT

P3IN.x

Module X IN

P3.2 to P3.7

P3.0, P3.1

NOTE: 0 ≤ x ≤ 7

0: Port Active 1: Segment xx

0 1 0 1

Function Active

Bus keeper

0: Input 1: Output

Pad Logic

P3.x

P3.0/S17 P3.1/S16 P3.2/S15 P3.3/S14 P3.4/S13 P3.5/S12 P3.6/S11

P3.7/S10

Direction

PnSEL.x PnDIR.x

P3SEL.0 P3DIR.0 P3OUT.0

P3SEL.1 P3DIR.1 P3OUT.1

P3SEL.2 P3DIR.2 P3OUT.2

P3SEL.3 P3DIR.3 P3OUT.3

P3SEL.4 P3DIR.4 P3OUT.4

P3SEL.5 P3DIR.5 P3OUT.5

P3SEL.6 P3DIR.6 P3OUT.6

P3SEL.7 P3DIR.7 P3OUT.7

Control

From Module

P3DIR.0

P3DIR.1

P3DIR.2

P3DIR.3

P3DIR.4

P3DIR.5

P3DIR.6

P3DIR.7

PnOUT.x

Module X

OUT

DVSS

PnIN.x Module X IN

P3IN.0

P3IN.1

P3IN.2

P3IN.3

P3IN.4

P3IN.5

P3IN.6

P3IN.7

Unused

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P4, P4.0 to P4.7, input/output with Schmitt-trigger

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

LCDM.5 LCDM.6 LCDM.7

Segment xx

P4SEL.x

P4DIR.x

Direction Control

From Module

P4OUT.x

Module X OUT

P4IN.x

Module X IN

0: Port Active 1: Segment xx

Function Active

1 0 1

NOTE: 0 ≤ x ≤ 7

Direction

PnSEL.x PnDIR.x

P4SEL.0 P4DIR.0 P4OUT.0

Control

From Module

P4DIR.0

PnOUT.x

Bus keeper

Module X

OUT

DVSS

Pad Logic

0: Input 1: Output

PnIN.x Module X IN

P4IN.0

Unused

P4.x

P4.0/S9 P4.1/S8 P4.2/S7 P4.3/S6 P4.4/S5 P4.5/S4 P4.6/S3 P4.7/S2

P4SEL.1 P4DIR.1 P4OUT.1

P4SEL.2 P4DIR.2 P4OUT.2

P4SEL.3 P4DIR.3 P4OUT.3

P4SEL.4 P4DIR.4 P4OUT.4

P4SEL.5 P4DIR.5 P4OUT.5

P4SEL.6 P4DIR.6 P4OUT.6

P4SEL.7 P4DIR.7 P4OUT.7

P4DIR.1

P4DIR.2

P4DIR.3

P4DIR.4

P4DIR.5

P4DIR.6

P4DIR.7

DVSS

P4IN.1

P4IN.2

P4IN.3

P4IN.4

P4IN.5

P4IN.6

P4IN.7

Unused

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

port P5, P5.0, P5.1, input/output with Schmitt-trigger

LCDM.5 LCDM.6 LCDM.7

Segment xx or

COMx or Rxx

P5SEL.x

P5DIR.x

Direction Control

From Module

P5OUT.x

Module X OUT

P5IN.x

Module X IN

NOTE: x = 0, 1

PnSEL.x PnDIR.x

P5SEL.0 P5DIR.0 P5OUT.0

From Module

0: Port Active 1: Segment

0 1 0 1

Direction

Control

P5DIR.0

Function Active

PnOUT.x

Module X

OUT

DVSS

Pad Logic

0: Input 1: Output

Bus keeper

PnIN.x

P5IN.0 S1

Module X IN

Unused

Segment

P5.x

P5.0/S1 P5.1/S0

P5SEL.1 P5DIR.1 P5OUT.1

P5DIR.1 DVSS

DVSS

P5IN.1 S0

Unused

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P5, P5.2 to P5.4, input/output with Schmitt-trigger

0: Port Active 1: COMx Function

Active

COMx

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

Pad Logic

P5SEL.x

P5DIR.x

Direction Control

From Module

P5OUT.x

Module X OUT

P5IN.x

Module X IN

NOTE: 2 ≤ x ≤ 4

PnSEL.x PnDIR.x

P5SEL.2 P5DIR.2 P5OUT.2

P5SEL.3 P5DIR.3 P5OUT.3

P5SEL.4 P5DIR.4 P5OUT.4

The direction control bits P5SEL.2, P5SEL.3, and P5SEL.4 are used to distinguish between port and common functions. Note that a 4MUX LCD requires all common signals COM3 to COM0, a 3MUX LCD requires COM2 to COM0, 2MUX LCD requires COM1 to COM0, and a static LCD requires only COM0.

1 0 1

Direction

Control

From Module

P5DIR.2

P5DIR.3 DVSS

P5DIR.4 DVSS

PnOUT.x

NOTE:

Module X

OUT

DVSS

0: Input 1: Output

Bus keeper

PnIN.x

P5IN.2 COM1

P5IN.3 COM2

P5IN.4 COM3

Module X IN

Unused

COMx

P5.x

P5.2/COM1 P5.3/COM2 P5.4/COM3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

port P5, P5.5 to P5.7, input/output with Schmitt-trigger

0: Port Active 1: Rxx Function

Active

Rxx

Pad Logic

P5SEL.x

P5DIR.x

Direction Control

From Module

P5OUT.x

Module X OUT

P5IN.x

Module X IN

NOTE: 5 ≤ x ≤ 7

PnSEL.x PnDIR.x

P5SEL.5 P5DIR.5 P5OUT.5

P5SEL.6 P5DIR.6 P5OUT.6

P5SEL.7 P5DIR.7 P5OUT.7

The direction control bits P5SEL.5, P5SEL.6, and P5SEL.7 are used to distinguish between port and LCD analog level functions. Note that 4MUX and 3MUX LCDs require all Rxx signals R33 to R03, a 2MUX LCD requires R33, R13, and R03, and a static LCD requires only R33 and R03.

1 0 1

Direction

Control

From Module

P5DIR.5

P5DIR.6 DVSS

P5DIR.7 DVSS

PnOUT.x

NOTE:

Module X

OUT

DVSS

0: Input 1: Output

Bus keeper

PnIN.x

P5IN.5 R13

P5IN.6 R23

P5IN.7 R33

Module X IN

Unused

P5.x

P5.5/R13 P5.6/R23 P5.7/R33

Rxx

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

input/output schematic (continued)

port P6, P6.0, P6.1, P6.2, P6.4, P6.5, input/output with Schmitt-trigger

P6SEL.x

P6DIR.x

Direction Control

From Module

P6OUT.x

Module X OUT

P6IN.x

0: Input 1: Output

Bus Keeper

MSP430xW42x

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

Pad Logic

P6.X

P6.0/SIFCH0 P6.1/SIFCH1 P6.2/SIFCH2 P6.4/SIFCI0 P6.5/SIFCI1

Module X IN

To/From Scan I/F

P6SEL.x must be set if the corresponding pins are used by the Scan IF.

x: Bit Identifier = 0, 1, 2, 4, or 5

NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if

the analog signal is in the range of transitions 0→1 or 1→0. The value of the throughput current depends on the driving capability of the gate. For MSP430, it is approximately 100 μA. Use P6SEL.x=1 to prevent throughput current. P6SEL.x should be set, if an analog signal is applied to the pin.

PnSEL.x

P6Sel.0 P6DIR.0 P6DIR.0 P6OUT.0 DV P6Sel.1 P6DIR.1 P6DIR.1 P6OUT.1 DV P6Sel.2 P6DIR.2 P6DIR.2 P6OUT.2 DV P6Sel.4 P6DIR.4 P6DIR.4 P6OUT.4 DV P6Sel.5 P6DIR.5 P6DIR.5 P6OUT.5 DV

NOTE: The signal at pins P6.x/SIFCHx and P6.x/SIFCIx are shared by Port P6 and the San IF module. P6SEL.x must be set if the corresponding

pins are used by the Scan IF.

PnDIR.x

Dir. Control

From Module

PnOUT.x Module X OUT PnIN.x Module X IN

P6IN.0 unused P6IN.1 unused P6IN.2 unused P6IN.4 unused P6IN.5 unused

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

port P6, P6.3 input/output with Schmitt-trigger

P6SEL.3

P6DIR.3

P6OUT.x

SIFCAOUT

P6IN.3

0: Input 1: Output

Bus Keeper

Pad Logic

P6.3/SIFCH3/SIFCAOUT

Module X IN

To/From Scan I/F

P6SEL.x must be set if the corresponding pins are used by the Scan IF.

NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if

P6SEL.3

0 0 P6.3 Input 0 1 P6.3 Output 1 0 SIFCH3 (Scan IF channel 3 excitation output and comparator input) 1 1 SIFCAOUT (Comparator output)

P6DIR.3 Port Function

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

input/output schematic (continued)

port P6, P6.6 input/output with Schmitt-trigger

P6SEL.6

P6DIR.6

0: Input 1: Output

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

P6OUT.6

DVss

P6IN.6

Module X IN

From Scan I/F DAC

To Scan I/F comparator input mux

P6SEL.x must be set if the corresponding pins are used by the Scan IF.

NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if

Bus Keeper

Pad Logic

P6.6/SIFCI2/DACOUT

P6SEL.6

0 0 P6.6 Input 0 1 P6.6 Output 1 0 SIFCI2 (Scan IF channel 2 comparator input) 1 1 SIFDAOUT (Scan IF DAC output)

P6DIR.6 Port Function

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

input/output schematic (continued)

port P6, P6.7 input/output with Schmitt-trigger

SVS VLDx=15

P6SEL.7 P6DIR.7

0: Input 1: Output

P6OUT.7

DVss

P6IN.7

Module X IN

SVS VLDx=15

To SVS

To Scan I/F comparator (+) terminal

P6SEL.x must be set if the corresponding pins are used by the Scan IF.

NOTE: Analog signals applied to digital gates can cause current flow from the positive to the negative terminal. The throughput current flows if

Bus Keeper

Pad Logic

P6.7/SIFCI3/SVSIN

SVS VLDx = 15

0 0 0 P6.7 Input 0 0 1 P6.7 Output 0 1 X SIFCI3 (Scan IF channel 3 comparator input) 1 X X SVSIN

P6SEL.7 P6DIR.7 Port Function

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output

TDO

Controlled by JTAG

JTAG

Controlled

by JTAG

TDI

Burn and Test

TDO/TDI

Fuse

Test

and

Emulation

Module

TMS

TCK

Tau ~ 50 ns

Brownout

TDI/TCLK

TMS

TCK

RST/NMI

D U S

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

APPLICATION INFORMATION

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, I taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated.

The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see Figure 21). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition).

The JTAG pins are terminated internally, and therefore do not require external termination.

, of 1.8 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be

Time TMS Goes Low After POR

TMS

TDI/TCLK

Figure 21. Fuse Check Mode Current, MSP430FW42x

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

Data Sheet Revision History

MSP430xW42x

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

Literature

Number

Updated functional block diagram (page 3) Clarified test conditions in recommended operating conditions table (page 18)

SLAS383B

NOTE: Page and figure numbers refer to the respective document revision.

Clarified test conditions in electrical characteristics table (page 19) Added I Clarified test conditions in DCO table (page 29) Changed t

for all ports in leakage current table (page 20)

lkg(Px.x)

maximum value from 4 ms to 10 ms in Flash memory table (page 36)

CPT

Summary

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

16-Jan-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

MSP430FW423IPM ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br)

MSP430FW423IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &

no Sb/Br)

MSP430FW425IPM ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br)

MSP430FW425IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &

no Sb/Br)

MSP430FW427IPM ACTIVE LQFP PM 64 160 Green (RoHS &

no Sb/Br)

MSP430FW427IPMR ACTIVE LQFP PM 64 1000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64) PLASTIC QUAD FLATPACK

0,50

0,27 0,17

7,50 TYP

10,20

9,80

12,20

11,80

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

1,45 1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 D. May also be thermally enhanced plastic with leads connected to the die pads.

0,75 0,45

Seating Plane

0,08

4040152/C 11/96

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TEXAS INSTRUMENTS MSP430xW42x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

description

functional block diagram

Terminal Functions

short-form description

instruction set

operating modes

interrupt vector addresses

special function registers

interrupt enable 1 and 2

interrupt flag register 1 and 2

module enable registers 1 and 2

memory organization

bootstrap loader (BSL)

flash memory

peripherals

oscillator and system clock

brownout, supply voltage supervisor

digital I/O

Basic Timer1

LCD drive

watchdog timer

comparator_A

scan IF

timer0_A3

timer1_A5

peripheral file map

absolute maximum ratings

recommended operating conditions

Schmitt-trigger inputs − Ports P1, P2, P3, P4, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK

inputs Px.x, TAx.x

outputs − Ports P1, P2, P3, P4, P5, and P6

output frequency

wake-up LPM3

Scan IF, port drive, port timing

Scan IF, sample capacitor/Ri timing

Scan IF, VCC/2 generator

Scan IF, Comparator

Scan IF, SIFCLK Oscillator

Flash Memory

JTAG Interface

APPLICATION INFORMATION

input/output schematic

Port P1, P1.0 to P1.5, input/output with Schmitt-trigger

Port P1, P1.6, P1.7 input/output with Schmitt-trigger

port P2, P2.0 to P2.7, input/output with Schmitt-trigger

port P3, P3.0 to P3.7, input/output with Schmitt-trigger

port P4, P4.0 to P4.7, input/output with Schmitt-trigger

port P5, P5.0, P5.1, input/output with Schmitt-trigger

port P5, P5.2 to P5.4, input/output with Schmitt-trigger

port P5, P5.5 to P5.7, input/output with Schmitt-trigger

port P6, P6.0, P6.1, P6.2, P6.4, P6.5, input/output with Schmitt-trigger

port P6, P6.3 input/output with Schmitt-trigger

port P6, P6.6 input/output with Schmitt-trigger

port P6, P6.7 input/output with Schmitt-trigger

JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output

JTAG fuse check mode

Data Sheet Revision History