TEXAS INSTRUMENTS MSP430xW42x Technical data

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

D Low Supply-Voltage Range, 1.8 V to 3.6 V D Ultralow-Power Consumption:

− Active Mode: 200 μA at 1 MHz, 2.2 V

− Standby Mode: 0.7 μA

− Off Mode (RAM Retention): 0.1 μA

D Five Power-Saving Modes D Wake-Up From Standby Mode in Less

Than 6 μs

D Frequency-Locked Loop, FLL+ D 16-Bit RISC Architecture, 125-ns

Instruction Cycle Time

D Scan IF for Background Water, Heat, and

Gas Volume Measurement

D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_A With Five

Capture/Compare Registers

D Integrated LCD Driver for Up to

96 Segments

D On-Chip Comparator

D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Brownout Detector D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D Bootstrap Loader in Flash Devices D Family Members Include:

− MSP430FW423: 8KB + 256B Flash Memory, 256B RAM

− MSP430FW425: 16KB + 256B Flash Memory, 512B RAM

− MSP430FW427: 32KB + 256B Flash Memory, 1KB RAM

D Available in 64-Pin Quad Flat Pack (QFP) D For Complete Module Descriptions, Refer

to the MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 μs.

The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 LCD segment drive capability, a scan interface, and 48 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and process the data and transmit them to a host system. The comparator and timers make the configurations ideal for gas, heat, and water meters, industrial meters, counter applications, handheld meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

−40°C to 85°C

pin designation, MSP430xW42x

AVCCDVSSAV

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC 64-PIN QFP

MSP430FW423IPM MSP430FW425IPM MSP430FW427IPM

P6.2/SIFCH2

P6.1/SIFCH1

P6.0/SIFCH0

RST/NMI

TCK

TMS

(PM)

TDI/TCLK

TDO/TDI

P1.0/TA0.0

P1.1/TA0.0/MCLK

P1.2/TA0.1

P1.3/TA1.0/SVSOUT

P1.4/TA1.0

P6.3/SIFCH3/SIFCAOUT

P6.4/SIFCI0 P6.5/SIFCI1

P6.6/SIFCI2/SIFDACOUT

P6.7/SIFCI3/SVSIN

SIFCI

XIN

XOUT

SIFVSS

SIFCOM

P5.1/S0 P5.0/S1 P4.7/S2 P4.6/S3 P4.5/S4

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P4.4/S5

P4.3/S6

P4.2/S7

P4.1/S8

P4.0/S9

MSP430xW42x

P3.7/S10

P3.6/S11

P3.5/S12

P3.4/S13

P3.3/S14

P3.2/S15

P3.1/S16

P3.0/S17

P2.7/SIFCLKG/S18

P1.5/TA0CLK/ACLK

P1.6/CA0

P1.7/CA1

P2.0/TA0.2

P2.1/TA1.1

P5.7/R33

P5.6/R23

P5.5/R13

41 40

R03

P5.4/COM3

P5.3/COM2

P5.2/COM1

COM0

P2.2/TA1.2/S23 P2.3/TA1.3/S22

34 33

P2.4/TA1.4/S21

P2.6/CAOUT/S19

P2.5/TA1CLK/S20

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functional block diagram

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

XOUT

XIN

Oscillator

FLL+

MCLK

8 MHz

CPU

incl. 16

Registers

Emulation

Module

JTAG

Interface

DVCCDVSSAVCCAV

ACLK

MAB

MDB

Flash

32KB 16KB

8KB

POR/

Multilevel

SVS/

Brownout

RST/NMI

SMCLK

RAM

1KB 512B 256B

Scan IF

Watchdog

Timer

WDT

15/16-Bit

Port 1

8 I/O

Interrupt

Capability

Timer0_A3

3 CC Reg

Port 2

8 I/O

Interrupt

Capability

Timer1_A5

5 CC Reg

Port 3

8 I/O

Comparator_

Port 4

8 I/O

Basic

Timer 1

1 Interrupt

Vector

Segments

1,2,3,4 MUX

LCD

Port 5

8 I/O

LCD

Port 6

8 I/O

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Terminal Functions

TERMINAL

NAME NO.

SIFVSS 10 Scan IF AFE reference supply voltage. P1.0/TA0.0 53 I/O General-purpose digital I/O/Timer0_A. Capture: CCI0A input, compare: Out0 output/BSL transmit P1.1/TA0.0/MCLK 52 I/O General-purpose digital I/O/Timer0_A. Capture: CCI0B input/MCLK output/BSL receive

P1.2/TA0.1 51 I/O General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output P1.3/TA1.0/

SVSOUT P1.4/TA1.0 49 I/O General-purpose digital I/O/Timer1_A, capture: CCI0A input, compare: Out0 output P1.5/TA0CLK/

ACLK P1.6/CA0 47 I/O General-purpose digital I/O/Comparator_A input P1.7/CA1 46 I/O General-purpose digital I/O/Comparator_A input P2.0/TA0.2 45 I/O General-purpose digital I/O/Timer0_A, capture: CCI2A input, compare: Out2 output P2.1/TA1.1 44 I/O General-purpose digital I/O/Timer0_A, capture: CCI1A input, compare: Out1 output P2.2/TA1.2/S23 35 I/O General-purpose digital I/O/Timer1_A, capture: CCI2A input, compare: Out2 output/LCD segment

P2.3/TA1.3/S22 34 I/O General-purpose digital I/O/Timer1_A, capture: CCI3A input, compare: Out3 output/LCD segment

P2.4/TA1.4/S21 33 I/O General-purpose digital I/O/Timer1_A, capture: CCI4A input, compare: Out4 output/LCD segment

P2.5/TA1CLK/S20 32 I/O General-purpose digital I/O/input of Timer1_A clock/LCD segment output 20 (see Note) P2.6/CAOUT/S19 31 I/O General-purpose digital I/O/Comparator_A output/LCD segment output 19 (see Note) P2.7/SIFCLKG/

S18 P3.0/S17 29 I/O General-purpose digital I/O/ LCD segment output 17 (see Note) P3.1/S16 28 I/O General-purpose digital I/O/ LCD segment output 16 (see Note) P3.2/S15 27 I/O General-purpose digital I/O/ LCD segment output 15 (see Note) P3.3/S14 26 I/O General-purpose digital I/O/ LCD segment output 14 (see Note) P3.4/S13 25 I/O General-purpose digital I/O/LCD segment output 13 (see Note) P3.5/S12 24 I/O General-purpose digital I/O/LCD segment output 12 (see Note) P3.6/S11 23 I/O General-purpose digital I/O/LCD segment output 11 (see Note) P3.7/S10 22 I/O General-purpose digital I/O/LCD segment output 10 (see Note)

NOTE: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

64 Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF

62 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, scan IF

63 Digital supply voltage, negative terminal.

50 I/O General-purpose digital I/O/Timer1_A, capture: CCI0B input/SVS: output of SVS comparator

48 I/O General-purpose digital I/O/input of Timer0_A clock/output of ACLK

30 I/O General-purpose digital I/O/Scan IF, signal SIFCLKG from internal clock generator/LCD segment

I/O

AFE, port 6, and LCD resistive divider circuitry; must not power up prior to DV

AFE. and port 6. Must be externally connected to DV

1 Digital supply voltage, positive terminal.

Note: TA0.0 is only an input on this pin.

Note: TA1.0 is only an input on this pin.

output 23 (see Note)

output 22 (see Note)

output 21 (see Note)

output 18 (see Note)

DESCRIPTION

. Internally connected to DVSS.

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MIXED SIGNAL MICROCONTROLLER

Terminal Functions (Continued)

MSP430xW42x

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

TERMINAL

NAME NO.

P4.0/S9 21 I/O General-purpose digital I/O/LCD segment output 9 (see Note) P4.1/S8 20 I/O General-purpose digital I/O/LCD segment output 8 (see Note) P4.2/S7 19 I/O General-purpose digital I/O/LCD segment output 7 (see Note) P4.3/S6 18 I/O General-purpose digital I/O/LCD segment output 6 (see Note) P4.4/S5 17 I/O General-purpose digital I/O/LCD segment output 5 (see Note) P4.5/S4 16 I/O General-purpose digital I/O/LCD segment output 4 (see Note) P4.6/S3 15 I/O General-purpose digital I/O/LCD segment output 3 (see Note) P4.7/S2 14 I/O General-purpose digital I/O/LCD segment output 2 (see Note) P5.0/S1 13 I/O General-purpose digital I/O/LCD segment output 1 (see Note) P5.1/S0 12 I/O General-purpose digital I/O/LCD segment output 0 (see Note) COM0 36 O Common output. COM0−3 are used for LCD backplanes P5.2/COM1 37 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes P5.3/COM2 38 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes P5.4/COM3 39 I/O General-purpose digital I/O/common output. COM0−3 are used for LCD backplanes R03 40 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R13 41 I/O General-purpose digital I/O/input port of third most positive analog LCD level (V4 or V3) P5.6/R23 42 I/O General-purpose digital I/O/input port of second most positive analog LCD level (V2) P5.7/R33 43 I/O General-purpose digital I/O/output port of most positive analog LCD level (V1) P6.0/SIFCH0 59 I/O General-purpose digital I/O/Scan IF, channel 0 sensor excitation output and signal input P6.1/SIFCH1 60 I/O General-purpose digital I/O/Scan IF, channel 1 sensor excitation output and signal input P6.2/SIFCH2 61 I/O General-purpose digital I/O/Scan IF, channel 2 sensor excitation output and signal input P6.3/SIFCH3/

SIFCAOUT P6.4/SIFCI0 3 I/O General-purpose digital I/O/Scan IF, channel 0 signal input to comparator P6.5/SIFCI1 4 I/O General-purpose digital I/O/Scan IF, channel 1 signal input to comparator P6.6/SIFCI2/

SIFDACOUT P6.7/

SIFCI3/SVSIN SIFCI 7 I Scan IF input to Comparator. SIFCOM 11 O Common termination for Scan IF sensors. RST/NMI 58 I Reset input or nonmaskable interrupt input port. TCK 57 I Test clock. TCK is the clock input port for device programming and test. TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TDO/TDI 54 I/O Test data output port. TDO/TDI data output or programming data input terminal. TMS 56 I Test mode select. TMS is used as an input port for device programming and test. XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT1.

NOTE: LCD function selected automatically when applicable LCD module control bits are set, not with PxSEL bits.

I/O

2 I/O General-purpose digital I/O/Scan IF, channel 3 sensor excitation output and signal input/Scan IF

comparator output

5 I/O General-purpose digital I/O/Scan IF, channel 2 signal input to comparator/10-bit DAC output

6 I/O General-purpose digital I/O/Scan IF, channel 3 signal input to comparator/SVS, analog input

DESCRIPTION

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)

Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)

Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)

Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect

autoincrement

Immediate D MOV #X,TONI MOV #45,TONI #45 −−> M(TONI)

NOTE: S = source D = destination

D MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 −−> R11

M(R10) −−> R11 R10 + 2−−> R10

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

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operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

− All clocks are active

D Low-power mode 0 (LPM0)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control remains active

D Low-power mode 1 (LPM1)

− CPU is disabled ACLK and SMCLK remain active, MCLK is available to modules FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator remains enabled ACLK remains active

D Low-power mode 3 (LPM3)

− CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled ACLK remains active

D Low-power mode 4 (LPM4)

− CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped

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interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power-up

External Reset

Watchdog

Flash memory

NMI

Oscillator Fault

Flash memory access violation

Timer1_A5 TA1CCR0 CCIFG (see Note 2) Maskable 0FFFAh 13

Timer1_A5

Comparator_A CMPAIFG Maskable 0FFF6h 11

Watchdog Timer WDTIFG Maskable 0FFF4h 10

Scan IF SIFIFG0 to SIFIFG6

Timer0_A3 TA0CCR0 CCIFG (see Note 2) Maskable 0FFECh 6

Timer0_A3

I/O port P1

(eight flags)

I/O port P2

(eight flags)

Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt-enable cannot.

WDTIFG

KEYV

(see Note 1)

NMIIFG

OFIFG

ACCVIFG

(see Notes 1 & 3)

TA1CCR1 CCIFG to

TA1CCR4 CCIFG,

TA1CTL TAIFG

(see Notes 1 & 2)

(See Note 1)

TA0CCR1 CCIFG, TA0CCR2 CCIFG,

TA0CTL TAIFG

(see Notes 1 & 2)

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

Reset 0FFFEh 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0FFF8h 12

Maskable 0FFF2h 9

Maskable 0FFEAh 5

Maskable 0FFE8h 4

Maskable 0FFE2h 1

0FFFCh 14

0FFF0h 8

0FFEEh 7

0FFE6h 3 0FFE4h 2

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

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special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits that are not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

interrupt enable 1 and 2

Address 00h ACCVIE NMIIE

Address 01h BTIE

7654 0

rw-0

7654 0321

rw-0

rw-0 rw-0 rw-0

321

OFIE WDTIE

WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is

configured in interval timer mode. OFIE: Oscillator-fault-interrupt enable NMIIE: Nonmaskable-interrupt enable ACCVIE: Flash access violation interrupt enable BTIE: Basic Timer1 interrupt enable

interrupt flag register 1 and 2

Address 02h NMIIFG

Address 03h BTIFG

7654 0

rw-0 rw-1 rw-(0)

7654 0321

rw-0

321

OFIFG WDTIFG

WDTIFG: Set on watchdog-timer overflow (in watchdog mode) or security key violation. Reset with VCC power-up,

or a reset condition at the RST

/NMI pin in reset mode. OFIFG: Flag set on oscillator fault NMIIFG: Set via RST

/NMI pin

BTIFG: Basic Timer1 interrupt flag

module enable registers 1 and 2

Address

04h/05h

Legend: rw:

rw-0,1: rw-(0,1):

7654 0321

Bit Can Be Read and Written Bit Can Be Read and Written. It Is Reset or Set by PUC. Bit Can Be Read and Written. It Is Reset or Set by POR. SFR Bit Not Present in Device

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memory organization

MSP430FW423 MSP430FW425 MSP430FW427

Memory Interrupt vector Code memory

Information memory Size 256 Byte

Boot memory Size 1KB

RAM Size 256 Byte

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.

Size Flash Flash

8-bit

8-bit SFR

8KB 0FFFFh − 0FFE0h 0FFFFh − 0E000h

010FFh − 01000h

0FFFh − 0C00h

02FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

16KB 0FFFFh − 0FFE0h 0FFFFh − 0C000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

512 Byte

03FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

32KB

0FFFFh − 0FFE0h

0FFFFh − 08000h

256 Byte

010FFh − 01000h

1KB

0FFFh − 0C00h

1KB

05FFh − 0200h 01FFh − 0100h

0FFh − 010h

0Fh − 00h

BSL Function PM Package Pins

Data Transmit 53 - P1.0

Data Receive 52 - P1.1

flash memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128

bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A and B can be erased individually, or as a group with segments 0−n.

Segments A and B are also called information memory.

D New devices may have some bytes programmed in the information memory (needed for test during

manufacturing). The user should perform an erase of the information memory prior to the first use.

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flash memory (continued)

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

8KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0E400h

0E3FFh

0E200h

0E1FFh

0E000h 010FFh

01080h

0107Fh

01000h

16KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

0C400h

0C3FFh

0C200h

0C1FFh

0C000h

010FFh

01080h 0107Fh

01000h

32KB

0FFFFh

0FE00h

0FDFFh

0FC00h

0FBFFh

0FA00h 0F9FFh

08400h

083FFh

08200h

081FFh

08000h

010FFh

01080h

0107Fh

01000h

Segment 0

With Interrupt Vectors

Segment 1

Segment 2

Main Memory

Segment n−1

Segment n

Segment A

Information Memory

Segment B

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430xW42x family of devices is supported by the FLL+ module that includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system cost and low-power consumption. The FLL+ features a digital frequency locked loop (FLL) hardware which in conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 μs. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal. D Main clock (MCLK), the system clock used by the CPU. D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.

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brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V have ramped to V reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when VCC reaches V

at that time. The user must insure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

Basic Timer1

The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic interrupts and clock for the LCD module.

LCD drive

The LCD driver generates the segment and common signals required to drive an LCD display. The LCD controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.

watchdog timer

may not

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

comparator_A

The primary function of the comparator_A module is to support precision slope analog−to−digital conversions, battery−voltage supervision, and monitoring of external analog signals.

scan IF

The scan interface is used to measure linear or rotational motion and supports LC and resistive sensors such as GMR sensors. The scan IF incorporates a V up to four sensors.

/2 generator, a comparator, and a 10-bit DAC and supports

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MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

timer0_A3

Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer0_A3 Signal Connections

Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number

48 - P1.5 TA0CLK TACLK

ACLK ACLK

SMCLK SMCLK 48 - P1.5 TA0CLK INCLK 53 - P1.0 TA0.0 CCI0A 52 - P1.1 TA0.0 CCI0B

51 - P1.2 TA0.1 CCI1A

CAOUT (internal) CCI1B

45 - P2.0 TA0.2 CCI2A

ACLK (internal) CCI2B

GND

Timer NA

53 - P1.0

CCR0 TA0.0

51 - P1.2

CCR1 TA0.1

45 - P2.0

CCR2 TA0.2

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MSP430xW42x MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

timer1_A5

Timer1_A5 is a 16-bit timer/counter with five capture/compare registers. Timer1_A5 can support multiple capture/compares, PWM outputs, and interval timing. Timer1_A5 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Timer1_A5 Signal Connections

Input Pin Number Device Input Signal Module Input Name Module Block Module Output Signal Output Pin Number

32 - P2.5 TA1CLK TACLK

ACLK ACLK

SMCLK SMCLK 32 - P2.5 TA1CLK INCLK 49 - P1.4 TA1.0 CCI0A 50 - P1.3 TA1.0 CCI0B

DV DV

GND

44 - P2.1 TA1.1 CCI1A

CAOUT (internal) CCI1B

DV DV

GND

35 - P2.2 TA1.2 CCI2A

SIFO0sig (internal) CCI2B

DV DV

GND

34 - P2.3 TA1.3 CCI3A

SIFO1sig (internal) CCI3B

DV DV

GND

33 - P2.4 TA1.4 CCI4A

SIFO2sig (internal) CCI4B

DV DV

GND

Timer NA

49 - P1.4

CCR0 TA1.0

44 - P2.1

CCR1 TA1.1

35 - P2.2

CCR2 TA1.2

34 - P2.3

CCR3 TA1.3

33 - P2.4

CCR4 TA1.4

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peripheral file map

Watchdog Watchdog Timer control WDTCTL 0120h Timer1_A5

Timer0_A3

Flash

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

PERIPHERALS WITH WORD ACCESS

Timer1_A interrupt vector TA1IV 011Eh Timer1_A control TA1CTL 0180h Capture/compare control 0 TA1CCTL0 0182h Capture/compare control 1 TA1CCTL1 0184h Capture/compare control 2 TA1CCTL2 0186h Capture/compare control 3 TA1CCTL3 0188h Capture/compare control 4 TA1CCTL4 018Ah Reserved 018Ch Reserved 018Eh Timer1_A register TA1R 0190h Capture/compare register 0 TA1CCR0 0192h Capture/compare register 1 TA1CCR1 0194h Capture/compare register 2 TA1CCR2 0196h Capture/compare register 3 TA1CCR3 0198h Capture/compare register 4 TA1CCR4 019Ah Reserved 019Ch Reserved 019Eh Timer0_A interrupt vector TA0IV 012Eh Timer0_A control TA0CTL0 0160h Capture/compare control 0 TA0CCTL0 0162h Capture/compare control 1 TA0CCTL1 0164h Capture/compare control 2 TA0CCTL2 0166h Reserved 0168h Reserved 016Ah Reserved 016Ch Reserved 016Eh Timer0_A register TA0R 0170h Capture/compare register 0 TA0CCR0 0172h Capture/compare register 1 TA0CCR1 0174h Capture/compare register 2 TA0CCR2 0176h Reserved 0178h Reserved 017Ah Reserved 017Ch Reserved 017Eh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

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PERIPHERALS WITH WORD ACCESS (CONTINUED)

Scan IF

LCD

Comparator_A

Brownout, SVS SVS control register SVSCTL 056h FLL+ Clock

Basic Timer1

SIF timing state machine 23 SIFTSM23 01FEh : : : SIF timing state machine 0 SIFTSM0 01D0h SIF DAC register 7 SIFDACR7 01CEh : : : SIF DAC register 0 SIFDACR0 01C0h SIF control register 5 SIFCTL5 01BEh SIF control register 4 SIFCTL4 01BCh SIF control register 3 SIFCTL3 01BAh SIF control register 2 SIFCTL2 01B8h SIF control register 1 SIFCTL1 01B6h SIF processing state machine vector SIFPSMV 01B4h SIF counter CNT1/2 SIFCNT 01B2h Reserved SIFDEBUG 01B0h

PERIPHERALS WITH BYTE ACCESS

LCD memory 20 LCDM20 0A4h : : : LCD memory 16 LCDM16 0A0h LCD memory 15 LCDM15 09Fh : : : LCD memory 1 LCDM1 091h LCD control and mode LCDCTL 090h Comparator_A port disable CAPD 05Bh Comparator_A control 2 CACTL2 05Ah Comparator_A control 1 CACTL1 059h

FLL+ Control 1 FLL_CTL1 054h FLL+ Control 0 FLL_CTL0 053h System clock frequency control SCFQCTL 052h System clock frequency integrator SCFI1 051h System clock frequency integrator SCFI0 050h BT counter 2 BTCNT2 047h BT counter 1 BTCNT1 046h BT control BTCTL 040h

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peripheral file map (continued)

Port P6

Port P5

Port P4

Port P3

Port P2

Port P1

Special Functions

MSP430xW42x

MIXED SIGNAL MICROCONTROLLER

SLAS383B − OCTOBER 2003 − REVISED JUNE 2007

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P6 selection P6SEL 037h Port P6 direction P6DIR 036h Port P6 output P6OUT 035h Port P6 input P6IN 034h Port P5 selection P5SEL 033h Port P5 direction P5DIR 032h Port P5 output P5OUT 031h Port P5 input P5IN 030h Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt-edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt-edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR module enable 2 ME2 005h SFR module enable 1 ME1 004h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

absolute maximum ratings

†

Voltage applied at VCC to VSS −0.3 V to + 4.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any pin (see Note) −0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Diode current at any device terminal . ±2 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature (unprogrammed device) −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature (programmed device) −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to V

applied to the TDI/TCLK pin when blowing the JTAG fuse.

. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

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+ 37 hidden pages

TEXAS INSTRUMENTS MSP430xW42x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

description

functional block diagram

Terminal Functions

short-form description

instruction set

operating modes

interrupt vector addresses

special function registers

interrupt enable 1 and 2

interrupt flag register 1 and 2

module enable registers 1 and 2

memory organization

bootstrap loader (BSL)

flash memory

peripherals

oscillator and system clock

brownout, supply voltage supervisor

digital I/O

Basic Timer1

LCD drive

watchdog timer

comparator_A

scan IF

timer0_A3

timer1_A5

peripheral file map

absolute maximum ratings