MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
− Active Mode: 280 μA at 1 MHz, 2.2 V
− Standby Mode: 1.1 μA
− Off Mode (RAM Retention): 0.1 μA
D Five Power Saving Modes
D Wake-Up From Standby Mode in Less
Than 6 μs
D 16-Bit RISC Architecture,
125-ns Instruction Cycle Time
D 12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
D 16-Bit Timer_B With Three
†
or Seven
‡
Capture/Compare-With-Shadow Registers
D 16-Bit Timer_A With Three
Capture/Compare Registers
D On-Chip Comparator
D Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1) —
MSP430x44x Devices
− One USART (USART0) —
MSP430x43x(1) Devices
D Brownout Detector
D Supply Voltage Supervisor/Monitor With
Programmable Level Detection
D Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
D Integrated LCD Driver for up to
160 Segments
D Bootstrap Loader
D Family Members Include:
− MSP430F435, MSP430F4351
16KB+256B Flash Memory,
512B RAM
− MSP430F436, MSP430F4361
24KB+256B Flash Memory,
1KB RAM
− MSP430F437, MSP430F4371
32KB+256B Flash Memory,
1KB RAM
− MSP430F447:
32KB+256B Flash Memory,
1KB RAM
− MSP430F448:
48KB+256B Flash Memory,
2KB RAM
− MSP430F449:
60KB+256B Flash Memory,
2KB RAM
§
:
§
:
§
:
D For Complete Module Descriptions, See
The MSP430x4xx Family User’s Guide,
Literature Number SLAU056
†
’F435, ’F436, and ’F437 devices
‡
’F447, ’F448, and ’F449 devices
§
The MSP430F43x1 devices are identical to the MSP430F43x
devices with the exception that the ADC12 module is not
implemented.
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 μs.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 2002−2007, Texas Instruments Incorporated
1
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
description (continued)
The MSP430x43x(1) and the MSP430x44x series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F43x1 devices), one or two universal serial
synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD)
with up to 160 segments.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers
make the configurations ideal for industrial control applications such as ripple counters, digital motor control,
EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code
and hardware-compatible family solution.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
PLASTIC 80-PIN QFP
(PN)
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
PLASTIC 100-PIN QFP
(PZ)
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
−40°C to 85°C
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x4351IPN, MSP430x4361IPN, MSP430x4371IPN
PN PACKAGE
(TOP VIEW)
SS1
CCAVSS
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
DV
AV
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
P1.3/TBOUTH/SVSOUT
P1.6/CA0
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
DV
CC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DV
SS
DV
SS
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
79 78 77 76 7580 74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
21
S10
P4.0/S9
25 26 27 28
24
S11
S12
MSP430F4351IPN
MSP430F4361IPN
MSP430F4371IPN
S13
S14
S15
72 71 7073
29
30 31 32 33
S16
S17
69 68
S20
P2.7/S18
67 66 65 64
34 35 36 37
S22
S23
S21
63 62 61
38 39 40
P3.7/S24
P3.6/S25
P3.5/S26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P3.4/S27
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DV
SS2
DV
CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P2.6/CAOUT/S19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P3.3/UCLK0/S28
3
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x4351IPZ, MSP430x4361IPZ, MSP430x4371IPZ
PZ PACKAGE
(TOP VIEW)
SS1
CCAVSS
P1.7/CA1
P1.5/TACLK/ACLK
P1.6/CA0
P2.0/TA2
79
80
81
82
47
46
45
44
DV
CC1
P6.3
P6.4
P6.5
P6.6
P6.7/SVSIN
Reserved
XIN
XOUT
DV
SS
DV
SS
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
DV
99
27
AV
98
28
P6.2
97
29
P6.1
96
30
P6.0
RST/NMI
94
95
32
31
TDI/TCLK
TCK
93
33
TDO/TDI
TMS
90
91
92
MSP430F4351IPZ
MSP430F4361IPZ
MSP430F4371IPZ
36
35
34
XT2IN
XT2OUT
88
89
38
37
P1.0/TA0
P1.1/TA0/MCLK
86
87
40
39
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.2/TA1
83
84
85
43
42
41
P2.3/TB2
P2.1/TB0
P2.2/TB1
76
77
78
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DV
SS2
DV
CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S21
S22
S14
S15
S16
S17
S18
S20
S19
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x435IPN, MSP430x436IPN, MSP430x437IPN
PN PACKAGE
(TOP VIEW)
SS1
CCAVSS
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
DV
AV
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDO/TDI
TDI/TCLK
XT2IN
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.6/CA0
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
P4.7/S2
P4.6/S3
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
79 78 77 76 7580 74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22 23
21
S10
P4.0/S9
25 26 27 28
24
S11
S12
S13
72 71 7073
MSP430F435IPN
MSP430F436IPN
MSP430F437IPN
29
S14
S15
S16
69 68
30 31 32 33
S17
67 66 65 64
34 35 36 37
S21
S20
S22
S23
P3.7/S24
63 62 61
38 39 40
P3.6/S25
P3.5/S26
P3.4/S27
P1.7/CA1
60
P2.0/TA2
59
P2.1/TB0
58
P2.2/TB1
57
P2.3/TB2
56
P2.4/UTXD0
55
P2.5/URXD0
54
DV
53
52
51
50
49
48
47
46
45
44
43
42
41
SS2
DV
CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P2.6/CAOUT/S19
P2.7/ADC12CLK/S18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P3.3/UCLK0/S28
5
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x435IPZ, MSP430x436IPZ, MSP430x437IPZ
PZ PACKAGE
(TOP VIEW)
SS1
CCAVSS
P1.7/CA1
P1.5/TACLK/ACLK
P1.6/CA0
80
81
82
46
45
44
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
DV
99
27
AV
98
28
97
29
P6.1/A1
P6.0/A0
P6.2/A2
95
96
31
30
RST/NMI
TCK
TMS
92
93
94
34
33
32
XT2IN
XT2OUT
89
37
88
38
P1.0/TA0
87
39
TDI/TCLK
TDO/TDI
90
91
MSP430F435IPZ
MSP430F436IPZ
MSP430F437IPZ
36
35
P1.3/TBOUTH/SVSOUT
P1.1/TA0/MCLK
86
40
P1.4/TBCLK/SMCLK
P1.2/TA1
83
84
85
43
42
41
P2.0/TA2
P2.1/TB0
78
79
48
47
P2.3/TB2
P2.2/TB1
76
77
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
DV
SS2
DV
CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/S39
S21
S22
S14
S15
S16
S17
S18
S20
S19
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
P4.5/S36
P4.4/S37
P4.3/S38
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
pin designation, MSP430x447IPZ, MSP430x448IPZ, MSP430x449IPZ
PZ PACKAGE
(TOP VIEW)
SS1
CCAVSS
P1.7/CA1
P1.5/TACLK/ACLK
P1.6/CA0
80
81
82
46
45
44
DV
CC1
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7/SVSIN
VREF+
XIN
XOUT
VeREF+
VREF−/VeREF−
P5.1/S0
P5.0/S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
26
DV
99
27
P6.2/A2
AV
97
98
29
28
P6.1/A1
P6.0/A0
RST/NMI
94
95
96
32
31
30
TDI/TCLK
TCK
93
33
TDO/TDI
TMS
90
91
92
MSP430F447IPZ
MSP430F448IPZ
MSP430F449IPZ
36
35
34
XT2IN
XT2OUT
88
89
38
37
P1.0/TA0
P1.1/TA0/MCLK
86
87
40
39
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.2/TA1
83
84
85
43
42
41
P2.0/TA2
P2.1/TB0
78
79
48
47
P2.3/TB2
P2.2/TB1
76
77
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
P2.4/UTXD0
P2.5/URXD0
P2.6/CAOUT
P2.7/ADC12CLK
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DV
SS2
DV
CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
S14
S15
S16
S21
S22
S17
S18
S20
S19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
P4.7/S34
P4.6/S35
4.3/SIMO1/S38
P4.4/SOMI1/S37
P4.5/UCLK1/S36
7
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 functional block diagram
DV
XIN
XOUT
CC1/2DVSS1/2AVCCAVSS
P1
8
P2
8
P3
P4
8
8
P5
8
P6
8
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Emulation
Module
JTAG
Interface
MCLK
ACLK
SMCLK
MAB
MDB
Flash
32KB
24KB
16KB
RAM
1KB
512B
POR/
SVS/
Brownout
RST/NMI
MSP430x43x functional block diagram
DV
CC1/2DVSS1/2AVCCAVSS
ACLK
SMCLK
Flash
32KB
24KB
16KB
RAM
1KB
512B
XT2IN
XT2OUT
XIN
Oscillator
FLL+
XOUT
MCLK
Port 1
8 I/O
Interrupt
Capability
P1
8
Port 1
8 I/O
Interrupt
Capability
Port 2
8 I/O
Interrupt
Capability
Watchdog
Timer
WDT
15/16-Bit
P2
8
Port 2
8 I/O
Interrupt
Capability
Port 3
8 I/O
Timer_B3
3 CC Reg
Shadow
Reg
P3
Port 3
8 I/O
8
UART Mode
SPI Mode
Segments
1,2,3,4 MUX
f
LCD
UART Mode
SPI Mode
USART0
LCD
128/160
USART0
Port 4
8 I/O
Timer_A3
3 CC Reg
P4
8
8
Port 4
8 I/O
Port 5
8 I/O
Comparator_
A
P5
8
Port 5
8 I/O
Port 6
6 I/O
Basic
Timer 1
1 Interrupt
Vector
P6
Port 6
6 I/O
8 MHz
CPU
incl. 16
Registers
Emulation
Module
JTAG
Interface
MAB
MDB
POR/
SVS/
Brownout
RST/NMI
ADC12
12-Bit
8 Channels
<10μs Conv.
Watchdog
Timer
WDT
15/16-Bit
Timer_B3
3 CC Reg
Shadow
Reg
Timer_A3
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
Segments
1,2,3,4 MUX
f
LCD
LCD
128/160
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x44x functional block diagram
DV
XIN
XOUT
CC1/2DVSS1/2AVCCAVSS
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
P1
8
P2
8
P3
P4
8
8
P5
8
P6
8
XT2IN
XT2OUT
Oscillator
FLL+
8 MHz
CPU
incl. 16
Registers
Emulation
Module
JTAG
Interface
MCLK
ACLK
SMCLK
Flash
60KB
48KB
32KB
MAB
MDB
Hardware
Multiplier
MPY, MPYS
MAC,MACS
RAM
2KB
1KB
POR/
SVS/
Brownout
RST/NMI
Port 1
8 I/O
Interrupt
Capability
ADC12
12-Bit
8 Channels
<10μs Conv.
Port 2
8 I/O
Interrupt
Capability
Watchdog
Timer
WDT
15/16-Bit
Port 3
8 I/O
Timer_B7
7 CC Reg
Shadow
Reg
Port 4
8 I/O
Timer_A3
3 CC Reg
Port 5
8 I/O
Comparator_
A
Port 6
6 I/O
Basic
Timer 1
1 Interrupt
Vector
USART0
USART1
UART Mode
SPI Mode
Segments
1,2,3,4 MUX
f
LCD
LCD
160
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions
TERMINAL
PN
NAME NO.
DV
CC1
P6.3 2 I/O P6.3 2 I/O General-purpose digital I/O
P6.4 3 I/O P6.4 3 I/O General-purpose digital I/O
P6.5 4 I/O P6.5 4 I/O General-purpose digital I/O
P6.6 5 I/O P6.6 5 I/O General-purpose digital I/O
P6.7/SVSIN 6 I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / input to brownout, supply voltage
Reserved 7 Reserved 7 Reserved, do not connect externally
XIN 8 I XIN 8 I
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
DV
SS
DV
SS
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/S18 30 I/O S18 30 O General-purpose digital I/O / LCD segment output 18
P2.6/CAOUT/S19 31 I/O S19 31 O
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
I/O
1 DV
10 I DV
11 I DV
PZ
NAME NO.
CC1
SS
SS
I/O
1 Digital supply voltage, positive terminal.
supervisor
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
10 I Connect to DV
11 I Connect to DV
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
SS
SS
DESCRIPTION
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
P3.3/UCLK0/S28 40 I/O S28 40 O
P3.2/SOMI0/S29 41 I/O S29 41 O
P3.1/SIMO0/S30 42 I/O S30 42 O
P3.0/STE0/S31 43 I/O S31 43 O
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O
P5.3/COM2 46 I/O P5.3/COM2 54 I/O
P5.4/COM3 47 I/O P5.4/COM3 55 I/O
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O
P5.6/R23 50 I/O P5.6/R23 58 I/O
P5.7/R33 51 I/O P5.7/R33 59 I/O
DV
CC2
DV
SS2
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
I/O
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
52 DV
53 DV
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7 72 I/O General-purpose digital I/O
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
PZ
NAME NO.
CC2
SS2
I/O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
60 Digital supply voltage, positive terminal.
61 Digital supply voltage, negative terminal.
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x1 Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O
P2.2/TB1 57 I/O P2.2/TB1 77 I/O
P2.1/TB0 58 I/O P2.1/TB0 78 I/O
P2.0/TA2 59 I/O P2.0/TA2 79 I/O
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
P1.3/TBOUTH/
SVSOUT
P1.2/TA1 65 I/O P1.2/TA1 85 I/O
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O
P1.0/TA0 67 I/O P1.0/TA0 87 I/O
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I
TDO/TDI 70 I/O TDO/TDI 90 I/O
TDI/TCLK 71 I TDI/TCLK 91 I
TMS 72 I TMS 92 I
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I
P6.0 75 I/O P6.0 95 I/O General-purpose digital I/O
P6.1 76 I/O P6.1 96 I/O General-purpose digital I/O
P6.2 77 I/O P6.2 97 I/O General-purpose digital I/O
AV
SS
DV
SS1
AV
CC
I/O
62 I/O
63 I/O
64 I/O
78 AV
79 DV
80 AV
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
P1.3/TBOUTH/
SVSOUT
SS
CC
PZ
NAME NO.
SS1
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
82 I/O
83 I/O
84 I/O
98
99 Digital supply voltage, negative terminal.
100
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
Test data output port. TDO/TDI data output or programming data input
terminal
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming
and test.
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry.
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, port 1, and LCD resistive divider circuitry;
must not power up prior to DV
DESCRIPTION
/DV
CC1
CC2
.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions
TERMINAL
PN
NAME NO.
DV
CC1
I/O
1 DV
P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5 4 I/O P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6 5 I/O P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN 6 I/O P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7—12-bit ADC, analog /
V
REF+
7 O V
REF+
XIN 8 I XIN 8 I
XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT1
Ve
V
REF+
REF−
/Ve
REF−
10 I Ve
11 I V
REF+
REF−
P5.1/S0 12 I/O P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
P4.7/S2 14 I/O S2 14 O General-purpose digital I/O / LCD segment output 2
P4.6/S3 15 I/O S3 15 O General-purpose digital I/O / LCD segment output 3
P4.5/S4 16 I/O S4 16 O General-purpose digital I/O / LCD segment output 4
P4.4/S5 17 I/O S5 17 O General-purpose digital I/O / LCD segment output 5
P4.3/S6 18 I/O S6 18 O General-purpose digital I/O / LCD segment output 6
P4.2/S7 19 I/O S7 19 O General-purpose digital I/O / LCD segment output 7
P4.1/S8 20 I/O S8 20 O General-purpose digital I/O / LCD segment output 8
P4.0/S9 21 I/O S9 21 O General-purpose digital I/O / LCD segment output 9
S10 22 O S10 22 O LCD segment output 10
S11 23 O S11 23 O LCD segment output 11
S12 24 O S12 24 O LCD segment output 12
S13 25 O S13 25 O LCD segment output 13
S14 26 O S14 26 O LCD segment output 14
S15 27 O S15 27 O LCD segment output 15
S16 28 O S16 28 O LCD segment output 16
S17 29 O S17 29 O LCD segment output 17
P2.7/ADC12CLK/
30 I/O S18 30 O General-purpose digital I/O / conversion clock—12-bit ADC / LCD
S18
P2.6/CAOUT/S19 31 I/O S19 31 O
S20 32 O S20 32 O LCD segment output 20
S21 33 O S21 33 O LCD segment output 21
S22 34 O S22 34 O LCD segment output 22
S23 35 O S23 35 O LCD segment output 23
P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24
P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25
P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26
P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27
PZ
NAME NO.
CC1
/Ve
REF−
I/O
DESCRIPTION
1 Digital supply voltage, positive terminal.
input to brownout, supply voltage supervisor
7 O Output of positive terminal of the reference voltage in the ADC
Input port for crystal oscillator XT1. Standard or watch crystals can be
connected.
10 I Input for an external reference voltage to the ADC
11 I
Negative terminal for the ADC’s reference voltage for both sources, the
internal reference voltage, or an external applied reference voltage.
segment output 18
General-purpose digital I/O / Comparator_A output / LCD segment
output 19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
P3.3/UCLK0/S28 40 I/O S28 40 O
P3.2/SOMI0/S29 41 I/O S29 41 O
P3.1/SIMO0/S30 42 I/O S30 42 O
P3.0/STE0/S31 43 I/O S31 43 O
COM0 44 O COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 45 I/O P5.2/COM1 53 I/O
P5.3/COM2 46 I/O P5.3/COM2 54 I/O
P5.4/COM3 47 I/O P5.4/COM3 55 I/O
R03 48 I R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 49 I/O P5.5/R13 57 I/O
P5.6/R23 50 I/O P5.6/R23 58 I/O
P5.7/R33 51 I/O P5.7/R33 59 I/O
DV
CC2
DV
SS2
P2.5/URXD0 54 I/O P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
I/O
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36
P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37
P4.3/S38 50 I/O General-purpose digital I/O / LCD segment output 38
P4.2/S39 51 I/O General-purpose digital I/O / LCD segment output 39
52 DV
53 DV
P4.1 62 I/O General-purpose digital I/O
P4.0 63 I/O General-purpose digital I/O
P3.7 64 I/O General-purpose digital I/O
P3.6 65 I/O General-purpose digital I/O
P3.5 66 I/O General-purpose digital I/O
P3.4 67 I/O General-purpose digital I/O
P3.3/UCLK0 68 I/O
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable USART0/SPI mode
P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
PZ
NAME NO.
CC2
SS2
I/O
General-purpose digital I/O / ext. clock i/p—USART0/UART or SPI
mode, clock o/p—USART0/SPI mode / LCD segment output 28
General-purpose digital I/O / slave out/master in of USART0/SPI mode
/ LCD segment output 29
General-purpose digital I/O / slave out/master out of USART0/SPI
mode / LCD segment output 30
General-purpose digital I/O / slave transmit enable-USART0/SPI
mode / LCD segment output 31
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / common output, COM0−3 are used for
LCD backplanes.
General-purpose digital I/O / input port of third most positive analog
LCD level (V4 or V3)
General-purpose digital I/O / input port of second most positive analog
LCD level (V2)
General-purpose digital I/O / output port of most positive analog LCD
level (V1)
60 Digital supply voltage, positive terminal.
61 Digital supply voltage, negative terminal.
General-purpose digital I/O / external clock input—USART0/UART or
SPI mode, clock output—USART0/SPI mode
DESCRIPTION
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
DESCRIPTION
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x43x Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
P2.4/UTXD0 55 I/O P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 56 I/O P2.3/TB2 76 I/O
P2.2/TB1 57 I/O P2.2/TB1 77 I/O
P2.1/TB0 58 I/O P2.1/TB0 78 I/O
P2.0/TA2 59 I/O P2.0/TA2 79 I/O
P1.7/CA1 60 I/O P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
P1.6/CA0 61 I/O P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
P1.3/TBOUTH/
SVSOUT
P1.2/TA1 65 I/O P1.2/TA1 85 I/O
P1.1/TA0/MCLK 66 I/O P1.1/TA0/MCLK 86 I/O
P1.0/TA0 67 I/O P1.0/TA0 87 I/O
XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 69 I XT2IN 89 I
TDO/TDI 70 I/O TDO/TDI 90 I/O
TDI/TCLK 71 I TDI/TCLK 91 I
TMS 72 I TMS 92 I
TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 74 I RST/NMI 94 I
P6.0/A0 75 I/O P6.0/A0 95 I/O General-purpose digital I/O / analog input a0 − 12-bit ADC
P6.1/A1 76 I/O P6.1/A1 96 I/O General-purpose digital I/O / analog input a1 − 12-bit ADC
P6.2/A2 77 I/O P6.2/A2 97 I/O General-purpose digital I/O / analog input a2 − 12-bit ADC
AV
SS
DV
SS1
AV
CC
I/O
62 I/O
63 I/O
64 I/O
78 AV
79 DV
80 AV
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
P1.3/TBOUTH/
SVSOUT
SS
CC
PZ
NAME NO.
SS1
I/O
General-purpose digital I/O / Timer_B3 CCR2.
Capture: CCI2A/CCI2B input, compare: Out2 output
General-purpose digital I/O / Timer_B3 CCR1.
Capture: CCI1A/CCI1B input, compare: Out1 output
General-purpose digital I/O / Timer_B3 CCR0.
Capture: CCI0A/CCI0B input, compare: Out0 output
General-purpose digital I/O / Timer_A
Capture: CCI2A input, compare: Out2 output
82 I/O
83 I/O
84 I/O
98
99 Digital supply voltage, negative terminal.
100
General-purpose digital I/O / Timer_A, clock signal TACLK input /
ACLK output (divided by 1, 2, 4, or 8)
General-purpose digital I/O / input clock TBCLK—Timer_B3 / submain
system clock SMCLK output
General-purpose digital I/O / switch all PWM digital output ports to high
impedance—Timer_B3 TB0 to TB2 / SVS: output of SVS comparator
General-purpose digital I/O / Timer_A, Capture: CCI1A input,
compare: Out1 output
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK
output. Note: TA0 is only an input on this pin / BSL receive
General-purpose digital I/O / Timer_A. Capture: CCI0A input,
compare: Out0 output / BSL transmit
Input port for crystal oscillator XT2. Only standard crystals can be
connected.
Test data output port. TDO/TDI data output or programming data input
terminal
Test data input or test clock input. The device protection fuse is
connected to TDI/TCLK.
Test mode select. TMS is used as an input port for device programming
and test.
General-purpose digital I/O / reset input or nonmaskable interrupt input
port
Analog supply voltage, negative terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry.
Analog supply voltage, positive terminal. Supplies SVS, brownout,
oscillator, comparator_A, ADC12, port 1, and LCD resistive divider
circuitry; must not power up prior to DV
DESCRIPTION
CC1
/DV
CC2
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions
TERMINAL
NAME NO.
DV
CC1
P6.3/A3 2 I/O General-purpose digital I/O / analog input a3—12-bit ADC
P6.4/A4 3 I/O General-purpose digital I/O / analog input a4—12-bit ADC
P6.5/A5 4 I/O General-purpose digital I/O / analog input a5—12-bit ADC
P6.6/A6 5 I/O General-purpose digital I/O / analog input a6—12-bit ADC
P6.7/A7/SVSIN 6 I/O
V
REF+
XIN 8 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT 9 O Output terminal of crystal oscillator XT1
Ve
REF+
V
/Ve
REF−
REF−
P5.1/S0 12 I/O General-purpose digital I/O / LCD segment output 0
P5.0/S1 13 I/O General-purpose digital I/O / LCD segment output 1
S2 14 O LCD segment output 2
S3 15 O LCD segment output 3
S4 16 O LCD segment output 4
S5 17 O LCD segment output 5
S6 18 O LCD segment output 6
S7 19 O LCD segment output 7
S8 20 O LCD segment output 8
S9 21 O LCD segment output 9
S10 22 O LCD segment output 10
S11 23 O LCD segment output 11
S12 24 O LCD segment output 12
S13 25 O LCD segment output 13
S14 26 O LCD segment output 14
S15 27 O LCD segment output 15
S16 28 O LCD segment output 16
S17 29 O LCD segment output 17
S18 30 O LCD segment output 18
S19 31 O LCD segment output 19
S20 32 O LCD segment output 20
S21 33 O LCD segment output 21
S22 34 O LCD segment output 22
S23 35 O LCD segment output 23
S24 36 O LCD segment output 24
S25 37 O LCD segment output 25
S26 38 O LCD segment output 26
S27 39 O LCD segment output 27
S28 40 O LCD segment output 28
I/O
1 Digital supply voltage, positive terminal.
General-purpose digital I/O / analog input a7—12-bit ADC / analog input to brownout, supply voltage
supervisor
7 O Output of positive terminal of the reference voltage in the ADC
10 I Input for an external reference voltage to the ADC
11 I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
DESCRIPTION
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
S29 41 O LCD segment output 29
S30 42 O LCD segment output 30
S31 43 O LCD segment output 31
S32 44 O LCD segment output 32
S33 45 O LCD segment output 33
P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34
P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35
P4.5/UCLK1/S36 48 I/O
P4.4/SOMI1/S37 49 I/O General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output 37
P4.3/SIMO1/S38 50 I/O General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output 38
P4.2/STE1/S39 51 I/O General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output 39
COM0 52 O COM0−3 are used for LCD backplanes.
P5.2/COM1 53 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
R03 56 I Input port of fourth positive (lowest) analog LCD level (V5)
P5.5/R13 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3)
P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V1)
DV
CC2
DV
SS2
P4.1/URXD1 62 I/O General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1 63 I/O General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output
P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output
P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output
P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCLK0 68 I/O
P3.2/SOMI0 69 I/O General-purpose digital I/O / slave out/master in of USART0/SPI mode
P3.1/SIMO0 70 I/O General-purpose digital I/O / slave in/master out of USART0/SPI mode
P3.0/STE0 71 I/O General-purpose digital I/O / slave transmit enable—USART0/SPI mode
P2.7/ADC12CLK 72 I/O General-purpose digital I/O / conversion clock—12-bit ADC
P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output
P2.5/URXD0 74 I/O General-purpose digital I/O / receive data in—USART0/UART mode
P2.4/UTXD0 75 I/O General-purpose digital I/O / transmit data out—USART0/UART mode
P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1 77 I/O General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0 78 I/O General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1 80 I/O General-purpose digital I/O / Comparator_A input
I/O DESCRIPTION
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
60 Digital supply voltage, positive terminal.
61 Digital supply voltage, negative terminal.
General-purpose digital I/O / external clock input—USART0/UART or SPI mode, clock
output—USART0/SPI mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
MSP430x44x Terminal Functions (Continued)
TERMINAL
PN
NAME NO.
P1.6/CA0 81 I/O General-purpose digital I/O / Comparator_A input
P1.5/TACLK/
ACLK
P1.4/TBCLK/
SMCLK
P1.3/TBOUTH/
SVSOUT
P1.2/TA1 85 I/O General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK 86 I/O
P1.0/TA0 87 I/O General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT 88 O Output terminal of crystal oscillator XT2
XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI 90 I/O Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK 91 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS 92 I Test mode select. TMS is used as an input port for device programming and test.
TCK 93 I Test clock. TCK is the clock input port for device programming and test.
RST/NMI 94 I Reset input or nonmaskable interrupt input port
P6.0/A0 95 I/O General-purpose digital I/O, analog input a0—12-bit ADC
P6.1/A1 96 I/O General-purpose digital I/O, analog input a1—12-bit ADC
P6.2/A2 97 I/O General-purpose digital I/O, analog input a2—12-bit ADC
AV
SS
DV
SS1
AV
CC
I/O DESCRIPTION
82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4, or 8)
83 I/O General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
84 I/O
98
99 Digital supply voltage, negative terminal.
100
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0 to TB6
/ SVS: output of SVS comparator
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12,
port 1, and LCD resistive divider circuitry.
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_A, ADC12, port 1,
and LCD resistive divider circuitry; must not power up prior to DV
CC1
/DV
CC2
.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
short-form description
CPU
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
Program Counter
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 −−−> R5
Single operands, destination only e.g. CALL R8 PC −−>(TOS), R8−−> PC
Relative jump, un/conditional e.g. JNE Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE S D SYNTAX EXAMPLE OPERATION
Register D
Indexed D D MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)−−> M(6+R6)
Symbolic (PC relative) D D MOV EDE,TONI M(EDE) −−> M(TONI)
Absolute D D MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT)
Indirect D MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6)
Indirect
autoincrement
Immediate D MOV #X,TONI MOV #45,TONI #45 −−> M(TONI)
NOTE: S = source D = destination
D
D MOV @Rn+,Rm MOV @R10+,R11
MOV Rs,Rd MOV R10,R11 R10 −−> R11
M(R10) −−> R11
R10 + 2−−> R10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
− All clocks are active
D Low-power mode 0 (LPM0)
− CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ loop control remains active
D Low-power mode 1 (LPM1)
− CPU is disabled
FLL+ loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 2 (LPM2)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3)
− CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4)
− CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh−0FFE0h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT
Power-Up
External Reset
Watchdog
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
Timer_B7
Timer_B7
Comparator_A CAIFG Maskable 0FFF6h 11
Watchdog Timer WDTIFG Maskable 0FFF4h 10
USART0 Receive URXIFG0 Maskable 0FFF2h 9
USART0 Transmit UTXIFG0 Maskable 0FFF0h 8
ADC12 (see Note 4) ADC12IFG (see Notes 1 and 2) Maskable 0FFEEh 7
Timer_A3 TACCR0 CCIFG (see Note 2) Maskable 0FFECh 6
Timer_A3
I/O Port P1 (Eight Flags)
USART1 Receive
USART1 Transmit
I/O Port P2 (Eight Flags)
Basic Timer1 BTIFG Maskable 0FFE0h 0, lowest
†
’43x(1) uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6
CCIFGs, and TBIFG
‡
USART1 is implemented in ’44x only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
4. ADC12 is not implemented in MSP430x43x1 devices.
†
†
‡
‡
it.
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
TBCCR0 CCIFG (see Note 2) Maskable 0FFFAh 13
TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2)
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
WDTIFG
KEYV
(see Note 1)
P1IFG.0 to P1IFG.7
(see Notes 1 and 2)
URXIFG1 Maskable 0FFE6h 3
UTXIFG1 Maskable 0FFE4h 2
P2IFG.0 to P2IFG.7
(see Notes 1 and 2)
Reset 0FFFEh 15, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable 0FFF8h 12
Maskable 0FFEAh 5
Maskable 0FFE8h 4
Maskable 0FFE2h 1
WORD
ADDRESS
0FFFCh 14
PRIORITY
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
MSP430x43x1, MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344F − JANUARY 2002 − REVISED MAY 2007
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
0h URXIE0 ACCVIE NMIIE
7654 0
UTXIE0 OFIE WDTIE
rw–0 rw–0 rw–0
rw–0 rw–0 rw–0
321
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
URXIE0: USART0: UART and SPI receive-interrupt enable
UTXIE0: USART0: UART and SPI transmit-interrupt enable
Address
01h URXIE1
7654 0
BTIE
rw–0
UTXIE1
rw–0 rw–0
321
URXIE1: USART1: UART and SPI receive-interrupt enable (MSP430F44x devices only)
UTXIE1: USART1: UART and SPI transmit-interrupt enable (MSP430F44x devices only)
BTIE: Basic timer interrupt enable
interrupt flag register 1 and 2
Address
02h URXIFG0 NMIIFG
7654 0
UTXIFG0 OFIFG WDTIFG
rw–1 rw–0
rw–0 rw–1 rw–(0)
321
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on V
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST
/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
Address
03h URXIFG1
7654 0
BTIFG
rw
UTXIFG1
rw–1 rw–0
321
URXIFG1: USART1: UART and SPI receive flag (MSP430F44x devices only)
UTXIFG1: USART1: UART and SPI transmit flag (MSP430F44x devices only)
BTIFG: Basic timer flag
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
Loading...